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39717 discussions

Re: [LinuxBIOS] CONFIG_LB_MEM_TOPK
by Lu, Yinghai 31 Mar '06

31 Mar '06

Some change in src/cpu/amd/car... YH -----Original Message----- From: Stefan Reinauer [mailto:stepan@openbios.org] Sent: Friday, March 31, 2006 2:40 AM To: Lu, Yinghai Cc: Ronald G Minnich; Jason Schildt; linuxbios(a)linuxbios.org Subject: Re: CONFIG_LB_MEM_TOPK * Lu, Yinghai <yinghai.lu(a)amd.com> [060331 04:13]: > I'm going to check in new cache_as_ram code. It is more solid and could > copy data from cache to ram. So we can pass some info from CAR stage to > RAM stage. > > I want to change the default value for CONFIG_LB_MEM_TOPK from 1024 to > 2048. > So I don't need to change every Opteron MB Config.lb... > > Let me know if is ok to you. Let me know where we can review that code before you go ahead and check it in. It's not in the issue tracker yet, is it? Stefan

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[LinuxBIOS] Issue Tracker Mails
by Stefan Reinauer 31 Mar '06

31 Mar '06

Hi, to get rid of all the spam in the issue tracker it is no longer possible to send mails to the tracker. Since we're going to switch over to bugzilla soon, this won't be a long term restriction. Stefan

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Re: [LinuxBIOS] Kernel will not boot
by Lu, Yinghai 28 Mar '06

28 Mar '06

Loglevel 8 is enough. Also you code base is some old. YH

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[LinuxBIOS] nforce2 geforce4
by v.r＠vif.com 28 Mar '06

28 Mar '06

ami 4mb flash asus a7n8x-vm 400mhz nforce2 geforce4 agp sempron 2500+ 333mhz pc3200 512m kingston I want to flash the board Anyone interested to help? Thanks

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[LinuxBIOS] Patch for advantech som_gx533
by Richard Smith 27 Mar '06

27 Mar '06

- The attached diff sets up a config for the Advantech gx533 eval board I have. - It also adds some verbosity and pass fail logic to the ram test. Since the ram test always printed "DRAM verified" regardless of pass or fail I worked for a long time trying to understand why I died when I jumped to RAM. When the real reason was that my RAM is hosed. So now if the RAM test fails then its _obvious_. Is 256 failed attempts before aborting really necessary? I mean > 1 is problem. Will anyone object to making the abort number much smaller? The changes are trivial so unless someone has objections I'll commit. Ok on to my debugging. So my RAM isn't playing nice. From the log you can see that Bit 8 is not clearing. Any suggestions on what register I should go tweak on to tune up my RAM? LinuxBIOS-1.1.8.0Fallback Sat Mar 25 03:09:37 CST 2006 starting... reboot from BIOS reset done cs5535 early Cpu core is 0000014e reboot from BIOS reset done pll_reset Ram1.00 Ram2.00 Ram3 Ram4 Done sdram_initialize Disable watchdog ffCAN NOT READ SUPERIO VID ff:ff Testing DRAM : 00000000-00004000 DRAM fill: 00000000-00004000 00000000 00004000 DRAM filled DRAM verify: 00000000-00004000 00000000 Fail: @0x00000000 Read value=0x00001000 Fail: @0x00000004 Read value=0x00001004 Fail: @0x00000008 Read value=0x00001008 Fail: @0x0000000c Read value=0x0000100c Fail: @0x00000010 Read value=0x00001010 Fail: @0x00000014 Read value=0x00001014 Fail: @0x00000018 Read value=0x00001018 Fail: @0x0000001c Read value=0x0000101c Fail: @0x00000020 Read value=0x00001020 <snip> Fail: @0x000003fc Read value=0x000013fc Fail: @0x00000400 Read value=0x00001400 Aborting. 00000400 DRAM did _NOT_ verify! Done. Testing DRAM : 00020000-00024000 DRAM fill: 00020000-00024000 00020000 00024000 DRAM filled DRAM verify: 00020000-00024000 00020000 Fail: @0x00020000 Read value=0x00021000 Fail: @0x00020004 Read value=0x00021004 Fail: @0x00020008 Read value=0x00021008 Fail: @0x0002000c Read value=0x0002100c Fail: @0x00020010 Read value=0x00021010 Fail: @0x00020014 Read value=0x00021014 Fail: @0x00020018 Read value=0x00021018 Fail: @0x0002001c Read value=0x0002101c <snip> Fail: @0x000203f0 Read value=0x000213f0 Fail: @0x000203f4 Read value=0x000213f4 Fail: @0x000203f8 Read value=0x000213f8 Fail: @0x000203fc Read value=0x000213fc Fail: @0x00020400 Read value=0x00021400 Aborting. 00020400 DRAM did _NOT_ verify! Done. Testing DRAM : 00000000-000a0000 DRAM fill: 00000000-000a0000 00000000 00010000 00020000 00030000 00040000 00050000 00060000 00070000 00080000 00090000 000a0000 DRAM filled DRAM verify: 00000000-000a0000 00000000 Fail: @0x00000000 Read value=0x00001000 Fail: @0x00000004 Read value=0x00001004 Fail: @0x00000008 Read value=0x00001008 Fail: @0x0000000c Read value=0x0000100c Fail: @0x00000010 Read value=0x00001010 Fail: @0x00000014 Read value=0x00001014 Fail: @0x00000018 Read value=0x00001018 Fail: @0x0000001c Read value=0x0000101c Fail: @0x00000020 Read value=0x00001020 <snip> Fail: @0x000003f0 Read value=0x000013f0 Fail: @0x000003f4 Read value=0x000013f4 Fail: @0x000003f8 Read value=0x000013f8 Fail: @0x000003fc Read value=0x000013fc Fail: @0x00000400 Read value=0x00001400 Aborting. 00000400 DRAM did _NOT_ verify! Done. Copying LinuxBIOS to ram. Jumping to LinuxBIOS. -- Richard A. Smith

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Re: [LinuxBIOS] [Fwd: Hardware Write-Protect for BIOS & EC]
by Lu, Yinghai 24 Mar '06

24 Mar '06

1. in you suggestion. When you are flash the rom, if sth go wrong (lose power), you will corrupt your rom. 2. are you going to use fallback image with normal image? If so you can disable the write to last 128K ( fallback image part) via HW jumper. ---- No one could change the fallback image without remove the jumper. Some MB already have that for last 64k. YH -----Original Message----- From: linuxbios-bounces(a)linuxbios.org [mailto:linuxbios-bounces@linuxbios.org] On Behalf Of Jim Gettys Sent: Thursday, March 23, 2006 7:26 AM To: LinuxBIOS Subject: [LinuxBIOS] [Fwd: Hardware Write-Protect for BIOS & EC] OK, here's the proposed solution for write protect of the OLPC BIOS. Short of phishing attacks, I think it should suffice; but I'd like people here to shoot at the scheme in case I'm missing something. Regards, - Jim -- Jim Gettys One Laptop Per Child

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Re: [LinuxBIOS] S2881 and linuxbios
by Lu, Yinghai 24 Mar '06

24 Mar '06

Good. Can you use memtest as your payload? 1. get memtest...enable serial port support, and compile it. 2. load it as payload for LinuxBIOS 3. or use Etherboot or Filo to load memtest. YH -----Original Message----- From: Per Gregers Bilse [mailto:bilse@networksignature.com] Sent: Friday, March 24, 2006 12:44 PM To: Lu, Yinghai Subject: RE: S2881 and linuxbios On Mar 23, 1:56pm yinghai.lu(a)amd.com wrote: > There is linux util under src/util/flashrom. Please use that to update > your BIOS. Thanks, that (and some payload tweaks) got me much further. I now have a kernel panic during booting. Could you possibly take a look at the output below and see if you spot something? I notice that it says the CMOS checksum is wrong, but I don't understand why; I use cmos_utils to write a CMOS image to CMOS before trying to boot with LinuxBIOS, so AFAIK it should have the correct checksum for LinuxBIOS. Thanks, best, -- Per LinuxBIOS-1.1.8_s2881_Normal Fri Mar 24 19:45:27 GMT 2006 starting... (0,1) link=00 (1,0) link=00 02 nodes in icotireal0:i ze d-.-- { APICID = 01 NODEID = 01 COREID = 00} --- SBLink=02 NC node|link=02 ht reset - LinuxBIOS-1.1.8_s2881_Normal Fri Mar 24 19:45:27 GMT 2006 starting... (0,1) link=00 (1,0) link=00 02 nodes i ncoirtei0a:l iz e--d-. { APICID = 01 NODEID = 01 COREID = 00} --- SBLink=02 NC node|link=02 Ram1.00 Ram1.01 Ram2.00 Ram2.01 Ram3 Initializing memory: done Initializing memory: done Ram4 v_esp=000cfd3c cpu_reset = 00000000 Clearing initial memory region: No cache as ram now - Use Ram as Stack now - done new_cpu_reset = 00000000 Copying LinuxBIOS to ram. src=fffa0004 dst=00004000 linxbios_ram.bin length = 000192ac Jumping to LinuxBIOS. LinuxBIOS-1.1.8_s2881_Normal Fri Mar 24 19:45:27 GMT 2006 booting... Enumerating buses... APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.3 siblings=0 CPU: APIC: 00 enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] enabled PCI: 00:19.3 siblings=0 CPU: APIC: 01 enabled PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] enabled PCI: 01:00.0 [1022/7450] enabled PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:00.0 [1022/7460] enabled PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7450] enabled PCI: 01:01.1 [1022/7451] enabled PCI: 01:02.0 [1022/7450] enabled PCI: 01:02.1 [1022/7451] enabled PCI: 01:03.0 [1022/7460] enabled PCI: 01:04.0 [1022/7468] enabled PCI: 01:04.1 [1022/7469] enabled PCI: 01:04.2 [1022/746a] enabled PCI: 01:04.3 [1022/746b] enabled PCI: pci_scan_bus for bus 2 PCI: 02:08.0 [8086/1027] enabled PCI: 02:09.0 [14e4/1648] enabled PCI: 02:09.1 [14e4/1648] enabled Disabling static device: PCI: 02:0a.0 Disabling static device: PCI: 02:0a.1 PCI: pci_scan_bus returning with max=02 PCI: 02: 100MHz PCI-X PCI: 02:08.0 AMD8131 PCI-X tuning PCI: pci_scan_bus for bus 3 PCI: 03:03.0 [14e4/16a7] enabled PCI: pci_scan_bus returning with max=03 PCI: 03: 133MHz PCI-X PCI: 03:03.0 AMD8131 PCI-X tuning PCI: pci_scan_bus for bus 4 PCI: 04:00.0 [1022/7464] enabled PCI: 04:00.1 [1022/7464] enabled PCI: 04:05.0 [1095/3114] enabled PCI: 04:06.0 [1002/4752] enabled PCI: pci_scan_bus returning with max=04 PNP: 002e.0 enabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled smbus: PCI: 01:04.3[0]->I2C: 01:50 enabled smbus: PCI: 01:04.3[0]->I2C: 01:51 enabled smbus: PCI: 01:04.3[0]->I2C: 01:52 enabled smbus: PCI: 01:04.3[0]->I2C: 01:53 enabled smbus: PCI: 01:04.3[0]->I2C: 01:54 enabled smbus: PCI: 01:04.3[0]->I2C: 01:55 enabled smbus: PCI: 01:04.3[0]->I2C: 01:56 enabled smbus: PCI: 01:04.3[0]->I2C: 01:57 enabled smbus: PCI: 01:04.3[0]->I2C: 01:2d enabled smbus: PCI: 01:04.3[0]->I2C: 01:2a enabled smbus: PCI: 01:04.3[0]->I2C: 01:49 enabled smbus: PCI: 01:04.3[0]->I2C: 01:4a enabled PCI: pci_scan_bus returning with max=04 PCI: pci_scan_bus returning with max=04 done Allocating resources... Reading resources... PCI: 01:01.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] bus 2 prefmem PCI: 01:02.0 1c <- [0x00fffff000 - 0x00ffffefff] bus 3 io PCI: 01:02.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] bus 3 prefmem PCI: 01:03.0 24 <- [0x00fff00000 - 0x00ffefffff] bus 4 prefmem Done reading resources. Setting resources... PCI: 00:18.0 1ba <- [0x00fe400000 - 0x00fe3fffff] prefmem <node 0 link 2> PCI: 00:18.0 1c2 <- [0x0000001000 - 0x0000003fff] io <node 0 link 2> PCI: 00:18.0 1b2 <- [0x00fd000000 - 0x00fe3fffff] mem <node 0 link 2> PCI: 01:01.0 1c <- [0x0000001000 - 0x0000001fff] bus 2 io PCI: 01:01.0 20 <- [0x00fe100000 - 0x00fe1fffff] bus 2 mem PCI: 02:08.0 10 <- [0x00fe180000 - 0x00fe19ffff] mem64 PCI: 02:08.0 18 <- [0x00fe100000 - 0x00fe13ffff] mem64 PCI: 02:08.0 20 <- [0x0000001000 - 0x000000103f] io PCI: 02:08.0 30 <- [0x00fe140000 - 0x00fe17ffff] romem PCI: 02:09.0 10 <- [0x00fe1a0000 - 0x00fe1affff] mem64 PCI: 02:09.0 18 <- [0x00fe1b0000 - 0x00fe1bffff] mem64 PCI: 02:09.1 10 <- [0x00fe1c0000 - 0x00fe1cffff] mem64 PCI: 02:09.1 18 <- [0x00fe1d0000 - 0x00fe1dffff] mem64 PCI: 01:01.1 10 <- [0x00fe300000 - 0x00fe300fff] mem64 PCI: 01:02.0 20 <- [0x00fe200000 - 0x00fe2fffff] bus 3 mem PCI: 03:03.0 10 <- [0x00fe200000 - 0x00fe20ffff] mem64 PCI: 01:02.1 10 <- [0x00fe301000 - 0x00fe301fff] mem64 PCI: 01:03.0 1c <- [0x0000002000 - 0x0000002fff] bus 4 io PCI: 01:03.0 20 <- [0x00fd000000 - 0x00fe0fffff] bus 4 mem PCI: 04:00.0 10 <- [0x00fe000000 - 0x00fe000fff] mem PCI: 04:00.1 10 <- [0x00fe001000 - 0x00fe001fff] mem PCI: 04:05.0 10 <- [0x0000002410 - 0x0000002417] io PCI: 04:05.0 14 <- [0x0000002430 - 0x0000002433] io PCI: 04:05.0 18 <- [0x0000002420 - 0x0000002427] io PCI: 04:05.0 1c <- [0x0000002440 - 0x0000002443] io PCI: 04:05.0 20 <- [0x0000002400 - 0x000000240f] io PCI: 04:05.0 24 <- [0x00fe003000 - 0x00fe0033ff] mem PCI: 04:06.0 10 <- [0x00fd000000 - 0x00fdffffff] mem PCI: 04:06.0 14 <- [0x0000002000 - 0x00000020ff] io PCI: 04:06.0 18 <- [0x00fe002000 - 0x00fe002fff] mem PCI: 04:06.0 30 <- [0x00fff80000 - 0x00fff9ffff] romem PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] irq PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] irq PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] io PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] irq PCI: 01:04.1 20 <- [0x0000003420 - 0x000000342f] io PCI: 01:04.2 10 <- [0x0000003400 - 0x000000341f] io PCI: 01:04.3 58 <- [0x0000003000 - 0x00000030ff] io Done setting resources. Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 140 PCI: 01:01.0 bridge ctrl <- 0003 PCI: 01:01.0 cmd <- 147 PCI: 02:08.0 cmd <- 143 PCI: 02:09.0 subsystem <- 10f1/2881 PCI: 02:09.0 cmd <- 142 PCI: 02:09.1 subsystem <- 10f1/2881 PCI: 02:09.1 cmd <- 142 PCI: 01:01.1 subsystem <- 10f1/2881 PCI: 01:01.1 cmd <- 146 PCI: 01:02.0 bridge ctrl <- 0003 PCI: 01:02.0 cmd <- 146 PCI: 03:03.0 cmd <- 142 PCI: 01:02.1 subsystem <- 10f1/2881 PCI: 01:02.1 cmd <- 146 PCI: 01:03.0 bridge ctrl <- 0003 PCI: 01:03.0 cmd <- 147 PCI: 04:00.0 subsystem <- 10f1/2881 PCI: 04:00.0 cmd <- 142 PCI: 04:00.1 subsystem <- 10f1/2881 PCI: 04:00.1 cmd <- 142 PCI: 04:05.0 subsystem <- 10f1/2881 PCI: 04:05.0 cmd <- 143 PCI: 04:06.0 subsystem <- 10f1/2881 PCI: 04:06.0 cmd <- 1c3 PCI: 01:04.0 subsystem <- 10f1/2881 PCI: 01:04.0 cmd <- 14f w83627hf hwm smbus enabled PCI: 01:04.1 subsystem <- 10f1/2881 PCI: 01:04.1 cmd <- 141 PCI: 01:04.2 subsystem <- 10f1/2881 PCI: 01:04.2 cmd <- 141 PCI: 01:04.3 subsystem <- 10f1/2881 PCI: 01:04.3 cmd <- 141 PCI: 00:18.1 subsystem <- 10f1/2881 PCI: 00:18.1 cmd <- 140 PCI: 00:18.2 subsystem <- 10f1/2881 PCI: 00:18.2 cmd <- 140 PCI: 00:18.3 cmd <- 140 PCI: 00:19.0 cmd <- 140 PCI: 00:19.1 cmd <- 140 PCI: 00:19.2 cmd <- 140 PCI: 00:19.3 cmd <- 140 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor AMD device f5a Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled microcode: equivalent processor rev id = 0x004a, patch id = 0x00000000 microcode: patch id that want to apply= 0x00000047 microcode: updated to patch id = 0x00000047 success Setting up local apic... apic_id: 0 done. Clearing memory 1024K - 524288K: ------- done CPU #0 Initialized start_eip=0x00010000 Initializing CPU #1 Waiting for 1 CPUS to stop CPU: vendor AMD device f5a Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled microcode: equivalent processor rev id = 0x004a, patch id = 0x00000000 microcode: patch id that want to apply= 0x00000047 microcode: updated to patch id = 0x00000047 success Setting up local apic... apic_id: 1 done. Clearing memory 524288K - 1048576K: -------- done CPU #1 Initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 01:01.0 init PCI: 02:09.0 init PCI: 02:09.1 init PCI: 01:02.0 init PCI: 01:03.0 init PCI: 04:05.0 init PCI: 04:06.0 init PCI: 01:04.0 init RTC Init RTC: Checksum invalid zeroing cmos enabling HPET @0xfed00000 PNP: 002e.0 init PNP: 002e.2 init PNP: 002e.5 init PNP: 002e.b init PCI: 01:04.1 init IDE1 IDE0 PCI: 01:04.3 init set power on after power fail smbus: PCI: 01:04.3[0]->I2C: 01:2d init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:19.0 init PCI: 00:19.1 init PCI: 00:19.2 init PCI: 00:19.3 init NB: Function 3 Misc Control.. done. PCI: 02:08.0 init PCI: 03:03.0 init Devices initialized Writing IRQ routing tables to 0xf0000...done. Wrote the mp table end at: 00000020 - 000001cc Moving GDT to 0x500...ok Wrote linuxbios table at: 00000530 - 00000ddc checksum 561a Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 33:stream_init() - rom_stream: 0xfff80000 - 0xfff9ffff Found ELF candiate at offset 0 Loading Etherboot version: 5.4.1 Dropping non PT_LOAD segment New segment addr 0x10000 size 0x3e7a0 offset 0x0 filesize 0xb600 (cleaned up) New segment addr 0x10000 size 0x3e7a0 offset 0x0 filesize 0xb600 Loading Segment: addr: 0x000000003ff90000 memsz: 0x0000000000032000 filesz: 0x000000000000b600 Clearing Segment: addr: 0x000000003ff9b600 memsz: 0x0000000000026a00 Loading Segment: addr: 0x0000000000042000 memsz: 0x000000000000c7a0 filesz: 0x0000000000000000 Clearing Segment: addr: 0x0000000000042000 memsz: 0x000000000000c7a0 Jumping to boot code at 0x100b0 CPU 2065 Mhz Etherboot 5.4.1 (GPL) http://etherboot.org Drivers: FILO Images: NBI ELF FreeBSD Multiboot a.out Protocols: DHCP TFTP Relocating _text from: [000101b0,0004e7a0) to [3fec1a10,3ff00000) Scanning PCI: found 25 devices Boot from (N)etwork (D)isk or (Q)uit? Probing pci disk... [FILO]boot eax = 0xc50401ac boot ebx = 0x00800401 boot arg = 0x00000000 FILO version 0.4.1 (bilse@sd3) Fri Mar 24 18:08:56 GMT 2006 Press <Enter> for default boot, or <Esc> for boot prompt... 5 4 3 2 1 timed out boot: hda1:/boot/vmlinuz-2.6.9-1.667smp initrd=/boot/initrd-2.6.9-1.667smp.img pci=noacpi ro root=/dev/hda1 console=ttyS0,19200 found PCI IDE controller 00001022:00007469 prog_if=0x0000008a primary channel: compatibility mode cmd_base=0x000001f0 ctrl_base=0x000003f4 Waiting for ide0 to become ready for reset... ok Testing for hda Probing for hda Init device params... ok hda: LBA: ST320413A Partition 1 start u length u Mounted ext2fs Not a bootable ELF image already open Found Linux version 2.6.9-1.667smp (bhcompile(a)tweety.build.redhat.com) #1 SMP Tue Nov 2 14:59:52 EST 2004 (protocol 0x00000203) (loadflags 0x00000001) bzImage. Setting up paramters at 0x00090000 ramtop=0x000ffc00k ext_mem_k=64512, alt_mem_k=1047552 original command line: "initrd=/boot/initrd-2.6.9-1.667smp.img pci=noacpi ro root=/dev/hda1 console=ttyS0,19200" kernel command line at 0x00091000 initrd=/boot/initrd-2.6.9-1.667smp.img kernel command line (48 bytes): "pci=noacpi ro root=/dev/hda1 console=ttyS0,19200" offset=0x00001600 addr=0x00100000 size=0x0014d2a0 Loading kernel... ok start=0x3fe4d000 end=0x3fec10e1 Loading initrd... ok eip=0x00100000 Jumping to entry point... Linux version 2.6.9-1.667smp (bhcompile(a)tweety.build.redhat.com) (gcc version 3.4.2 20041017 (Red Hat 3.4.2-6.fc3)) #1 SMP Tue Nov 2 14:59:52 EST 2004 BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 0000000000000e44 type 16 BIOS-e820: 0000000000000e44 - 00000000000a0000 (usable) BIOS-e820: 00000000000f0000 - 00000000000f0400 type 16 BIOS-e820: 0000000000100000 - 0000000040000000 (usable) 0MB HIGHMEM available. 1024MB LOWMEM available. found SMP MP-table at 00000010 NX (Execute Disable) protection: active DMI not present. Using APIC driver default ACPI: Unable to locate RSDP Intel MultiProcessor Specification v1.4 Virtual Wire compatibility mode. OEM ID: TYAN Product ID: S2881 APIC at: 0xFEE00000 Processor #0 15:5 APIC version 16 Processor #1 15:5 APIC version 16 I/O APIC #2 Version 17 at 0xFEC00000. I/O APIC #3 Version 17 at 0xFE300000. I/O APIC #4 Version 17 at 0xFE301000. Enabling APIC mode: Flat. Using 3 I/O APICs Processors: 2 Built 1 zonelists Kernel command line: pci=noacpi ro root=/dev/hda1 console=ttyS0,19200 mapped 4G/4G trampoline to fffec000. Initializing CPU#0 CPU 0 irqstacks, hard=023ce000 soft=023ae000 PID hash table entries: 4096 (order: 12, 65536 bytes) Detected 1993.323 MHz processor. Using tsc for high-res timesource Console: colour dummy device 80x25 Dentry cache hash table entries: 262144 (order: 8, 1048576 bytes) Inode-cache hash table entries: 131072 (order: 7, 524288 bytes) Memory: 1033248k/1048576k available (1772k kernel code, 14740k reserved, 736k data, 184k init, 0k highmem) Security Scaffold v1.0.0 initialized SELinux: Initializing. SELinux: Starting in permissive mode There is already a security framework initialized, register_security failed. selinux_register_security: Registering secondary module capability Capability LSM initialized as secondary Mount-cache hash table entries: 512 (order: 0, 4096 bytes) CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) CPU: L2 Cache: 1024K (64 bytes/line) Intel machine check architecture supported. Intel machine check reporting enabled on CPU#0. Enabling fast FPU save and restore... done. Enabling unmasked SIMD FPU exception support... done. Checking 'hlt' instruction... OK. CPU0: AMD 02/05 stepping 0a per-CPU timeslice cutoff: 2925.27 usecs. task migration cache decay timeout: 3 msecs. Booting processor 1/1 eip 3000 CPU 1 irqstacks, hard=023cf000 soft=023af000 Initializing CPU#1 CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) CPU: L2 Cache: 1024K (64 bytes/line) Intel machine check architecture supported. Intel machine check reporting enabled on CPU#1. CPU1: AMD 02/05 stepping 0a Total of 2 processors activated (7897.08 BogoMIPS). ENABLING IO-APIC IRQs ..TIMER: vector=0x31 pin1=2 pin2=0 checking TSC synchronization across 2 CPUs: passed. Brought up 2 CPUs zapping low mappings. checking if image is initramfs... it is Freeing initrd memory: 464k freed NET: Registered protocol family 16 CPU 0: Machine Check Exception: 0000000000000004 Bank 4: f60320018f080813 at 00000000000e0010 Kernel panic - not syncing: CPU context corrupt ## ENDS

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Re: [LinuxBIOS] [Fwd: Hardware Write-Protect for BIOS & EC]
by Wahl, David 24 Mar '06

24 Mar '06

A corrupted ROM has to be followed by a system restore, either manual or automatic, depending on the level of intelligence you want to build into the hardware. I have seen scenarios where restore partition is in an unwritable location and there is a ROM in some safe location whose sole purpose is to restore from the protected partition. thanks, d. -----Original Message----- From: linuxbios-bounces(a)linuxbios.org [mailto:linuxbios-bounces@linuxbios.org] On Behalf Of Ronald G Minnich Sent: Thursday, March 23, 2006 10:38 AM To: Lu, Yinghai Cc: jg(a)laptop.org; LinuxBIOS Subject: Re: [LinuxBIOS] [Fwd: Hardware Write-Protect for BIOS & EC] Lu, Yinghai wrote: > 1. in you suggestion. When you are flash the rom, if sth go wrong > (lose power), you will corrupt your rom. > 2. are you going to use fallback image with normal image? > If so you can disable the write to last 128K ( fallback image part) > via HW jumper. ---- No one could change the fallback image without > remove the jumper. Some MB already have that for last 64k. I think that having a 'you can never write this' bios image would be useful. The power fail scenario is a concern. ron -- linuxbios mailing list linuxbios(a)linuxbios.org http://www.openbios.org/mailman/listinfo/linuxbios

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[LinuxBIOS] [Fwd: Hardware Write-Protect for BIOS & EC]
by Jim Gettys 23 Mar '06

23 Mar '06

OK, here's the proposed solution for write protect of the OLPC BIOS. Short of phishing attacks, I think it should suffice; but I'd like people here to shoot at the scheme in case I'm missing something. Regards, - Jim -- Jim Gettys One Laptop Per Child

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[LinuxBIOS] OLPC Keyboard/System Controller ENE KB3920
by Bari Ari 22 Mar '06

22 Mar '06

Jim, I see from the OLPC Wiki http://wiki.laptop.org/wiki/Hardware_specification that the ENE KB3920 http://www.ene.com.tw/ is to be used for keyboard scan and system management. Are there plans to keep the code for this open as well? Many types of these controllers share memory space with the flash that stores the BIOS. The KB3920 data sheet is not available from the ENE website. Do you know if this device has enough flash, OTP or mask ROM to hold all of it's own code or will it share with the system BIOS? -Bari

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