coreboot

coreboot@coreboot.org

6 participants
39687 discussions

Please could you review the XMP / custom RAM timings patches for AMD ?
by Mike Banon 01 Dec '20

01 Dec '20

Dear friends, These patches are of a critical importance - they help to increase the performance of AMD boards up to 20%. However, despite their small size and simplicity, they are waiting for your review for more than 6 months already. :( And it's sad to see the "unofficial patches" list of csb_patcher.sh growing. Please, could you take a look? https://review.coreboot.org/c/coreboot/+/40488 https://review.coreboot.org/c/coreboot/+/40489 Best regards, Mike Banon

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Accessing extended capabilities PCI registers?
by Rafael Send 01 Dec '20

01 Dec '20

Hi, Breaking this out from my other email for title clarity purposes, hope that's ok. Anyway, I think my issue comes down to coreboot not being able to access (?) PCI extended registers in the current setup. I guess this is a general question: CAN coreboot access the extended capabilities registers of PCI devices? If yes, are there any special options that need to be set or adjusted during the build? I've attached a "pci -i" dump from the EFI shell for my device on stock BIOS vs coreboot - as one can see, the coreboot log ends before outputting any of the extended registers whereas the BIOS log dumps the full config space. Any ideas for what I could try here, or reasons why it might not (be expected to) work? Cheers, R

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Upcoming virtual OSFC 2020
by Philipp Deppenwiese 30 Nov '20

30 Nov '20

Hello people, This is a last reminder on the upcoming OSFC 2020 (www.osfc.io) which will start tomorrow noon CET. If you are interested in attending the conference, please get your tickets via https://hopin.com/events/osfc-2020 Best regards, Philipp

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Feature request: add payload "Tianocore with SeaBIOS CSM"
by Volkert 30 Nov '20

30 Nov '20

Hi! This is my first post in this mailing list. Nice to meet you all. I have a feature request. (I'm not sure if I'm the first to request this, so feel free to direct me to any existing discussions about this topic, if there is one.) Would it be possible to add a payload option "Tianocore with SeaBIOS CSM" in the config menu? Right now, we have to choose between a Tianocore payload and a SeaBIOS payload, or otherwise provide our own manually built payload. It's possible for SeaBIOS to be built as a Compatibility Support Module (CSM) FOR UEFI BIOSes, and Tianocore can be built with the resulting CSM. However, right now people need to first build SeaBIOS as a CSM, then build Tianocore with the CSM and then add it as a custom ELF executable payload during the "make menuconfig" or "make nconfig" stage of the Coreboot build procedure. Those are quite a few extra error-prone manual steps. It would be really helpful if all these manual steps could be skipped by adding this payload option to the existing payload options and doing all the required intermediate building for us. The vendor BIOS that I wish to replace with Coreboot already contains a UEFI with a CSM, and I'd like to preserve that functionality once I switch to Coreboot. I'm sure I'm not the only one who'd like to have the flexibility of being able to boot both modern OSes through UEFI and legacy OSes using the CSM. Since new UEFI hardware will be shipping without CSMs as of 2020, having this in Coreboot by default would make Coreboot even more attractive to people who'd like to add back such legacy compatibility. Thanks for considering this!

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Change wcaps value through cim_verb_data[]
by Andy Pont 27 Nov '20

27 Nov '20

Hello, With the stock BIOS in the board I am working on one of the nodes for the ALC256 CODEC is: Node 0x21 [Pin Complex] wcaps 0x40058d: Stereo Amp-Out Control: name="Headphone Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1 Amp-Out vals: [0x80 0x80] Pincap 0x0001001c: OUT HP EAPD Detect EAPD 0x2: EAPD Pin Default 0x02214020: [Jack] HP Out at Ext Front Conn = 1/8, Color = Green DefAssociation = 0x2, Sequence = 0x0 Pin-ctls: 0xc0: OUT HP Unsolicited: tag=01, enabled=1 Power states: D0 D1 D2 D3 EPSS Power: setting=D0, actual=D0 Connection: 2 0x02 0x03* In the real world we are finding that the detection of headphones being plugged in aren’t being detected and the audio continues to be played through the onboard speakers. Based on experimentation the customer has determined that the alc256-asus-mic quirk in the Linux kernel gets it work properly but I want to fix this issue properly in Coreboot. The only change in the output of /proc/asound/card/codec#0 appears to be: Node 0x21 [Pin Complex] wcaps 0x40058d: Stereo Amp-Out changes to: Node 0x21 [Pin Complex] wcaps 0x03211020: Stereo Amp-Out I’m assuming that this needs me to add some raw 32bit values into cim_verb_data[] as well as the AZALIA_PIN_CFG() definitions that I already have. Based on what I have seen in files such (src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h then I guess this is going to be multiple values that will be of the form 0x021xxxxx. How do I convert the change I need to make to fill in the xxxxx values? -Andy.

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Splashscreens
by Andy Pont 27 Nov '20

27 Nov '20

Hello, Using the VBT route for graphics initialisation and TianoCore as the payload gives two options within .config for splash screen: CONFIG_BOOTSPLASH: This option shows a graphical bootsplash screen. The graphics are loaded from the CBFS file bootsplash.jpg. CONFIG_TIANOCORE_BOOTSPLASH_IMAGE: Select this option if you have a bootsplash image that you would like to be used. If this option is not selected, the default coreboot logo (European Brown Hare) will used. Do I need to define both? What are the requirements for the images in terms of size, colour depth, etc? -Andy.

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One too many I2C busses
by Andy Pont 25 Nov '20

25 Nov '20

Hello all, When I boot my board (Intel Comet Lake based) using Coreboot I have one too many I2C busses compared to the stock AMI BIOS. Using i2cdetect under Ubuntu with the stock BIOS it shows: $ i2cdetect -l i2c-3 unknown i915 gmbus dpc N/A i2c-1 unknown Synopsys DesignWare I2C adapter N/A i2c-6 unknown DPDDC-A N/A i2c-4 unknown i915 gmbus misc N/A i2c-2 unknown i915 gmbus dpb N/A i2c-0 unknown SMBus I801 adapter at efa0 N/A i2c-7 unknown DPDDC-C N/A i2c-5 unknown i915 gmbus dpd N/A When I run the same command having booted using Coreboot then it gives: $ i2cdetect -l i2c-3 unknown i915 gmbus dpb N/A i2c-1 unknown SMBus I801 adapter at efa0 N/A i2c-8 unknown DPDDC-C N/A i2c-6 unknown i915 gmbus dpd N/A i2c-4 unknown i915 gmbus dpc N/A i2c-2 unknown Synopsys DesignWare I2C adapter N/A i2c-0 unknown Synopsys DesignWare I2C adapter N/A i2c-7 unknown DPDDC-A N/A i2c-5 unknown i915 gmbus misc N/A I’m guessing these are controlled by the devices that are configured in the devicetree.cb file. What I have currently that appears to be related to I2C is: register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }” device pci 15.0 on end # I2C #0 device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 device pci 19.0 off end # I2C #4 device pci 19.1 off end # I2C #5 device pci 1f.4 on end # SMBus The definitions of “on” and “off” are based on lspci only reporting PCI devices 15.0 and 1f.4 when Linux is booted using the stock BIOS. -Andy.

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Idiots guide to devicetree.cb
by Andy Pont 25 Nov '20

25 Nov '20

Hello, Is there an idiots guide to the definitions in devicetree.cb? Trying to make sense of the USB and PCIe configuration stuff. -Andy.

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Assembling all the parts needed for display
by Andy Pont 24 Nov '20

24 Nov '20

Hello, I’m trying to find and fit all of the pieces together to get the display running on my custom platform (based on Intel Comet Lake). Here are the known facts... 1. The LCD including the backlight enable and PWM signals are all connected to the eDP interface on the SoC. 2. When I booted the board using the regular AMI BIOS lspci reported: 00:02.0 VGA compatible controller [0300]: Intel Corporation Device [8086:9bca] (rev 04) (prog-if 00 [VGA controller]) DeviceName: Onboard - Video Subsystem: Device [1e50:800b] 3. I have managed to extract a VGA BIOS from the AMI BIOS file but the PCIR structure lists Vendor ID: 0x8086, Device ID: 0x0406 4. I have also managed to extract a VBT binary from the AMI BIOS file and have included it in the Coreboot image: In the debug output when booting there are some VGA related messages: POST: 0x73 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device POST: 0x75 PCI: 00:02.0 init FMAP: area COREBOOT found @ 490200 (11992576 bytes) CBFS: Locating 'vbt.bin' CBFS: 'vbt.bin' not found. FMAP: area COREBOOT found @ 490200 (11992576 bytes) CBFS: Locating 'pci8086,9b41.rom' CBFS: 'pci8086,9b41.rom' not found. PCI Option ROM loading disabled for PCI: 00:02.0 GMA: locate_vbt_vbios: c3e1 d591 6a 52 5f GMA: VBT couldn't be found Questions… 1. Why is the debug output claiming there is no vbt.bin file when it is lised in the output at the end of the built (Size 1168 LZMA, 4608 decompressed)? 2. Why is it searching for pci8086,9b41.rom? I haven’t defined this and the only reference I can see is in the system76/lemp9/Kconfig file? 3. Why doesn’t the VGA BIOS that I have extracted from the AMI BIOS file match the PCI VID/DID of the VGA controller? 4. What else am I missing in order to get the screen to light up? -Andy.

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Coreboot computer doesn't boot with 2 CPU
by d.verdi 24 Nov '20

24 Nov '20

Hi to all, I had this problem: when I start the computer with 1 cpu (opteron 6282se) everything is fine, if I add the second CPU, the computer doesn't boot, did you have any suggestions? I put only 2 rams module, following the Asus kgpe d16 manual, is that the correct order (one in the first and one in the last orange socket)? Thank you very much Dave

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