Hi, Breaking this out from my other email for title clarity purposes, hope that's ok.
Anyway, I think my issue comes down to coreboot not being able to access (?) PCI extended registers in the current setup.
I guess this is a general question: CAN coreboot access the extended capabilities registers of PCI devices? If yes, are there any special options that need to be set or adjusted during the build?
I've attached a "pci -i" dump from the EFI shell for my device on stock BIOS vs coreboot - as one can see, the coreboot log ends before outputting any of the extended registers whereas the BIOS log dumps the full config space.
Any ideas for what I could try here, or reasons why it might not (be expected to) work?
Cheers, R
Hi,
On 25. 11. 20 20:26, Rafael Send wrote:
Any ideas for what I could try here, or reasons why it might not (be expected to) work?
The extended PCI configuration space access requires a special memory region (up 256MiB) which translate accesses to the PCI configuration cycles. It is exported via ACPI table MMCONFIG. Each 4K basically is one PCI/PCIe device first is bus 0, device 0, fn 0 second is fn 1 etc etc.
So, this information about this special area has to be somehow available to your EFI shell. Sorry I don't know how this works I could only give you this general overview.
Some chipsets also support backdoor access to the extended PCIe config space, by utilizing the reserved bits in the 0xcf8 access I/O port to address the extra offsets. This is non-standard chipset dependent feature which is usually even off.
Thanks, Rudolf
Hi, Thanks for the information - it's more than I've had before.
Maybe someone else can shed more light on the exact workings, but in the meantime I'll take a look at MMCONFIG.
Cheers, Rafael
On Fri, Nov 27, 2020 at 10:45 AM Rudolf Marek r.marek@assembler.cz wrote:
Hi,
On 25. 11. 20 20:26, Rafael Send wrote:
Any ideas for what I could try here, or reasons why it might not (be
expected to) work?
The extended PCI configuration space access requires a special memory region (up 256MiB) which translate accesses to the PCI configuration cycles. It is exported via ACPI table MMCONFIG. Each 4K basically is one PCI/PCIe device first is bus 0, device 0, fn 0 second is fn 1 etc etc.
So, this information about this special area has to be somehow available to your EFI shell. Sorry I don't know how this works I could only give you this general overview.
Some chipsets also support backdoor access to the extended PCIe config space, by utilizing the reserved bits in the 0xcf8 access I/O port to address the extra offsets. This is non-standard chipset dependent feature which is usually even off.
Thanks, Rudolf
-
Rafael Send -
Rudolf Marek