Hello,
I’m trying to find and fit all of the pieces together to get the display running on my custom platform (based on Intel Comet Lake). Here are the known facts...
1. The LCD including the backlight enable and PWM signals are all connected to the eDP interface on the SoC.
2. When I booted the board using the regular AMI BIOS lspci reported: 00:02.0 VGA compatible controller [0300]: Intel Corporation Device [8086:9bca] (rev 04) (prog-if 00 [VGA controller]) DeviceName: Onboard - Video Subsystem: Device [1e50:800b]
3. I have managed to extract a VGA BIOS from the AMI BIOS file but the PCIR structure lists Vendor ID: 0x8086, Device ID: 0x0406
4. I have also managed to extract a VBT binary from the AMI BIOS file and have included it in the Coreboot image:
In the debug output when booting there are some VGA related messages:
POST: 0x73 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
POST: 0x75 PCI: 00:02.0 init FMAP: area COREBOOT found @ 490200 (11992576 bytes) CBFS: Locating 'vbt.bin' CBFS: 'vbt.bin' not found. FMAP: area COREBOOT found @ 490200 (11992576 bytes) CBFS: Locating 'pci8086,9b41.rom' CBFS: 'pci8086,9b41.rom' not found. PCI Option ROM loading disabled for PCI: 00:02.0 GMA: locate_vbt_vbios: c3e1 d591 6a 52 5f GMA: VBT couldn't be found
Questions…
1. Why is the debug output claiming there is no vbt.bin file when it is lised in the output at the end of the built (Size 1168 LZMA, 4608 decompressed)?
2. Why is it searching for pci8086,9b41.rom? I haven’t defined this and the only reference I can see is in the system76/lemp9/Kconfig file?
3. Why doesn’t the VGA BIOS that I have extracted from the AMI BIOS file match the PCI VID/DID of the VGA controller?
4. What else am I missing in order to get the screen to light up?
-Andy.
1. Can you provide complete dump of cbfs content which is displayed at end of make.
2. Check menuconfig or open .config in your favorite editor & check there for file name.
3. This link might be of help: https://www.coreboot.org/SeaBIOS#Adding_a_VGA_option_ROM & https://www.coreboot.org/VGA_support#How_to_retrieve_a_good_video_bios
4. You need not add both vbios & vbt. Either go with vbios or with vbt. If you plan to use Seabios as payload then vgabios should be fine. And let SeaBios run VGA bios to init display. Refer link above on how to add them.
If you intend to go with vbt.bin then check if extracted vbt.bin is correct or not by comparing it with https://github.com/intel/FSP/blob/master/CometLakeFspBinPkg/CometLakeV/Sampl...
Also you mentioned about custom board, check if PWM signal from SoC is properly connected to eDP connector(This depends on panel), If you have Oscilloscope, then check for PWM signal. It should be high or wave with some duty cycle. This starts only after proper display init. Also check VR's related to eDP backlight are able to turn on & provide right power to LED backlight.
Regards, Naresh Solanki
On Mon, Nov 23, 2020 at 8:55 PM Andy Pont andy.pont@sdcsystems.com wrote:
Hello,
I’m trying to find and fit all of the pieces together to get the display running on my custom platform (based on Intel Comet Lake). Here are the known facts...
- The LCD including the backlight enable and PWM signals are all
connected to the eDP interface on the SoC.
- When I booted the board using the regular AMI BIOS lspci reported: 00:02.0 VGA compatible controller [0300]: Intel Corporation Device
[8086:9bca] (rev 04) (prog-if 00 [VGA controller]) DeviceName: Onboard - Video Subsystem: Device [1e50:800b]
- I have managed to extract a VGA BIOS from the AMI BIOS file but the
PCIR structure lists Vendor ID: 0x8086, Device ID: 0x0406
- I have also managed to extract a VBT binary from the AMI BIOS file
and have included it in the Coreboot image:
In the debug output when booting there are some VGA related messages:
POST: 0x73 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
POST: 0x75 PCI: 00:02.0 init FMAP: area COREBOOT found @ 490200 (11992576 bytes) CBFS: Locating 'vbt.bin' CBFS: 'vbt.bin' not found. FMAP: area COREBOOT found @ 490200 (11992576 bytes) CBFS: Locating 'pci8086,9b41.rom' CBFS: 'pci8086,9b41.rom' not found. PCI Option ROM loading disabled for PCI: 00:02.0 GMA: locate_vbt_vbios: c3e1 d591 6a 52 5f GMA: VBT couldn't be found
Questions…
- Why is the debug output claiming there is no vbt.bin file when it is
lised in the output at the end of the built (Size 1168 LZMA, 4608 decompressed)?
- Why is it searching for pci8086,9b41.rom? I haven’t defined this and
the only reference I can see is in the system76/lemp9/Kconfig file?
- Why doesn’t the VGA BIOS that I have extracted from the AMI BIOS file
match the PCI VID/DID of the VGA controller?
- What else am I missing in order to get the screen to light up?
-Andy.
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Naresh wrote…
- Can you provide complete dump of cbfs content which is displayed at
end of make.
FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 41108 none cpu_microcode_blob.bin 0xa180 microcode 191488 none fallback/ramstage 0x38e00 stage 94587 none vgaroms/seavgabios.bin 0x4ffc0 raw 28160 none config 0x56e40 raw 226 none revision 0x56f80 raw 680 none spd.bin 0x57280 spd 1536 none fallback/dsdt.aml 0x578c0 raw 8596 none payload_revision 0x59ac0 raw 237 none (empty) 0x59c00 null 408 none fspm.bin 0x59dc0 fsp 581632 none vbt.bin 0xe7e00 raw 1168 LZMA (4608 decompressed) payload_config 0xe8300 raw 1760 none (empty) 0xe8a40 null 856 none fsps.bin 0xe8dc0 fsp 189109 LZMA (212992 decompressed) fallback/postcar 0x1170c0 stage 18352 none fallback/payload 0x11b8c0 simple elf 68746 none (empty) 0x12c5c0 null 10713048 none bootblock 0xb63dc0 bootblock 49152 none
- Check menuconfig or open .config in your favorite editor & check
there for file name.
I can’t see anything in the .config file that references pci8086,9b41.rom - however see below...
- This link might be of help:
https://www.coreboot.org/SeaBIOS#Adding_a_VGA_option_ROM & https://www.coreboot.org/VGA_support#How_to_retrieve_a_good_video_bios
I used the information in the “UEFI Method” section of that page to extract the VGA BIOS that I have.
- You need not add both vbios & vbt.
Either go with vbios or with vbt. If you plan to use Seabios as payload then vgabios should be fine. And let SeaBios run VGA bios to init display. Refer link above on how to add them.
If you intend to go with vbt.bin then check if extracted vbt.bin is correct or not by comparing it with https://github.com/intel/FSP/blob/master/CometLakeFspBinPkg/CometLakeV/Sampl...
I can’t guarantee that SeaBIOS will be the final payload - the end customer hasn’t specified yet. It is likely that it will need to be UEFI compatible so could end up being TianoCore. On that basis, I think I need to go down the vbt.bin file route. The vbt.bin file that I have extracted is almost identical to the one in the repo you reference. There are some bytes that are different which I assume are the timing specific information for the panel in this laptop.
Also you mentioned about custom board, check if PWM signal from SoC is properly connected to eDP connector(This depends on panel),
According to the schematics, the eDP_BKLTEN and eDP_BKLTCTL signals from the SoC go to the eDP connector (give or take the usual passives along the way) and the eDP_VDDEN signal from the SoC is used to turn on the 3.3V supply to the LCD.
If you have Oscilloscope, then check for PWM signal. It should be high or wave with some duty cycle. This starts only after proper display init. Also check VR's related to eDP backlight are able to turn on & provide right power to LED backlight.
Will have a probe around and see if I can see what is going on.
-Andy.
Cbfs dump clearly shows presence of vbt.bin in COREBOOT region. It's strange that during runtime it was not able to detect the same. I guess you need to focus around here. Can you enable cbfs specific debug messages(CONFIG_DEBUG_CBFS) and provide/check logs?
If vbt.bin is located and passed to fsps.bin then display should init. Then you can check hw signals if needed.
Regards, Naresh
On Mon, 23 Nov, 2020, 10:27 pm Andy Pont, andy.pont@sdcsystems.com wrote:
Naresh wrote…
- Can you provide complete dump of cbfs content which is displayed at end
of make.
FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 41108 none cpu_microcode_blob.bin 0xa180 microcode 191488 none fallback/ramstage 0x38e00 stage 94587 none vgaroms/seavgabios.bin 0x4ffc0 raw 28160 none config 0x56e40 raw 226 none revision 0x56f80 raw 680 none spd.bin 0x57280 spd 1536 none fallback/dsdt.aml 0x578c0 raw 8596 none payload_revision 0x59ac0 raw 237 none (empty) 0x59c00 null 408 none fspm.bin 0x59dc0 fsp 581632 none vbt.bin 0xe7e00 raw 1168 LZMA (4608 decompressed) payload_config 0xe8300 raw 1760 none (empty) 0xe8a40 null 856 none fsps.bin 0xe8dc0 fsp 189109 LZMA (212992 decompressed) fallback/postcar 0x1170c0 stage 18352 none fallback/payload 0x11b8c0 simple elf 68746 none (empty) 0x12c5c0 null 10713048 none bootblock 0xb63dc0 bootblock 49152 none
- Check menuconfig or open .config in your favorite editor & check there
for file name.
I can’t see anything in the .config file that references pci8086,9b41.rom
- however see below...
- This link might be of help:
https://www.coreboot.org/SeaBIOS#Adding_a_VGA_option_ROM & https://www.coreboot.org/VGA_support#How_to_retrieve_a_good_video_bios
I used the information in the “UEFI Method” section of that page to extract the VGA BIOS that I have.
- You need not add both vbios & vbt.
Either go with vbios or with vbt. If you plan to use Seabios as payload then vgabios should be fine. And let SeaBios run VGA bios to init display. Refer link above on how to add them.
If you intend to go with vbt.bin then check if extracted vbt.bin is correct or not by comparing it with https://github.com/intel/FSP/blob/master/CometLakeFspBinPkg/CometLakeV/Sampl...
I can’t guarantee that SeaBIOS will be the final payload - the end customer hasn’t specified yet. It is likely that it will need to be UEFI compatible so could end up being TianoCore. On that basis, I think I need to go down the vbt.bin file route. The vbt.bin file that I have extracted is almost identical to the one in the repo you reference. There are some bytes that are different which I assume are the timing specific information for the panel in this laptop.
Also you mentioned about custom board, check if PWM signal from SoC is properly connected to eDP connector(This depends on panel),
According to the schematics, the eDP_BKLTEN and eDP_BKLTCTL signals from the SoC go to the eDP connector (give or take the usual passives along the way) and the eDP_VDDEN signal from the SoC is used to turn on the 3.3V supply to the LCD.
If you have Oscilloscope, then check for PWM signal. It should be high or wave with some duty cycle. This starts only after proper display init. Also check VR's related to eDP backlight are able to turn on & provide right power to LED backlight.
Will have a probe around and see if I can see what is going on.
-Andy.
Naresh wrote…
Cbfs dump clearly shows presence of vbt.bin in COREBOOT region. It's strange that during runtime it was not able to detect the same. I guess you need to focus around here. Can you enable cbfs specific debug messages(CONFIG_DEBUG_CBFS) and provide/check logs?
If vbt.bin is located and passed to fsps.bin then display should init. Then you can check hw signals if needed.
I think my external programmer has been lying to me when it said it had been reprogramming the flash. I only discovered this when I tried to program Coreboot with a TianoCore payload and was still seeing debug messages from SeaBIOS.
Having actually reprogrammed the board properly I now have a working display and with TianoCore as a payload Ubuntu is loading from the NVMe SSD!
Just need to work through and see what is still broken.
Thanks again for your help.
-Andy.
-
Andy Pont -
Naresh G. Solanki