coreboot

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39687 discussions

Information about "HP-Compaq 8200 Elite SFF"
by dac9＠emailportal.ch 15 Nov '20

15 Nov '20

Hi guys Thanks a lot for the great work on coreboot. I'm looking for install coreboot on my "HP-Compaq 8200 Elite SFF", so I was happy to found your site: https://doc.coreboot.org/mainboard/hp/compaq_8200_sff.html In this documentation stands: "Internal programming: The SPI flash can be accessed using flashrom.". So I tried to read the factory-BIOS with flashrom but without success. Please consult the annexed log-file. Could you please explain-me why reading with the internal-programmer doesn't work for me? Thanks in advance Best regards Dario

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Including a video BIOS
by Andy Pont 12 Nov '20

12 Nov '20

Hello, Using the instructions in the old Wiki page [1] I have used the UEFI method and UEFI tool to extract the video BIOS from the standard binary that comes with the board. I have followed the layout of some of the other Kconfig files in the mainboard directory and added the following to my boards Kconfig: config BOARD_SPECIFIC_OPTIONS ... select VGA_BIOS ... config VGA_BIOS_ID string default "8086,0406" config VGA_BIOS_FILE string default "pci8086,0406.rom" When I try to build with that I get an error: make: *** No rule to make target 'pci8086,0406.rom', needed by 'build/coreboot.pre'. Stop. The other mainboards that use this methodology all seem to have “select GFX_GMA_PANEL_1_ON_LVDS” but as my display is connected directly to the eDP port I added “select GFX_GMA_PANEL_1_ON_EDP”. This in turn appears to need “select GFX_GMA”. Now when I try to build I get: warning: (BOARD_SPECIFIC_OPTIONS) selects GFX_GMA which has unmet direct dependencies ((NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X || NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE) && (MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID)) The board I am working with uses Comet Lake so I have "select SOC_INTEL_COMETLAKE” in the board specific options. Am I going about this the wrong way or does the depends on list for GFX_GMA in src/drivers/intel/gma/Kconfig need SOC_INTEL_COMETLAKE adding to the list? -Andy. [1] - https://www.coreboot.org/VGA_support

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ALC256 datasheet
by Andy Pont 12 Nov '20

12 Nov '20

Hello all, A bit of a long shot… does anyone have a datasheet for the ALC256 HDA audio CODEC? I know that the device exists as I have some boards with it on (that I am working on a Coreboot port for) on my desk but a look on the Realtek website doesn’t yield anything. Thanks, -Andy.

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Flashing coreboot and Intel Flash Descriptor Erase Issue
by Balaji Sivakumar 11 Nov '20

11 Nov '20

Hello Everyone, We are using SPI flash(Macronix) to program the BIOS. And we use an external programmer to flash the BIOS (coreboot including FD+ME) into SPI Flash (16384 kB, SPI), it works fine and boots well. The board is functional and we have successfully booted a kernel on it. Am working on adding a feature to upgrading the BIOS (complete IFD+ME+Coreboot) using intel-spi driver at the OS level. Able to successfully take the backup full 16MB spi nor flash data which includes IFD+ME+BIOS using flashrom Internal Programmer option and it is identified as Opaque flash chip and using dd command as well. But we are seeing the erase fail through both flashrom and flash_erase utility. I believe it fails to erase at the flash descriptor location. As far as Read/Write access to the SPI regions, I have enabled the Host CPU BIOS write access and ME Master Access as 0xFFFF through Intel FIT Tool but still not able to erase it and it fails. Is there anything that could be preventing to enable read/write access to the Intel flash descriptor or any SOC SPI controller protection to access the Flash descriptor? Any pointers would be appreciated. Thanks Balaji

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Deprecating spurious PCI bus master enabling (was Re: Planning the next coreboot release)
by Nico Huber 10 Nov '20

10 Nov '20

Hi, On 04.11.20 23:21, Angel Pons wrote: > 3. Please take a look at the preliminary release notes in > Documentation/releases/coreboot-4.13-relnotes.md and add whatever > happened since 4.12 that is worth mentioning. If unsure, simply push a > change to Gerrit and have your fellow developers discuss it. I have a candidate for a deprecation warning: We're currently working to make all not (clearly) necessary PCI bus master enabling optional. The added Kconfig option still defaults to `y` [1], for compatibility reasons. This has security implications and hence I propose to proceed as follows: After the follow-up (spring) release, * remove the option and the code using it, or at least * reduce its usage to a minimum and change the default to `n`. This should give people enough time to test (with the option disabled) and potentially fix their payloads (and OS?). If there are no concerns, I'll add that to the release notes. There are cases where enabling PCI bus mastering already in coreboot might be necessary. For instance, Intel documents for their integrated graphics to enable it before the initialization sequence (without tel- ling us why and tests show that it ignores the bit anyway *shrug*). And also cases where it's clearly necessary, e.g. before hiding a PCI devices configuration space to put it into ACPI mode (if the OS is not aware of the device' PCI nature, it can't know that bus mastering needs to be enabled). If anybody knows or discovers more cases where it needs to be enabled in advance by coreboot, please mention it here. Nico [1] https://review.coreboot.org/c/coreboot/+/42459

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Flashing coreboot and Intel Flash Descriptor Erase Issue
by Balaji Sivakumar 10 Nov '20

10 Nov '20

We are using SPI flash(Macronix) to program the BIOS. And we use an external programmer to flash the BIOS (coreboot including FD+ME) into SPI Flash (16384 kB, SPI), it works fine and boots well. The board is functional and we have successfully booted a kernel on it. Am working on adding a feature to upgrading the BIOS (complete IFD+ME+Coreboot) using intel-spi driver at the OS level. Able to successfully take the backup full 16MB spi nor flash data which includes IFD+ME+BIOS using flashrom Internal Programmer option and it is identified as Opaque flash chip and using dd command as well. But we are seeing the erase fail through both flashrom and flash_erase utility. I believe it fails to erase at the flash descriptor location. As far as Read/Write access to the SPI regions, I have enabled the Host CPU BIOS write access and ME Master Access as 0xFFFF through Intel FIT Tool but still not able to erase it and it fails. Is there anything that could be preventing to enable read/write access to the Intel flash descriptor or any SOC SPI controller protection to access the Flash descriptor? -- Thanks, Balaji

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Is HP ProLiant DL360e Gen8 supported in Coreboot?
by jjs8＠gmx.com 09 Nov '20

09 Nov '20

Hello! I'm trying to find if my hardware supports Coreboot. I found 1 table which is retired, second that is probably not retired and then current documentation that doesn't seem to say as much. So, sorry if I missed it. Will Coreboot work with HP ProLiant DL360e Gen8? Flashrom worked ok but not great. Northbridge is Intel Sandy Bridge-E 07, Southbridge Intel X79 05. References: https://www.coreboot.org/Supported_Chipsets_and_Devices https://coreboot.org/status/board-status.html https://support.hpe.com/hpesc/public/docDisplay?docId=c03361169&docLocale=e… https://browser.geekbench.com/geekbench3/1879558 https://doc.coreboot.org/mainboard/index.html https://doc.coreboot.org/northbridge/intel/sandybridge/index.html Flashrom log: ------------------------ flashrom v1.2 on Linux 5.4.0-42-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found chipset "Intel C60x/X79". Enabling flash write... FREG0: Flash Descriptor region (0x00000000-0x0000ffff) is read-only. FREG2: Management Engine region (0x00010000-0x001fffff) is locked. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see https://flashrom.org/ME for details. At least some flash regions are read protected. You have to use a flash layout and include only accessible regions. For write operations, you'll additionally need the --noverify-all switch. See manpage for more details. OK. Found Macronix flash chip "MX25L1605" (2048 kB, SPI) mapped at physical address 0x00000000ffe00000. Found Macronix flash chip "MX25L1605A/MX25L1606E/MX25L1608E" (2048 kB, SPI) mapped at physical address 0x00000000ffe00000. Found Macronix flash chip "MX25L1605D/MX25L1608D/MX25L1673E" (2048 kB, SPI) mapped at physical address 0x00000000ffe00000. Multiple flash chip definitions match the detected chip(s): "MX25L1605", "MX25L1605A/MX25L1606E/MX25L1608E", "MX25L1605D/MX25L1608D/MX25L1673E" Please specify which chip definition to use with the -c <chipname> option. ------------------------

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AMD AGESA: Missing PCI bridge 00:15.2 on Asus F2A85-M PRO
by Paul Menzel 08 Nov '20

08 Nov '20

Dear coreboot folks, Trying to finish the Asus F2A85-M PRO coreboot port (AMD Family 15h/Hudson), the internal network device does not work with the state from [1]. With the vendor firmware 6601, it is 04:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] (rev 09) behind PCI bridge 00:15.2. > -[0000:00]-+-00.0 > +-00.2 > +-01.0 > +-01.1 > +-10.0 > +-10.1 > +-11.0 > +-12.0 > +-12.2 > +-13.0 > +-13.2 > +-14.0 > +-14.2 > +-14.3 > +-14.4-[01]-- > +-15.0-[02]-- > +-15.1-[03]----00.0 > +-15.2-[04]----00.0 > +-18.0 > +-18.1 > +-18.2 > +-18.3 > +-18.4 > \-18.5 In the current state [1], coreboot says device 00:15.2 is disabled > Show all devs... After init. > Root Device: enabled 1 > CPU_CLUSTER: 0: enabled 1 > DOMAIN: 0000: enabled 1 > APIC: 10: enabled 1 > PCI: 00:00.0: enabled 1 > PCI: 00:00.2: enabled 1 > PCI: 00:01.0: enabled 1 > PCI: 00:01.1: enabled 1 > PCI: 00:02.0: enabled 0 > PCI: 00:03.0: enabled 0 > PCI: 00:04.0: enabled 0 > PCI: 00:05.0: enabled 0 > PCI: 00:06.0: enabled 0 > PCI: 00:07.0: enabled 0 > PCI: 00:08.0: enabled 0 > PCI: 00:10.0: enabled 1 > PCI: 00:10.1: enabled 1 > PCI: 00:11.0: enabled 1 > PCI: 00:12.0: enabled 1 > PCI: 00:12.2: enabled 1 > PCI: 00:13.0: enabled 1 > PCI: 00:13.2: enabled 1 > PCI: 00:14.0: enabled 1 > PCI: 00:14.1: enabled 0 > PCI: 00:14.2: enabled 1 > PCI: 00:14.3: enabled 1 > PCI: 00:14.4: enabled 1 > PCI: 00:14.7: enabled 0 > PCI: 00:15.0: enabled 1 > PCI: 00:15.1: enabled 1 > PCI: 00:15.2: enabled 0 > PCI: 00:18.0: enabled 1 But it is enabled in the devicetree `src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb`. device pci 15.2 on end # PCI bridge Please find the spew log attached. Any help is appreciated. Kind regards, Paul [1]: https://review.coreboot.org/c/coreboot/+/46021/ "mb/asus/f2a85-m_pro: Enable super-i/o LDNs 0x0f and 0x14"

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Native RAM init
by Alif Ilhan 06 Nov '20

06 Nov '20

hello, Is there a way to extract mrc.bin from a normal(not chromehook rom) bios binary from the flash dump? There's no chromebook available with the Atom N2600 chip. There is one with Atom N570, but will it work? If not then I want to know if native ram init is supported in CedarTrail chipsets. I think it should be because Sandy bridge is supported and they were simillar(I think). CedarTail has no FSPs available on github so I must have to build the non-FPS version.....which means I cannot get mrc.bin.

2 1

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 06 Nov '20

06 Nov '20

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 2 new defect(s) introduced to coreboot found with Coverity Scan. 91 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 1436157: Memory - illegal accesses (OVERRUN) /src/lib/fw_config.c: 86 in fw_config_get_found() ________________________________________________________________________________________________________ *** CID 1436157: Memory - illegal accesses (OVERRUN) /src/lib/fw_config.c: 86 in fw_config_get_found() 80 return __ffs64(mask); 81 } 82 83 const struct fw_config *fw_config_get_found(uint64_t field_mask) 84 { 85 const struct fw_config *config; >>> CID 1436157: Memory - illegal accesses (OVERRUN) >>> Overrunning array "cached_configs" of 64 4-byte elements at element index 4294967295 (byte offset 17179869183) using index "probe_index(field_mask)" (which evaluates to 4294967295). 86 config = cached_configs[probe_index(field_mask)]; 87 if (config && config->mask == field_mask) 88 return config; 89 90 return NULL; 91 } ** CID 1436156: Memory - corruptions (OVERRUN) /src/lib/fw_config.c: 116 in fw_config_init() ________________________________________________________________________________________________________ *** CID 1436156: Memory - corruptions (OVERRUN) /src/lib/fw_config.c: 116 in fw_config_init() 110 if (!dev->probe_list) 111 continue; 112 113 for (probe = dev->probe_list; probe && probe->mask != 0; probe++) { 114 if (fw_config_probe(probe)) { 115 match = true; >>> CID 1436156: Memory - corruptions (OVERRUN) >>> Overrunning array "cached_configs" of 64 4-byte elements at element index 4294967295 (byte offset 17179869183) using index "probe_index(probe->mask)" (which evaluates to 4294967295). 116 cached_configs[probe_index(probe->mask)] = probe; 117 break; 118 } 119 } 120 121 if (!match) { ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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