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Patch merged into coreboot/master: d0cf472 Fix the blank in acpi_tables.c
by gerrit＠coreboot.org 18 Apr '12

18 Apr '12

the following patch was just integrated into master: commit d0cf472c8f7aaebda3706d5e7ff03440437b749d Author: zbao <fishbaozi(a)gmail.com> Date: Wed Apr 18 11:28:07 2012 +0800 Fix the blank in acpi_tables.c Change-Id: I65d50616e49802b7bb13f02369c4898fa4a238a4 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Wed Apr 18 13:05:28 2012, giving +2 See … [View More]

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Patch set updated for coreboot: 060fba7 S3: Use old heap during normal boot
by Zheng Bao 18 Apr '12

18 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/904 -gerrit commit 060fba770b8e067defb91ed7ba266fced87e438a Author: zbao <fishbaozi(a)gmail.com> Date: Wed Apr 18 16:59:53 2012 +0800 S3: Use old heap during normal boot During normal boot, the cbmem is uninitialized. So it is illegal to find the heap in cbmem. Change-Id: I8b5e1dbf1124819ed91693a86a6dbe41aea109e5 Signed-off-by: Zheng … [View More]

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Patch set updated for coreboot: c076afd s3: Use old heap during normal boot
by Zheng Bao 17 Apr '12

17 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/904 -gerrit commit c076afd137fda12ace65ada0b3dd95c14ea88a1e Author: zbao <fishbaozi(a)gmail.com> Date: Wed Apr 18 12:56:09 2012 +0800 s3: Use old heap during normal boot During normal boot, the cbmem is uninitialized. So it is illegal to find the heap in cbmem. Change-Id: I8b5e1dbf1124819ed91693a86a6dbe41aea109e5 Signed-off-by: Zheng … [View More]

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New patch to review for coreboot: 0e51575 s3: Use old heap during normal boot During normal boot, the cbmem is uninitialized. So it is illegal to find the heap in cbmem.
by Zheng Bao 17 Apr '12

17 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/904 -gerrit commit 0e51575316977452449f4353d94b5244770990f0 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Apr 18 12:54:20 2012 +0800 s3: Use old heap during normal boot During normal boot, the cbmem is uninitialized. So it is illegal to find the heap in cbmem. Change-Id: I8b5e1dbf1124819ed91693a86a6dbe41aea109e5 Signed-off-by: Zheng Bao &… [View More]

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Patch set updated for coreboot: a99159b Leverage the Pstate table created by AGESA.
by Zheng Bao 17 Apr '12

17 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/884 -gerrit commit a99159bd88b984957714dc8f123a8126b5e9404a Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 12 11:27:26 2012 +0800 Leverage the Pstate table created by AGESA. The name of processor created by AGESA is P00n, whose P is BLDCFG_PROCESSOR_SCOPE_NAME(is 'C' if it is undefined.) and n starts from 0. The dsdt should be aligned with … [View More]that. This feature has only been tested on persimmon. The changes on all the other boards were propagated. Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/dinar/acpi/cpstate.asl | 74 -------------- src/mainboard/amd/dinar/acpi_tables.c | 8 +- src/mainboard/amd/dinar/dsdt.asl | 48 +++++++--- src/mainboard/amd/inagua/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/inagua/acpi_tables.c | 8 +- src/mainboard/amd/inagua/dsdt.asl | 24 ++++- src/mainboard/amd/persimmon/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/persimmon/acpi_tables.c | 8 +- src/mainboard/amd/persimmon/dsdt.asl | 24 ++++- src/mainboard/amd/south_station/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/south_station/acpi_tables.c | 12 +- src/mainboard/amd/south_station/dsdt.asl | 24 ++++- src/mainboard/amd/torpedo/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/torpedo/dsdt.asl | 18 ++-- src/mainboard/amd/union_station/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/union_station/acpi_tables.c | 12 +- src/mainboard/amd/union_station/dsdt.asl | 24 ++++- src/mainboard/asrock/e350m1/acpi/cpstate.asl | 75 -------------- src/mainboard/asrock/e350m1/acpi_tables.c | 12 +- src/mainboard/asrock/e350m1/dsdt.asl | 24 ++++- src/mainboard/supermicro/h8qgi/acpi/cpstate.asl | 75 -------------- src/mainboard/supermicro/h8qgi/acpi_tables.c | 8 +- src/mainboard/supermicro/h8qgi/dsdt.asl | 115 +++++++++++----------- 23 files changed, 222 insertions(+), 746 deletions(-) diff --git a/src/mainboard/amd/dinar/acpi/cpstate.asl b/src/mainboard/amd/dinar/acpi/cpstate.asl deleted file mode 100644 index 64b3f16..0000000 --- a/src/mainboard/amd/dinar/acpi/cpstate.asl +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index 1b80b18..a6382fe 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -297,7 +297,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -305,11 +306,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); } else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl index 1cbb05e..501ec78 100644 --- a/src/mainboard/amd/dinar/dsdt.asl +++ b/src/mainboard/amd/dinar/dsdt.asl @@ -51,37 +51,61 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x0 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU2, /* name space name */ + C002, /* name space name */ 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU3, /* name space name */ + C003, /* name space name */ 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } + Processor( + C004, /* name space name */ + 4, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C005, /* name space name */ + 5, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C006, /* name space name */ + 6, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C007, /* name space name */ + 7, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } } /* End _PR scope */ /* PIC IRQ mapping registers, C00h-C01h. */ diff --git a/src/mainboard/amd/inagua/acpi/cpstate.asl b/src/mainboard/amd/inagua/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/inagua/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 6c1acc8..923d0bf 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -264,7 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -273,12 +274,9 @@ unsigned long write_acpi_tables(unsigned long start) ssdt = (acpi_header_t *) current; current += ssdt->length; acpi_add_table(rsdp,ssdt); - } - else { + } else { printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 361adbb..7708676 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/persimmon/acpi/cpstate.asl b/src/mainboard/amd/persimmon/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/persimmon/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 043ba3c..4a44a5a 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -264,7 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -273,12 +274,9 @@ unsigned long write_acpi_tables(unsigned long start) ssdt = (acpi_header_t *) current; current += ssdt->length; acpi_add_table(rsdp,ssdt); - } - else { + } else { printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index b480c33..bd9ce74 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/south_station/acpi/cpstate.asl b/src/mainboard/amd/south_station/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/south_station/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 8d32614..f430087 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -263,7 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -271,12 +273,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 7f03a43..b18bcb2 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/torpedo/acpi/cpstate.asl b/src/mainboard/amd/torpedo/acpi/cpstate.asl deleted file mode 100755 index 5eca9cc..0000000 --- a/src/mainboard/amd/torpedo/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index a8a731d..758fba5 100755 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -51,36 +51,32 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU2, /* name space name */ + C002, /* name space name */ 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU3, /* name space name */ + C003, /* name space name */ 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/union_station/acpi/cpstate.asl b/src/mainboard/amd/union_station/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/union_station/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index fc26df2..e32a42b 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -263,7 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -271,12 +273,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index fb2cfe8..7e49fd4 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/asrock/e350m1/acpi/cpstate.asl b/src/mainboard/asrock/e350m1/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/asrock/e350m1/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index fc26df2..e32a42b 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -263,7 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -271,12 +273,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 97533c1..c2ea1fb 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index ac9acd6..77c0772 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -297,7 +297,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -305,11 +306,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); } else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index 137a90d..2955eea 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -65,69 +65,68 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - P000, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0x00, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - //#include "acpi/cpstate.asl" } - Processor(P001, 0x01, 0x00000000, 0x00) {} - Processor(P002, 0x02, 0x00000000, 0x00) {} - Processor(P003, 0x03, 0x00000000, 0x00) {} - Processor(P004, 0x04, 0x00000000, 0x00) {} - Processor(P005, 0x05, 0x00000000, 0x00) {} - Processor(P006, 0x06, 0x00000000, 0x00) {} - Processor(P007, 0x07, 0x00000000, 0x00) {} - Processor(P008, 0x08, 0x00000000, 0x00) {} - Processor(P009, 0x09, 0x00000000, 0x00) {} - Processor(P00A, 0x0A, 0x00000000, 0x00) {} - Processor(P00B, 0x0B, 0x00000000, 0x00) {} - Processor(P00C, 0x0C, 0x00000000, 0x00) {} - Processor(P00D, 0x0D, 0x00000000, 0x00) {} - Processor(P00E, 0x0E, 0x00000000, 0x00) {} - Processor(P00F, 0x0F, 0x00000000, 0x00) {} - Processor(P010, 0x10, 0x00000000, 0x00) {} - Processor(P011, 0x11, 0x00000000, 0x00) {} - Processor(P012, 0x12, 0x00000000, 0x00) {} - Processor(P013, 0x13, 0x00000000, 0x00) {} - Processor(P014, 0x14, 0x00000000, 0x00) {} - Processor(P015, 0x15, 0x00000000, 0x00) {} - Processor(P016, 0x16, 0x00000000, 0x00) {} - Processor(P017, 0x17, 0x00000000, 0x00) {} - Processor(P018, 0x18, 0x00000000, 0x00) {} - Processor(P019, 0x19, 0x00000000, 0x00) {} - Processor(P01A, 0x1A, 0x00000000, 0x00) {} - Processor(P01B, 0x1B, 0x00000000, 0x00) {} - Processor(P01C, 0x1C, 0x00000000, 0x00) {} - Processor(P01D, 0x1D, 0x00000000, 0x00) {} - Processor(P01E, 0x1E, 0x00000000, 0x00) {} - Processor(P01F, 0x1F, 0x00000000, 0x00) {} - Processor(P020, 0x20, 0x00000000, 0x00) {} - Processor(P021, 0x21, 0x00000000, 0x00) {} - Processor(P022, 0x22, 0x00000000, 0x00) {} - Processor(P023, 0x23, 0x00000000, 0x00) {} - Processor(P024, 0x24, 0x00000000, 0x00) {} - Processor(P025, 0x25, 0x00000000, 0x00) {} - Processor(P026, 0x26, 0x00000000, 0x00) {} - Processor(P027, 0x27, 0x00000000, 0x00) {} - Processor(P028, 0x28, 0x00000000, 0x00) {} - Processor(P029, 0x29, 0x00000000, 0x00) {} - Processor(P02A, 0x2A, 0x00000000, 0x00) {} - Processor(P02B, 0x2B, 0x00000000, 0x00) {} - Processor(P02C, 0x2C, 0x00000000, 0x00) {} - Processor(P02D, 0x2D, 0x00000000, 0x00) {} - Processor(P02E, 0x2E, 0x00000000, 0x00) {} - Processor(P02F, 0x2F, 0x00000000, 0x00) {} - Alias (P000, CPU0) - Alias (P001, CPU1) - Alias (P002, CPU2) - Alias (P003, CPU3) - Alias (P004, CPU4) - Alias (P005, CPU5) - Alias (P006, CPU6) - Alias (P007, CPU7) - Alias (P008, CPU8) + Processor(C001, 0x01, 0x00000000, 0x00) {} + Processor(C002, 0x02, 0x00000000, 0x00) {} + Processor(C003, 0x03, 0x00000000, 0x00) {} + Processor(C004, 0x04, 0x00000000, 0x00) {} + Processor(C005, 0x05, 0x00000000, 0x00) {} + Processor(C006, 0x06, 0x00000000, 0x00) {} + Processor(C007, 0x07, 0x00000000, 0x00) {} + Processor(C008, 0x08, 0x00000000, 0x00) {} + Processor(C009, 0x09, 0x00000000, 0x00) {} + Processor(C00A, 0x0A, 0x00000000, 0x00) {} + Processor(C00B, 0x0B, 0x00000000, 0x00) {} + Processor(C00C, 0x0C, 0x00000000, 0x00) {} + Processor(C00D, 0x0D, 0x00000000, 0x00) {} + Processor(C00E, 0x0E, 0x00000000, 0x00) {} + Processor(C00F, 0x0F, 0x00000000, 0x00) {} + Processor(C010, 0x10, 0x00000000, 0x00) {} + Processor(C011, 0x11, 0x00000000, 0x00) {} + Processor(C012, 0x12, 0x00000000, 0x00) {} + Processor(C013, 0x13, 0x00000000, 0x00) {} + Processor(C014, 0x14, 0x00000000, 0x00) {} + Processor(C015, 0x15, 0x00000000, 0x00) {} + Processor(C016, 0x16, 0x00000000, 0x00) {} + Processor(C017, 0x17, 0x00000000, 0x00) {} + Processor(C018, 0x18, 0x00000000, 0x00) {} + Processor(C019, 0x19, 0x00000000, 0x00) {} + Processor(C01A, 0x1A, 0x00000000, 0x00) {} + Processor(C01B, 0x1B, 0x00000000, 0x00) {} + Processor(C01C, 0x1C, 0x00000000, 0x00) {} + Processor(C01D, 0x1D, 0x00000000, 0x00) {} + Processor(C01E, 0x1E, 0x00000000, 0x00) {} + Processor(C01F, 0x1F, 0x00000000, 0x00) {} + Processor(C020, 0x20, 0x00000000, 0x00) {} + Processor(C021, 0x21, 0x00000000, 0x00) {} + Processor(C022, 0x22, 0x00000000, 0x00) {} + Processor(C023, 0x23, 0x00000000, 0x00) {} + Processor(C024, 0x24, 0x00000000, 0x00) {} + Processor(C025, 0x25, 0x00000000, 0x00) {} + Processor(C026, 0x26, 0x00000000, 0x00) {} + Processor(C027, 0x27, 0x00000000, 0x00) {} + Processor(C028, 0x28, 0x00000000, 0x00) {} + Processor(C029, 0x29, 0x00000000, 0x00) {} + Processor(C02A, 0x2A, 0x00000000, 0x00) {} + Processor(C02B, 0x2B, 0x00000000, 0x00) {} + Processor(C02C, 0x2C, 0x00000000, 0x00) {} + Processor(C02D, 0x2D, 0x00000000, 0x00) {} + Processor(C02E, 0x2E, 0x00000000, 0x00) {} + Processor(C02F, 0x2F, 0x00000000, 0x00) {} + Alias (C000, CPU0) + Alias (C001, CPU1) + Alias (C002, CPU2) + Alias (C003, CPU3) + Alias (C004, CPU4) + Alias (C005, CPU5) + Alias (C006, CPU6) + Alias (C007, CPU7) + Alias (C008, CPU8) } /* End _PR scope */ /* PIC IRQ mapping registers, C00h-C01h */ [View Less]

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Patch set updated for coreboot: 6a28f1e Fix messy code in ALIB
by Zheng Bao 17 Apr '12

17 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/885 -gerrit commit 6a28f1e5cf0a7bb94e57545533aa08dccd08bffe Author: zbao <fishbaozi(a)gmail.com> Date: Fri Apr 13 13:48:50 2012 +0800 Fix messy code in ALIB Fix the copy-paste typo in ALIB talbe creation. ssdt is useless here. Change-Id: I250066eb5f755275f75c37789ce8760de35b046b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> … [View More]Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/dinar/acpi_tables.c | 4 ++-- src/mainboard/amd/inagua/acpi_tables.c | 7 +++---- src/mainboard/amd/persimmon/acpi_tables.c | 7 +++---- src/mainboard/amd/south_station/acpi_tables.c | 7 +++---- src/mainboard/amd/union_station/acpi_tables.c | 7 +++---- src/mainboard/asrock/e350m1/acpi_tables.c | 7 +++---- src/mainboard/supermicro/h8qgi/acpi_tables.c | 4 ++-- 7 files changed, 19 insertions(+), 24 deletions(-) diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index a6382fe..e2a8a44 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -290,9 +290,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); + acpi_add_table(rsdp, (void *)alib); } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 923d0bf..29a8423 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -256,11 +256,10 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + acpi_add_table(rsdp, (void *)alib); + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 4a44a5a..cb415fd 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -256,11 +256,10 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + acpi_add_table(rsdp, (void *)alib); + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index f430087..b6c9b9f 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -256,11 +256,10 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + acpi_add_table(rsdp, (void *)alib); + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index e32a42b..5c958a0 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -256,11 +256,10 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + acpi_add_table(rsdp, (void *)alib); + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index e32a42b..5c958a0 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -256,11 +256,10 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + acpi_add_table(rsdp, (void *)alib); + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 77c0772..f6db214 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -290,9 +290,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); + acpi_add_table(rsdp, (void *)alib); } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } [View Less]

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New patch to review for coreboot: d0cf472 Fix the blank in acpi_tables.c
by Zheng Bao 17 Apr '12

17 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/903 -gerrit commit d0cf472c8f7aaebda3706d5e7ff03440437b749d Author: zbao <fishbaozi(a)gmail.com> Date: Wed Apr 18 11:28:07 2012 +0800 Fix the blank in acpi_tables.c Change-Id: I65d50616e49802b7bb13f02369c4898fa4a238a4 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/… [View More]bimini_fam10/acpi_tables.c | 18 +++++++++--------- src/mainboard/amd/dinar/acpi_tables.c | 12 ++++++------ src/mainboard/amd/inagua/acpi_tables.c | 2 +- src/mainboard/amd/mahogany_fam10/acpi_tables.c | 16 ++++++++-------- .../amd/serengeti_cheetah_fam10/acpi_tables.c | 18 +++++++++--------- src/mainboard/amd/south_station/acpi_tables.c | 2 +- src/mainboard/amd/tilapia_fam10/acpi_tables.c | 18 +++++++++--------- src/mainboard/amd/torpedo/acpi_tables.c | 16 ++++++++-------- 8 files changed, 51 insertions(+), 51 deletions(-) diff --git a/src/mainboard/amd/bimini_fam10/acpi_tables.c b/src/mainboard/amd/bimini_fam10/acpi_tables.c index 7be5aaa..d7a1f24 100644 --- a/src/mainboard/amd/bimini_fam10/acpi_tables.c +++ b/src/mainboard/amd/bimini_fam10/acpi_tables.c @@ -128,7 +128,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; // it will used by fadt memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -137,14 +137,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; // it will be used by fadt current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -155,7 +155,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -163,7 +163,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -171,7 +171,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) current; acpi_create_srat(srat); @@ -179,7 +179,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, srat); /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) current; acpi_create_slit(slit); @@ -187,7 +187,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, slit); /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)current; memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); @@ -216,7 +216,7 @@ unsigned long write_acpi_tables(unsigned long start) } else { c = (u8) ('A' + i - 1 - 6); } - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt ssdtx = (acpi_header_t *)current; switch (sysconf.hcid[i]) { diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index e2a8a44..db01d79 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -237,7 +237,7 @@ unsigned long write_acpi_tables(unsigned long start) * We explicitly add these tables later on: */ #ifdef UNUSED_CODE // Don't need HPET table. we have one in dsdt - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -246,7 +246,7 @@ unsigned long write_acpi_tables(unsigned long start) #endif /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -254,14 +254,14 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* HEST */ - current = (current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; hest = (acpi_hest_t *)current; acpi_write_hest((void *)current); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -273,7 +273,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -285,7 +285,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = (current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 29a8423..a4504d4 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -216,7 +216,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* HEST */ - current = (current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; hest = (acpi_hest_t *)current; acpi_write_hest((void *)current); acpi_add_table(rsdp, (void *)current); diff --git a/src/mainboard/amd/mahogany_fam10/acpi_tables.c b/src/mainboard/amd/mahogany_fam10/acpi_tables.c index 1f7c2f7..7e89881 100644 --- a/src/mainboard/amd/mahogany_fam10/acpi_tables.c +++ b/src/mainboard/amd/mahogany_fam10/acpi_tables.c @@ -144,7 +144,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; // it will used by fadt memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -153,14 +153,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; // it will be used by fadt current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -171,7 +171,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -179,7 +179,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -187,7 +187,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) current; acpi_create_srat(srat); @@ -195,7 +195,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, srat); /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) current; acpi_create_slit(slit); @@ -203,7 +203,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, slit); /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot PSTATE/TOM SSDT at %lx\n", current); ssdt = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index 87cadc0..2c112f9 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -198,7 +198,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -207,14 +207,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -225,7 +225,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -233,7 +233,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n", current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -241,7 +241,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) current; acpi_create_srat(srat); @@ -249,7 +249,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, srat); /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) current; acpi_create_slit(slit); @@ -257,7 +257,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, slit); /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)current; memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); @@ -287,7 +287,7 @@ unsigned long write_acpi_tables(unsigned long start) else { c = (u8) ('A' + i - 1 - 6); } - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index b6c9b9f..5c958a0 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -216,7 +216,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* HEST */ - current = (current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; hest = (acpi_hest_t *)current; acpi_write_hest((void *)current); acpi_add_table(rsdp, (void *)current); diff --git a/src/mainboard/amd/tilapia_fam10/acpi_tables.c b/src/mainboard/amd/tilapia_fam10/acpi_tables.c index 4e10d5b..c44fe33 100644 --- a/src/mainboard/amd/tilapia_fam10/acpi_tables.c +++ b/src/mainboard/amd/tilapia_fam10/acpi_tables.c @@ -128,7 +128,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; // it will used by fadt memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -137,14 +137,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; // it will be used by fadt current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -155,7 +155,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -163,7 +163,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -171,7 +171,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) current; acpi_create_srat(srat); @@ -179,7 +179,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, srat); /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) current; acpi_create_slit(slit); @@ -187,7 +187,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, slit); /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)current; memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); @@ -216,7 +216,7 @@ unsigned long write_acpi_tables(unsigned long start) } else { c = (u8) ('A' + i - 1 - 6); } - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt ssdtx = (acpi_header_t *)current; switch (sysconf.hcid[i]) { diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c index 9cad9fa..2e04c57 100644 --- a/src/mainboard/amd/torpedo/acpi_tables.c +++ b/src/mainboard/amd/torpedo/acpi_tables.c @@ -164,7 +164,7 @@ unsigned long write_acpi_tables(unsigned long start) * We explicitly add these tables later on: */ #if 0 // Don't need HPET table. - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -173,7 +173,7 @@ unsigned long write_acpi_tables(unsigned long start) #endif /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -188,7 +188,7 @@ unsigned long write_acpi_tables(unsigned long start) current += ((acpi_header_t *)current)->length; /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -200,7 +200,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -212,7 +212,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -234,7 +234,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; // it will used by fadt memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -243,14 +243,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; // it will be used by fadt current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); [View Less]

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Re: [coreboot] [geda-user] Re: Dual SPI Flash adapter
by Oliver Schinagl 17 Apr '12

17 Apr '12

Hi, I've threw out half the schema and incorporated the dual FET switch. So far only the schema, any input appreciated! I think worked in Peter's suggestions. I added two resistors, S1 and S2 who's purpouse is to bypass the FET switch if one would choose not to use one, I figured using a really small SMD footprint should work allright as a solder bridge? Only downside is you'd have two 10k resistors when using a resistor network. When using a 100k resistor network that's less of an … [View More]issue, but I only have some salvaged 103 ones :p One could always only solder two SMD resistors where the resistor network lives of course. I'll work on the PCB the next few days, if people don't want me to throw everything around again :) Oliver On 04/05/12 13:40, Oliver Schinagl wrote: > On 04/05/12 06:16, Peter Stuge wrote: >> Peter Stuge wrote: >>> It's a mux on the CS/ line of two SPI flash chips. >> >> Oliver, I really think you should add a real mux to the PCB, and have >> that be "remote controlled" by the jumper or mechanical switch. > Why is that recommended? If using a jumper cap, it shouldn't be able to > go wrong? Chip1 active, none active, chip2 active? To which I can't > understand why that extra component would help. > > Not that I don't believe you :p I know nothing of this stuff, but the > goal was to make this board as simple as possible. >> >> It's a small board but I think it can be done. The design I used on > I think it would make the board a little bigger again, or actually the > SOIC8 3306 could fit on top between the connector, so I think it may be > possible using the same size :) Dunno if routing will be still possible :p > >> the M57SLI (see http://stuge.se/m57sli/ if curious) is shown in the > > Now the left schematic is what your motherboard does? The top right is > what's the smallest component count and the ride side is with an easier > switch, but higher component count? > > >> attachment, but I suggest to make some improvements: >> >> 1. change things around so that the switch common is GND >> 2. look for little logic to reduce component count >> >> The attachment has two suggested circuits using little logic, one >> with only two components (3306+resistorpack) but which then requires >> a SPDT switch, and one with three components (3306+1g14+resistorpack) >> but which only requires shorting a jumper to ground to switch between >> flash chips. > Even though I am sure that the 3306 method would be better, I don't > understand quite how and why it's needed. Also I haven't found a 3306 on > any of my pcb's to scavenge one off :) I'd reccon the simpler design > would allow for easier adaption? > > Finally, I notice you use 100k resistorpacks, but in a previous message > I recall you mentioning anything between 1k and 10k should be good? (I > happen to have a 103 resistor pack on a pcb here is my wondering :) >> >> >> //Peter > [View Less]

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Binary blobs in the source tree (was: Re: New patch to review for coreboot: e4fc528 Add the memory reference code binary for sandybridge chipsets)
by Carl-Daniel Hailfinger 17 Apr '12

17 Apr '12

Am 15.04.2012 04:57 schrieb ron minnich: > On Sat, Apr 14, 2012 at 3:12 AM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > >> I hope this is not going into the main repository, but into some >> separate repository instead. >> Right now we can tell people that all code in our official git >> repository is GPL-compatible, and I'd like to keep it that way. > We maintain GPL V2 compatibility as this is a blob that is placed into … [View More]

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Patch merged into coreboot/master: cf2748d lint: tighten whitespace check some more
by gerrit＠coreboot.org 17 Apr '12

17 Apr '12

the following patch was just integrated into master: commit cf2748dfffc75ca94e5397e59e549c1e451b9dcd Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Apr 12 15:23:58 2012 +0200 lint: tighten whitespace check some more Don't test executable files nor object files, even if the former might render the test useless on win32 (executable bit isn't well defined there). Change-Id: Ifb6fc83243289d266f439316c14b6b009f8da5fc Signed-off-by: Patrick … [View More]

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Re: [coreboot] Binary blobs in the source tree (was: Re: New patch to review for coreboot: e4fc528 Add the memory reference code binary for sandybridge chipsets)
by Carl-Daniel Hailfinger 17 Apr '12

17 Apr '12

Am 15.04.2012 22:08 schrieb ron minnich: > On Sun, Apr 15, 2012 at 3:49 PM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: >> Am 15.04.2012 04:57 schrieb ron minnich: >> It's a slippery slope, though. We call the blob from coreboot and expect >> it to return to coreboot (whether the return is a JMP/RET/... doesn't >> matter). Unless I'm mistaken, we've never done that before, > We've been doing it for almost ten years, first with vga … [View More]bios and then > with microcode. In the latter case, the microcode was a binary blob > linked in to coreboot which we called. The Intel MRC is actually less > connected, as it is a blob in cbfs. I thought the microcode updates were not executed as binary blobs, but rather uploaded (or banged into a register) into the CPU. >> and if we do >> this now in the official tree, it will be very hard to refuse merging >> chipset init blobs (well, pretty much any init blob), and for some >> chipset/CPU combinations coreboot may turn into a simple blob aggregator >> with PCI init. That's a scenario I'm very afraid of. > it's a danger. It's something we have to watch for. I've made it clear > to the vendors that's not what we want. They seem to be listening. Glad to hear that. > But we can not escape some minimal set of blobs unless we wish to drop > x86 platforms (or most of them) because > it's getting to be impossible to turn on an x86 without these blobs. Is this a problem for all x86 CPU vendors? I don't believe in "name and shame", but at least knowing if there is unaffected hardware would help making an informed decision. By the way, we should really document in the wiki what's going on outside the coreboot code paths before and during startup. > The next blob I have to commit is the ME binary, and that's not even > run by the x86, but by the external RISC CPU. And, you can't turn on > the platform without it. > >> Microcode is conceptually different. It's a stream of bytes you bang >> into some register, you don't execute it as normal code on your CPU. CPU >> microcode is like a network card's internal firmware: outside the scope >> of coreboot. > I see no difference but I'm not really here for a debate. If we can't > come to convergence I'll just make a separate repo.And, I suppose this > means there's no objections to me putting the ME binary blob into the > tree? Now that you're explicitly asking me, I'd like to keep ME/IMC (Management Engine/Internal Management Controller) binary blobs out as well. Rudolf has worked quite a bit on a free IMC firmware for recent AMD chipsets, and there's a faint hope (i.e. wishful thinking) we'll get something like that for Intel as well one day. The same applies to firmware for standalone EC (Embedded Controller) in laptops/servers. >> I heard rumors that the MRC blob is only a stopgap solution because >> there wasn't sufficient time to write+QA RAM init code for the >> sandybridge platform, and such code might materialize later. > That rumor is complete and total random noise (to use a polite word). > You heard it here first. I don't know why people make that stuff up. Wishful thinking maybe? I really hoped the rumor would be true. Probably a classic telephone game: "MRC blob is a hard requirement" -> "would be nice if we had a MRC blob replacement" -> "maybe someone is already working on that" -> "surely somone must be working on that, it's an obvious goal". > So, one more cycle of this discussion and then I'd like to come to a > decision. We've still got lots to do so we can give you all a coreboot > release at the same time the laptop is for sale! I'm all for having a separate git tree with all sorts of helpful/necessary blobs hosted at coreboot.org, because that gives us the option to keep the trees in sync and it also makes coreboot.org the canonical source of everything you might ever want or need for a firmware build. (CPU microcode updates should remain in the main source tree, though.) Regards, Carl-Daniel -- http://www.hailfinger.org/ [View Less]

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blobs
by ron minnich 17 Apr '12

17 Apr '12

Please find here: ssh://review.coreboot.org:29418/blobs.git blobs needed for the two google systems. I will be removing the blob from the coreboot tree today. I hope this helps bring the discussion to a close :-) ron

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Patch merged into coreboot/master: e4fc528 Add the memory reference code binary for sandybridge chipsets
by gerrit＠coreboot.org 17 Apr '12

17 Apr '12

the following patch was just integrated into master: commit e4fc5283d5c2e5fe8f75875a8229319696f8990b Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 12 04:26:22 2012 -0700 Add the memory reference code binary for sandybridge chipsets This binary is required for anyone who wishes to build a sandybridge mainboard. Change-Id: I779ef5e2b77166b81cb05eada37291368e74fbb6 Signed-off-by: Ron Minnich <rminnich(a)gmail.com> Build-Tested: build bot (… [View More]

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Re: [coreboot] [SPAM] Re: Binary blobs in the source tree (was: Re: New patchto review for coreboot: e4fc528 Add the memory reference codebinary for sandybridge chipsets)
by Xavi Drudis Ferran 17 Apr '12

17 Apr '12

On Tue 17/04/12 04:53 , Peter Stuge <peter(a)stuge.se> wrote: > > You imply that you experience a change in direction, but as I tried > to make clear already in my last email, I do not consider coreboot > to have changed direction at all. The recent progress is a leap > forward; as already confirmed by Andrew, coreboot is more valuable > with Sandy Bridge support. > We disagree about change of directions. We agree that the value of coreboot is different with or … [View More]without that blob. I prefer the previous value. My preference is of no particular concern since I don't have commit rights and tend to seek consensus more than clearness of my own preferences. > > if coreboot starts filling with blobs it will be just another BIOS, > > only somewhat delayed or playing catchup with some features. > > I'm not sure if you realize how absurd that is. In case you didn't > notice, coreboot has been playing catchup with all hardware for the > first 12 years. > And I guess it will still play catchup with blobs. When AMD started commiting lots of code for their chipsets this didn't magically create implementations for all the AMD enabled motherboards out there. Before the blob, it was a catchuper which had the unique value that was free and could be modified and understood. After the blob it won't have this value, just like most BIOSes, and will still be a catchuper. It will just be trying to catch up with a bigger slice of available hardware. But I'm playing too much devil advocate. If the blob was free software the new hardware support would be much welcome. > You may think that 12 years is a long time for a project, but in fact > coreboot is only since a year or so, when AMD announced their > support, starting to grow up, and even then there are many things > that desperately require your contributions to increase it's success. > I want to thank AMD for their support. But I also want to thank all people that worked in coreboot those 12 years. AMD may not have come without them. > OR - you can go to a vendor and pay them for the service of doing it > on your behalf. Currently there exists no such service for coreboot, > but the more popular coreboot becomes the more likely it is that such > a service provider (or several!) will appear. > > YOU have to research details to ensure that YOUR requirements are met. > > Blobs do not change this fundamental fact in any way. Blobs reduce the set of people able to adapt them to just one party. Blobs provide functionality that may discourage some people to implement free alternatives (fortunately you try to compensate by encouraging people to do so). > If there are no > blobs then your "zero blobs" requirement is very easy to check off > the list of requirements, while other metrics such as "computational > performance" or "power consumption" remain exactly as difficult to > check. > If there are blobs you still have to measure performace or power. > You have no right to spit on coreboot (which is what you say that you > would do if it became "a blob loader") just because one part of it > solves problems which you do not want to solve, while other parts > solve exactly the problems you do want to solve. > Sorry. I didn't mean to spit on coreboot, just on some options about its future. But I didn't mean to spit at all. I just didn't feel commited enough to be more polite than some rushed people. Maybe I wasn't just polite enough. Sorry about that. > Further, as Ron already pointed out - and as you know from your > experience with PC bootstrapping, you can't really ignore that many > coreboot systems already depend on another blob during startup - the > VGA BIOS. It's not really related to coreboot, but to the way the PC > platform is expected to work by PC operating systems. > Nonfree VGA BIOSes are not distributed with coreboot as far as I know. I would have objected just the same to committing nonfree VGA BIOSes. I wish one can do without them, but I haven't claimed that's possible. > > it will be like what linux has become, you no longer know much by > > the statement that linux runs on something. If android is free > > software > > Who has said that Android is free software? That's stupid. If you > want to discuss Linux not being free enough then you can always try > to take it up with Linus. > I was just trying to show examples of projects that include free and nonfree parts and achieve what you seek: support for more hardware. And I hinted at what I don't like from them, that they make really hard to tell free from nonfree apart. > > Coreboot may choose to go that route > > Third time: coreboot has never changed direction and I do not see any > reason to do so in the future. > Coreboot is not yourself only. It's very likely more yourself than myself, but you can't just decide it on your own. And there are other people objecting, maybe with a better attitude than myself. > that fit their needs. You can pretend that coreboot actually does not > support Sandy Bridge and Ivy Bridge at all, and you are still golden! > A free software project is some people trying to work together to achieve some goal. When you use a free software project you have some work already done for you. Keeping the code free, legaly sound and testing it with different hardware is an important work that I appreciate in free software projects. Projects which mix free and nonfree parts and require users to identify the nonfree parts, learn what they support and pretend they aren't there, don't provide this work done and I miss it. > Indeed it is. What you write is extremely offensive. You are > disrespecting the magnitude and excellence of the work that has been > contributed to the coreboot project by the Chromebook team and I just > find that to be really really poor form, regardless of your reasons. > I didn't mean to offend anyone. If I did I apologise. I just want the work of all previous committers to a truly free software project to be respected. I may be attributing intentions to others, but I'll have to make do with that until I learn mind reading. > > Does someone else besides intel and google have permission to > > distribute the blobs? > > Please see > http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure > > I expect you to actually have solid knowledge of this already, since > you have already sent contributions. > You can rest. I stand by my sign off. My contribution was a) small b) possibly replaceable with later code by AMD c) safe to sign off to the best of my knowledge. This assumes the code present in coreboot before my changes was legally safe, since my contribution is a derived work of it, but I didn't do any legal audit of code already in the repository. Now that you pointed this out, let me quote that page: License Issues * Contributed code must be GPL'd (preferrably 'GPLv2 or any later version', but 'GPLv2' is fine, too). At the very minimum the code must have a GPL-compatible license. My understanding of a GPL-compatible license is one that in particular allows anyone with the binary to obtain the source from the distributor. Mr. Ron Minnich, please, I downloaded e4fc5283d5c2e5fe8f75875a8229319696f8990b and can't find the licence, can you specify which GPL-compatible license it is under ? Can you please provide the source code ? > > coreboot users have usually assumed they had permission to > > distribute the tree freely under GPL, > > You speak for all of them? I am sure that you realize how absurd > that is. Noone can claim anything on behalf of "coreboot users." > In the same message you linked to a page that demands each contribution to be signed off, defines sign off as a process whereby the contributor grants or certifies the availability of an open source license and the open source license is further constrained to a GPL-compatible license, preferably GPLv2 or later. GPL-compatible licenses grant the right to distribute the licensed material. By "freely distributing" I meant distributing under some conditions that keep the software free. In the sense I meant, a tree full of GPL licensed content can be "freely distributed". By "freely distributed" I didn't mean unconstrained by the GPL. I'm sorry for any misunderstanding. Mr. Stuge, can people assume the page you just sent to accurately describe this project ? > > Ask away about anything that is unclear! Thanks. I'm trying. > Reality check. Vendors are not fighting each other over who can be > more compatible with coreboot. For 12 years coreboot has been chasing > hardware. You need to understand the full impact of this. > Reality check. The fact that google wants to buy millions of chromebooks and their available firmware does not fit their requirements, so they want to use coreboot with a blob for some hardware models will not magically lead every OEM to implement coreboot for their systems. A new system will be added, the legal clarity of the project will be compromised, and people will still wait for the next volunteer to port a similar board replacing or working around the blob if the hardware requires it. > > if you can't even rely on a FSF priority project to get free > > software. > > As I am sure that you already know, coreboot is not an FSF project. > Sorry for writing too loosely. I meant : "If you can't even rely in a project that appears in the FSF's high priority projects list to get free software." See http://www.fsf.org/campaigns/priority-projects/ The fact that FSF asked people to help coreboot does not mean that coreboot is a FSF project. I didn't mean it. I just meant that I expected them to ask support only for free software (and I believe they're not aware of the issue or are waiting for a resolution before editing that page). > I will not bother biting on this last piece of flame bait. I am > confident that you understand that coreboot is more free than your > other options. If it's not free enough for you at this time then > please either go away or please help us out. In any case you are > *NOT* helping by complaining. > Very clear, mister. I hope I can help by asking for license clarification. That's hopefully more constructive than talking about pride, half-bakeness or likeliness of future hardware support. [View Less]

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Patch merged into coreboot/master: 705d2ea Intel e7505: handlers for undocumented registers
by gerrit＠coreboot.org 17 Apr '12

17 Apr '12

the following patch was just integrated into master: commit 705d2eac86a12704489033c5a115ae8bae43f6f5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Apr 12 22:46:23 2012 +0300 Intel e7505: handlers for undocumented registers Makes the code a bit more readable, IMO. There is no clean way to implement this as the affected registers are undocumented. Seems ROMCC cannot handle the enum. Also any of my future changes would not be even abuild tested … [View More]

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Patch merged into coreboot/master: 1576dc1 kconfig: Improve 'General setup' menu docs.
by gerrit＠coreboot.org 17 Apr '12

17 Apr '12

the following patch was just integrated into master: commit 1576dc110e01f397853aeb828483f71603a57fa8 Author: Uwe Hermann <uwe(a)hermann-uwe.de> Date: Thu Apr 12 22:00:03 2012 +0200 kconfig: Improve 'General setup' menu docs. - Add documentation for COMPILER_GCC, and COMPILER_LLVM_CLANG. - SCANBUILD_ENABLE, CCACHE: Amend documentation. - SCANBUILD_REPORT_LOCATION: Document default dir, names of scan-build dirs. - INCLUDE_CONFIG_FILE: Add more … [View More]

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coreboot/Flashrom: Sponsor needed for promotion for LinuxTag or any other IT fair, trade show, conference
by Paul Menzel 17 Apr '12

17 Apr '12

Dear coreboot and Flashrom folks, the idea is to give out flash chips for free to people (LinuxTag in Berlin from May 23rd to 26th) asking them to test Flashrom and try coreboot. Where the flash chips are given away, at the coreboot or Flashrom booth or at the sponsor’s booth does not matter much. Reason ------ In my experience having to buy flash chips (or a programmer) is the biggest hurdle to development or testing. Although 20 € for shipping and such is not *that* much it seems to be … [View More]for some people. Additionally since mostly you cannot buy such things in the shop around the corner it is quite time consuming to shop online. Benefits -------- For coreboot it could mean just telling people to build an image similar to their board, switch the chip, flash the image to the given chip and then test it. So because people coming home having means to try coreboot (more) easily will get them to the project. For Flashrom people could test if their mainboard supports all operations, especially erase and wrote, so we could better coverage of mainboard support [1]. Of course only for boards supporting the given away chip. Type of chip ------------ I have not much of a clue, but I guess the flash chip should have DIP8 form factor and support the SPI protocol. The size should be 16 or 32 Mb MBit. Help is needed here for suggestions. Quantity and Price ------------------ 500 or 1000 chip should be a reasonable amount to get. One developer (in Europe?) (going to most fairs) could store them and if there is another event (in Europe) the developer will not attend then he could mail a certain amount of chips to developers attending that event. On IRC scientes found an offer for order of 1000+ pieces for an 32Mbit chip for $1.77 for a piece. Therefore getting 1000 chips would cost 2000 $/€. Money and sponsors ------------------ It would be great if a company or organization would be willing to finance that project. Maybe the developers who work at company/organizations doing coreboot or Flashrom work or deployment could lobby for the support in their company/organization. Besides good press coverage and improved reputation I write up some arguments for some companies or organizations. ### AMD ### Although a statement was made to support coreboot and code for chipset support is contributed, board ports are lacking. Making it easy for people to port coreboot to more AMD boards and by doing so also fix bug or clean up the code should be in AMD’s interest. ### Intel ### The known reasons apply. Now that the coreboot team at Google made the Sandy Bridge port for their Chromebooks [3], it easier than ever to make a port for other Intel boards with that chipset. ### Google ### Just plain Free Software principle. By having people work with or try out coreboot, code Google uses will be tested and improved. Also Google doing Flashrom development more testing would be beneficial in that area too. ### Microsoft, Ubuntu and other Free Software distributions ### Having a BIOS replacement which takes less time to initialize the hardware and let the operating system take over, will (indirectly) improve the experience of their users. ### FSF (Free Software Foundation) ### As coreboot is a high priority project at the FSF they could support such promotions financially. ### BSI (Bundesamt für Sicherheit in der Informationstechnik) ### Having companies and citizens using coreboot will be lead to more secure systems, since coreboot being free software it can be audited by everyone and updates do not depend on the willingness of the vendor. It would be awesome if we could get that project going. I am curious how it will turn out. Thanks, Paul [1] http://flashrom.org/Supported_hardware#Supported_mainboards [2] http://flashrom.org/Technology [3] http://blogs.coreboot.org/blog/2012/04/02/google-releases-sandybridge-suppo… [4] http://www.fsf.org/campaigns/priority-projects/ [View Less]

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Patch merged into coreboot/master: fcb4358 More portable s3 scratch space creation
by gerrit＠coreboot.org 17 Apr '12

17 Apr '12

the following patch was just integrated into master: commit fcb4358908704fa31adc3eb051692307fc2a89ce Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Apr 12 15:03:22 2012 +0200 More portable s3 scratch space creation echo -n isn't portable. echo -e isn't portable. that bash loop isn't portable. So let's try something else. Change-Id: Ie73aa1c09d90c11a5c4952a332d4c2058390b5db Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> … [View More]

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Patch set updated for coreboot: 6a7857a Do not produce temp s3.rom if HAVE_ACPI_RESUME is no.
by Zheng Bao 16 Apr '12

16 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/902 -gerrit commit 6a7857a7b7f69b7979886598a31da0fdeeb8b4c3 Author: zbao <fishbaozi(a)gmail.com> Date: Tue Apr 17 11:33:27 2012 +0800 Do not produce temp s3.rom if HAVE_ACPI_RESUME is no. s3.rom is useless for all the other boards which S3 resume is not validated. Yes, sooner or later when CBFS is able to allocated an area, the s3.rom is no … [View More]

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New patch to review for coreboot: 25c9c62 Do not produce temp s3.rom if HAVE_ACPI_RESUME is no.
by Zheng Bao 16 Apr '12

16 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/902 -gerrit commit 25c9c627957b5954ee7e473e3caeced28dbb7215 Author: zbao <fishbaozi(a)gmail.com> Date: Tue Apr 17 11:16:23 2012 +0800 Do not produce temp s3.rom if HAVE_ACPI_RESUME is no. s3.rom is useless for all the other boards which S3 resume is not validated. Yes, sooner or later when CBFS is able to allocated an area, the s3.rom is no … [View More]

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Re: [coreboot] coccinelle project for i915 graphics driver for coreboot
by Kevin O'Connor 16 Apr '12

16 Apr '12

On Mon, Apr 09, 2012 at 11:30:34AM -0700, ron minnich wrote: > I'm trying an experiment and I welcome anyone who wants to help. > > It's a simple idea motivated by a very hard problem. The problem is > that we have unending problems with binary video bioses. We'd like to > get to a source based video bios on, e.g., chromebook. [...] > Now why do it this way? Why not just do a one time hack of the driver > code to a coreboot driver? One possibility would be to create your … [View More]

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Patch set updated for coreboot: a442eaf nvramtool: Unify nvramtool and build_opt_tbl
by Vikram Narayanan 16 Apr '12

16 Apr '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/898 -gerrit commit a442eafcfe6bd399a6eac61952170f763d45ac22 Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 14 15:25:13 2012 +0530 nvramtool: Unify nvramtool and build_opt_tbl As cmos.layout parsing capabilities are already there in nvramtool, use those than using build_opt_tbl.c. Add binary and header file generation … [View More]in nvramtool. Make appropriate changes to Makefile.inc. Change-Id: Iaf3f5d4f51451aeb33c92800a0c895045f2388cf Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/arch/x86/Makefile.inc | 13 +- util/nvramtool/accessors/layout-text.c | 226 ++++++++++++++++++++++++++++++++ util/nvramtool/accessors/layout-text.h | 2 + util/nvramtool/cli/nvramtool.c | 18 +++- util/nvramtool/cli/opts.c | 9 +- util/nvramtool/cli/opts.h | 4 +- util/nvramtool/common.c | 2 + util/nvramtool/layout.h | 8 +- 8 files changed, 267 insertions(+), 15 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8783d4b..d3b5e07 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -128,18 +128,15 @@ bootsplash.jpg-type := bootsplash ####################################################################### # i386 specific tools +NVRAMTOOL:=$(objutil)/nvramtool/nvramtool -$(OPTION_TABLE_H): $(objutil)/options/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout +$(OPTION_TABLE_H): $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout @printf " OPTION $(subst $(obj)/,,$(@))\n" - $(objutil)/options/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --header $@ + $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -H $@ -$(obj)/cmos_layout.bin: $(objutil)/options/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout +$(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout @printf " OPTION $(subst $(obj)/,,$(@))\n" - $(objutil)/options/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --binary $@ - -$(objutil)/options/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc80/mc146818rtc.h $(top)/src/include/boot/coreboot_tables.h - @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) $< -o $@ + $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ ####################################################################### # Build the coreboot_ram (stage 2) diff --git a/util/nvramtool/accessors/layout-text.c b/util/nvramtool/accessors/layout-text.c index cbe698c..7b1bbd3 100644 --- a/util/nvramtool/accessors/layout-text.c +++ b/util/nvramtool/accessors/layout-text.c @@ -1,6 +1,12 @@ /*****************************************************************************\ * layout-text.c ***************************************************************************** + * Copyright (C) 2012, Vikram Narayanan + * Unified build_opt_tbl and nvramtool + * build_opt_tbl.c + * Copyright (C) 2003 Eric Biederman (ebiederm(a)xmission.com) + * Copyright (C) 2007-2010 coresystems GmbH + * * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. * Written by Dave Peterson <dsp(a)llnl.gov> <dave_peterson(a)pobox.com>. @@ -186,6 +192,7 @@ static int line_num; static const char *layout_filename = NULL; +#define ROUNDUP4(x) (x += (4 - (x % 4))) /**************************************************************************** * set_layout_filename * @@ -218,6 +225,225 @@ void get_layout_from_file(void) fclose(f); } +static int is_ident_nondigit(int c) +{ + int result; + switch(c) { + case 'A': case 'B': case 'C': case 'D': + case 'E': case 'F': case 'G': case 'H': + case 'I': case 'J': case 'K': case 'L': + case 'M': case 'N': case 'O': case 'P': + case 'Q': case 'R': case 'S': case 'T': + case 'U': case 'V': case 'W': case 'X': + case 'Y': case 'Z': + case 'a': case 'b': case 'c': case 'd': + case 'e': case 'f': case 'g': case 'h': + case 'i': case 'j': case 'k': case 'l': + case 'm': case 'n': case 'o': case 'p': + case 'q': case 'r': case 's': case 't': + case 'u': case 'v': case 'w': case 'x': + case 'y': case 'z': + case '_': + result = 1; + break; + default: + result = 0; + break; + } + return result; +} + +static int is_ident(char *str) +{ + int result; + int ch; + ch = *str; + result = 0; + if (is_ident_nondigit(ch)) { + do { + str++; + ch = *str; + } while(ch && (is_ident_nondigit(ch) || (isdigit(ch)))); + result = (ch == '\0'); + } + return result; +} + +int write_cmos_layout_bin(FILE *f) +{ + const cmos_entry_t *cmos_entry; + const cmos_enum_t *cmos_enum; + cmos_checksum_layout_t layout; + struct cmos_option_table table; + struct cmos_entries entry; + struct cmos_enums cenum; + struct cmos_checksum csum; + size_t sum = 0; + int len; + + for (cmos_entry = first_cmos_entry(); cmos_entry != NULL; + cmos_entry = next_cmos_entry(cmos_entry)) { + + if (cmos_entry == first_cmos_entry()) { + sum += sizeof(table); + table.header_length = sizeof(table); + table.tag = LB_TAG_CMOS_OPTION_TABLE; + + if (fwrite((char *)&table, sizeof(table), 1, f) != 1) { + perror("Error writing image file"); + goto err; + } + } + + memset(&entry, 0, sizeof(entry)); + entry.tag = LB_TAG_OPTION; + entry.config = cmos_entry->config; + entry.config_id = (uint32_t)cmos_entry->config_id; + entry.bit = cmos_entry->bit; + entry.length = cmos_entry->length; + + if (!is_ident((char *)cmos_entry->name)) { + fprintf(stderr, + "Error - Name %s is an invalid identifier\n", + cmos_entry->name); + goto err; + } + + memcpy(entry.name, cmos_entry->name, strlen(cmos_entry->name)); + entry.name[strlen(cmos_entry->name)] = '\0'; + len = strlen(cmos_entry->name) + 1; + + if (len % 4) + ROUNDUP4(len); + + entry.size = sizeof(entry) - CMOS_MAX_NAME_LENGTH + len; + sum += entry.size; + if (fwrite((char *)&entry, entry.size, 1, f) != 1) { + perror("Error writing image file"); + goto err; + } + } + + for (cmos_enum = first_cmos_enum(); + cmos_enum != NULL; cmos_enum = next_cmos_enum(cmos_enum)) { + memset(&cenum, 0, sizeof(cenum)); + cenum.tag = LB_TAG_OPTION_ENUM; + memcpy(cenum.text, cmos_enum->text, strlen(cmos_enum->text)); + cenum.text[strlen(cmos_enum->text)] = '\0'; + len = strlen((char *)cenum.text) + 1; + + if (len % 4) + ROUNDUP4(len); + + cenum.config_id = cmos_enum->config_id; + cenum.value = cmos_enum->value; + cenum.size = sizeof(cenum) - CMOS_MAX_TEXT_LENGTH + len; + sum += cenum.size; + if (fwrite((char *)&cenum, cenum.size, 1, f) != 1) { + perror("Error writing image file"); + goto err; + } + } + + layout.summed_area_start = cmos_checksum_start; + layout.summed_area_end = cmos_checksum_end; + layout.checksum_at = cmos_checksum_index; + checksum_layout_to_bits(&layout); + + csum.tag = LB_TAG_OPTION_CHECKSUM; + csum.size = sizeof(csum); + csum.range_start = layout.summed_area_start; + csum.range_end = layout.summed_area_end; + csum.location = layout.checksum_at; + csum.type = CHECKSUM_PCBIOS; + sum += csum.size; + + if (fwrite((char *)&csum, csum.size, 1, f) != 1) { + perror("Error writing image file"); + goto err; + } + + if (fseek(f, sizeof(table.tag), SEEK_SET) != 0) { + perror("Error while seeking"); + goto err; + } + + if (fwrite((char *)&sum, sizeof(table.tag), 1, f) != 1) { + perror("Error writing image file"); + goto err; + } + return sum; + +err: + fclose(f); + exit(1); +} + +void write_cmos_output_bin(const char *binary_filename) +{ + FILE *fp; + + if ((fp = fopen(binary_filename, "wb")) == NULL) { + fprintf(stderr, + "%s: Can not open file %s for writing: " + "%s\n", prog_name, binary_filename, strerror(errno)); + exit(1); + } + write_cmos_layout_bin(fp); + fclose(fp); +} + +void write_cmos_layout_header(const char *header_filename) +{ + FILE *fp; + const cmos_entry_t *cmos_entry; + cmos_checksum_layout_t layout; + + if ((fp = fopen(header_filename, "w+")) == NULL) { + fprintf(stderr, + "%s: Can't open file %s for writing: %s\n", + prog_name, header_filename, strerror(errno)); + exit(1); + } + + fprintf(fp, "/**\n * This is an autogenerated file. Do not EDIT.\n" + " * All changes made to this file will be lost.\n" + " * See mainboard's cmos.layout file.\n */\n" + "\n#ifndef __OPTION_TABLE_H\n" + "#define __OPTION_TABLE_H\n\n"); + + for (cmos_entry = first_cmos_entry(); cmos_entry != NULL; + cmos_entry = next_cmos_entry(cmos_entry)) { + + if (!is_ident((char *)cmos_entry->name)) { + fprintf(stderr, + "Error - Name %s is an invalid identifier\n", + cmos_entry->name); + fclose(fp); + exit(1); + } + + fprintf(fp, "#define CMOS_VSTART_%s\t%d\n", + cmos_entry->name, cmos_entry->bit); + fprintf(fp, "#define CMOS_VLEN_%s\t%d\n", + cmos_entry->name, cmos_entry->length); + } + + layout.summed_area_start = cmos_checksum_start; + layout.summed_area_end = cmos_checksum_end; + layout.checksum_at = cmos_checksum_index; + checksum_layout_to_bits(&layout); + + fprintf(fp, "\n#define LB_CKS_RANGE_START %d\n", + layout.summed_area_start / 8); + fprintf(fp, "#define LB_CKS_RANGE_END %d\n", + layout.summed_area_end / 8); + fprintf(fp, "#define LB_CKS_LOC %d\n", + layout.checksum_at / 8); + fprintf(fp, "\n#endif /* __OPTION_TABLE_H */\n"); + + fclose(fp); +} /**************************************************************************** * write_cmos_layout * diff --git a/util/nvramtool/accessors/layout-text.h b/util/nvramtool/accessors/layout-text.h index 21997e9..e6b4397 100644 --- a/util/nvramtool/accessors/layout-text.h +++ b/util/nvramtool/accessors/layout-text.h @@ -37,5 +37,7 @@ void set_layout_filename(const char filename[]); void get_layout_from_file(void); void write_cmos_layout(FILE * f); +void write_cmos_output_bin(const char *binary_filename); +void write_cmos_layout_header(const char *header_filename); #endif /* LAYOUT_FILE_H */ diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c index bcb10bb..f3fb16d 100644 --- a/util/nvramtool/cli/nvramtool.c +++ b/util/nvramtool/cli/nvramtool.c @@ -62,6 +62,8 @@ static void op_write_cmos_dump(void); static void op_read_cmos_dump(void); static void op_show_cmos_hex_dump(void); static void op_show_cmos_dumpfile(void); +static void op_write_cmos_layout_bin(void); +static void op_write_cmos_layout_header(void); static int list_one_param(const char name[], int show_name); static int list_all_params(void); static void list_param_enums(const char name[]); @@ -86,9 +88,23 @@ static const op_fn_t op_fns[] = { op_show_version, op_write_cmos_dump, op_read_cmos_dump, op_show_cmos_hex_dump, - op_show_cmos_dumpfile + op_show_cmos_dumpfile, + op_write_cmos_layout_bin, + op_write_cmos_layout_header }; +static void op_write_cmos_layout_bin(void) +{ + get_layout_from_file(); + write_cmos_output_bin(nvramtool_op.param); +} + +static void op_write_cmos_layout_header(void) +{ + get_layout_from_file(); + write_cmos_layout_header(nvramtool_op.param); +} + static const hexdump_format_t cmos_dump_format = { 16, 2, "", " | ", " ", " | ", '.' }; diff --git a/util/nvramtool/cli/opts.c b/util/nvramtool/cli/opts.c index 4949649..8e920e8 100644 --- a/util/nvramtool/cli/opts.c +++ b/util/nvramtool/cli/opts.c @@ -41,7 +41,7 @@ static void register_op_modifier(nvramtool_op_modifier_t mod, char mod_param[]); static void resolve_op_modifiers(void); static void sanity_check_args(void); -static const char getopt_string[] = "-ab:B:c::C:dD:e:hil::np:r:tvw:xX:y:Y"; +static const char getopt_string[] = "-ab:B:c::C:dD:e:hH:iL:l::np:r:tvw:xX:y:Y"; /**************************************************************************** * parse_nvramtool_args @@ -100,6 +100,9 @@ void parse_nvramtool_args(int argc, char *argv[]) case 'h': register_op(&op_found, NVRAMTOOL_OP_SHOW_USAGE, NULL); break; + case 'H': + register_op(&op_found, NVRAMTOOL_OP_WRITE_HEADER_FILE, optarg); + break; case 'i': register_op(&op_found, NVRAMTOOL_OP_CMOS_SET_PARAMS_STDIN, NULL); @@ -108,6 +111,10 @@ void parse_nvramtool_args(int argc, char *argv[]) register_op(&op_found, NVRAMTOOL_OP_LBTABLE_SHOW_INFO, handle_optional_arg(argc, argv)); break; + case 'L': + register_op(&op_found, NVRAMTOOL_OP_WRITE_BINARY_FILE, + optarg); + break; case 'n': register_op_modifier(NVRAMTOOL_MOD_SHOW_VALUE_ONLY, NULL); diff --git a/util/nvramtool/cli/opts.h b/util/nvramtool/cli/opts.h index f46f254..a011ef1 100644 --- a/util/nvramtool/cli/opts.h +++ b/util/nvramtool/cli/opts.h @@ -48,7 +48,9 @@ typedef enum { NVRAMTOOL_OP_SHOW_VERSION = 0, NVRAMTOOL_OP_WRITE_CMOS_DUMP, NVRAMTOOL_OP_READ_CMOS_DUMP, NVRAMTOOL_OP_SHOW_CMOS_HEX_DUMP, - NVRAMTOOL_OP_SHOW_CMOS_DUMPFILE + NVRAMTOOL_OP_SHOW_CMOS_DUMPFILE, + NVRAMTOOL_OP_WRITE_BINARY_FILE, + NVRAMTOOL_OP_WRITE_HEADER_FILE } nvramtool_op_t; typedef struct { diff --git a/util/nvramtool/common.c b/util/nvramtool/common.c index 91fcccc..15f8b0d 100644 --- a/util/nvramtool/common.c +++ b/util/nvramtool/common.c @@ -98,6 +98,8 @@ void usage(FILE * outfile) "VALUE.\n" " -l [ARG]: Show coreboot table info for ARG, or " "all ARG choices.\n" + " -L OUTPUT_BIN Write CMOS layout file in binary format\n" + " -H OUTPUT_HDR Write CMOS layout file in header format\n" " -d: Show low-level dump of coreboot table.\n" " -Y: Show CMOS layout info.\n" " -b OUTPUT_FILE: Dump CMOS memory contents to file.\n" diff --git a/util/nvramtool/layout.h b/util/nvramtool/layout.h index d99275c..082c31b 100644 --- a/util/nvramtool/layout.h +++ b/util/nvramtool/layout.h @@ -46,10 +46,10 @@ #define LAYOUT_CHECKSUM_LOCATION_OUT_OF_RANGE (LAYOUT_RESULT_START + 9) typedef enum { - CMOS_ENTRY_ENUM, - CMOS_ENTRY_HEX, - CMOS_ENTRY_STRING, - CMOS_ENTRY_RESERVED + CMOS_ENTRY_ENUM = 'e', + CMOS_ENTRY_HEX = 'h', + CMOS_ENTRY_STRING = 's', + CMOS_ENTRY_RESERVED = 'r', } cmos_entry_config_t; /* This represents a CMOS parameter. */ [View Less]

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Patch set updated for coreboot: 512774e nvramtool: Allow spaces in enumeration names
by Vikram Narayanan 16 Apr '12

16 Apr '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/901 -gerrit commit 512774e9f487cfefd8daeb0b02704d7133f85ce7 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Apr 14 16:21:39 2012 +0200 nvramtool: Allow spaces in enumeration names Change-Id: Id526e74f06fb15d4692d7b6edc8b5863f2d42c50 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/nvramtool/accessors/… [View More]

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Patch merged into coreboot/master: 5ccfb7f S3 code in the mainboard.
by gerrit＠coreboot.org 16 Apr '12

16 Apr '12

the following patch was just integrated into master: commit 5ccfb7fc1276278529653e49d8c8faf67770ef25 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Apr 13 13:42:46 2012 +0800 S3 code in the mainboard. Persimmon is the demo board. Tested by Linux and Windows 7. Change-Id: I5ded942b51e63ebeb08ace0b202b4ed239b0c14c Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri … [View More]

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Patch merged into coreboot/master: 915f427 S3 code in coreboot public folder.
by gerrit＠coreboot.org 16 Apr '12

16 Apr '12

the following patch was just integrated into master: commit 915f42708f3dad4f34d06fd8af89ca8d90177b4b Author: zbao <fishbaozi(a)gmail.com> Date: Fri Apr 13 13:42:15 2012 +0800 S3 code in coreboot public folder. 1. Move the Stack to high memory. 2. Restore the MTRR before Coreboot jump to the wakeup vector. Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.… [View More]

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Trac reminder: list of new ticket(s)
by coreboot tracker 16 Apr '12

16 Apr '12

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Patch merged into coreboot/master: cb313ee ACPI HEST table.
by gerrit＠coreboot.org 15 Apr '12

15 Apr '12

the following patch was just integrated into master: commit cb313ee348521ed0a2ee44c9481673d9ca969808 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Apr 13 13:57:14 2012 +0800 ACPI HEST table. HEST feature starts from ACPI 4.0. HEST is one of four kinds of tables of ACPI Platform Error Interfaces (APEI). In Windows world, APEI is called Windows Hardware Error Architecture (WHEA). APEI consists of four separate tables: 1. Error Record … [View More]

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Patch set updated for coreboot: cb313ee ACPI HEST table.
by Zheng Bao 15 Apr '12

15 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/888 -gerrit commit cb313ee348521ed0a2ee44c9481673d9ca969808 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Apr 13 13:57:14 2012 +0800 ACPI HEST table. HEST feature starts from ACPI 4.0. HEST is one of four kinds of tables of ACPI Platform Error Interfaces (APEI). In Windows world, APEI is called Windows Hardware Error Architecture (… [View More]WHEA). APEI consists of four separate tables: 1. Error Record Serialization Table (ERST) 2. BOOT Error Record Table (BERT) 3. Hardware Error Source Table (HEST) 4. Error Injection Table (EINJ) All these 4 tables have the same header as FADT, MADT, etc. They are pointed by RSDP. For the HEST, it contains the error source. The types of them are defined as type description 1. Machine Check Exception (MCE) 2. Corrected Machine Check (CMC) 3. NMI Error 6. PCI Express Root Port AER 7. PCI Express Device AER 8. PCI Express Bridge AER 9. Generic Hardware Error Source Error source types 3, 4, and 5 are reserved for legacy reasons and must not be used. Currently AMD board only provide part of "Machine Check Exception (MCE)" & Corrected Machine Check (CMC)". we need to provide the header of each error source. Other types of Error Sources is in TODO list. Only persimmon is tested. Linux can add HEST feature. The dmesg says, ACPI: HEST 0000000066fe5010 00198 (v03 CORE COREBOOT 00000000 CORE 00000000) ...... HEST: Table parsing has been initialized. No more message is got. Windows can boot with this patch. Havent found a way to test it. Change-Id: I447e7f57b8e8f0433a145a43d0710910afabf00f Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/arch/x86/boot/acpi.c | 83 +++++++++++++++++++++++++ src/arch/x86/include/arch/acpi.h | 35 ++++++++++ src/mainboard/amd/dinar/acpi_tables.c | 33 +++++++++- src/mainboard/amd/inagua/acpi_tables.c | 49 ++++++++++++--- src/mainboard/amd/persimmon/acpi_tables.c | 49 ++++++++++++--- src/mainboard/amd/south_station/acpi_tables.c | 49 ++++++++++++--- src/mainboard/amd/torpedo/acpi_tables.c | 26 ++++++++ src/mainboard/amd/union_station/acpi_tables.c | 49 ++++++++++++--- src/mainboard/asrock/e350m1/acpi_tables.c | 49 ++++++++++++--- src/mainboard/supermicro/h8qgi/acpi_tables.c | 33 +++++++++- 10 files changed, 401 insertions(+), 54 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index f17e73e..010ba9f 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -467,6 +467,89 @@ void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt) rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t)); } +unsigned long __attribute__((weak)) acpi_fill_hest(acpi_hest_t *hest) +{ + return (unsigned long)hest; +} + +unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 data_len) +{ + acpi_header_t *header = &(hest->header); + acpi_hest_hen_t *hen; + void *pos; + u16 len; + + pos = esd; + memset(pos, 0, sizeof(acpi_hest_esd_t)); + len = 0; + esd->type = type; /* MCE */ + esd->source_id = hest->error_source_count; + esd->flags = 0; /* FIRMWARE_FIRST */ + esd->enabled = 1; + esd->prealloc_erecords = 1; + esd->max_section_per_record = 0x1; + + len += sizeof(acpi_hest_esd_t); + pos = esd + 1; + + switch (type) { + case 0: /* MCE */ + break; + case 1: /* CMC */ + hen = (acpi_hest_hen_t *) (pos); + memset(pos, 0, sizeof(acpi_hest_hen_t)); + hen->type = 3; /* SCI? */ + hen->length = sizeof(acpi_hest_hen_t); + hen->conf_we = 0; /* Configuration Write Enable. */ + hen->poll_interval = 0; + hen->vector = 0; + hen->sw2poll_threshold_val = 0; + hen->sw2poll_threshold_win = 0; + hen->error_threshold_val = 0; + hen->error_threshold_win = 0; + len += sizeof(acpi_hest_hen_t); + pos = hen + 1; + break; + case 2: /* NMI */ + case 6: /* AER Root Port */ + case 7: /* AER Endpoint */ + case 8: /* AER Bridge */ + case 9: /* Generic Hardware Error Source. */ + /* TODO: */ + break; + default: + printk(BIOS_DEBUG, "Invalid type of Error Source."); + break; + } + hest->error_source_count ++; + + memcpy(pos, data, data_len); + len += data_len; + header->length += len; + + return len; +} + +/* ACPI 4.0 */ +void acpi_write_hest(acpi_hest_t *hest) +{ + acpi_header_t *header = &(hest->header); + + memset(hest, 0, sizeof(acpi_hest_t)); + + memcpy(header->signature, "HEST", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->length += sizeof(acpi_hest_t); + header->revision = 1; + + acpi_fill_hest(hest); + + /* Calculate checksums. */ + header->checksum = acpi_checksum((void *)hest, header->length); +} + #if CONFIG_HAVE_ACPI_RESUME == 1 void suspend_resume(void) { diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 8c521af..60e400d 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -357,6 +357,37 @@ typedef struct acpi_ecdt { u8 ec_id[]; /* EC ID */ } __attribute__ ((packed)) acpi_ecdt_t; +/* HEST (Hardware Error Source Table) */ +typedef struct acpi_hest { + struct acpi_table_header header; + u32 error_source_count; + /* error_source_struct(s) */ +} __attribute__ ((packed)) acpi_hest_t; + +/* Error Source Descriptors */ +typedef struct acpi_hest_esd { + u16 type; + u16 source_id; + u16 resv; + u8 flags; + u8 enabled; + u32 prealloc_erecords; /* The number of error records to pre-allocate for this error source. */ + u32 max_section_per_record; +} __attribute__ ((packed)) acpi_hest_esd_t; + +/* Hardware Error Notification */ +typedef struct acpi_hest_hen { + u8 type; + u8 length; + u16 conf_we; /* Configuration Write Enable */ + u32 poll_interval; + u32 vector; + u32 sw2poll_threshold_val; + u32 sw2poll_threshold_win; + u32 error_threshold_val; + u32 error_threshold_win; +} __attribute__ ((packed)) acpi_hest_hen_t; + /* These are implemented by the target port or north/southbridge. */ unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); @@ -412,6 +443,10 @@ void acpi_write_rsdt(acpi_rsdt_t *rsdt); void acpi_write_xsdt(acpi_xsdt_t *xsdt); void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt); +void acpi_write_hest(acpi_hest_t *hest); +unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 len); +unsigned long acpi_fill_hest(acpi_hest_t *hest); + #if CONFIG_HAVE_ACPI_RESUME /* 0 = S0, 1 = S1 ...*/ extern u8 acpi_slp_type; diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index ee00e81..1b80b18 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -122,6 +122,24 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -172,6 +190,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *ssdt2; acpi_header_t *alib; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -234,6 +253,13 @@ unsigned long write_acpi_tables(unsigned long start) current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ current = ( current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); @@ -272,7 +298,7 @@ unsigned long write_acpi_tables(unsigned long start) } #if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -285,7 +311,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp,ssdt); #endif - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); @@ -313,6 +339,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "fadt\n"); dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); #endif printk(BIOS_INFO, "ACPI: done.\n"); diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 8f47591..6c1acc8 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -105,6 +105,24 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -132,6 +150,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *ssdt2; acpi_header_t *alib; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -154,7 +173,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -163,14 +182,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -181,7 +200,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -189,15 +208,22 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -211,7 +237,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -225,7 +251,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { @@ -239,7 +265,7 @@ unsigned long write_acpi_tables(unsigned long start) } #if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -254,7 +280,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp,ssdt); #endif - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); @@ -288,6 +314,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "fadt\n"); dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); #endif printk(BIOS_INFO, "ACPI: done.\n"); diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 9526fea..043ba3c 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -105,6 +105,24 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -132,6 +150,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *ssdt2; acpi_header_t *alib; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -154,7 +173,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -163,14 +182,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -181,7 +200,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -189,15 +208,22 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -211,7 +237,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -225,7 +251,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { @@ -239,7 +265,7 @@ unsigned long write_acpi_tables(unsigned long start) } #if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -254,7 +280,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp,ssdt); #endif - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); @@ -288,6 +314,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "fadt\n"); dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); #endif printk(BIOS_INFO, "ACPI: done.\n"); diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 2e6e50f..8d32614 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -104,6 +104,24 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -131,6 +149,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *ssdt2; acpi_header_t *alib; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -153,7 +172,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -162,14 +181,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -180,7 +199,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -188,15 +207,22 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -210,7 +236,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -224,7 +250,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { @@ -238,7 +264,7 @@ unsigned long write_acpi_tables(unsigned long start) } #if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -252,7 +278,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp,ssdt); #endif - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); @@ -283,6 +309,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "fadt\n"); dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); #endif printk(BIOS_INFO, "ACPI: done.\n"); diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c index 3ba789d..9cad9fa 100644 --- a/src/mainboard/amd/torpedo/acpi_tables.c +++ b/src/mainboard/amd/torpedo/acpi_tables.c @@ -93,6 +93,24 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -120,6 +138,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_facs_t *facs; acpi_header_t *dsdt; acpi_header_t *ssdt; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -161,6 +180,13 @@ unsigned long write_acpi_tables(unsigned long start) current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ current = ( current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 2e6e50f..fc26df2 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -104,6 +104,24 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -131,6 +149,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *ssdt2; acpi_header_t *alib; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -153,7 +172,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -162,14 +181,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -180,7 +199,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -188,15 +207,22 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -210,7 +236,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -224,7 +250,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { @@ -238,7 +264,7 @@ unsigned long write_acpi_tables(unsigned long start) } #if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -252,7 +278,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp,ssdt); #endif - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); @@ -283,6 +309,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "fadt\n"); dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); #endif printk(BIOS_INFO, "ACPI: done.\n"); diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 2e6e50f..fc26df2 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -104,6 +104,24 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -131,6 +149,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *ssdt2; acpi_header_t *alib; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -153,7 +172,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -162,14 +181,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -180,7 +199,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -188,15 +207,22 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -210,7 +236,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -224,7 +250,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { @@ -238,7 +264,7 @@ unsigned long write_acpi_tables(unsigned long start) } #if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -252,7 +278,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp,ssdt); #endif - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); @@ -283,6 +309,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "fadt\n"); dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); #endif printk(BIOS_INFO, "ACPI: done.\n"); diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 7314283..ac9acd6 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -122,6 +122,24 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -172,6 +190,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *ssdt2; acpi_header_t *alib; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -234,6 +253,13 @@ unsigned long write_acpi_tables(unsigned long start) current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ current = ( current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); @@ -272,7 +298,7 @@ unsigned long write_acpi_tables(unsigned long start) } #if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -285,7 +311,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp,ssdt); #endif - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); @@ -313,6 +339,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "fadt\n"); dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); #endif printk(BIOS_INFO, "ACPI: done.\n"); [View Less]

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Re: [coreboot] New patch to review for coreboot: e4fc528 Add the memory reference code binary for sandybridge chipsets
by Luc Verhaegen 15 Apr '12

15 Apr '12

On Sat, Apr 14, 2012 at 07:57:19PM -0700, ron minnich wrote: > On Sat, Apr 14, 2012 at 3:12 AM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > > > I hope this is not going into the main repository, but into some > > separate repository instead. > > Right now we can tell people that all code in our official git > > repository is GPL-compatible, and I'd like to keep it that way. > > We maintain GPL V2 compatibility as this is … [View More]

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Patch merged into coreboot/master: 19807ed cmos.layout: Remove invalid warning
by gerrit＠coreboot.org 15 Apr '12

15 Apr '12

the following patch was just integrated into master: commit 19807eda20ce738b5419cb003f1aeae6d0e2fbcd Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 14 15:51:53 2012 +0530 cmos.layout: Remove invalid warning "This file must be in UNIX format" is not valid anymore. Change-Id: I86169b12e7db159c1d3f380b0434874e9b6f5274 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sun … [View More]

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Patch set updated for coreboot: 19807ed cmos.layout: Remove invalid warning
by Vikram Narayanan 15 Apr '12

15 Apr '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/899 -gerrit commit 19807eda20ce738b5419cb003f1aeae6d0e2fbcd Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 14 15:51:53 2012 +0530 cmos.layout: Remove invalid warning "This file must be in UNIX format" is not valid anymore. Change-Id: I86169b12e7db159c1d3f380b0434874e9b6f5274 Signed-off-by: Vikram Narayanan <… [View More]

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New patch to review for coreboot: e4fc528 Add the memory reference code binary for sandybridge chipsets
by Ronald G. Minnich 14 Apr '12

14 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/897 -gerrit commit e4fc5283d5c2e5fe8f75875a8229319696f8990b Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 12 04:26:22 2012 -0700 Add the memory reference code binary for sandybridge chipsets This binary is required for anyone who wishes to build a sandybridge mainboard. Change-Id: … [View More]

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New patch to review for coreboot: c036828 ASUS M4A785T-M mainboard: fix screen flickering issues
by Denis Carikli 14 Apr '12

14 Apr '12

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/900 -gerrit commit c03682861a1d8716900b74ec3f197faa9a68cecd Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sat Apr 14 14:30:49 2012 +0200 ASUS M4A785T-M mainboard: fix screen flickering issues Without that fix the screen flickered with resolutions superior to 832x624 because the cpu_ht_freq was 0 (so it ran at 200Mhz). … [View More]

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Re: [coreboot] coreboot Digest, Vol 86, Issue 47
by Ken Phillis Jr 14 Apr '12

14 Apr '12

On Sat, Apr 14, 2012 at 1:55 PM, Paul Menzel wrote: > Dear Ken, > > > first off topic. > > 0. The spelling is coreboot, i. e. all lowercase. > 1. Please do not send HTML message to mailing lists [1]. > 2. Using Gmail Web interface the down side is it wraps line > automatically which is bad if you paste stuff. Since they will not fix > that, you should think about using a mail program. > > I normally have "rich formatting" disabled ( html messages ), however i … [View More]forgot this. > Am Freitag, den 13.04.2012, 23:31 -0500 schrieb Ken Phillis Jr: > > Just another board support request... If there's any other information that > > is required, please ask me... > > > > General Board information: > > =============================================================================== > > Vendor: GIGABYTE > > Model: GA-MA790XT-UD4P (rev. 1.0) > > Product Page: http://www.gigabyte.us/products/product-page.aspx?pid=3010 > > North Bridge: AMD 790X > > South Bridge: AMD SB750 > > [?] > > As Peter wrote, you need to do the port yourself. Two good things > though, coreboot folks will help you if you have problems and your > components seem to be supported. So if you are willing to spend some > time, you should be able to complete that port. > I do expect some hassles with actual board to get fully configured. This is one of the Gigabyte boards that features dual-Bios on the board directly. > Please read the coreboot Wiki. You need to make sure to recover. Is the > flash chip socketed on your board? If yes, just get some back up chips, > find an already supported board similar to yours, build an image, > connect a second system over serial line to capture debugging output and > work your way through it. If something fails, just boot the system with > your back up flash chip, switch the flash chip and write another > (hopefully improved) image to it. > There is no flash chip socket on this board, and I do not have another computer that features a serial port. Actually, on a side note, what's the past trial and error that happened when dealing with other gigabyte boards that feature a dual-bios setup? On this board, there is two flash chips: I don't know what the ITE IT8720F super i/o chip clearly states that i cannot write to the bios on this chip, and when you look at the board, The chip is physically located over near the PCI Slots near the edge of the board. The other flash chip is the south bridge for the board. This is located over near the SATA ports under the heatsink. And finally, I do know that the bios chips are located near the southbridge. They have labels of M_BIOS, and B_BIOS. I know that there is a similar board already supported in CoreBoot... That board is the Gigabyte MA785GMT-UD2H. http://www.gigabyte.us/products/product-page.aspx?pid=3395#ov The only differences on this is that the dual-bios is located near the Super I/O that near the main power connector. > We are looking forward to your port! > > > Thanks, > > Paul > > > [1] http://en.opensuse.org/openSUSE:Mailing_list_netiquette [View Less]

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Re: [coreboot] Add Support for Gigabyte GA-MA790XT-UD4P
by Paul Menzel 14 Apr '12

14 Apr '12

Dear Ken, first off topic. 0. The spelling is coreboot, i. e. all lowercase. 1. Please do not send HTML message to mailing lists [1]. 2. Using Gmail Web interface the down side is it wraps line automatically which is bad if you paste stuff. Since they will not fix that, you should think about using a mail program. Am Freitag, den 13.04.2012, 23:31 -0500 schrieb Ken Phillis Jr: > Just another board support request... If there's any other information that > is required, please ask me...… [View More]

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MB A8N5X // nforce4 chipsets // wake on lan capability
by F M 14 Apr '12

14 Apr '12

Dear Sirs, I am writing to you regarding the above mentionned MB (and most probably on all nForce4 mb's) Wake on lan capabilities. At page : http://www.coreboot.org/ASUS_A8N5X you mention "The on-board ethernet device doesn't seem to support WOL (also not mentioned in the manual)" Please not that i am using this capability with this MB es follows (This is a known 'bug' from Nvidia nforce4 chipsets): If your ethernet's MAC address is *00:AB:34:FE:67:CD for exemple, you will need to type the … [View More]

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Re: [coreboot] CoreBoot: Add Support for Gigabyte GA-MA790XT-UD4P
by Peter Stuge 14 Apr '12

14 Apr '12

Ken Phillis Jr wrote: > Just another board support request... This is not really something compatible with the coreboot community development model. If you need the board supported you have to do it yourself. //Peter

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New patch to review for coreboot: f3befe2 nvramtool: Allow spaces in enumeration names
by Patrick Georgi 14 Apr '12

14 Apr '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/901 -gerrit commit f3befe21fc8542342f3c08ba7b2061cfcc661065 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Apr 14 16:21:39 2012 +0200 nvramtool: Allow spaces in enumeration names Change-Id: Id526e74f06fb15d4692d7b6edc8b5863f2d42c50 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/nvramtool/accessors/… [View More]

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New patch to review for coreboot: 9a258e6 cmos.layout: Remove invalid warning
by Vikram Narayanan 14 Apr '12

14 Apr '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/899 -gerrit commit 9a258e6907d235411c5069778923535467f76d1f Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 14 15:51:53 2012 +0530 cmos.layout: Remove invalid warning "This file must be in UNIX format" is not valid anymore. Change-Id: I86169b12e7db159c1d3f380b0434874e9b6f5274 Signed-off-by: Vikram Narayanan <… [View More]

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New patch to review for coreboot: c65489f nvramtool: Unify nvramtool and build_opt_tbl
by Vikram Narayanan 14 Apr '12

14 Apr '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/898 -gerrit commit c65489f0b556a1e57adade6da8fdbcc06e5deeab Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 14 15:25:13 2012 +0530 nvramtool: Unify nvramtool and build_opt_tbl As cmos.layout parsing capabilities are already there in nvramtool, use those than using build_opt_tbl.c. Add binary and header file generation … [View More]in nvramtool. Make appropriate changes to Makefile.inc. Change-Id: Iaf3f5d4f51451aeb33c92800a0c895045f2388cf Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/arch/x86/Makefile.inc | 16 +- util/nvramtool/accessors/layout-text.c | 242 ++++++++++++++++++++++++++++++++ util/nvramtool/accessors/layout-text.h | 2 + util/nvramtool/cli/nvramtool.c | 18 +++- util/nvramtool/cli/opts.c | 9 +- util/nvramtool/cli/opts.h | 4 +- util/nvramtool/common.c | 2 + util/nvramtool/layout.h | 8 +- 8 files changed, 286 insertions(+), 15 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8783d4b..6d9bdaf 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -128,18 +128,18 @@ bootsplash.jpg-type := bootsplash ####################################################################### # i386 specific tools +NVRAMTOOL:=$(obj)/nvramtool -$(OPTION_TABLE_H): $(objutil)/options/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout - @printf " OPTION $(subst $(obj)/,,$(@))\n" - $(objutil)/options/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --header $@ +$(NVRAMTOOL): $(objutil)/nvramtool/nvramtool + cp $< $@ -$(obj)/cmos_layout.bin: $(objutil)/options/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout +$(OPTION_TABLE_H): $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout @printf " OPTION $(subst $(obj)/,,$(@))\n" - $(objutil)/options/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --binary $@ + $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -H $@ -$(objutil)/options/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc80/mc146818rtc.h $(top)/src/include/boot/coreboot_tables.h - @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) $< -o $@ +$(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout + @printf " OPTION $(subst $(obj)/,,$(@))\n" + $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ ####################################################################### # Build the coreboot_ram (stage 2) diff --git a/util/nvramtool/accessors/layout-text.c b/util/nvramtool/accessors/layout-text.c index 5f7cade..f656b22 100644 --- a/util/nvramtool/accessors/layout-text.c +++ b/util/nvramtool/accessors/layout-text.c @@ -1,6 +1,12 @@ /*****************************************************************************\ * layout-text.c ***************************************************************************** + * Copyright (C) 2012, Vikram Narayanan + * Unified build_opt_tbl and nvramtool + * build_opt_tbl.c + * Copyright (C) 2003 Eric Biederman (ebiederm(a)xmission.com) + * Copyright (C) 2007-2010 coresystems GmbH + * * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. * Written by Dave Peterson <dsp(a)llnl.gov> <dave_peterson(a)pobox.com>. @@ -186,6 +192,7 @@ static int line_num; static const char *layout_filename = NULL; +#define ALIGN(x) (x += (4 - (x % 4))) /**************************************************************************** * set_layout_filename * @@ -218,6 +225,241 @@ void get_layout_from_file(void) fclose(f); } +static int is_ident_digit(int c) +{ + int result; + switch(c) { + case '0': case '1': case '2': case '3': + case '4': case '5': case '6': case '7': + case '8': case '9': + result = 1; + break; + default: + result = 0; + break; + } + return result; +} + +static int is_ident_nondigit(int c) +{ + int result; + switch(c) { + case 'A': case 'B': case 'C': case 'D': + case 'E': case 'F': case 'G': case 'H': + case 'I': case 'J': case 'K': case 'L': + case 'M': case 'N': case 'O': case 'P': + case 'Q': case 'R': case 'S': case 'T': + case 'U': case 'V': case 'W': case 'X': + case 'Y': case 'Z': + case 'a': case 'b': case 'c': case 'd': + case 'e': case 'f': case 'g': case 'h': + case 'i': case 'j': case 'k': case 'l': + case 'm': case 'n': case 'o': case 'p': + case 'q': case 'r': case 's': case 't': + case 'u': case 'v': case 'w': case 'x': + case 'y': case 'z': + case '_': + result = 1; + break; + default: + result = 0; + break; + } + return result; +} + +static int is_ident(char *str) +{ + int result; + int ch; + ch = *str; + result = 0; + if (is_ident_nondigit(ch)) { + do { + str++; + ch = *str; + } while(ch && (is_ident_nondigit(ch) || (is_ident_digit(ch)))); + result = (ch == '\0'); + } + return result; +} + +int write_cmos_layout_bin(FILE *f) +{ + const cmos_entry_t *cmos_entry; + const cmos_enum_t *cmos_enum; + cmos_checksum_layout_t layout; + struct cmos_option_table table; + struct cmos_entries entry; + struct cmos_enums cenum; + struct cmos_checksum csum; + size_t sum = 0; + int len; + + for (cmos_entry = first_cmos_entry(); cmos_entry != NULL; + cmos_entry = next_cmos_entry(cmos_entry)) { + + if (cmos_entry == first_cmos_entry()) { + sum += sizeof(table); + table.header_length = sizeof(table); + table.tag = LB_TAG_CMOS_OPTION_TABLE; + + if (fwrite((char *)&table, sizeof(table), 1, f) != 1) { + perror("Error writing image file"); + goto err; + } + } + + memset(&entry, 0, sizeof(entry)); + entry.tag = LB_TAG_OPTION; + entry.config = cmos_entry->config; + entry.config_id = (uint32_t)cmos_entry->config_id; + entry.bit = cmos_entry->bit; + entry.length = cmos_entry->length; + + if (!is_ident((char *)cmos_entry->name)) { + fprintf(stderr, + "Error - Name %s is an invalid identifier\n", + cmos_entry->name); + goto err; + } + + memcpy(entry.name, cmos_entry->name, strlen(cmos_entry->name)); + entry.name[strlen(cmos_entry->name)] = '\0'; + len = strlen(cmos_entry->name) + 1; + + if (len % 4) + ALIGN(len); + + entry.size = sizeof(entry) - CMOS_MAX_NAME_LENGTH + len; + sum += entry.size; + if (fwrite((char *)&entry, entry.size, 1, f) != 1) { + perror("Error writing image file"); + goto err; + } + } + + for (cmos_enum = first_cmos_enum(); + cmos_enum != NULL; cmos_enum = next_cmos_enum(cmos_enum)) { + memset(&cenum, 0, sizeof(cenum)); + cenum.tag = LB_TAG_OPTION_ENUM; + memcpy(cenum.text, cmos_enum->text, strlen(cmos_enum->text)); + cenum.text[strlen(cmos_enum->text)] = '\0'; + len = strlen((char *)cenum.text) + 1; + + if (len % 4) + ALIGN(len); + + cenum.config_id = cmos_enum->config_id; + cenum.value = cmos_enum->value; + cenum.size = sizeof(cenum) - CMOS_MAX_TEXT_LENGTH + len; + sum += cenum.size; + if (fwrite((char *)&cenum, cenum.size, 1, f) != 1) { + perror("Error writing image file"); + goto err; + } + } + + layout.summed_area_start = cmos_checksum_start; + layout.summed_area_end = cmos_checksum_end; + layout.checksum_at = cmos_checksum_index; + checksum_layout_to_bits(&layout); + + csum.tag = LB_TAG_OPTION_CHECKSUM; + csum.size = sizeof(csum); + csum.range_start = layout.summed_area_start; + csum.range_end = layout.summed_area_end; + csum.location = layout.checksum_at; + csum.type = CHECKSUM_PCBIOS; + sum += csum.size; + + if (fwrite((char *)&csum, csum.size, 1, f) != 1) { + perror("Error writing image file"); + goto err; + } + + if (fseek(f, sizeof(table.tag), SEEK_SET) != 0) { + perror("Error while seeking"); + goto err; + } + + if (fwrite((char *)&sum, sizeof(table.tag), 1, f) != 1) { + perror("Error writing image file"); + goto err; + } + return sum; + +err: + fclose(f); + exit(1); +} + +void write_cmos_output_bin(const char *binary_filename) +{ + FILE *fp; + + if ((fp = fopen(binary_filename, "wb")) == NULL) { + fprintf(stderr, + "%s: Can not open file %s for writing: " + "%s\n", prog_name, binary_filename, strerror(errno)); + exit(1); + } + write_cmos_layout_bin(fp); + fclose(fp); +} + +void write_cmos_layout_header(const char *header_filename) +{ + FILE *fp; + const cmos_entry_t *cmos_entry; + cmos_checksum_layout_t layout; + + if ((fp = fopen(header_filename, "w+")) == NULL) { + fprintf(stderr, + "%s: Can't open file %s for writing: %s\n", + prog_name, header_filename, strerror(errno)); + exit(1); + } + + fprintf(fp, "/**\n * This is an autogenerated file. Do not EDIT.\n" + " * All changes made to this file will be lost.\n" + " * See mainboard's cmos.layout file.\n */\n" + "\n#ifndef __OPTION_TABLE_H\n" + "#define __OPTION_TABLE_H\n\n"); + + for (cmos_entry = first_cmos_entry(); cmos_entry != NULL; + cmos_entry = next_cmos_entry(cmos_entry)) { + + if (!is_ident((char *)cmos_entry->name)) { + fprintf(stderr, + "Error - Name %s is an invalid identifier\n", + cmos_entry->name); + fclose(fp); + exit(1); + } + + fprintf(fp, "#define CMOS_VSTART_%s\t%d\n", + cmos_entry->name, cmos_entry->bit); + fprintf(fp, "#define CMOS_VLEN_%s\t%d\n", + cmos_entry->name, cmos_entry->length); + } + + layout.summed_area_start = cmos_checksum_start; + layout.summed_area_end = cmos_checksum_end; + layout.checksum_at = cmos_checksum_index; + checksum_layout_to_bits(&layout); + + fprintf(fp, "\n#define LB_CKS_RANGE_START %d\n", + layout.summed_area_start / 8); + fprintf(fp, "#define LB_CKS_RANGE_END %d\n", + layout.summed_area_end / 8); + fprintf(fp, "#define LB_CKS_LOC %d\n", + layout.checksum_at / 8); + fprintf(fp, "\n#endif /* __OPTION_TABLE_H */\n"); + + fclose(fp); +} /**************************************************************************** * write_cmos_layout * diff --git a/util/nvramtool/accessors/layout-text.h b/util/nvramtool/accessors/layout-text.h index 21997e9..e6b4397 100644 --- a/util/nvramtool/accessors/layout-text.h +++ b/util/nvramtool/accessors/layout-text.h @@ -37,5 +37,7 @@ void set_layout_filename(const char filename[]); void get_layout_from_file(void); void write_cmos_layout(FILE * f); +void write_cmos_output_bin(const char *binary_filename); +void write_cmos_layout_header(const char *header_filename); #endif /* LAYOUT_FILE_H */ diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c index bcb10bb..f3fb16d 100644 --- a/util/nvramtool/cli/nvramtool.c +++ b/util/nvramtool/cli/nvramtool.c @@ -62,6 +62,8 @@ static void op_write_cmos_dump(void); static void op_read_cmos_dump(void); static void op_show_cmos_hex_dump(void); static void op_show_cmos_dumpfile(void); +static void op_write_cmos_layout_bin(void); +static void op_write_cmos_layout_header(void); static int list_one_param(const char name[], int show_name); static int list_all_params(void); static void list_param_enums(const char name[]); @@ -86,9 +88,23 @@ static const op_fn_t op_fns[] = { op_show_version, op_write_cmos_dump, op_read_cmos_dump, op_show_cmos_hex_dump, - op_show_cmos_dumpfile + op_show_cmos_dumpfile, + op_write_cmos_layout_bin, + op_write_cmos_layout_header }; +static void op_write_cmos_layout_bin(void) +{ + get_layout_from_file(); + write_cmos_output_bin(nvramtool_op.param); +} + +static void op_write_cmos_layout_header(void) +{ + get_layout_from_file(); + write_cmos_layout_header(nvramtool_op.param); +} + static const hexdump_format_t cmos_dump_format = { 16, 2, "", " | ", " ", " | ", '.' }; diff --git a/util/nvramtool/cli/opts.c b/util/nvramtool/cli/opts.c index 4949649..8e920e8 100644 --- a/util/nvramtool/cli/opts.c +++ b/util/nvramtool/cli/opts.c @@ -41,7 +41,7 @@ static void register_op_modifier(nvramtool_op_modifier_t mod, char mod_param[]); static void resolve_op_modifiers(void); static void sanity_check_args(void); -static const char getopt_string[] = "-ab:B:c::C:dD:e:hil::np:r:tvw:xX:y:Y"; +static const char getopt_string[] = "-ab:B:c::C:dD:e:hH:iL:l::np:r:tvw:xX:y:Y"; /**************************************************************************** * parse_nvramtool_args @@ -100,6 +100,9 @@ void parse_nvramtool_args(int argc, char *argv[]) case 'h': register_op(&op_found, NVRAMTOOL_OP_SHOW_USAGE, NULL); break; + case 'H': + register_op(&op_found, NVRAMTOOL_OP_WRITE_HEADER_FILE, optarg); + break; case 'i': register_op(&op_found, NVRAMTOOL_OP_CMOS_SET_PARAMS_STDIN, NULL); @@ -108,6 +111,10 @@ void parse_nvramtool_args(int argc, char *argv[]) register_op(&op_found, NVRAMTOOL_OP_LBTABLE_SHOW_INFO, handle_optional_arg(argc, argv)); break; + case 'L': + register_op(&op_found, NVRAMTOOL_OP_WRITE_BINARY_FILE, + optarg); + break; case 'n': register_op_modifier(NVRAMTOOL_MOD_SHOW_VALUE_ONLY, NULL); diff --git a/util/nvramtool/cli/opts.h b/util/nvramtool/cli/opts.h index f46f254..a011ef1 100644 --- a/util/nvramtool/cli/opts.h +++ b/util/nvramtool/cli/opts.h @@ -48,7 +48,9 @@ typedef enum { NVRAMTOOL_OP_SHOW_VERSION = 0, NVRAMTOOL_OP_WRITE_CMOS_DUMP, NVRAMTOOL_OP_READ_CMOS_DUMP, NVRAMTOOL_OP_SHOW_CMOS_HEX_DUMP, - NVRAMTOOL_OP_SHOW_CMOS_DUMPFILE + NVRAMTOOL_OP_SHOW_CMOS_DUMPFILE, + NVRAMTOOL_OP_WRITE_BINARY_FILE, + NVRAMTOOL_OP_WRITE_HEADER_FILE } nvramtool_op_t; typedef struct { diff --git a/util/nvramtool/common.c b/util/nvramtool/common.c index 91fcccc..15f8b0d 100644 --- a/util/nvramtool/common.c +++ b/util/nvramtool/common.c @@ -98,6 +98,8 @@ void usage(FILE * outfile) "VALUE.\n" " -l [ARG]: Show coreboot table info for ARG, or " "all ARG choices.\n" + " -L OUTPUT_BIN Write CMOS layout file in binary format\n" + " -H OUTPUT_HDR Write CMOS layout file in header format\n" " -d: Show low-level dump of coreboot table.\n" " -Y: Show CMOS layout info.\n" " -b OUTPUT_FILE: Dump CMOS memory contents to file.\n" diff --git a/util/nvramtool/layout.h b/util/nvramtool/layout.h index d99275c..39a4159 100644 --- a/util/nvramtool/layout.h +++ b/util/nvramtool/layout.h @@ -46,10 +46,10 @@ #define LAYOUT_CHECKSUM_LOCATION_OUT_OF_RANGE (LAYOUT_RESULT_START + 9) typedef enum { - CMOS_ENTRY_ENUM, - CMOS_ENTRY_HEX, - CMOS_ENTRY_STRING, - CMOS_ENTRY_RESERVED + CMOS_ENTRY_ENUM = 0x65, + CMOS_ENTRY_HEX = 0x68, + CMOS_ENTRY_STRING = 0x96, + CMOS_ENTRY_RESERVED = 0x72, } cmos_entry_config_t; /* This represents a CMOS parameter. */ [View Less]

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CoreBoot: Add Support for Gigabyte GA-MA790XT-UD4P
by Ken Phillis Jr 13 Apr '12

13 Apr '12

Just another board support request... If there's any other information that is required, please ask me... General Board information: =============================================================================== Vendor: GIGABYTE Model: GA-MA790XT-UD4P (rev. 1.0) Product Page: http://www.gigabyte.us/products/product-page.aspx?pid=3010 North Bridge: AMD 790X South Bridge: AMD SB750 Output from: lspci -tvnn =============================================================================== -[0000:… [View More]00]-+-00.0 ATI Technologies Inc RD780 Northbridge only dual slot PCI-e_GFX and HT1 K8 part [1002:5958] +-02.0-[01]--+-00.0 ATI Technologies Inc Juniper [Radeon HD 5700 Series] [1002:68b8] | \-00.1 ATI Technologies Inc Juniper HDMI Audio [Radeon HD 5700 Series] [1002:aa58] +-04.0-[02]--+-00.0 JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller [197b:2363] | \-00.1 JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller [197b:2363] +-07.0-[03]----00.0 Conexant Systems, Inc. CX23885 PCI Video and Audio Decoder [14f1:8852] +-0a.0-[04]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] +-11.0 ATI Technologies Inc SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] +-12.0 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] +-12.1 ATI Technologies Inc SB7x0 USB OHCI1 Controller [1002:4398] +-12.2 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] +-13.0 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] +-13.1 ATI Technologies Inc SB7x0 USB OHCI1 Controller [1002:4398] +-13.2 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] +-14.0 ATI Technologies Inc SBx00 SMBus Controller [1002:4385] +-14.1 ATI Technologies Inc SB7x0/SB8x0/SB9x0 IDE Controller [1002:439c] +-14.2 ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] +-14.3 ATI Technologies Inc SB7x0/SB8x0/SB9x0 LPC host controller [1002:439d] +-14.4-[05]----0e.0 Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) [104c:8024] +-14.5 ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI2 Controller [1002:4399] +-18.0 Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] +-18.1 Advanced Micro Devices [AMD] Family 10h Processor Address Map [1022:1201] +-18.2 Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller [1022:1202] +-18.3 Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control [1022:1203] \-18.4 Advanced Micro Devices [AMD] Family 10h Processor Link Control [1022:1204] =============================================================================== Output from: superiotool -dV (only what was found) =============================================================================== Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8720F (id=0x8720, rev=0x8) at 0x2e Register dump: idx 20 21 22 23 24 2b val 87 20 08 80 00 00 def 87 20 05 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 04 00 80 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 val 01 03 f8 04 00 50 def 00 03 f8 04 00 50 LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 val 00 00 00 00 00 50 def 00 02 f8 03 00 50 LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 00 00 00 00 00 00 04 08 def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 02 28 00 00 00 10 00 0e 80 80 3e 1b def 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 48 def 01 00 60 00 64 01 02 48 LDN 0x06 (Mouse) idx 30 70 71 f0 val 00 00 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 e5 e6 e7 e9 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff val 00 90 00 41 00 00 01 00 00 02 20 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 40 01 00 00 80 00 01 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 26 00 00 00 00 00 cc 00 00 00 def 00 ff 00 40 00 00 03 00 00 00 00 00 00 00 00 NA 38 00 00 00 00 00 00 00 20 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 NA 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 00 00 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 06 =============================================================================== Output from: sudo flashrom -V ( Only the chipsets) =============================================================================== flashrom v0.9.4-r1394 on Linux 3.0.0-13-generic (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1403M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 1009 us, 10000 myus = 10012 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Gigabyte Technology Co., Ltd." DMI string system-product-name: "GA-MA790XT-UD4P" DMI string system-version: " " DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." DMI string baseboard-product-name: "GA-MA790XT-UD4P" DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8720 on port 0x2e Found chipset "AMD SB700/SB710/SB750/SB850" with PCI ID 1002:439d. Enabling flash write... SPI base address is at 0xfec10000 AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0 PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1 SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=4, SpiBridgeDisable=1, DropOneClkOnRd=0 NormSpeed is 33 MHz GPIO11 used for SPI_DO GPIO12 used for SPI_DI GPIO31 used for SPI_HOLD GPIO32 used for SPI_CS GPIO47 used for SPI_CLK SB700 IMC is not active. ROM strap override is not active OK. This chipset supports the following protocols: LPC, FWH, SPI. No IT87* serial flash segment enabled. =============================================================================== Output from: sudo flashrom -V ( Only the Flash CHip) =============================================================================== Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L8005" (1024 kB, SPI) at physical address 0xfff00000. =============================================================================== [View Less]

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Hyper Transport init for M4A785T-M
by Denis 'GNUtoo' Carikli 13 Apr '12

13 Apr '12

Hi, I've still my screen flickering issues(screen flickers for resolutions which are superior to 832x624 ) on the M4A785T-M mainboard. I've been investigating and here's what I found: In src/southbridge/amd/rs780/early_setup.c there is: printk(BIOS_INFO, "rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq); In the rs780_htinit function, which prints 0 as cpu_ht_freq. Then it assumes the CPU is k8 (I've a fam10h: model name : AMD Athlon(tm) II X2 250 Processor) and it doesn't do the … [View More]

1 1

ASUS M2V partial success, help needed (Was: Re: ASUS M2V problems)
by G 13 Apr '12

13 Apr '12

On Wed, Apr 11, 2012 at 10:48 AM, G <tjmadwja(a)gmail.com> wrote: > On Tue, Apr 10, 2012 at 5:26 PM, Marc Jones <marcj303(a)gmail.com> wrote: >> On Tue, Apr 10, 2012 at 7:37 AM, G <tjmadwja(a)gmail.com> wrote: >>> Hi, >>> >>> I'm trying to get coreboot onto my old ASUS M2V (rev. 1.01g) >>> motherboard, but so far I've had no luck. I'm currently trying to >>> get the coreinfo payload running, as that seems like the simplest … [View More]>>> test case (I've also tried seabios, and failed). >>> >>> After flashing, when I boot, nothing happens. No beeps, the >>> monitor remains in power-save mode, the keyboard doesn't respond >>> to any keypresses (not even holding down several keys for a long >>> time generates any beeps), no blinking status LEDs, nothing on >>> the serial port. Nothing. >>> >>> I've tried with two different revisions, one from 2010-11-24 (the >>> one that adds S3 support for ASUS M2V), and one from 2012-02-21 >>> (all later revisions fail to compile with lots of different CBMEM >>> problems). >>> >>> In the 2010-11-24 revision, I've had to add >>> reg++; reg--; >>> in src/northbridge/amd/amdk8/raminit_f_dqs.c:setup_mtrr_dqs() and >>> regm3++; regm3--; >>> in src/southbridge/via/vt8237r/vt8237_ctrl.c:vt8237_cfg() to get >>> rid of warnings about unused variables. >>> >>> Flashing is done by simply running: >>> ./flashrom -V -w coreboot.rom -c W39V040C >>> >>> Does anyone here have any idea what might be wrong? Anyone got a >>> working .config, tips to use a certain known working revision, a >>> know working version of flashrom (although flashing two different >>> versions of ASUS's BIOS using flashrom works well, so I'm >>> guessing neither flashrom nor my usage of it is to blame), a >>> working coreboot.rom they can share, or anything else that might >>> help me move forward? >>> >>> Using Debian unstable to build, if that's any help. >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> http://www.coreboot.org/mailman/listinfo/coreboot >> >> >> Hi, >> >> You will need to capture some output from coreboot to find where your >> system is having problems. >> >> http://www.coreboot.org/FAQ#How_do_I_use_a_null-modem_cable_to_get_coreboot… > > Thanks for the reply, but unfortunately, as I wrote in my > original mail, I get nothing on the serial port. [snip] I've had some partial success, after fiddling around with my config options. Adding more debug output gives activity on the serial port, but still nothing on the display and no beeps, or reactions from the keyboard. Attached are both my current .config and the output generated over the serial line, as captured by minicom on another machine. This is from an ASUS M2V motherboard, with an AMD Sempron 2800+ CPU (family 15, model 79, stepping 2 according to /proc/cpuinfo), two Kingston KVR667D2N5K2/2G memory sticks (total 2GB RAM), and an ASUS EAX300LE-A334C/TD (EAX300/TD/P/128M/A) graphics card (I have also tried with an old ATI PCI MACH64 card from 1996, no difference). If anyone could tell me what I'm doing wrong, or at least what I should try next, I'd be grateful. [View Less]

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Patch merged into coreboot/master: 6967e3f kconfig: Fix 'make gconfig'.
by gerrit＠coreboot.org 13 Apr '12

13 Apr '12

the following patch was just integrated into master: commit 6967e3f7239b3afe9c73ac97c6035c52d828b1a2 Author: Uwe Hermann <uwe(a)hermann-uwe.de> Date: Thu Apr 12 21:39:27 2012 +0200 kconfig: Fix 'make gconfig'. Change-Id: Id2d0735d875b40e131fc2aada27435fdcbacc8cb Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Apr 13 10:51:39 2012, giving +2 See http://review.coreboot.org/891 for details. -gerrit

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Patch merged into coreboot/master: e1c24d5 Bifferboard: Fix MAINBOARD_PART_NUMBER.
by gerrit＠coreboot.org 13 Apr '12

13 Apr '12

the following patch was just integrated into master: commit e1c24d5e477e497d993697311ef57b33fbc2ba1f Author: Uwe Hermann <uwe(a)hermann-uwe.de> Date: Thu Apr 12 22:48:57 2012 +0200 Bifferboard: Fix MAINBOARD_PART_NUMBER. Change-Id: I4acbeee8a0d26fae220ac22940b6f924e19af19c Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build-Tested: build bot (Jenkins) at Thu Apr 12 23:06:40 2012, giving +1 Reviewed-By: Rudolf Marek <r.marek(a)assembler.cz> at Fri Apr … [View More]

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New patch to review for coreboot: 3aeb337 Intel e7505: refactor only
by Kyösti Mälkki 13 Apr '12

13 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/896 -gerrit commit 3aeb3375fd4a681d42453fd8cd27792ce7fb25e2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Apr 12 22:59:41 2012 +0300 Intel e7505: refactor only Drop comments (from e7501 era) which no longer seem to apply with e7505. Write the semi-constant D0:F0 table as code. Some register settings seem to be in … [View More]different order compared with vendor BIOS, and will be handled by follow-up patches. Split RCOMP register copy function in two parts. Change-Id: I8739d3b2bbad5861118e8b16ccea1dd86991204f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/e7505/raminit.c | 462 +++++++-------------------------- 1 files changed, 93 insertions(+), 369 deletions(-) diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index e98a042..e8fa263 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -100,228 +100,37 @@ static const uint8_t dual_channel_parameters[] = { SPD_NUM_BANKS_PER_SDRAM }; - /* - * Table: constant_register_values - */ -static const long constant_register_values[] = { - /* SVID - Subsystem Vendor Identification Register - * 0x2c - 0x2d - * [15:00] Subsytem Vendor ID (Indicates system board vendor) - */ - /* SID - Subsystem Identification Register - * 0x2e - 0x2f - * [15:00] Subsystem ID + /* Comments here are remains of e7501 or even 855PM. + * They might be partially (in)correct for e7505. */ - // Not everyone wants to be Super Micro Computer, Inc. - // The mainboard should set this if desired. - // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16), - /* Undocumented - * (DRAM Read Timing Control, if similar to 855PM?) - * 0x80 - 0x81 + /* (DRAM Read Timing Control, if similar to 855PM?) + * 0x80 - 0x81 documented differently for e7505 * This register has something to do with CAS latencies, * possibily this is the real chipset control. * At 0x00 CAS latency 1.5 works. * At 0x06 CAS latency 2.5 works. * At 0x01 CAS latency 2.0 works. - */ - /* This is still undocumented in e7501, but with different values + * + * This is still undocumented in e7501, but with different values * CAS 2.0 values taken from Intel BIOS settings, others are a guess * and may be terribly wrong. Old values preserved as comments until I * figure this out for sure. * e7501 docs claim that CAS1.5 is unsupported, so it may or may not * work at all. * Steven James 02/06/2003 - */ - /* NOTE: values now configured in configure_e7501_cas_latency() based + * + * NOTE: values now configured in configure_e7501_cas_latency() based * on SPD info and total number of DIMMs (per Intel) */ - /* FDHC - Fixed DRAM Hole Control - * 0x58 + /* FDHC - Fixed DRAM Hole Control ??? + * 0x58 undocumented for e7505, memory hole in southbridge configuration? * [7:7] Hole_Enable * 0 == No memory Hole * 1 == Memory Hole from 15MB to 16MB * [6:0] Reserved - * - * PAM - Programmable Attribute Map - * 0x59 [1:0] Reserved - * 0x59 [5:4] 0xF0000 - 0xFFFFF - * 0x5A [1:0] 0xC0000 - 0xC3FFF - * 0x5A [5:4] 0xC4000 - 0xC7FFF - * 0x5B [1:0] 0xC8000 - 0xCBFFF - * 0x5B [5:4] 0xCC000 - 0xCFFFF - * 0x5C [1:0] 0xD0000 - 0xD3FFF - * 0x5C [5:4] 0xD4000 - 0xD7FFF - * 0x5D [1:0] 0xD8000 - 0xDBFFF - * 0x5D [5:4] 0xDC000 - 0xDFFFF - * 0x5E [1:0] 0xE0000 - 0xE3FFF - * 0x5E [5:4] 0xE4000 - 0xE7FFF - * 0x5F [1:0] 0xE8000 - 0xEBFFF - * 0x5F [5:4] 0xEC000 - 0xEFFFF - * 00 == DRAM Disabled (All Access go to memory mapped I/O space) - * 01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space) - * 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space) - * 11 == Normal (All Access go to DRAM) - */ - - // Map all legacy ranges to DRAM - 0x58, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24), - 0x5C, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24), - - /* DRB - DRAM Row Boundary Registers - * 0x60 - 0x6F - * An array of 8 byte registers, which hold the ending - * memory address assigned to each pair of DIMMS, in 64MB - * granularity. - */ - // Conservatively say each row has 64MB of ram, we will fix this up later - // NOTE: These defaults allow us to prime all of the DIMMs on the board - // without jumping through 36-bit adddressing hoops, even if the - // total memory is > 4 GB. Changing these values may break do_ram_command()! - 0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24), -// 0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24), - 0x64, 0x00000000, (0x04 << 0) | (0x04 << 8) | (0x04 << 16) | (0x04 << 24), - - /* DRA - DRAM Row Attribute Register - * 0x70 Row 0,1 - * 0x71 Row 2,3 - * 0x72 Row 4,5 - * 0x73 Row 6,7 - * [7:7] Device width for Odd numbered rows - * 0 == 8 bits wide x8 - * 1 == 4 bits wide x4 - * [6:4] Row Attributes for Odd numbered rows - * 010 == 8KB (for dual-channel) - * 011 == 16KB (for dual-channel) - * 100 == 32KB (for dual-channel) - * 101 == 64KB (for dual-channel) - * Others == Reserved - * [3:3] Device width for Even numbered rows - * 0 == 8 bits wide x8 - * 1 == 4 bits wide x4 - * [2:0] Row Attributes for Even numbered rows - * 010 == 8KB (for dual-channel) - * 011 == 16KB (for dual-channel) - * 100 == 32KB (for dual-channel) - * 101 == 64KB (This page size appears broken) - * Others == Reserved */ - // NOTE: overridden by configure_e7501_row_attributes(), later - 0x70, 0x00000000, 0, - - /* DRT - DRAM Timing Register - * 0x78 - * [31:30] Reserved - * [29:29] Back to Back Write-Read Turn Around - * 0 == 3 clocks between WR-RD commands - * 1 == 2 clocks between WR-RD commands - * [28:28] Back to Back Read-Write Turn Around - * 0 == 5 clocks between RD-WR commands - * 1 == 4 clocks between RD-WR commands - * [27:27] Back to Back Read Turn Around - * 0 == 4 clocks between RD commands - * 1 == 3 clocks between RD commands - * [26:24] Read Delay (tRD) - * 000 == 7 clocks - * 001 == 6 clocks - * 010 == 5 clocks - * Others == Reserved - * [23:19] Reserved - * [18:16] DRAM idle timer - * 000 == infinite - * 011 == 16 dram clocks - * 001 == 0 clocks - * [15:11] Reserved - * [10:09] Active to Precharge (tRAS) - * 00 == 7 clocks - * 01 == 6 clocks - * 10 == 5 clocks - * 11 == Reserved - * [08:06] Reserved - * [05:04] Cas Latency (tCL) - * 00 == 2.5 Clocks - * 01 == 2.0 Clocks - * 10 == Reserved (was 1.5 Clocks for E7500) - * 11 == Reserved - * [03:03] Write Ras# to Cas# Delay (tRCD) - * 0 == 3 DRAM Clocks - * 1 == 2 DRAM Clocks - * [02:01] Read RAS# to CAS# Delay (tRCD) - * 00 == reserved - * 01 == reserved - * 10 == 3 DRAM Clocks - * 11 == 2 DRAM Clocks - * [00:00] DRAM RAS# to Precharge (tRP) - * 0 == 3 DRAM Clocks - * 1 == 2 DRAM Clocks - */ - - // Some earlier settings: - /* Most aggressive settings possible */ -// 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|CAS_LATENCY|(1<<3)|(1<<1)|(1<<0), -// 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0), -// 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0), - - // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and - // Back-to-Back Write-Read Turnaround. All others are configured based on SPD. -// 0x78, 0xD7F8FFFF, (1 << 29) | (1 << 27) | (1 << 16), - 0x78, 0xC7F8FFFF, (0x03<<16)|(0x28<<24), - - /* FIXME why was I attempting to set a reserved bit? */ - /* 0x0100040f */ - - /* DRC - DRAM Contoller Mode Register - * 0x7c - * [31:30] Reserved - * [29:29] Initialization Complete - * 0 == Not Complete - * 1 == Complete - * [28:23] Reserved - * [22:22] Channels - * 0 == Single channel - * 1 == Dual Channel - * [21:20] DRAM Data Integrity Mode - * 00 == Disabled, no ECC - * 01 == Reserved - * 10 == Error checking, using chip-kill, with correction - * 11 == Reserved - * [19:18] DRB Granularity (Read-Only) - * 00 == 32 MB quantities (single channel mode) - * 01 == 64 MB quantities (dual-channel mode) - * 10 == Reserved - * 11 == Reserved - * [17:17] (Intel Undocumented) should always be set to 1 (SJM: comment inconsistent with current setting, below) - * [16:16] Command Per Clock - Address/Control Assertion Rule (CPC) - * 0 == 2n Rule - * 1 == 1n rule - * [15:11] Reserved - * [10:08] Refresh mode select - * 000 == Refresh disabled - * 001 == Refresh interval 15.6 usec - * 010 == Refresh interval 7.8 usec - * 011 == Refresh interval 64 usec - * 111 == Refresh every 64 clocks (fast refresh) - * [07:07] Reserved - * [06:04] Mode Select (SMS) - * 000 == Reserved (was Self Refresh Mode in E7500) - * 001 == NOP Command - * 010 == All Banks Precharge - * 011 == Mode Register Set - * 100 == Extended Mode Register Set - * 101 == Reserved - * 110 == CBR Refresh - * 111 == Normal Operation - * [03:00] Reserved - */ -// .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8), -// .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8), -// .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8), - - // Default to dual-channel mode, ECC, 1-clock address/cmd hold - // NOTE: configure_e7501_dram_controller_mode() configures further -// 0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8), - 0x7c, 0xffcef8f7, 0x00210008, /* Another Intel undocumented register * 0x88 - 0x8B @@ -336,118 +145,8 @@ static const long constant_register_values[] = { * 0 == Normal operation? * 1 == Reset? */ - // NOTE: Some factory BIOSs don't do this. - // Doesn't seem to matter either way. - 0x88, 0xffffff00, 0x80, - - /* CLOCK_DIS - CK/CK# Disable Register - * 0x8C - * [7:7] DDR Frequency - * 0 == 100 MHz (200 MHz data rate) - * 1 == 133 MHz (266 MHz data rate) - * [6:4] Reserved - * [3:3] CK3 - * 0 == Enable - * 1 == Disable - * [2:2] CK2 - * 0 == Enable - * 1 == Disable - * [1:1] CK1 - * 0 == Enable - * 1 == Disable - * [0:0] CK0 - * 0 == Enable - * 1 == Disable - */ - // NOTE: Disable all clocks initially; turn ones we need back on - // in enable_e7501_clocks() - 0x8C, 0xfffffff0, 0xf, - - /* TOLM - Top of Low Memory Register - * 0xC4 - 0xC5 - * [15:11] Top of low memory (TOLM) - * The address below 4GB that should be treated as RAM, - * on a 128MB granularity. - * [10:00] Reserved - */ - /* REMAPBASE - Remap Base Address Regsiter - * 0xC6 - 0xC7 - * [15:10] Reserved - * [09:00] Remap Base Address [35:26] 64M aligned - * Bits [25:0] are assumed to be 0. - */ - - // NOTE: TOLM overridden by configure_e7501_ram_addresses() - 0xc4, 0xfc0007ff, (0x2000 << 0) | (0x3ff << 16), - - /* REMAPLIMIT - Remap Limit Address Register - * 0xC8 - 0xC9 - * [15:10] Reserved - * [09:00] Remap Limit Address [35:26] 64M aligned - * When remaplimit < remapbase the remap window is disabled. - */ - 0xc8, 0xfffffc00, 0, - - /* DVNP - Device Not Present Register - * 0xE0 - 0xE1 - * [15:05] Reserved - * [04:04] Device 4 Function 1 Present - * 0 == Present - * 1 == Absent - * [03:03] Device 3 Function 1 Present - * 0 == Present - * 1 == Absent - * [02:02] Device 2 Function 1 Present - * 0 == Present - * 1 == Absent - * [01:01] Reserved - * [00:00] Device 0 Function 1 Present - * 0 == Present - * 1 == Absent - */ - - // Enable D0:D1, disable D2:F1, D3:F1, D4:F1 -// 0xe0, 0xffffffe2, (1 << 4) | (1 << 3) | (1 << 2) | (0 << 0), - 0xe0, 0xfffffffa, 0x0, - - // Undocumented - 0xd8, 0xffff9fff, 0x00000000, - - // Undocumented - this is pure conjecture based on similarity to 855PM - /* MCHTST - MCH Test Register - * 0xF4 - 0xF7 - * [31:31] Purpose unknown - * [30:30] Purpose unknown - * [29:23] Unknown - not used? - * [22:22] System Memory MMR Enable - * 0 == Disable: mem space and BAR at 0x14 are not accessible - * 1 == Enable: mem space and BAR at 0x14 are accessible - * [21:20] Purpose unknown - * [19:02] Unknown - not used? - * [01:01] D6EN (Device #6 enable) - * 0 == Disable - * 1 == Enable - * [00:00] Unknown - not used? - */ - -// 0xf4, 0x3f8ffffd, 0x40300002, - -#ifdef SUSPICIOUS_LOOKING_CODE - // SJM: Undocumented. - // This will access D2:F0:0x50, is this correct?? - 0x1050, 0xffffffcf, 0x00000030, -#endif -}; - - /* DDR RECOMP tables */ -#if 0 -// Slew table for 1x drive? -static const uint32_t 1x_slew_table[] = { - 0x44332211, 0xc9776655, 0xffffffff, 0xffffffff, - 0x22111111, 0x55444332, 0xfffca876, 0xffffffff, -}; -#endif +/* DDR RECOMP tables */ // Slew table for 2x drive? static const uint32_t slew_2x[] = { 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff, @@ -995,6 +694,9 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) dimm_start_64M_multiple = 0; + /* FIXME: Only address the number of rows present in the system? + * Seems like rows 4-7 overlap with 0-3. + */ for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) { uint8_t dimm_end_64M_multiple = pci_read_config8(MCHDEV, DRB_ROW_0 + i); @@ -1003,7 +705,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) dimm_start_address &= 0x3ffffff; dimm_start_address |= dimm_start_64M_multiple << 26; read32(dimm_start_address); - // Set the start of the next DIMM + // Set the start of the next DIMM dimm_start_64M_multiple = dimm_end_64M_multiple; } } @@ -1756,47 +1458,6 @@ static void RAM_RESET_DDR_PTR(void) } /** - * Set E7501 registers that are either independent of DIMM specifics, or - * establish default settings that will be overridden when we learn the - * specifics. - * - * This sets PCI configuration registers to known good values based on the - * table 'constant_register_values', which are a triple of configuration - * register offset, mask, and bits to set. - */ -static void ram_set_d0f0_regs(void) -{ - int i; - int num_values = ARRAY_SIZE(constant_register_values); - - ASSERT((num_values % 3) == 0); // Bad table? - - for (i = 0; i < num_values; i += 3) { - - uint32_t register_offset = constant_register_values[i]; - uint32_t bits_to_mask = constant_register_values[i + 1]; - uint32_t bits_to_set = constant_register_values[i + 2]; - uint32_t register_value; - - // It's theoretically possible to set values for something other than D0:F0, - // but it's not typically done here - ASSERT(!(register_offset & 0xFFFFFF00)); - - // bits_to_mask and bits_to_set should not reference the same bits - // Again, not strictly an error, but flagged as a potential bug - ASSERT((bits_to_mask & bits_to_set) == 0); - - register_value = - pci_read_config32(MCHDEV, register_offset); - register_value &= bits_to_mask; - register_value |= bits_to_set; - - pci_write_config32(MCHDEV, register_offset, - register_value); - } -} - -/** * Copy 64 bytes from one location to another. * * @param src_addr TODO @@ -1822,20 +1483,13 @@ static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr) * Comments below are conjecture based on apparent similarity between the * E7501 and these two chips. */ -static void ram_set_rcomp_regs(void) +static void rcomp_copy_registers(void) { uint32_t dword; - uint8_t strength_control, revision; + uint8_t strength_control; RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n"); - /* Set the RCOMP MMIO base address */ - mchtest_control(RCOMP_BAR_ENABLE); - pci_write_config32(MCHDEV, SMRBASE, RCOMP_MMIO); - - /* Block RCOMP updates while we configure the registers */ - rcomp_smr_control(RCOMP_HOLD); - /* Begin to write the RCOMP registers */ write8(RCOMP_MMIO + 0x2c, 0x0); @@ -1902,7 +1556,6 @@ static void ram_set_rcomp_regs(void) write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x1a0); write16(RCOMP_MMIO + 0x4e, 0); - dword = read32(RCOMP_MMIO + 0x400); dword &= 0x7f7fffff; write32(RCOMP_MMIO + 0x400, dword); @@ -1910,18 +1563,27 @@ static void ram_set_rcomp_regs(void) dword = read32(RCOMP_MMIO + 0x408); dword &= 0x7f7fffff; write32(RCOMP_MMIO + 0x408, dword); +} + +static void ram_set_rcomp_regs(void) +{ + /* Set the RCOMP MMIO base address */ + mchtest_control(RCOMP_BAR_ENABLE); + pci_write_config32(MCHDEV, SMRBASE, RCOMP_MMIO); + /* Block RCOMP updates while we configure the registers */ + rcomp_smr_control(RCOMP_HOLD); + rcomp_copy_registers(); d060_control(D060_CMD_0); mchtest_control(MCHTST_CMD_0); - revision = pci_read_config8(MCHDEV, 0x08); + uint8_t revision = pci_read_config8(MCHDEV, 0x08); if (revision >= 3) { rcomp_smr_control(RCOMP_SMR_00); rcomp_smr_control(RCOMP_SMR_01); } rcomp_smr_control(RCOMP_RELEASE); - /* Wait 40 usec */ SLOW_DOWN_IO; @@ -2084,11 +1746,73 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) */ static void sdram_set_registers(const struct mem_controller *ctrl) { - RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); - DUMPNORTH(); + uint32_t dword; + uint16_t word; + uint8_t byte; ram_set_rcomp_regs(); - ram_set_d0f0_regs(); + + /* Enable 0:0.1, 0:2.1 */ + word = pci_read_config16(MCHDEV, DVNP); + word &= ~0x05; + pci_write_config16(MCHDEV, DVNP, word); + + /* Disable high-memory remap (power-on defaults, really) */ + pci_write_config16(MCHDEV, REMAPBASE, 0x03ff); + pci_write_config16(MCHDEV, REMAPLIMIT, 0x0); + + /* Disable legacy MMIO (0xC0000-0xEFFFF is DRAM) */ + int i; + pci_write_config8(MCHDEV, PAM_0, 0x30); + for (i=1; i<=6; i++) + pci_write_config8(MCHDEV, PAM_0 + i, 0x33); + + /* Conservatively say each row has 64MB of ram, we will fix this up later + * Initial TOLM 8 rows 64MB each (1<<3 * 1<<26) >> 16 = 1<<13 + * + * FIXME: Hard-coded limit to first four rows to prevent overlap! + */ + pci_write_config32(MCHDEV, DRB_ROW_0, 0x04030201); + pci_write_config32(MCHDEV, DRB_ROW_4, 0x04040404); + //pci_write_config32(MCHDEV, DRB_ROW_4, 0x08070605); + pci_write_config16(MCHDEV, TOLM, (1<<13)); + + /* DIMM clocks off */ + pci_write_config8(MCHDEV, CKDIS, 0xff); + + /* reset row attributes */ + pci_write_config32(MCHDEV, DRA, 0x0); + + // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and + // Back-to-Back Write-Read Turnaround. All others are configured based on SPD. + dword = pci_read_config32(MCHDEV, DRT); + dword &= 0xC7F8FFFF; + dword |= (0x28<<24)|(0x03<<16); + pci_write_config32(MCHDEV, DRT, dword); + + dword = pci_read_config32(MCHDEV, DRC); + dword &= 0xffcef8f7; + dword |= 0x00210008; + pci_write_config32(MCHDEV, DRC, dword); + + /* Undocumented */ + pci_write_config8(MCHDEV, 0x88, 0x80); + + /* Undocumented. Set much later in vendor BIOS. */ + byte = pci_read_config8(MCHDEV, 0xd9); + byte &= ~0x60; + pci_write_config8(MCHDEV, 0xd9, byte); + +#ifdef SUSPICIOUS_LOOKING_CODE + /* This will access D2:F0:0x50, is this correct?? + * Vendor BIOS reads Device ID before this is set. + * Undocumented in the p64h2 PCI-X bridge datasheet. + */ + byte = pci_read_config8(PCI_DEV(0,2,0), 0x50); + byte &= 0xcf; + byte |= 0x30 + pci_write_config8(PCI_DEV(0,2,0), 0x50, byte); +#endif uint8_t revision = pci_read_config8(MCHDEV, 0x08); if (revision >= 3) [View Less]

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New patch to review for coreboot: 705d2ea Intel e7505: handlers for undocumented registers
by Kyösti Mälkki 13 Apr '12

13 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/895 -gerrit commit 705d2eac86a12704489033c5a115ae8bae43f6f5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Apr 12 22:46:23 2012 +0300 Intel e7505: handlers for undocumented registers Makes the code a bit more readable, IMO. There is no clean way to implement this as the affected registers are undocumented. Seems … [View More]ROMCC cannot handle the enum. Also any of my future changes would not be even abuild tested as there is no longer a board with ROMCC and this chipset. E7505 chipset is CAR only from now on. Change-Id: I0e2d8ba0c7ed7cce46d9eafb8d8badf04cf75f7a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/e7505/raminit.c | 164 +++++++++++++++++++++------------ 1 files changed, 103 insertions(+), 61 deletions(-) diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 29eb42b..e98a042 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -486,51 +486,109 @@ static inline void local_mdelay(int i) #define EXTRA_DELAY DO_DELAY /*----------------------------------------------------------------------------- -Handle (undocumented) control bits in device 0:6.0 +Handle (undocumented) control bits MCHTST and PCI_DEV(0,6,0) -----------------------------------------------------------------------------*/ +typedef enum { + MCHTST_CMD_0, + D060_ENABLE, + D060_DISABLE, + RCOMP_BAR_ENABLE, + RCOMP_BAR_DISABLE, +} mchtst_cc; + +typedef enum { + D060_CMD_0, + D060_CMD_1, +} d060_cc; + +typedef enum { + RCOMP_HOLD, + RCOMP_RELEASE, + RCOMP_SMR_00, + RCOMP_SMR_01, +} rcomp_smr_cc; /** + * MCHTST - 0xF4 - 0xF7 -- Based on similarity to 855PM * + * [31:31] Purpose unknown + * [30:30] Purpose unknown + * [29:23] Unknown - not used? + * [22:22] System Memory MMR Enable + * 0 == Disable: mem space and BAR at 0x14 are not accessible + * 1 == Enable: mem space and BAR at 0x14 are accessible + * [21:20] Purpose unknown + * [19:02] Unknown - not used? + * [01:01] D6EN (Device #6 enable) + * 0 == Disable + * 1 == Enable + * [00:00] Unknown - not used? */ -static void ram_handle_d060_1(void) +static inline void mchtest_control(mchtst_cc cmd) { - uint32_t dword; - - dword = pci_read_config32(MCHDEV, MCHTST); - dword |= 0x02; + uint32_t dword = pci_read_config32(MCHDEV, MCHTST); + switch (cmd) { + case MCHTST_CMD_0: + dword &= ~(3 << 30); + break; + case RCOMP_BAR_ENABLE: + dword |= (1 << 22); + break; + case RCOMP_BAR_DISABLE: + dword &= ~(1 << 22); + break; + case D060_ENABLE: + dword |= (1 << 1); + break; + case D060_DISABLE: + dword &= ~(1 << 1); + break; + }; pci_write_config32(MCHDEV, MCHTST, dword); +} - dword = pci_read_config32(D060DEV, 0xf0); - dword |= 0x04; - pci_write_config32(D060DEV, 0xf0, dword); - dword = pci_read_config32(MCHDEV, MCHTST); - dword &= ~0x02; - pci_write_config32(MCHDEV, MCHTST, dword); +/** + * + */ +static inline void d060_control(d060_cc cmd) +{ + mchtest_control(D060_ENABLE); + uint32_t dword = pci_read_config32(D060DEV, 0xf0); + switch (cmd) { + case D060_CMD_0: + dword |= (1 << 2); + break; + case D060_CMD_1: + dword |= (3 << 27); + break; + } + pci_write_config32(D060DEV, 0xf0, dword); + mchtest_control(D060_DISABLE); } /** * */ -static void ram_handle_d060_2(void) +static inline void rcomp_smr_control(rcomp_smr_cc cmd) { - uint32_t dword; - uint8_t revision; - - revision = pci_read_config8(MCHDEV, 0x08); - if (revision >= 3) { - dword = pci_read_config32(MCHDEV, MCHTST); - dword |= 0x02; - pci_write_config32(MCHDEV, MCHTST, dword); - - dword = pci_read_config32(D060DEV, 0xf0); - dword |= 0x18000000; - pci_write_config32(D060DEV, 0xf0, dword); - - dword = pci_read_config32(MCHDEV, MCHTST); - dword &= ~0x02; - pci_write_config32(MCHDEV, MCHTST, dword); + uint32_t dword = read32(RCOMP_MMIO + SMRCTL); + switch (cmd) { + case RCOMP_HOLD: + dword |= (1 << 9); + break; + case RCOMP_RELEASE: + dword &= ~((1 << 9) | (3 << 0)); + dword |= (1 << 10) | (1 << 0); + break; + case RCOMP_SMR_00: + dword &= ~(1 << 8); + break; + case RCOMP_SMR_01: + dword |= (1 << 10) | (1 << 8); + break; } + write32(RCOMP_MMIO + SMRCTL, dword); } /*----------------------------------------------------------------------------- @@ -1771,18 +1829,12 @@ static void ram_set_rcomp_regs(void) RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n"); - /*enable access to the rcomp bar */ - dword = pci_read_config32(MCHDEV, MCHTST); - dword |= (1 << 22); - pci_write_config32(MCHDEV, MCHTST, dword); - - // Set the RCOMP MMIO base address + /* Set the RCOMP MMIO base address */ + mchtest_control(RCOMP_BAR_ENABLE); pci_write_config32(MCHDEV, SMRBASE, RCOMP_MMIO); - // Block RCOMP updates while we configure the registers - dword = read32(RCOMP_MMIO + SMRCTL); - dword |= (1 << 9); - write32(RCOMP_MMIO + SMRCTL, dword); + /* Block RCOMP updates while we configure the registers */ + rcomp_smr_control(RCOMP_HOLD); /* Begin to write the RCOMP registers */ write8(RCOMP_MMIO + 0x2c, 0x0); @@ -1859,36 +1911,23 @@ static void ram_set_rcomp_regs(void) dword &= 0x7f7fffff; write32(RCOMP_MMIO + 0x408, dword); - ram_handle_d060_1(); - - dword = pci_read_config32(MCHDEV, MCHTST); - dword &= 0x3fffffff; - pci_write_config32(MCHDEV, MCHTST, dword); + d060_control(D060_CMD_0); + mchtest_control(MCHTST_CMD_0); revision = pci_read_config8(MCHDEV, 0x08); if (revision >= 3) { - dword = read32(RCOMP_MMIO + SMRCTL); - dword &= ~0x100; - write32(RCOMP_MMIO + SMRCTL, dword); - dword = read32(RCOMP_MMIO + SMRCTL); - dword |= 0x500; - write32(RCOMP_MMIO + SMRCTL, dword); + rcomp_smr_control(RCOMP_SMR_00); + rcomp_smr_control(RCOMP_SMR_01); } - dword = read32(RCOMP_MMIO + SMRCTL); - dword &= ~0x203; - dword |= 0x401; - write32(RCOMP_MMIO + SMRCTL, dword); + rcomp_smr_control(RCOMP_RELEASE); + /* Wait 40 usec */ SLOW_DOWN_IO; - // Clear the RCOMP MMIO base address + /* Clear the RCOMP MMIO base address */ pci_write_config32(MCHDEV, SMRBASE, 0); - /*disable access to the rcomp bar */ - dword = pci_read_config32(MCHDEV, MCHTST); - dword &= ~(1 << 22); - pci_write_config32(MCHDEV, MCHTST, dword); - + mchtest_control(RCOMP_BAR_DISABLE); } /*----------------------------------------------------------------------------- @@ -2050,7 +2089,10 @@ static void sdram_set_registers(const struct mem_controller *ctrl) ram_set_rcomp_regs(); ram_set_d0f0_regs(); - ram_handle_d060_2(); + + uint8_t revision = pci_read_config8(MCHDEV, 0x08); + if (revision >= 3) + d060_control(D060_CMD_1); } /** [View Less]

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Patch set updated for coreboot: ec59075 Fix messy code in ALIB
by Zheng Bao 12 Apr '12

12 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/885 -gerrit commit ec59075b9eec1e99e1a8febebffbd78329e0ad41 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Apr 13 13:48:50 2012 +0800 Fix messy code in ALIB The address return from PICK_ALIB is not protected by Coreboot. We need to use the "current", which is the correct way to allocate the ACPI table. Change-Id: … [View More]I250066eb5f755275f75c37789ce8760de35b046b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/dinar/acpi_tables.c | 4 ++-- src/mainboard/amd/inagua/acpi_tables.c | 7 +++---- src/mainboard/amd/persimmon/acpi_tables.c | 7 +++---- src/mainboard/amd/south_station/acpi_tables.c | 7 +++---- src/mainboard/amd/union_station/acpi_tables.c | 7 +++---- src/mainboard/asrock/e350m1/acpi_tables.c | 7 +++---- src/mainboard/supermicro/h8qgi/acpi_tables.c | 4 ++-- 7 files changed, 19 insertions(+), 24 deletions(-) diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index 741ba99..4ebe5be 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -264,9 +264,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); + acpi_add_table(rsdp, (void *)alib); } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index e521b4b..c79614e 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -230,11 +230,10 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + acpi_add_table(rsdp, (void *)alib); + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 00a08d2..39de42b 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -230,11 +230,10 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + acpi_add_table(rsdp, (void *)alib); + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index c49a8e2..55bb564 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -230,11 +230,10 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + acpi_add_table(rsdp, (void *)alib); + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index c49a8e2..55bb564 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -230,11 +230,10 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + acpi_add_table(rsdp, (void *)alib); + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index c49a8e2..55bb564 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -230,11 +230,10 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + acpi_add_table(rsdp, (void *)alib); + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 7b97a92..1111a2a 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -264,9 +264,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + alib = (acpi_header_t *) current; current += alib->length; - acpi_add_table(rsdp,alib); + acpi_add_table(rsdp, (void *)alib); } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } [View Less]

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Patch set updated for coreboot: 915f427 S3 code in coreboot public folder.
by Zheng Bao 12 Apr '12

12 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/623 -gerrit commit 915f42708f3dad4f34d06fd8af89ca8d90177b4b Author: zbao <fishbaozi(a)gmail.com> Date: Fri Apr 13 13:42:15 2012 +0800 S3 code in coreboot public folder. 1. Move the Stack to high memory. 2. Restore the MTRR before Coreboot jump to the wakeup vector. Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a Signed-off-by: … [View More]Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/Kconfig | 4 + src/arch/x86/boot/tables.c | 1 + src/cpu/amd/agesa/Makefile.inc | 2 + src/cpu/amd/agesa/cache_as_ram.inc | 7 + src/cpu/amd/agesa/family14/Kconfig | 5 + src/cpu/amd/agesa/family14/model_14_init.c | 125 +++++---- src/cpu/amd/agesa/s3_resume.c | 326 ++++++++++++++++++++++ src/cpu/amd/agesa/s3_resume.h | 42 +++ src/include/cbmem.h | 10 +- src/lib/cbmem.c | 1 + src/northbridge/amd/agesa/Kconfig | 4 + src/northbridge/amd/agesa/family14/northbridge.c | 77 ++++-- 12 files changed, 529 insertions(+), 75 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index b0261d9..149568a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -222,6 +222,10 @@ config HAVE_INIT_TIMER default n if UDELAY_IO default y +config HIGH_SCRATCH_MEMORY_SIZE + hex + default 0x0 + config HAVE_MAINBOARD_RESOURCES bool default n diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index b7dc4fe..70f3117 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -237,6 +237,7 @@ struct lb_memory *write_tables(void) * the result right now. If it fails, ACPI resume will be disabled. */ cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); + cbmem_add(CBMEM_ID_RESUME_SCRATCH, CONFIG_HIGH_SCRATCH_MEMORY_SIZE); #endif #if CONFIG_MULTIBOOT diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index fb536dd..696173d 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -21,5 +21,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15 +romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c ramstage-y += apic_timer.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index f328db4..2124bf3 100755 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -86,6 +86,13 @@ disable_cache_as_ram: /* Save return stack */ movd %esp, %xmm0 + /* Disable cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + invd + AMD_DISABLE_STACK /* Restore the return stack */ diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 702270c..6713660 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -67,3 +67,8 @@ config HAVE_INIT_TIMER default y depends on CPU_AMD_AGESA_FAMILY14 +config HIGH_SCRATCH_MEMORY_SIZE + hex + # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) + default 0x71000 + depends on CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 577da1b..d90695a 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -32,6 +32,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam14.h> +#include <arch/acpi.h> +#include <cpu/amd/agesa/s3_resume.h> #define MCI_STATUS 0x401 @@ -57,69 +59,84 @@ void wrmsr_amd(u32 index, msr_t msr) static void model_14_init(device_t dev) { - printk(BIOS_DEBUG, "Model 14 Init.\n"); - - u8 i; - msr_t msr; - int msrno; + u32 i; + msr_t msr; #if CONFIG_LOGICAL_CPUS == 1 - u32 siblings; + u32 siblings; +#endif + printk(BIOS_DEBUG, "Model 14 Init.\n"); + + disable_cache (); + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14. + * TODO: + * amd_setup_mtrrs(); + */ + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + /* Set shadow WB, RdMEM, WrMEM */ + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.hi = msr.lo = 0x1e1e1e1e; + wrmsr(0x250, msr); + wrmsr(0x258, msr); + for (i = 0x268; i <= 0x26f; i++) + wrmsr(i, msr); + + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type == 3) + restore_mtrr(); #endif - disable_cache (); - /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - - // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs - msr.lo = msr.hi = 0; - wrmsr (0x259, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); - - /* disable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - enable_cache (); - - /* zero the machine check error status registers */ - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < 6; i++) { - wrmsr(MCI_STATUS + (i * 4), msr); - } - - /* Enable the local cpu apics */ - setup_lapic(); + x86_mtrr_check(); + x86_enable_cache(); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + /* Enable the local cpu apics */ + setup_lapic(); #if CONFIG_LOGICAL_CPUS == 1 - siblings = cpuid_ecx(0x80000008) & 0xff; - - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } #endif - /* DisableCf8ExtCfg */ - msr = rdmsr(NB_CFG_MSR); - msr.hi &= ~(1 << (46 - 32)); - wrmsr(NB_CFG_MSR, msr); + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); - /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); + printk(BIOS_SPEW, "%s done.\n", __func__); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c new file mode 100644 index 0000000..16c959a --- /dev/null +++ b/src/cpu/amd/agesa/s3_resume.c @@ -0,0 +1,326 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/x86/cache.h> +#if CONFIG_WRITE_HIGH_TABLES +#include <cbmem.h> +#endif +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <string.h> +#include "Porting.h" +#include "BiosCallOuts.h" +#include "s3_resume.h" +#include "agesawrapper.h" + +#ifndef __PRE_RAM__ +#include "spi.h" +#endif + +void restore_mtrr(void) +{ + u32 msr; + volatile UINT32 *msrPtr = (volatile UINT32 *)S3_DATA_MTRR_POS; + msr_t msr_data; + + printk(BIOS_SPEW, "%s\n", __func__); + + disable_cache(); + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Now restore the Fixed MTRRs */ + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x250, msr_data); + + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x258, msr_data); + + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x259, msr_data); + + for (msr = 0x268; msr <= 0x26F; msr++) { + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(msr, msr_data); + } + + /* Disable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Restore the Variable MTRRs */ + for (msr = 0x200; msr <= 0x20F; msr++) { + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(msr, msr_data); + } + + /* Restore SYSCFG MTRR */ + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(SYS_CFG, msr_data); +} + +inline void *backup_resume(void) +{ + unsigned long high_ram_base; + void *resume_backup_memory; + + /* Start address of high memory tables */ + high_ram_base = (u32) get_cbmem_toc(); + + /* + * printk(BIOS_DEBUG, "CBMEM TOC is at: %x\n", (u32_t)high_ram_base); + * printk(BIOS_DEBUG, "CBMEM TOC 0-size:%x\n ",(u32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); + */ + + cbmem_reinit((u64) high_ram_base); + + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (((u32) resume_backup_memory == 0) + || ((u32) resume_backup_memory == -1)) { + printk(BIOS_ERR, "Error: resume_backup_memory: %x\n", + (u32) resume_backup_memory); + for (;;) ; + } + + return resume_backup_memory; +} + +void move_stack_high_mem(void) +{ + void *high_stack; + + high_stack = cbmem_find(CBMEM_ID_RESUME_SCRATCH); + memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE)); + + __asm__ + volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" + (high_stack - BSP_STACK_BASE_ADDR) + :); +} + +void OemAgesaSaveMtrr(void) +{ +#ifndef __PRE_RAM__ + u32 spi_address; + msr_t msr_data; + device_t dev; + u32 nvram_pos = S3_DATA_MTRR_POS; + u32 i; + + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Fixed MTRRs */ + msr_data = rdmsr(0x250); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + msr_data = rdmsr(0x258); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + msr_data = rdmsr(0x259); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + for (i = 0x268; i < 0x270; i++) { + msr_data = rdmsr(i); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + } + + /* Disable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Variable MTRRs */ + for (i = 0x200; i < 0x210; i++) { + msr_data = rdmsr(i); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + } + + /* SYS_CFG */ + msr_data = rdmsr(0xC0010010); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + /* TOM */ + msr_data = rdmsr(0xC001001A); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + /* TOM2 */ + msr_data = rdmsr(0xC001001D); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + +#endif +} + +void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data) +{ + AMD_CONFIG_PARAMS StdHeader; + if (S3DataType == S3DataTypeNonVolatile) { + *Data = (void *)S3_DATA_NONVOLATILE_POS; + *DataSize = *(UINTN *) (*Data); + *Data += 4; + } else { + *DataSize = *(UINTN *) S3_DATA_VOLATILE_POS; + *Data = (void *) GetHeapBase(&StdHeader); + memcpy((void *)(*Data), (void *)(S3_DATA_VOLATILE_POS + 4), *DataSize); + } +} + +#ifndef __PRE_RAM__ +u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) +{ + + u32 pos = S3_DATA_VOLATILE_POS; + u32 spi_address, data; + u32 nvram_pos; + device_t dev; + + if (S3DataType == S3DataTypeNonVolatile) { + pos = S3_DATA_NONVOLATILE_POS; + } else { /* S3DataTypeVolatile */ + pos = S3_DATA_VOLATILE_POS; + } + + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + + /* printk(BIOS_DEBUG, "spi_address=%x\n", spi_address); */ + read_spi_id((u8 *) spi_address); + write_spi_status((u8 *)spi_address, 0); + if (S3DataType == S3DataTypeNonVolatile) { + sector_erase_spi((u8 *) spi_address, S3_DATA_NONVOLATILE_POS); + } else { + sector_erase_spi((u8 *) spi_address, S3_DATA_VOLATILE_POS); + sector_erase_spi((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x1000); + sector_erase_spi((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x2000); + sector_erase_spi((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x3000); + } + + nvram_pos = 0; + dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos, DataSize); + + for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { + data = *(u32 *) (Data + nvram_pos); + dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos + 4, + *(u32 *) (Data + nvram_pos)); + } + + return AGESA_SUCCESS; +} +#endif + +void set_resume_cache(void) +{ + msr_t msr; + + /* disable fixed mtrr for now, it will be enabled by mtrr restore */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); + wrmsr(SYSCFG_MSR, msr); + + /* Enable caching for 0 - coreboot ram using variable mtrr */ + msr.lo = 0 | MTRR_TYPE_WRBACK; + msr.hi = 0; + wrmsr(MTRRphysBase_MSR(0), msr); + msr.lo = ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid; + msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; + wrmsr(MTRRphysMask_MSR(0), msr); + + /* Set the default memory type and disable fixed and enable variable MTRRs */ + msr.hi = 0; + msr.lo = (1 << 11); + wrmsr(MTRRdefType_MSR, msr); + + enable_cache(); +} + +void s3_resume(void) +{ + int status; + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + status = agesawrapper_amds3laterestore(); + if (status) + printk(BIOS_DEBUG, "error level: %x \n", (u32) status); + else + printk(BIOS_DEBUG, "passed.\n"); +} diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h new file mode 100644 index 0000000..22a7271 --- /dev/null +++ b/src/cpu/amd/agesa/s3_resume.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef S3_RESUME_H +#define S3_RESUME_H + +#define S3_DATA_NONVOLATILE_POS 0xFFFF4000 +#define S3_DATA_VOLATILE_POS 0xFFFF0000 +#define S3_DATA_MTRR_POS 0xFFFF3100 + +typedef enum { + S3DataTypeNonVolatile=0, ///< NonVolatile Data Type + S3DataTypeVolatile ///< Volatile Data Type +} S3_DATA_TYPE; + +void restore_mtrr(void); +void s3_resume(void); +inline void *backup_resume(void); +void set_resume_cache(void); +void move_stack_high_mem(void); + +u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data); +void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data); +void OemAgesaSaveMtrr (void); + +#endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index c55a7ca..33e2de4 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -28,17 +28,18 @@ #endif #if CONFIG_HAVE_ACPI_RESUME -#define HIGH_MEMORY_SIZE ((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE) -#define HIGH_MEMORY_SAVE ( HIGH_MEMORY_SIZE - HIGH_MEMORY_DEF_SIZE ) +#define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) +#define HIGH_MEMORY_SIZE (HIGH_MEMORY_SAVE + CONFIG_HIGH_SCRATCH_MEMORY_SIZE + HIGH_MEMORY_DEF_SIZE) /* Delegation of resume backup memory so we don't have to * (slowly) handle backing up OS memory in romstage.c */ #define CBMEM_BOOT_MODE 0x610 #define CBMEM_RESUME_BACKUP 0x614 -#else + +#else /* CONFIG_HAVE_ACPI_RESUME */ #define HIGH_MEMORY_SIZE HIGH_MEMORY_DEF_SIZE -#endif +#endif /* CONFIG_HAVE_ACPI_RESUME */ #define CBMEM_ID_FREESPACE 0x46524545 #define CBMEM_ID_GDT 0x4c474454 @@ -47,6 +48,7 @@ #define CBMEM_ID_PIRQ 0x49525154 #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_RESUME 0x5245534d +#define CBMEM_ID_RESUME_SCRATCH 0x52455343 #define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_MRCDATA 0x4d524344 diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index b09b070..e54e1c0 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -254,6 +254,7 @@ void cbmem_list(void) case CBMEM_ID_PIRQ: printk(BIOS_DEBUG, "IRQ TABLE "); break; case CBMEM_ID_MPTABLE: printk(BIOS_DEBUG, "SMP TABLE "); break; case CBMEM_ID_RESUME: printk(BIOS_DEBUG, "ACPI RESUME"); break; + case CBMEM_ID_RESUME_SCRATCH: printk(BIOS_DEBUG, "ACPISCRATCH"); break; case CBMEM_ID_SMBIOS: printk(BIOS_DEBUG, "SMBIOS "); break; case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break; case CBMEM_ID_CONSOLE: printk(BIOS_DEBUG, "CONSOLE "); break; diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 2ee921b..ebdda38 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -27,6 +27,10 @@ config CONSOLE_VGA_MULTI bool default n +config S3_VGA_ROM_RUN + bool + default n + source src/northbridge/amd/agesa/family10/Kconfig source src/northbridge/amd/agesa/family12/Kconfig source src/northbridge/amd/agesa/family14/Kconfig diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 15efe12..2647814 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -745,20 +745,46 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(device_t dev) { +extern u8 acpi_slp_type; + +static void domain_enable_resources(device_t dev) +{ u32 val; #if CONFIG_AMD_SB_CIMX + #if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + sb_After_Pci_Init(); + sb_Mid_Post_Init(); + } else { + sb_After_Pci_Restore_Init(); + } + #else sb_After_Pci_Init(); sb_Mid_Post_Init(); + #endif #endif /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n"); - val = agesawrapper_amdinitmid(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); + +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); } +#else + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); +#endif printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); } @@ -788,24 +814,41 @@ static void cpu_bus_set_resources(device_t dev) { pci_dev_set_resources(dev); } -static void cpu_bus_init(device_t dev) { - struct device_path cpu_path; +static u32 cpu_bus_scan(device_t dev, u32 max) +{ device_t cpu; - int apic_id; + struct device_path cpu_path; + int apic_id, cores_found; - initialize_cpus(dev->link_list); + /* There is only one node for fam14, but there may be multiple cores. */ + cpu = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (!cpu) + printk(BIOS_ERR, "ERROR: %02x:%02x.0 not found", 0, 0x18); - /* Build the AP cpu device path(s) */ - for (apic_id = 1; apic_id < CONFIG_MAX_CPUS; apic_id++) { + cores_found = (pci_read_config32(dev_find_slot(0,PCI_DEVFN(0x18,0x3)), 0xe8) >> 12) & 3; + printk(BIOS_DEBUG, " AP siblings=%d\n", cores_found); + + + for (apic_id = 0; apic_id <= cores_found; apic_id++) { cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = apic_id; - cpu = alloc_dev(dev->link_list, &cpu_path); - if (!cpu) - return; - cpu->enabled = 1; - cpu->path.apic.node_id = 0; - cpu->path.apic.core_id = apic_id; + cpu = alloc_find_dev(dev->link_list, &cpu_path); + if (cpu) { + cpu->enabled = 1; + cpu->path.apic.node_id = 0; + cpu->path.apic.core_id = apic_id; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } else { + cpu->enabled = 0; + } } + return max; +} + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); } /* North Bridge Structures */ @@ -844,7 +887,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = cpu_bus_set_resources, .enable_resources = NULL, .init = cpu_bus_init, - .scan_bus = NULL, + .scan_bus = cpu_bus_scan, }; static void root_complex_enable_dev(struct device *dev) { [View Less]

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Patch set updated for coreboot: 5ccfb7f S3 code in the mainboard.
by Zheng Bao 12 Apr '12

12 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/624 -gerrit commit 5ccfb7fc1276278529653e49d8c8faf67770ef25 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Apr 13 13:42:46 2012 +0800 S3 code in the mainboard. Persimmon is the demo board. Tested by Linux and Windows 7. Change-Id: I5ded942b51e63ebeb08ace0b202b4ed239b0c14c Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-… [View More]by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/persimmon/BiosCallOuts.c | 40 +++--- src/mainboard/amd/persimmon/BiosCallOuts.h | 4 +- src/mainboard/amd/persimmon/Kconfig | 1 + src/mainboard/amd/persimmon/PlatformGnbPcie.c | 2 +- .../amd/persimmon/PlatformGnbPcieComplex.h | 1 + src/mainboard/amd/persimmon/agesawrapper.c | 160 +++++++++++++++++++- src/mainboard/amd/persimmon/agesawrapper.h | 5 + src/mainboard/amd/persimmon/buildOpts.c | 6 +- src/mainboard/amd/persimmon/get_bus_conf.c | 21 ++- src/mainboard/amd/persimmon/mainboard.c | 16 ++- src/mainboard/amd/persimmon/romstage.c | 90 +++++++++-- 11 files changed, 296 insertions(+), 50 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 7323832..52eb9dd 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -119,8 +119,10 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams->BufferPointer = NULL; AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + printk(BIOS_SPEW, "%s BiosHeapBaseAddr: %x\n", __func__, (u32) BiosHeapBaseAddr); if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { /* First allocation */ @@ -229,26 +231,26 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_BUFFER_NODE *PrevNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *NextNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + /* Find target node to deallocate in list of allocated nodes. - Return AGESA_BOUNDS_CHK if the BufferHandle is not found + Return AGESA_BOUNDS_CHK if the BufferHandle is not found */ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); @@ -355,8 +357,8 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index d9e4497..071c73c 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -23,8 +23,8 @@ #include "Porting.h" #include "AGESA.h" -#define BIOS_HEAP_START_ADDRESS 0x00010000 -#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ +#define BIOS_HEAP_SIZE 0x20000 +#define BSP_STACK_BASE_ADDR 0x30000 typedef struct _BIOS_HEAP_MANAGER { //UINT32 AvailableSize; diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 9212e20..27e27a5 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES + select HAVE_ACPI_RESUME select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index 5e37f51..bdfcb66 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -23,6 +23,7 @@ #include "heapManager.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include "BiosCallOuts.h" #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -165,4 +166,3 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; } - diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index b50cb1a..a49be62 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -23,6 +23,7 @@ #include "Porting.h" #include "AGESA.h" #include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 6e9997f..6bba7ca 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -33,10 +33,13 @@ #include "cpuLateInit.h" #include "Dispatcher.h" #include "cpuCacheInit.h" +#include "heapManager.h" #include "amdlib.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" #include <arch/io.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cbmem.h> #define FILECODE UNASSIGNED_FILE_FILECODE @@ -209,7 +212,7 @@ agesawrapper_amdinitreset ( if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); return (UINT32)status; - } +} UINT32 agesawrapper_amdinitearly ( @@ -243,6 +246,17 @@ agesawrapper_amdinitearly ( return (UINT32)status; } +UINT32 GetHeapBase( + AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 high_heap; + + high_heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* base + high_stack_size */ + + return high_heap; +} + UINT32 agesawrapper_amdinitpost ( VOID @@ -272,7 +286,7 @@ agesawrapper_amdinitpost ( AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ - BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader); HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { @@ -496,6 +510,148 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } +#if CONFIG_HAVE_ACPI_RESUME == 1 +UINT32 +agesawrapper_amdinitresume ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amds3laterestore ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdS3LateParams, + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + + AmdCreateStruct (&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +#ifndef __PRE_RAM__ +UINT32 +agesawrapper_amdS3Save ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdInterfaceParams, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save (AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + S3DataType = S3DataTypeNonVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage + ); + } + + OemAgesaSaveMtrr(); + AmdReleaseStruct (&AmdInterfaceParams); + + return (UINT32)Status; +} +#endif /* #ifndef __PRE_RAM__ */ +#endif /* CONFIG_HAVE_ACPI_RESUME */ + UINT32 agesawrapper_amdlaterunaptask ( UINT32 Func, diff --git a/src/mainboard/amd/persimmon/agesawrapper.h b/src/mainboard/amd/persimmon/agesawrapper.h index 7bed570..7babd58 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.h +++ b/src/mainboard/amd/persimmon/agesawrapper.h @@ -84,7 +84,12 @@ UINT32 agesawrapper_amdreadeventlog (void); UINT32 agesawrapper_amdinitcpuio (void); UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdinitresume (void); +UINT32 agesawrapper_amdS3Save (void); +UINT32 agesawrapper_amds3laterestore (void); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); void *agesawrapper_getlateinitptr (int pick); +UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); + #endif diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 3e5b14e..389e1d4 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -120,8 +120,8 @@ #define AGESA_ENTRY_INIT_LATE TRUE #define AGESA_ENTRY_INIT_S3SAVE TRUE #define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -169,7 +169,7 @@ //#define BLDCFG_USE_HT_ASSIST TRUE //#define BLDCFG_USE_ATM_MODE TRUE //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE +#define BLDCFG_S3_LATE_RESTORE TRUE //#define BLDCFG_USE_32_BYTE_REFRESH FALSE //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE //#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 0142762..4c094ae 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -51,6 +51,9 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +#endif void get_bus_conf(void) { @@ -80,11 +83,20 @@ void get_bus_conf(void) * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + status = agesawrapper_amdS3Save(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } +#else status = agesawrapper_amdinitlate(); - if(status) { + if(status) printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - +#endif sbdn_sb800 = 0; for (i = 0; i < 3; i++) { @@ -124,7 +136,8 @@ void get_bus_conf(void) for (j = bus_sb800[2]; j < bus_isa; j++) bus_type[j] = 1; - /* I/O APICs: APIC ID Version State Address */ + + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 3b181a1..9a8428e 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -23,10 +23,13 @@ #include <arch/io.h> #include <boot/tables.h> #include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -//#include <southbridge/amd/sb800/sb800.h> +#include <southbridge/amd/sb800/sb800.h> +#include <arch/acpi.h> #include "chip.h" +#include "BiosCallOuts.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/amd/mtrr.h> void set_pcie_reset(void); void set_pcie_dereset(void); @@ -56,6 +59,14 @@ static void persimmon_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); +/* + * The mainboard is the first place that we get control in ramstage. Check + * for S3 resume and call the approriate AGESA/CIMx resume functions. + */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + acpi_slp_type = acpi_get_sleep_type(); +#endif + #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; uint32_t sys_mem; @@ -110,6 +121,7 @@ int add_mainboard_resources(struct lb_memory *mem) #endif return 0; } + struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = persimmon_enable, diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index dfb1aca..f1d1b2a 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -35,9 +35,14 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "pc80/i8254.c" #include "pc80/i8259.c" +#include <cpu/x86/cache.h> #include "sb_cimx.h" #include "SBPLATFORM.h" +#include "cbmem.h" +#include "cpu/amd/mtrr.h" +#include "cpu/amd/agesa/s3_resume.h" +void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) @@ -46,6 +51,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; +#if CONFIG_HAVE_ACPI_RESUME == 1 + void *resume_backup_memory; +#endif + /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) @@ -98,28 +107,75 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - post_code(0x40); - printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); - val = agesawrapper_amdinitpost (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); - - post_code(0x41); - printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); - val = agesawrapper_amdinitenv (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ +#endif + post_code(0x40); + printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); + val = agesawrapper_amdinitpost (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x42); + printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); + val = agesawrapper_amdinitenv (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); + val = agesawrapper_amdinitresume(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + val = agesawrapper_amds3laterestore (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x61); + printk(BIOS_DEBUG, "Find resume memory location\n"); + resume_backup_memory = backup_resume(); + + post_code(0x62); + printk(BIOS_DEBUG, "Move CAR stack.\n"); + move_stack_high_mem(); + printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); + + post_code(0x63); + disable_cache_as_ram(); + printk(BIOS_DEBUG, "CAR disabled.\n"); + set_resume_cache(); + + /* + * Copy the system memory that is in the ramstage area to the + * reserved area. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); + + printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + } +#endif /* Initialize i8259 pic */ - post_code(0x41); + post_code(0x43); setup_i8259 (); /* Initialize i8254 timers */ - post_code(0x42); + post_code(0x44); setup_i8254 (); post_code(0x50); [View Less]

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New patch to review for coreboot: e1c24d5 Bifferboard: Fix MAINBOARD_PART_NUMBER.
by Uwe Hermann 12 Apr '12

12 Apr '12

Uwe Hermann (uwe(a)hermann-uwe.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/894 -gerrit commit e1c24d5e477e497d993697311ef57b33fbc2ba1f Author: Uwe Hermann <uwe(a)hermann-uwe.de> Date: Thu Apr 12 22:48:57 2012 +0200 Bifferboard: Fix MAINBOARD_PART_NUMBER. Change-Id: I4acbeee8a0d26fae220ac22940b6f924e19af19c Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> --- src/mainboard/bifferos/bifferboard/Kconfig | 2 +- … [View More]

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Patch merged into coreboot/master: a312f01 cbfstool: pretty print cmos layout files
by gerrit＠coreboot.org 12 Apr '12

12 Apr '12

the following patch was just integrated into master: commit a312f010eb33da82cacaad0fea46a86ea3e954d7 Author: Mathias Krause <minipli(a)googlemail.com> Date: Thu Apr 12 21:36:23 2012 +0200 cbfstool: pretty print cmos layout files While at it, also make the array static - no need to export this symbol. Change-Id: I7fdcda2b80150b6f32b5bc3e0957998a4fd43fce Signed-off-by: Mathias Krause <minipli(a)googlemail.com> Reviewed-By: Patrick Georgi <patrick(a)… [View More]

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New patch to review for coreboot: 1576dc1 kconfig: Improve 'General setup' menu docs.
by Uwe Hermann 12 Apr '12

12 Apr '12

Uwe Hermann (uwe(a)hermann-uwe.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/893 -gerrit commit 1576dc110e01f397853aeb828483f71603a57fa8 Author: Uwe Hermann <uwe(a)hermann-uwe.de> Date: Thu Apr 12 22:00:03 2012 +0200 kconfig: Improve 'General setup' menu docs. - Add documentation for COMPILER_GCC, and COMPILER_LLVM_CLANG. - SCANBUILD_ENABLE, CCACHE: Amend documentation. - SCANBUILD_REPORT_LOCATION: … [View More]Document default dir, names of scan-build dirs. - INCLUDE_CONFIG_FILE: Add more verbose docs, show how to use it. - Fix typos/cosmetics/indentation, improve wording on some items. Change-Id: I6b67b2c777868e4421405caaffe6631e69dddad2 Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> --- src/Kconfig | 92 ++++++++++++++++++++++++++++++++++++++++++++-------------- 1 files changed, 70 insertions(+), 22 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index b0261d9..31e1b2e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -17,7 +17,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -mainmenu "Coreboot Configuration" +mainmenu "coreboot configuration" menu "General setup" @@ -47,7 +47,7 @@ config CBFS_PREFIX by default, "normal" is a common alternative. choice - prompt "Compiler" + prompt "Compiler to use" default COMPILER_GCC help This option allows you to select the compiler used for building @@ -55,39 +55,61 @@ choice config COMPILER_GCC bool "GCC" + help + Use the GNU Compiler Collection (GCC) to build coreboot. + + For details see http://gcc.gnu.org. + config COMPILER_LLVM_CLANG bool "LLVM/clang" + help + Use LLVM/clang to build coreboot. + + For details see http://clang.llvm.org. + endchoice config SCANBUILD_ENABLE - bool "Build with scan-build for static analysis" + bool "Build with scan-build for static code analysis" default n help - Changes the build process to scan-build is used. - Requires scan-build in path. + Changes the build process to use scan-build (a utility for + running the clang static code analyzer from the command line). + + Requires the scan-build utility in your system $PATH. + + For details see http://clang-analyzer.llvm.org/scan-build.html. config SCANBUILD_REPORT_LOCATION - string "Directory to put scan-build report in" + string "Directory for the scan-build report(s)" default "" depends on SCANBUILD_ENABLE help - Where the scan-build report should be stored + Directory where the scan-build reports should be stored in. The + reports are stored in subdirectories of the form 'yyyy-mm-dd-*' + in the specified directory. + + If this setting is left empty, the coreboot top-level directory + will be used to store the report subdirectories. config CCACHE - bool "ccache" + bool "Use ccache to speed up (re)compilation" default n help Enables the use of ccache for faster builds. - Requires ccache in path. + + Requires the ccache utility in your system $PATH. + + For details see https://ccache.samba.org. config SCONFIG_GENPARSER bool "Generate SCONFIG parser using flex and bison" default n depends on EXPERT help - Enable this option if you are working on the sconfig - device tree parser and made changes to sconfig.l and - sconfig.y. + Enable this option if you are working on the sconfig device tree + parser and made changes to sconfig.l and sconfig.y. + Otherwise, say N. config USE_OPTION_TABLE @@ -96,7 +118,7 @@ config USE_OPTION_TABLE depends on HAVE_OPTION_TABLE help Enable this option if coreboot shall read options from the "CMOS" - NVRAM instead of using hard coded values. + NVRAM instead of using hard-coded values. config COMPRESS_RAMSTAGE bool "Compress ramstage with LZMA" @@ -104,29 +126,55 @@ config COMPRESS_RAMSTAGE help Compress ramstage to save memory in the flash image. Note that decompression might slow down booting if the boot flash - is connected through a slow Link (i.e. SPI) + is connected through a slow link (i.e. SPI). config INCLUDE_CONFIG_FILE - bool "Include the coreboot config file into the ROM image" + bool "Include the coreboot .config file into the ROM image" default y - help - Include in CBFS the coreboot config file that was used to compile the ROM image + help + Include the .config file that was used to compile coreboot + in the (CBFS) ROM image. This is useful if you want to know which + options were used to build a specific coreboot.rom image. + + Saying Y here will increase the image size by 2-3kB. + + You can use the following command to easily list the options: + + grep -a CONFIG_ coreboot.rom + + Alternatively, you can also use cbfstool to print the image + contents (including the raw 'config' item we're looking for). + + Example: + + $ cbfstool coreboot.rom print + coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, + offset 0x0 + Alignment: 64 bytes + + Name Offset Type Size + cmos_layout.bin 0x0 cmos layout 1159 + fallback/romstage 0x4c0 stage 339756 + fallback/coreboot_ram 0x53440 stage 186664 + fallback/payload 0x80dc0 payload 51526 + config 0x8d740 raw 3324 + (empty) 0x8e480 null 3610440 config EARLY_CBMEM_INIT bool "Initialize CBMEM while in ROM stage" default n help - Make coreboot initialize the cbmem structures while running in rom - stage. This could be useful when the rom stage wants to communicate + Make coreboot initialize the cbmem structures while running in ROM + stage. This could be useful when the ROM stage wants to communicate some, for instance, execution timestamps. config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" depends on EARLY_CBMEM_INIT help - Make coreboot create a table of timer id/timer value pairs to - allow measuring time spent at different phases of the boot - process. + Make coreboot create a table of timer-ID/timer-value pairs to + allow measuring time spent at different phases of the boot process. + endmenu source src/mainboard/Kconfig [View Less]

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New patch to review for coreboot: a312f01 cbfstool: pretty print cmos layout files
by Mathias Krause 12 Apr '12

12 Apr '12

Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/892 -gerrit commit a312f010eb33da82cacaad0fea46a86ea3e954d7 Author: Mathias Krause <minipli(a)googlemail.com> Date: Thu Apr 12 21:36:23 2012 +0200 cbfstool: pretty print cmos layout files While at it, also make the array static - no need to export this symbol. Change-Id: I7fdcda2b80150b6f32b5bc3e0957998a4fd43fce Signed-off-by: … [View More]

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New patch to review for coreboot: 6967e3f kconfig: Fix 'make gconfig'.
by Uwe Hermann 12 Apr '12

12 Apr '12

Uwe Hermann (uwe(a)hermann-uwe.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/891 -gerrit commit 6967e3f7239b3afe9c73ac97c6035c52d828b1a2 Author: Uwe Hermann <uwe(a)hermann-uwe.de> Date: Thu Apr 12 21:39:27 2012 +0200 kconfig: Fix 'make gconfig'. Change-Id: Id2d0735d875b40e131fc2aada27435fdcbacc8cb Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> --- util/kconfig/Makefile | 1 + util/kconfig/lkc.h | 2 +- … [View More]

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Patch set updated for coreboot: fcb4358 More portable s3 scratch space creation
by Patrick Georgi 12 Apr '12

12 Apr '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/889 -gerrit commit fcb4358908704fa31adc3eb051692307fc2a89ce Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Apr 12 15:03:22 2012 +0200 More portable s3 scratch space creation echo -n isn't portable. echo -e isn't portable. that bash loop isn't portable. So let's try something else. Change-Id: … [View More]

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New patch to review for coreboot: cf2748d lint: tighten whitespace check some more
by Patrick Georgi 12 Apr '12

12 Apr '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/890 -gerrit commit cf2748dfffc75ca94e5397e59e549c1e451b9dcd Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Apr 12 15:23:58 2012 +0200 lint: tighten whitespace check some more Don't test executable files nor object files, even if the former might render the test useless on win32 (executable bit isn't well defined there). … [View More]

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New patch to review for coreboot: 42e55bb More portable s3 scratch space creation
by Patrick Georgi 12 Apr '12

12 Apr '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/889 -gerrit commit 42e55bbf332c7c5f137c02c40a124237ebad42fb Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Apr 12 15:03:22 2012 +0200 More portable s3 scratch space creation echo -n isn't portable. echo -e isn't portable. that bash loop isn't portable. So let's try something else. Change-Id: … [View More]

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New patch to review for coreboot: 0b8964e ACPI HEST table.
by Zheng Bao 12 Apr '12

12 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/888 -gerrit commit 0b8964e47af35034c60eac1a447605c8c25c1269 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 12 17:49:37 2012 +0800 ACPI HEST table. HEST feature starts from ACPI 4.0. HEST is one of four kinds of tables of ACPI Platform Error Interfaces (APEI). In Windows world, APEI is called Windows Hardware Error Architecture (… [View More]WHEA). APEI consists of four separate tables: 1. Error Record Serialization Table (ERST) 2. BOOT Error Record Table (BERT) 3. Hardware Error Source Table (HEST) 4. Error Injection Table (EINJ) All these 4 tables have the same header as FADT, MADT, etc. They are pointed by RSDP. For the HEST, it contains the error source. The types of them are defined as type description 1. Machine Check Exception (MCE) 2. Corrected Machine Check (CMC) 3. NMI Error 6. PCI Express Root Port AER 7. PCI Express Device AER 8. PCI Express Bridge AER 9. Generic Hardware Error Source Error source types 3, 4, and 5 are reserved for legacy reasons and must not be used. Currently AMD board only provide part of "Machine Check Exception (MCE)" & Corrected Machine Check (CMC)". we need to provide the header of each error source. Other types of Error Sources is in TODO list. Only persimmon is tested. Linux can add HEST feature. The dmesg says, ACPI: HEST 0000000066fe5010 00198 (v03 CORE COREBOOT 00000000 CORE 00000000) ...... HEST: Table parsing has been initialized. No more message is got. Change-Id: I447e7f57b8e8f0433a145a43d0710910afabf00f Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/arch/x86/boot/acpi.c | 83 +++++++++++++++++++++++++ src/arch/x86/include/arch/acpi.h | 35 ++++++++++ src/mainboard/amd/dinar/acpi_tables.c | 31 +++++++++- src/mainboard/amd/inagua/acpi_tables.c | 47 +++++++++++--- src/mainboard/amd/persimmon/acpi_tables.c | 47 +++++++++++--- src/mainboard/amd/south_station/acpi_tables.c | 47 +++++++++++--- src/mainboard/amd/torpedo/acpi_tables.c | 24 +++++++ src/mainboard/amd/union_station/acpi_tables.c | 47 +++++++++++--- src/mainboard/asrock/e350m1/acpi_tables.c | 47 +++++++++++--- src/mainboard/supermicro/h8qgi/acpi_tables.c | 31 +++++++++- 10 files changed, 385 insertions(+), 54 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index f17e73e..010ba9f 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -467,6 +467,89 @@ void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt) rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t)); } +unsigned long __attribute__((weak)) acpi_fill_hest(acpi_hest_t *hest) +{ + return (unsigned long)hest; +} + +unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 data_len) +{ + acpi_header_t *header = &(hest->header); + acpi_hest_hen_t *hen; + void *pos; + u16 len; + + pos = esd; + memset(pos, 0, sizeof(acpi_hest_esd_t)); + len = 0; + esd->type = type; /* MCE */ + esd->source_id = hest->error_source_count; + esd->flags = 0; /* FIRMWARE_FIRST */ + esd->enabled = 1; + esd->prealloc_erecords = 1; + esd->max_section_per_record = 0x1; + + len += sizeof(acpi_hest_esd_t); + pos = esd + 1; + + switch (type) { + case 0: /* MCE */ + break; + case 1: /* CMC */ + hen = (acpi_hest_hen_t *) (pos); + memset(pos, 0, sizeof(acpi_hest_hen_t)); + hen->type = 3; /* SCI? */ + hen->length = sizeof(acpi_hest_hen_t); + hen->conf_we = 0; /* Configuration Write Enable. */ + hen->poll_interval = 0; + hen->vector = 0; + hen->sw2poll_threshold_val = 0; + hen->sw2poll_threshold_win = 0; + hen->error_threshold_val = 0; + hen->error_threshold_win = 0; + len += sizeof(acpi_hest_hen_t); + pos = hen + 1; + break; + case 2: /* NMI */ + case 6: /* AER Root Port */ + case 7: /* AER Endpoint */ + case 8: /* AER Bridge */ + case 9: /* Generic Hardware Error Source. */ + /* TODO: */ + break; + default: + printk(BIOS_DEBUG, "Invalid type of Error Source."); + break; + } + hest->error_source_count ++; + + memcpy(pos, data, data_len); + len += data_len; + header->length += len; + + return len; +} + +/* ACPI 4.0 */ +void acpi_write_hest(acpi_hest_t *hest) +{ + acpi_header_t *header = &(hest->header); + + memset(hest, 0, sizeof(acpi_hest_t)); + + memcpy(header->signature, "HEST", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->length += sizeof(acpi_hest_t); + header->revision = 1; + + acpi_fill_hest(hest); + + /* Calculate checksums. */ + header->checksum = acpi_checksum((void *)hest, header->length); +} + #if CONFIG_HAVE_ACPI_RESUME == 1 void suspend_resume(void) { diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 8c521af..60e400d 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -357,6 +357,37 @@ typedef struct acpi_ecdt { u8 ec_id[]; /* EC ID */ } __attribute__ ((packed)) acpi_ecdt_t; +/* HEST (Hardware Error Source Table) */ +typedef struct acpi_hest { + struct acpi_table_header header; + u32 error_source_count; + /* error_source_struct(s) */ +} __attribute__ ((packed)) acpi_hest_t; + +/* Error Source Descriptors */ +typedef struct acpi_hest_esd { + u16 type; + u16 source_id; + u16 resv; + u8 flags; + u8 enabled; + u32 prealloc_erecords; /* The number of error records to pre-allocate for this error source. */ + u32 max_section_per_record; +} __attribute__ ((packed)) acpi_hest_esd_t; + +/* Hardware Error Notification */ +typedef struct acpi_hest_hen { + u8 type; + u8 length; + u16 conf_we; /* Configuration Write Enable */ + u32 poll_interval; + u32 vector; + u32 sw2poll_threshold_val; + u32 sw2poll_threshold_win; + u32 error_threshold_val; + u32 error_threshold_win; +} __attribute__ ((packed)) acpi_hest_hen_t; + /* These are implemented by the target port or north/southbridge. */ unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); @@ -412,6 +443,10 @@ void acpi_write_rsdt(acpi_rsdt_t *rsdt); void acpi_write_xsdt(acpi_xsdt_t *xsdt); void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt); +void acpi_write_hest(acpi_hest_t *hest); +unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 len); +unsigned long acpi_fill_hest(acpi_hest_t *hest); + #if CONFIG_HAVE_ACPI_RESUME /* 0 = S0, 1 = S1 ...*/ extern u8 acpi_slp_type; diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index ee00e81..0e86e29 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -122,6 +122,22 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -172,6 +188,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *ssdt2; acpi_header_t *alib; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -234,6 +251,13 @@ unsigned long write_acpi_tables(unsigned long start) current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ current = ( current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); @@ -272,7 +296,7 @@ unsigned long write_acpi_tables(unsigned long start) } #if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -285,7 +309,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp,ssdt); #endif - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); @@ -313,6 +337,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "fadt\n"); dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); #endif printk(BIOS_INFO, "ACPI: done.\n"); diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 8f47591..6bf195d 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -105,6 +105,22 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -132,6 +148,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *ssdt2; acpi_header_t *alib; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -154,7 +171,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -163,14 +180,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -181,7 +198,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -189,15 +206,22 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -211,7 +235,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -225,7 +249,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { @@ -239,7 +263,7 @@ unsigned long write_acpi_tables(unsigned long start) } #if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -254,7 +278,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp,ssdt); #endif - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); @@ -288,6 +312,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "fadt\n"); dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); #endif printk(BIOS_INFO, "ACPI: done.\n"); diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 9526fea..ade14d0 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -105,6 +105,22 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -132,6 +148,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *ssdt2; acpi_header_t *alib; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -154,7 +171,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -163,14 +180,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -181,7 +198,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -189,15 +206,22 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -211,7 +235,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -225,7 +249,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { @@ -239,7 +263,7 @@ unsigned long write_acpi_tables(unsigned long start) } #if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -254,7 +278,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp,ssdt); #endif - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); @@ -288,6 +312,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "fadt\n"); dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); #endif printk(BIOS_INFO, "ACPI: done.\n"); diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 2e6e50f..5d0b2ec 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -104,6 +104,22 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -131,6 +147,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *ssdt2; acpi_header_t *alib; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -153,7 +170,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -162,14 +179,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -180,7 +197,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -188,15 +205,22 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -210,7 +234,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -224,7 +248,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { @@ -238,7 +262,7 @@ unsigned long write_acpi_tables(unsigned long start) } #if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -252,7 +276,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp,ssdt); #endif - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); @@ -283,6 +307,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "fadt\n"); dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); #endif printk(BIOS_INFO, "ACPI: done.\n"); diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c index 3ba789d..94935be 100644 --- a/src/mainboard/amd/torpedo/acpi_tables.c +++ b/src/mainboard/amd/torpedo/acpi_tables.c @@ -93,6 +93,22 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -120,6 +136,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_facs_t *facs; acpi_header_t *dsdt; acpi_header_t *ssdt; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -161,6 +178,13 @@ unsigned long write_acpi_tables(unsigned long start) current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ current = ( current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 2e6e50f..e1bcac9 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -104,6 +104,22 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -131,6 +147,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *ssdt2; acpi_header_t *alib; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -153,7 +170,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -162,14 +179,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -180,7 +197,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -188,15 +205,22 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -210,7 +234,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -224,7 +248,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { @@ -238,7 +262,7 @@ unsigned long write_acpi_tables(unsigned long start) } #if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -252,7 +276,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp,ssdt); #endif - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); @@ -283,6 +307,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "fadt\n"); dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); #endif printk(BIOS_INFO, "ACPI: done.\n"); diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 2e6e50f..e1bcac9 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -104,6 +104,22 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -131,6 +147,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *ssdt2; acpi_header_t *alib; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -153,7 +170,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdt(rsdt); /* DSDT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -162,14 +179,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); @@ -180,7 +197,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -188,15 +205,22 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { @@ -210,7 +234,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SLIT */ - current = ( current + 0x07) & -0x08; + current = (current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { @@ -224,7 +248,7 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { @@ -238,7 +262,7 @@ unsigned long write_acpi_tables(unsigned long start) } #if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -252,7 +276,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp,ssdt); #endif - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); @@ -283,6 +307,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "fadt\n"); dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); #endif printk(BIOS_INFO, "ACPI: done.\n"); diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 7314283..7441b20 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -122,6 +122,22 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -172,6 +188,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *ssdt2; acpi_header_t *alib; + acpi_hest_t *hest; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -234,6 +251,13 @@ unsigned long write_acpi_tables(unsigned long start) current += madt->header.length; acpi_add_table(rsdp, madt); + /* HEST */ + current = (current + 0x07) & -0x08; + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + /* SRAT */ current = ( current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); @@ -272,7 +296,7 @@ unsigned long write_acpi_tables(unsigned long start) } #if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { @@ -285,7 +309,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp,ssdt); #endif - current = ( current + 0x0f) & -0x10; + current = (current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); ssdt2 = (acpi_header_t *) current; acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); @@ -313,6 +337,9 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "fadt\n"); dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); #endif printk(BIOS_INFO, "ACPI: done.\n"); [View Less]

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Patch merged into coreboot/master: 25fcc40 Convert AOpen DXPL Plus mainboard to CAR
by gerrit＠coreboot.org 12 Apr '12

12 Apr '12

the following patch was just integrated into master: commit 25fcc40db87b15a123d70cf64297a3ed08b31979 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Apr 11 12:19:03 2012 +0300 Convert AOpen DXPL Plus mainboard to CAR Tested on real hardware, mainboard with dual Xeon P4 HT CPUs requires cache-as-ram init code with AP SIPI protocol. Also enable 2nd CPU and PATA and clean-up Kconfig and ACPI. Change-Id: … [View More]

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Patch merged into coreboot/master: 624c4fe Add support for aligned allocation
by gerrit＠coreboot.org 12 Apr '12

12 Apr '12

the following patch was just integrated into master: commit 624c4fed563e3bc8e8fe900f1b8ad705a1700c37 Author: Ron Minnich <rminnich(a)gmail.com> Date: Wed Apr 11 10:30:15 2012 -0700 Add support for aligned allocation Add a memalign function and have malloc use it. Also, change the default alignment for malloc to u64-aligned. Change-Id: I0788637008f5cb5ac801d8bbdc430ca992c98e81 Signed-off-by: Ron Minnich <rminnich(a)gmail.com> See http://review.… [View More]

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Patch set updated for coreboot: a7ae186 Leverage the Pstate table created by AGESA.
by Zheng Bao 11 Apr '12

11 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/884 -gerrit commit a7ae186ed9dcd7edf501c14bde5480fdaff99c2a Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 12 11:27:26 2012 +0800 Leverage the Pstate table created by AGESA. The name of processor created by AGESA is P00n, whose P is BLDCFG_PROCESSOR_SCOPE_NAME(is 'C' if it is undefined.) and n starts from 0. The dsdt should be aligned with … [View More]that. This feature has only been tested on persimmon. The changes on all the other boards were propagated. Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/dinar/acpi/cpstate.asl | 74 -------------- src/mainboard/amd/dinar/acpi_tables.c | 8 +- src/mainboard/amd/dinar/dsdt.asl | 48 +++++++--- src/mainboard/amd/inagua/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/inagua/acpi_tables.c | 8 +- src/mainboard/amd/inagua/dsdt.asl | 24 ++++- src/mainboard/amd/persimmon/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/persimmon/acpi_tables.c | 8 +- src/mainboard/amd/persimmon/dsdt.asl | 24 ++++- src/mainboard/amd/south_station/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/south_station/acpi_tables.c | 12 +- src/mainboard/amd/south_station/dsdt.asl | 24 ++++- src/mainboard/amd/torpedo/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/torpedo/dsdt.asl | 18 ++-- src/mainboard/amd/union_station/acpi/cpstate.asl | 75 -------------- src/mainboard/amd/union_station/acpi_tables.c | 12 +- src/mainboard/amd/union_station/dsdt.asl | 24 ++++- src/mainboard/asrock/e350m1/acpi/cpstate.asl | 75 -------------- src/mainboard/asrock/e350m1/acpi_tables.c | 12 +- src/mainboard/asrock/e350m1/dsdt.asl | 24 ++++- src/mainboard/supermicro/h8qgi/acpi/cpstate.asl | 75 -------------- src/mainboard/supermicro/h8qgi/acpi_tables.c | 8 +- src/mainboard/supermicro/h8qgi/dsdt.asl | 115 +++++++++++----------- 23 files changed, 222 insertions(+), 746 deletions(-) diff --git a/src/mainboard/amd/dinar/acpi/cpstate.asl b/src/mainboard/amd/dinar/acpi/cpstate.asl deleted file mode 100644 index 64b3f16..0000000 --- a/src/mainboard/amd/dinar/acpi/cpstate.asl +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index ee00e81..741ba99 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -271,7 +271,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -279,11 +280,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); } else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl index 1cbb05e..501ec78 100644 --- a/src/mainboard/amd/dinar/dsdt.asl +++ b/src/mainboard/amd/dinar/dsdt.asl @@ -51,37 +51,61 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x0 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU2, /* name space name */ + C002, /* name space name */ 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU3, /* name space name */ + C003, /* name space name */ 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } + Processor( + C004, /* name space name */ + 4, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C005, /* name space name */ + 5, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C006, /* name space name */ + 6, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C007, /* name space name */ + 7, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } } /* End _PR scope */ /* PIC IRQ mapping registers, C00h-C01h. */ diff --git a/src/mainboard/amd/inagua/acpi/cpstate.asl b/src/mainboard/amd/inagua/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/inagua/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 8f47591..e521b4b 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -238,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -247,12 +248,9 @@ unsigned long write_acpi_tables(unsigned long start) ssdt = (acpi_header_t *) current; current += ssdt->length; acpi_add_table(rsdp,ssdt); - } - else { + } else { printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 361adbb..7708676 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/persimmon/acpi/cpstate.asl b/src/mainboard/amd/persimmon/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/persimmon/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 9526fea..00a08d2 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -238,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -247,12 +248,9 @@ unsigned long write_acpi_tables(unsigned long start) ssdt = (acpi_header_t *) current; current += ssdt->length; acpi_add_table(rsdp,ssdt); - } - else { + } else { printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index b480c33..bd9ce74 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/south_station/acpi/cpstate.asl b/src/mainboard/amd/south_station/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/south_station/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 2e6e50f..c49a8e2 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -237,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -245,12 +247,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 7f03a43..b18bcb2 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/torpedo/acpi/cpstate.asl b/src/mainboard/amd/torpedo/acpi/cpstate.asl deleted file mode 100755 index 5eca9cc..0000000 --- a/src/mainboard/amd/torpedo/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index a8a731d..758fba5 100755 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -51,36 +51,32 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU2, /* name space name */ + C002, /* name space name */ 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU3, /* name space name */ + C003, /* name space name */ 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/union_station/acpi/cpstate.asl b/src/mainboard/amd/union_station/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/amd/union_station/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 2e6e50f..c49a8e2 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -237,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -245,12 +247,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index fb2cfe8..7e49fd4 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/asrock/e350m1/acpi/cpstate.asl b/src/mainboard/asrock/e350m1/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/asrock/e350m1/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 2e6e50f..c49a8e2 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -237,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -245,12 +247,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 97533c1..c2ea1fb 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl deleted file mode 100644 index 5eca9cc..0000000 --- a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This file defines the processor and performance state capability - * for each core in the system. It is included into the DSDT for each - * core. It assumes that each core of the system has the same performance - * characteristics. -*/ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - { - Scope (\_PR) { - Processor(CPU0,0,0x808,0x06) { - #include "cpstate.asl" - } - Processor(CPU1,1,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU2,2,0x0,0x0) { - #include "cpstate.asl" - } - Processor(CPU3,3,0x0,0x0) { - #include "cpstate.asl" - } - } -*/ - /* P-state support: The maximum number of P-states supported by the */ - /* CPUs we'll use is 6. */ - /* Get from AMI BIOS. */ - Name(_PSS, Package(){ - Package () - { - 0x00000AF0, - 0x0000BF81, - 0x00000002, - 0x00000002, - 0x00000000, - 0x00000000 - }, - - Package () - { - 0x00000578, - 0x000076F2, - 0x00000002, - 0x00000002, - 0x00000001, - 0x00000001 - } - }) - - Name(_PCT, Package(){ - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, - ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} - }) - - Method(_PPC, 0){ - Return(0) - } diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 7314283..7b97a92 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -271,7 +271,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -279,11 +280,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); } else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index 137a90d..2955eea 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -65,69 +65,68 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - P000, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0x00, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - //#include "acpi/cpstate.asl" } - Processor(P001, 0x01, 0x00000000, 0x00) {} - Processor(P002, 0x02, 0x00000000, 0x00) {} - Processor(P003, 0x03, 0x00000000, 0x00) {} - Processor(P004, 0x04, 0x00000000, 0x00) {} - Processor(P005, 0x05, 0x00000000, 0x00) {} - Processor(P006, 0x06, 0x00000000, 0x00) {} - Processor(P007, 0x07, 0x00000000, 0x00) {} - Processor(P008, 0x08, 0x00000000, 0x00) {} - Processor(P009, 0x09, 0x00000000, 0x00) {} - Processor(P00A, 0x0A, 0x00000000, 0x00) {} - Processor(P00B, 0x0B, 0x00000000, 0x00) {} - Processor(P00C, 0x0C, 0x00000000, 0x00) {} - Processor(P00D, 0x0D, 0x00000000, 0x00) {} - Processor(P00E, 0x0E, 0x00000000, 0x00) {} - Processor(P00F, 0x0F, 0x00000000, 0x00) {} - Processor(P010, 0x10, 0x00000000, 0x00) {} - Processor(P011, 0x11, 0x00000000, 0x00) {} - Processor(P012, 0x12, 0x00000000, 0x00) {} - Processor(P013, 0x13, 0x00000000, 0x00) {} - Processor(P014, 0x14, 0x00000000, 0x00) {} - Processor(P015, 0x15, 0x00000000, 0x00) {} - Processor(P016, 0x16, 0x00000000, 0x00) {} - Processor(P017, 0x17, 0x00000000, 0x00) {} - Processor(P018, 0x18, 0x00000000, 0x00) {} - Processor(P019, 0x19, 0x00000000, 0x00) {} - Processor(P01A, 0x1A, 0x00000000, 0x00) {} - Processor(P01B, 0x1B, 0x00000000, 0x00) {} - Processor(P01C, 0x1C, 0x00000000, 0x00) {} - Processor(P01D, 0x1D, 0x00000000, 0x00) {} - Processor(P01E, 0x1E, 0x00000000, 0x00) {} - Processor(P01F, 0x1F, 0x00000000, 0x00) {} - Processor(P020, 0x20, 0x00000000, 0x00) {} - Processor(P021, 0x21, 0x00000000, 0x00) {} - Processor(P022, 0x22, 0x00000000, 0x00) {} - Processor(P023, 0x23, 0x00000000, 0x00) {} - Processor(P024, 0x24, 0x00000000, 0x00) {} - Processor(P025, 0x25, 0x00000000, 0x00) {} - Processor(P026, 0x26, 0x00000000, 0x00) {} - Processor(P027, 0x27, 0x00000000, 0x00) {} - Processor(P028, 0x28, 0x00000000, 0x00) {} - Processor(P029, 0x29, 0x00000000, 0x00) {} - Processor(P02A, 0x2A, 0x00000000, 0x00) {} - Processor(P02B, 0x2B, 0x00000000, 0x00) {} - Processor(P02C, 0x2C, 0x00000000, 0x00) {} - Processor(P02D, 0x2D, 0x00000000, 0x00) {} - Processor(P02E, 0x2E, 0x00000000, 0x00) {} - Processor(P02F, 0x2F, 0x00000000, 0x00) {} - Alias (P000, CPU0) - Alias (P001, CPU1) - Alias (P002, CPU2) - Alias (P003, CPU3) - Alias (P004, CPU4) - Alias (P005, CPU5) - Alias (P006, CPU6) - Alias (P007, CPU7) - Alias (P008, CPU8) + Processor(C001, 0x01, 0x00000000, 0x00) {} + Processor(C002, 0x02, 0x00000000, 0x00) {} + Processor(C003, 0x03, 0x00000000, 0x00) {} + Processor(C004, 0x04, 0x00000000, 0x00) {} + Processor(C005, 0x05, 0x00000000, 0x00) {} + Processor(C006, 0x06, 0x00000000, 0x00) {} + Processor(C007, 0x07, 0x00000000, 0x00) {} + Processor(C008, 0x08, 0x00000000, 0x00) {} + Processor(C009, 0x09, 0x00000000, 0x00) {} + Processor(C00A, 0x0A, 0x00000000, 0x00) {} + Processor(C00B, 0x0B, 0x00000000, 0x00) {} + Processor(C00C, 0x0C, 0x00000000, 0x00) {} + Processor(C00D, 0x0D, 0x00000000, 0x00) {} + Processor(C00E, 0x0E, 0x00000000, 0x00) {} + Processor(C00F, 0x0F, 0x00000000, 0x00) {} + Processor(C010, 0x10, 0x00000000, 0x00) {} + Processor(C011, 0x11, 0x00000000, 0x00) {} + Processor(C012, 0x12, 0x00000000, 0x00) {} + Processor(C013, 0x13, 0x00000000, 0x00) {} + Processor(C014, 0x14, 0x00000000, 0x00) {} + Processor(C015, 0x15, 0x00000000, 0x00) {} + Processor(C016, 0x16, 0x00000000, 0x00) {} + Processor(C017, 0x17, 0x00000000, 0x00) {} + Processor(C018, 0x18, 0x00000000, 0x00) {} + Processor(C019, 0x19, 0x00000000, 0x00) {} + Processor(C01A, 0x1A, 0x00000000, 0x00) {} + Processor(C01B, 0x1B, 0x00000000, 0x00) {} + Processor(C01C, 0x1C, 0x00000000, 0x00) {} + Processor(C01D, 0x1D, 0x00000000, 0x00) {} + Processor(C01E, 0x1E, 0x00000000, 0x00) {} + Processor(C01F, 0x1F, 0x00000000, 0x00) {} + Processor(C020, 0x20, 0x00000000, 0x00) {} + Processor(C021, 0x21, 0x00000000, 0x00) {} + Processor(C022, 0x22, 0x00000000, 0x00) {} + Processor(C023, 0x23, 0x00000000, 0x00) {} + Processor(C024, 0x24, 0x00000000, 0x00) {} + Processor(C025, 0x25, 0x00000000, 0x00) {} + Processor(C026, 0x26, 0x00000000, 0x00) {} + Processor(C027, 0x27, 0x00000000, 0x00) {} + Processor(C028, 0x28, 0x00000000, 0x00) {} + Processor(C029, 0x29, 0x00000000, 0x00) {} + Processor(C02A, 0x2A, 0x00000000, 0x00) {} + Processor(C02B, 0x2B, 0x00000000, 0x00) {} + Processor(C02C, 0x2C, 0x00000000, 0x00) {} + Processor(C02D, 0x2D, 0x00000000, 0x00) {} + Processor(C02E, 0x2E, 0x00000000, 0x00) {} + Processor(C02F, 0x2F, 0x00000000, 0x00) {} + Alias (C000, CPU0) + Alias (C001, CPU1) + Alias (C002, CPU2) + Alias (C003, CPU3) + Alias (C004, CPU4) + Alias (C005, CPU5) + Alias (C006, CPU6) + Alias (C007, CPU7) + Alias (C008, CPU8) } /* End _PR scope */ /* PIC IRQ mapping registers, C00h-C01h */ [View Less]

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Patch set updated for coreboot: 85f52c8 Fix messy code in ALIB
by Zheng Bao 11 Apr '12

11 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/885 -gerrit commit 85f52c8e80831acb0de3898bdfad73081c091a49 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 12 11:28:11 2012 +0800 Fix messy code in ALIB The address return from PICK_ALIB is not protected by Coreboot. We need to use the "current", which is the correct way to allocate the ACPI table. Change-Id: … [View More]I250066eb5f755275f75c37789ce8760de35b046b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/dinar/acpi_tables.c | 3 +-- src/mainboard/amd/inagua/acpi_tables.c | 6 ++---- src/mainboard/amd/persimmon/acpi_tables.c | 6 ++---- src/mainboard/amd/south_station/acpi_tables.c | 6 ++---- src/mainboard/amd/union_station/acpi_tables.c | 6 ++---- src/mainboard/asrock/e350m1/acpi_tables.c | 6 ++---- src/mainboard/supermicro/h8qgi/acpi_tables.c | 3 +-- 7 files changed, 12 insertions(+), 24 deletions(-) diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index 741ba99..6fa9c6f 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -264,9 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index e521b4b..0588d04 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 00a08d2..789c11d 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index c49a8e2..21281c8 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index c49a8e2..21281c8 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index c49a8e2..21281c8 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 7b97a92..e587334 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -264,9 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } [View Less]

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Patch merged into coreboot/master: f8300b4 S3 code in vendorcode folder.
by gerrit＠coreboot.org 11 Apr '12

11 Apr '12

the following patch was just integrated into master: commit f8300b4e154e265ae2e281b61761428f487774b3 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 5 13:20:50 2012 +0800 S3 code in vendorcode folder. Change the ExecuteFinalHltInstruction to assembly code. so we can make sure the code can run stackless. Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.… [View More]

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Patch merged into coreboot/master: a3650b6 Add Southbridge support for S3.
by gerrit＠coreboot.org 11 Apr '12

11 Apr '12

the following patch was just integrated into master: commit a3650b6cd356973f8b89c955533137be5cfa4b47 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 5 13:18:49 2012 +0800 Add Southbridge support for S3. 1. Add some CIMX call for S3. 2. Detect sleep type. Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue … [View More]

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Patch merged into coreboot/master: 316c124 Unify IO APIC address specification
by gerrit＠coreboot.org 11 Apr '12

11 Apr '12

the following patch was just integrated into master: commit 316c124a98f563fe16721f37f98440b68491a249 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 18:54:37 2012 +0100 Unify IO APIC address specification Some places still hardcoded the address instead of using IO_APIC_ADDR. Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Sat Mar 10 09:… [View More]

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Patch set updated for coreboot: 624c4fe Add support for aligned allocation
by Ronald G. Minnich 11 Apr '12

11 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/887 -gerrit commit 624c4fed563e3bc8e8fe900f1b8ad705a1700c37 Author: Ron Minnich <rminnich(a)gmail.com> Date: Wed Apr 11 10:30:15 2012 -0700 Add support for aligned allocation Add a memalign function and have malloc use it. Also, change the default alignment for malloc to u64-aligned. Change-Id: … [View More]I0788637008f5cb5ac801d8bbdc430ca992c98e81 Signed-off-by: Ron Minnich <rminnich(a)gmail.com> --- src/include/stdlib.h | 1 + src/lib/malloc.c | 23 ++++++++++++++++------- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 5465c14..bd0ee30 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -12,6 +12,7 @@ #define MAX(a,b) ((a) > (b) ? (a) : (b)) #if !defined(__PRE_RAM__) +void *memalign(size_t boundary, size_t size); void *malloc(size_t size); void free(void *ptr); #endif diff --git a/src/lib/malloc.c b/src/lib/malloc.c index c10750d..2e700f7 100644 --- a/src/lib/malloc.c +++ b/src/lib/malloc.c @@ -11,29 +11,38 @@ extern unsigned char _heap, _eheap; static void *free_mem_ptr = &_heap; /* Start of heap */ static void *free_mem_end_ptr = &_eheap; /* End of heap */ -void *malloc(size_t size) +/* We don't restrict the boundary. This is firmware, + * you are supposed to know what you are doing. + */ +void *memalign(size_t boundary, size_t size) { void *p; - MALLOCDBG("%s Enter, size %ld, free_mem_ptr %p\n", __func__, size, free_mem_ptr); + MALLOCDBG("%s Enter, boundary %ld, size %ld, free_mem_ptr %p\n", + __func__, boundary, size, free_mem_ptr); /* Overzealous linker check */ if (free_mem_ptr <= 0) - die("Error! malloc: Free_mem_ptr <= 0"); + die("Error! memalign: Free_mem_ptr <= 0"); - free_mem_ptr = (void *)ALIGN((unsigned long)free_mem_ptr, 4); + free_mem_ptr = (void *)ALIGN((unsigned long)free_mem_ptr, boundary); - p = (void *) free_mem_ptr; + p = free_mem_ptr; free_mem_ptr += size; if (free_mem_ptr >= free_mem_end_ptr) - die("Error! malloc: Out of memory (free_mem_ptr >= free_mem_end_ptr)"); + die("Error! memalign: Out of memory (free_mem_ptr >= free_mem_end_ptr)"); - MALLOCDBG("malloc %p\n", p); + MALLOCDBG("memalign %p\n", p); return p; } +void *malloc(size_t size) +{ + return memalign(sizeof(u64), size); +} + void free(void *where) { /* Don't care */ [View Less]

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Patch merged into coreboot/master: 7f83ace Intel e7505: cleanups
by gerrit＠coreboot.org 11 Apr '12

11 Apr '12

the following patch was just integrated into master: commit 7f83ace920173381d4a6316a375b685735d424fa Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 10 19:55:19 2012 +0300 Intel e7505: cleanups Fix delay loop comments. Time waited and the comments did not match in the origin (e7501), so delays currently "just work". Move reset detection to main raminit and don't use generic sdram_initialize for now, as there are local debug functions I … [View More]

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Patch merged into coreboot/master: ddfe8df Intel e7505: renames only
by gerrit＠coreboot.org 11 Apr '12

11 Apr '12

the following patch was just integrated into master: commit ddfe8df0d5fa6466be8cb908aaaf5f08ad0293bc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 10 16:11:53 2012 +0300 Intel e7505: renames only Drop maybe-prefix in registers and tables. Have a name in place of PCI_DEV(x,y,z) to avoid confusion. Change-Id: I88f51b50d7fd83294aa14455a83418630e1bab85 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (… [View More]

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New patch to review for coreboot: d08b499 Add support for aligned allocation
by Ronald G. Minnich 11 Apr '12

11 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/887 -gerrit commit d08b4997b8eb0d2677bc243650862a1cbda43105 Author: Ron Minnich <rminnich(a)gmail.com> Date: Wed Apr 11 10:30:15 2012 -0700 Add support for aligned allocation Add a memalign function and have malloc use it. Also, change the default alignment for malloc to u64-aligned. Change-Id: … [View More]I0788637008f5cb5ac801d8bbdc430ca992c98e81 Signed-off-by: Ron Minnich <rminnich(a)gmail.com> --- src/include/stdlib.h | 1 + src/lib/malloc.c | 21 +++++++++++++++------ 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 5465c14..bd0ee30 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -12,6 +12,7 @@ #define MAX(a,b) ((a) > (b) ? (a) : (b)) #if !defined(__PRE_RAM__) +void *memalign(size_t boundary, size_t size); void *malloc(size_t size); void free(void *ptr); #endif diff --git a/src/lib/malloc.c b/src/lib/malloc.c index c10750d..14219f6 100644 --- a/src/lib/malloc.c +++ b/src/lib/malloc.c @@ -11,29 +11,38 @@ extern unsigned char _heap, _eheap; static void *free_mem_ptr = &_heap; /* Start of heap */ static void *free_mem_end_ptr = &_eheap; /* End of heap */ -void *malloc(size_t size) +/* We don't restrict the boundary. This is firmware, + * you are supposed to know what you are doing. + */ +void *memalign(size_t boundary, size_t size) { void *p; - MALLOCDBG("%s Enter, size %ld, free_mem_ptr %p\n", __func__, size, free_mem_ptr); + MALLOCDBG("%s Enter, boundary %ld, size %ld, free_mem_ptr %p\n", + __func__, boundary, size, free_mem_ptr); /* Overzealous linker check */ if (free_mem_ptr <= 0) - die("Error! malloc: Free_mem_ptr <= 0"); + die("Error! memalign: Free_mem_ptr <= 0"); - free_mem_ptr = (void *)ALIGN((unsigned long)free_mem_ptr, 4); + free_mem_ptr = (void *)ALIGN((unsigned long)free_mem_ptr, boundary); p = (void *) free_mem_ptr; free_mem_ptr += size; if (free_mem_ptr >= free_mem_end_ptr) - die("Error! malloc: Out of memory (free_mem_ptr >= free_mem_end_ptr)"); + die("Error! memalign: Out of memory (free_mem_ptr >= free_mem_end_ptr)"); - MALLOCDBG("malloc %p\n", p); + MALLOCDBG("memalign %p\n", p); return p; } +void *malloc(size_t size) +{ + return memalign(sizeof(u64), size); +} + void free(void *where) { /* Don't care */ [View Less]

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Patch set updated for coreboot: 25fcc40 Convert AOpen DXPL Plus mainboard to CAR
by Kyösti Mälkki 11 Apr '12

11 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/886 -gerrit commit 25fcc40db87b15a123d70cf64297a3ed08b31979 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Apr 11 12:19:03 2012 +0300 Convert AOpen DXPL Plus mainboard to CAR Tested on real hardware, mainboard with dual Xeon P4 HT CPUs requires cache-as-ram init code with AP SIPI protocol. Also enable 2nd CPU and … [View More]PATA and clean-up Kconfig and ACPI. Change-Id: I415482f3af22df79d82492c49aed83549f29aa56 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/aopen/dxplplusu/Kconfig | 18 ----------- src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl | 8 +++-- src/mainboard/aopen/dxplplusu/acpi/i82801db.asl | 2 +- src/mainboard/aopen/dxplplusu/devicetree.cb | 3 ++ src/mainboard/aopen/dxplplusu/dsdt.asl | 2 + src/mainboard/aopen/dxplplusu/romstage.c | 34 ++------------------- 6 files changed, 15 insertions(+), 52 deletions(-) diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index c3025d1..da03491 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -8,8 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82870 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_LPC47M10X - select ROMCC - select HAVE_HARD_RESET # select HAVE_PIRQ_TABLE # select PIRQ_ROUTE select UDELAY_TSC @@ -24,14 +22,6 @@ config MAINBOARD_PART_NUMBER string default "DXPL Plus-U" -config DCACHE_RAM_BASE - hex - default 0xcf000 - -config DCACHE_RAM_SIZE - hex - default 0x1000 - config IRQ_SLOT_COUNT int default 12 @@ -40,18 +30,10 @@ config BOARD_HAS_FADT bool default y -config LOGICAL_CPUS - bool - default n - config MAX_CPUS int default 4 -config MAX_PHYSICAL_CPUS - int - default 2 - config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex default 0x0 diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl index 0effe93..463b6be 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl @@ -44,8 +44,8 @@ Name (PBRS, ResourceTemplate () /* Top Of Lowmemory to IOAPIC */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0x02000000, 0xFEBFFFFF, - 0x00000000, 0xFCC00000, ,, _Y08, AddressRangeMemory, TypeStatic) + 0x00000000, 0x00000000, 0xFEBFFFFF, + 0x00000000, IO_APIC_ADDR, ,, _Y08, AddressRangeMemory, TypeStatic) }) @@ -54,11 +54,13 @@ Method (_CRS, 0, NotSerialized) /* Top Of Lowmemory to IOAPIC */ CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML) + CreateDWordField (PBRS, \_SB.PCI0._Y08._MAX, MEMH) CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM) And (\_SB.PCI0.TOLM, 0xF800, Local1) ShiftRight (Local1, 0x04, Local1) ShiftLeft (Local1, 0x14, MEML) - Subtract (0xFEC00000, MEML, LENM) + Subtract (IO_APIC_ADDR, 0x01, MEMH) + Subtract (IO_APIC_ADDR, MEML, LENM) Return (PBRS) } diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl index bb8c321..a1a23f2 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl @@ -96,7 +96,7 @@ Device (ICH0) Name (MSBF, ResourceTemplate () { /* IOAPIC 0 */ - Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000,) + Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000,) IO (Decode16, 0x0, 0x0, 0x80, 0x0, PMIO) IO (Decode16, 0x0, 0x0, 0x40, 0x0, GPIO) diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb index d465a82..94a38d7 100644 --- a/src/mainboard/aopen/dxplplusu/devicetree.cb +++ b/src/mainboard/aopen/dxplplusu/devicetree.cb @@ -24,6 +24,7 @@ chip northbridge/intel/e7505 device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 device lapic 0 on end + device lapic 6 on end end end @@ -79,6 +80,8 @@ chip northbridge/intel/e7505 end end device pci 1f.1 on end # IDE + register "ide0_enable" = "1" + register "ide1_enable" = "1" device pci 1f.3 on end # SMBus device pci 1f.5 on end # AC97 Audio device pci 1f.6 off end # AC97 Modem diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl index 31cfa88..095df06 100644 --- a/src/mainboard/aopen/dxplplusu/dsdt.asl +++ b/src/mainboard/aopen/dxplplusu/dsdt.asl @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/ioapic.h> + DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 573e0f1..73e445b 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -27,6 +27,8 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> +#include <cpu/x86/bist.h> +#include <spd.h> #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/early_smbus.c" @@ -35,13 +37,6 @@ #include "northbridge/intel/e7505/debug.c" #include "superio/smsc/lpc47m10x/early_serial.c" -#if !CONFIG_CACHE_AS_RAM -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#endif -#include "cpu/x86/bist.h" - -#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) @@ -50,21 +45,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -/* Cache-As-Ram compiles for this board, but with the CPUs I have, - * it halts on boot while in Local Apic ID negotiation. - */ - -#if CONFIG_CACHE_AS_RAM -#define BOARD_MAIN(x) void main(x) -#define early_mtrr_init() do {} while (0) -#else -#define BOARD_MAIN(x) static void main(x) -#endif - #include "northbridge/intel/e7505/raminit.c" -// This function MUST appear last (ROMCC limitation) -BOARD_MAIN(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl[] = { { @@ -75,12 +58,6 @@ BOARD_MAIN(unsigned long bist) }, }; - if (bist == 0) { - // Skip this if there was a built in self test failure - early_mtrr_init(); - enable_lapic(); - } - // Get the serial port running and print a welcome banner lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); @@ -94,8 +71,5 @@ BOARD_MAIN(unsigned long bist) sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } - // NOTE: ROMCC dies with an internal compiler error - // if the following line is removed. - print_debug("SDRAM is up.\r\n"); - + print_debug("SDRAM is up.\n"); } [View Less]

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Re: [coreboot] ASUS M2V problems
by G 11 Apr '12

11 Apr '12

On Tue, Apr 10, 2012 at 5:26 PM, Marc Jones <marcj303(a)gmail.com> wrote: > On Tue, Apr 10, 2012 at 7:37 AM, G <tjmadwja(a)gmail.com> wrote: >> Hi, >> >> I'm trying to get coreboot onto my old ASUS M2V (rev. 1.01g) >> motherboard, but so far I've had no luck. I'm currently trying to >> get the coreinfo payload running, as that seems like the simplest >> test case (I've also tried seabios, and failed). >> >> After flashing, when I … [View More]boot, nothing happens. No beeps, the >> monitor remains in power-save mode, the keyboard doesn't respond >> to any keypresses (not even holding down several keys for a long >> time generates any beeps), no blinking status LEDs, nothing on >> the serial port. Nothing. >> >> I've tried with two different revisions, one from 2010-11-24 (the >> one that adds S3 support for ASUS M2V), and one from 2012-02-21 >> (all later revisions fail to compile with lots of different CBMEM >> problems). >> >> In the 2010-11-24 revision, I've had to add >> reg++; reg--; >> in src/northbridge/amd/amdk8/raminit_f_dqs.c:setup_mtrr_dqs() and >> regm3++; regm3--; >> in src/southbridge/via/vt8237r/vt8237_ctrl.c:vt8237_cfg() to get >> rid of warnings about unused variables. >> >> Flashing is done by simply running: >> ./flashrom -V -w coreboot.rom -c W39V040C >> >> Does anyone here have any idea what might be wrong? Anyone got a >> working .config, tips to use a certain known working revision, a >> know working version of flashrom (although flashing two different >> versions of ASUS's BIOS using flashrom works well, so I'm >> guessing neither flashrom nor my usage of it is to blame), a >> working coreboot.rom they can share, or anything else that might >> help me move forward? >> >> Using Debian unstable to build, if that's any help. >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > > Hi, > > You will need to capture some output from coreboot to find where your > system is having problems. > > http://www.coreboot.org/FAQ#How_do_I_use_a_null-modem_cable_to_get_coreboot… Thanks for the reply, but unfortunately, as I wrote in my original mail, I get nothing on the serial port. When I boot the standard ASUS M2V BIOS, with a null-modem cable plugged in, then exactly as I power on the M2V system, minicom on the other end briefly (less than a second) switches from Offline to Online, and then back to Offline, and then the system continues to boot. Booting coreboot, minicom switches from Offline to Online exactly when I power on the M2V system, and then the minicom status on the other machine remains Online, but nothing ever arrives in the minicom terminal window, and nothing else happens (no beeps, not LEDs, nothing on the screen, just plain nothing). I have tested that the minicom connection over null-modem cable between my M2V computer and the other machine works after booting the standard ASUS M2V BIOS, although I then have HW flow control enabled, which is then disabled before trying to boot the coreboot BIOS. And yes, I have checked the serial port settings in the coreboot config and they are set to the correct values. So, anyone got a working .config and/or working coreboot.rom I can try? A known working coreboot revision I should download and compile? Or any other tips/pointers? [View Less]

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New patch to review for coreboot: f95e0fe Convert AOpen DXPL Plus mainboard to CAR
by Kyösti Mälkki 11 Apr '12

11 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/886 -gerrit commit f95e0fe6634b6693ca2ea37b4383236a0b017f69 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 10 21:18:36 2012 +0300 Convert AOpen DXPL Plus mainboard to CAR Mainboard with hyper-threading P4 CPUs, requires a cache-as-ram init code with AP SIPI protocol. Also clean-up Kconfig and some ACPI. … [View More]Change-Id: I415482f3af22df79d82492c49aed83549f29aa56 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/aopen/dxplplusu/Kconfig | 18 ----------- src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl | 8 +++-- src/mainboard/aopen/dxplplusu/acpi/i82801db.asl | 2 +- src/mainboard/aopen/dxplplusu/devicetree.cb | 1 + src/mainboard/aopen/dxplplusu/dsdt.asl | 2 + src/mainboard/aopen/dxplplusu/romstage.c | 34 ++------------------- 6 files changed, 13 insertions(+), 52 deletions(-) diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index c3025d1..da03491 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -8,8 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82870 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_LPC47M10X - select ROMCC - select HAVE_HARD_RESET # select HAVE_PIRQ_TABLE # select PIRQ_ROUTE select UDELAY_TSC @@ -24,14 +22,6 @@ config MAINBOARD_PART_NUMBER string default "DXPL Plus-U" -config DCACHE_RAM_BASE - hex - default 0xcf000 - -config DCACHE_RAM_SIZE - hex - default 0x1000 - config IRQ_SLOT_COUNT int default 12 @@ -40,18 +30,10 @@ config BOARD_HAS_FADT bool default y -config LOGICAL_CPUS - bool - default n - config MAX_CPUS int default 4 -config MAX_PHYSICAL_CPUS - int - default 2 - config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex default 0x0 diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl index 0effe93..463b6be 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl @@ -44,8 +44,8 @@ Name (PBRS, ResourceTemplate () /* Top Of Lowmemory to IOAPIC */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0x02000000, 0xFEBFFFFF, - 0x00000000, 0xFCC00000, ,, _Y08, AddressRangeMemory, TypeStatic) + 0x00000000, 0x00000000, 0xFEBFFFFF, + 0x00000000, IO_APIC_ADDR, ,, _Y08, AddressRangeMemory, TypeStatic) }) @@ -54,11 +54,13 @@ Method (_CRS, 0, NotSerialized) /* Top Of Lowmemory to IOAPIC */ CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML) + CreateDWordField (PBRS, \_SB.PCI0._Y08._MAX, MEMH) CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM) And (\_SB.PCI0.TOLM, 0xF800, Local1) ShiftRight (Local1, 0x04, Local1) ShiftLeft (Local1, 0x14, MEML) - Subtract (0xFEC00000, MEML, LENM) + Subtract (IO_APIC_ADDR, 0x01, MEMH) + Subtract (IO_APIC_ADDR, MEML, LENM) Return (PBRS) } diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl index bb8c321..a1a23f2 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl @@ -96,7 +96,7 @@ Device (ICH0) Name (MSBF, ResourceTemplate () { /* IOAPIC 0 */ - Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000,) + Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000,) IO (Decode16, 0x0, 0x0, 0x80, 0x0, PMIO) IO (Decode16, 0x0, 0x0, 0x40, 0x0, GPIO) diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb index d465a82..42c1571 100644 --- a/src/mainboard/aopen/dxplplusu/devicetree.cb +++ b/src/mainboard/aopen/dxplplusu/devicetree.cb @@ -24,6 +24,7 @@ chip northbridge/intel/e7505 device lapic_cluster 0 on chip cpu/intel/socket_mPGA604 device lapic 0 on end + device lapic 6 on end end end diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl index 31cfa88..095df06 100644 --- a/src/mainboard/aopen/dxplplusu/dsdt.asl +++ b/src/mainboard/aopen/dxplplusu/dsdt.asl @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/ioapic.h> + DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 573e0f1..73e445b 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -27,6 +27,8 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> +#include <cpu/x86/bist.h> +#include <spd.h> #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/early_smbus.c" @@ -35,13 +37,6 @@ #include "northbridge/intel/e7505/debug.c" #include "superio/smsc/lpc47m10x/early_serial.c" -#if !CONFIG_CACHE_AS_RAM -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#endif -#include "cpu/x86/bist.h" - -#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) @@ -50,21 +45,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -/* Cache-As-Ram compiles for this board, but with the CPUs I have, - * it halts on boot while in Local Apic ID negotiation. - */ - -#if CONFIG_CACHE_AS_RAM -#define BOARD_MAIN(x) void main(x) -#define early_mtrr_init() do {} while (0) -#else -#define BOARD_MAIN(x) static void main(x) -#endif - #include "northbridge/intel/e7505/raminit.c" -// This function MUST appear last (ROMCC limitation) -BOARD_MAIN(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl[] = { { @@ -75,12 +58,6 @@ BOARD_MAIN(unsigned long bist) }, }; - if (bist == 0) { - // Skip this if there was a built in self test failure - early_mtrr_init(); - enable_lapic(); - } - // Get the serial port running and print a welcome banner lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); @@ -94,8 +71,5 @@ BOARD_MAIN(unsigned long bist) sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } - // NOTE: ROMCC dies with an internal compiler error - // if the following line is removed. - print_debug("SDRAM is up.\r\n"); - + print_debug("SDRAM is up.\n"); } [View Less]

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New patch to review for coreboot: a9a03db Fix messy code in ALIB
by Zheng Bao 11 Apr '12

11 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/885 -gerrit commit a9a03db0d3018a9f5b79fb942dccd29438eaf7f4 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Apr 11 15:41:17 2012 +0800 Fix messy code in ALIB The address return from PICK_ALIB is not protected by Coreboot. We need to use the "current", which is the correct way to allocate the ACPI table. Change-Id: … [View More]I250066eb5f755275f75c37789ce8760de35b046b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/dinar/acpi_tables.c | 3 +-- src/mainboard/amd/inagua/acpi_tables.c | 6 ++---- src/mainboard/amd/persimmon/acpi_tables.c | 6 ++---- src/mainboard/amd/south_station/acpi_tables.c | 6 ++---- src/mainboard/amd/union_station/acpi_tables.c | 6 ++---- src/mainboard/asrock/e350m1/acpi_tables.c | 6 ++---- src/mainboard/supermicro/h8qgi/acpi_tables.c | 3 +-- 7 files changed, 12 insertions(+), 24 deletions(-) diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index 741ba99..6fa9c6f 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -264,9 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index e521b4b..0588d04 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 00a08d2..789c11d 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index c49a8e2..21281c8 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index c49a8e2..21281c8 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index c49a8e2..21281c8 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -230,11 +230,9 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); - } - else { + } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 7b97a92..e587334 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -264,9 +264,8 @@ unsigned long write_acpi_tables(unsigned long start) alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); if (alib != NULL) { memcpy((void *)current, alib, alib->length); - ssdt = (acpi_header_t *) current; + acpi_add_table(rsdp, (void *)current); current += alib->length; - acpi_add_table(rsdp,alib); } else { printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } [View Less]

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New patch to review for coreboot: e520f75 Leverage the Pstate table created by AGESA.
by Zheng Bao 11 Apr '12

11 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/884 -gerrit commit e520f750d05434957cdcc150c801006af5081fa9 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Apr 11 14:24:30 2012 +0800 Leverage the Pstate table created by AGESA. The name of processor created by AGESA is P00n, whose P is BLDCFG_PROCESSOR_SCOPE_NAME and n starts from 0. The dsdt should be aligned with that. This feature has … [View More]only been tested on persimmon. The changes on all the other boards were propagated. Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/dinar/acpi_tables.c | 8 +- src/mainboard/amd/dinar/dsdt.asl | 48 ++++++++--- src/mainboard/amd/inagua/acpi_tables.c | 8 +- src/mainboard/amd/inagua/dsdt.asl | 24 ++++-- src/mainboard/amd/persimmon/acpi_tables.c | 8 +- src/mainboard/amd/persimmon/dsdt.asl | 24 ++++-- src/mainboard/amd/south_station/acpi_tables.c | 12 ++-- src/mainboard/amd/south_station/dsdt.asl | 24 ++++-- src/mainboard/amd/torpedo/dsdt.asl | 18 ++--- src/mainboard/amd/union_station/acpi_tables.c | 12 ++-- src/mainboard/amd/union_station/dsdt.asl | 24 ++++-- src/mainboard/asrock/e350m1/acpi_tables.c | 12 ++-- src/mainboard/asrock/e350m1/dsdt.asl | 24 ++++-- src/mainboard/supermicro/h8qgi/acpi_tables.c | 8 +- src/mainboard/supermicro/h8qgi/dsdt.asl | 114 ++++++++++++------------ 15 files changed, 222 insertions(+), 146 deletions(-) diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index ee00e81..741ba99 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -271,7 +271,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -279,11 +280,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); } else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl index 1cbb05e..501ec78 100644 --- a/src/mainboard/amd/dinar/dsdt.asl +++ b/src/mainboard/amd/dinar/dsdt.asl @@ -51,37 +51,61 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ - 0x00 /* PBLKLEN for boot processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x0 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU2, /* name space name */ + C002, /* name space name */ 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU3, /* name space name */ + C003, /* name space name */ 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } + Processor( + C004, /* name space name */ + 4, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C005, /* name space name */ + 5, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C006, /* name space name */ + 6, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C007, /* name space name */ + 7, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } } /* End _PR scope */ /* PIC IRQ mapping registers, C00h-C01h. */ diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 8f47591..e521b4b 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -238,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -247,12 +248,9 @@ unsigned long write_acpi_tables(unsigned long start) ssdt = (acpi_header_t *) current; current += ssdt->length; acpi_add_table(rsdp,ssdt); - } - else { + } else { printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 361adbb..7708676 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 9526fea..00a08d2 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -238,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -247,12 +248,9 @@ unsigned long write_acpi_tables(unsigned long start) ssdt = (acpi_header_t *) current; current += ssdt->length; acpi_add_table(rsdp,ssdt); - } - else { + } else { printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index b480c33..bd9ce74 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 2e6e50f..c49a8e2 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -237,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -245,12 +247,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 7f03a43..b18bcb2 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index a8a731d..758fba5 100755 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -51,36 +51,32 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU2, /* name space name */ + C002, /* name space name */ 2, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU3, /* name space name */ + C003, /* name space name */ 3, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 2e6e50f..c49a8e2 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -237,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -245,12 +247,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index fb2cfe8..7e49fd4 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 2e6e50f..c49a8e2 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -237,7 +238,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -245,12 +247,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); + } else { + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 97533c1..c2ea1fb 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -64,21 +64,33 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - CPU0, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0, /* Unique number for this processor */ - 0x808, /* PBLK system I/O address !hardcoded! */ + 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } Processor( - CPU1, /* name space name */ + C001, /* name space name */ 1, /* Unique number for this processor */ - 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810 , /* PBLK system I/O address !hardcoded! */ 0x00 /* PBLKLEN for boot processor */ ) { - #include "acpi/cpstate.asl" } } /* End _PR scope */ diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 7314283..7b97a92 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -271,7 +271,8 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } -#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + /* Keep the comment for a while. */ current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); @@ -279,11 +280,10 @@ unsigned long write_acpi_tables(unsigned long start) memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; + acpi_add_table(rsdp,ssdt); } else { - printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n"); } - acpi_add_table(rsdp,ssdt); -#endif current = ( current + 0x0f) & -0x10; printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index 137a90d..39ad9d8 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -65,69 +65,69 @@ DefinitionBlock ( */ Scope (\_PR) { /* define processor scope */ Processor( - P000, /* name space name */ + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ 0x00, /* Unique number for this processor */ 0x810, /* PBLK system I/O address !hardcoded! */ 0x06 /* PBLKLEN for boot processor */ ) { //#include "acpi/cpstate.asl" } - Processor(P001, 0x01, 0x00000000, 0x00) {} - Processor(P002, 0x02, 0x00000000, 0x00) {} - Processor(P003, 0x03, 0x00000000, 0x00) {} - Processor(P004, 0x04, 0x00000000, 0x00) {} - Processor(P005, 0x05, 0x00000000, 0x00) {} - Processor(P006, 0x06, 0x00000000, 0x00) {} - Processor(P007, 0x07, 0x00000000, 0x00) {} - Processor(P008, 0x08, 0x00000000, 0x00) {} - Processor(P009, 0x09, 0x00000000, 0x00) {} - Processor(P00A, 0x0A, 0x00000000, 0x00) {} - Processor(P00B, 0x0B, 0x00000000, 0x00) {} - Processor(P00C, 0x0C, 0x00000000, 0x00) {} - Processor(P00D, 0x0D, 0x00000000, 0x00) {} - Processor(P00E, 0x0E, 0x00000000, 0x00) {} - Processor(P00F, 0x0F, 0x00000000, 0x00) {} - Processor(P010, 0x10, 0x00000000, 0x00) {} - Processor(P011, 0x11, 0x00000000, 0x00) {} - Processor(P012, 0x12, 0x00000000, 0x00) {} - Processor(P013, 0x13, 0x00000000, 0x00) {} - Processor(P014, 0x14, 0x00000000, 0x00) {} - Processor(P015, 0x15, 0x00000000, 0x00) {} - Processor(P016, 0x16, 0x00000000, 0x00) {} - Processor(P017, 0x17, 0x00000000, 0x00) {} - Processor(P018, 0x18, 0x00000000, 0x00) {} - Processor(P019, 0x19, 0x00000000, 0x00) {} - Processor(P01A, 0x1A, 0x00000000, 0x00) {} - Processor(P01B, 0x1B, 0x00000000, 0x00) {} - Processor(P01C, 0x1C, 0x00000000, 0x00) {} - Processor(P01D, 0x1D, 0x00000000, 0x00) {} - Processor(P01E, 0x1E, 0x00000000, 0x00) {} - Processor(P01F, 0x1F, 0x00000000, 0x00) {} - Processor(P020, 0x20, 0x00000000, 0x00) {} - Processor(P021, 0x21, 0x00000000, 0x00) {} - Processor(P022, 0x22, 0x00000000, 0x00) {} - Processor(P023, 0x23, 0x00000000, 0x00) {} - Processor(P024, 0x24, 0x00000000, 0x00) {} - Processor(P025, 0x25, 0x00000000, 0x00) {} - Processor(P026, 0x26, 0x00000000, 0x00) {} - Processor(P027, 0x27, 0x00000000, 0x00) {} - Processor(P028, 0x28, 0x00000000, 0x00) {} - Processor(P029, 0x29, 0x00000000, 0x00) {} - Processor(P02A, 0x2A, 0x00000000, 0x00) {} - Processor(P02B, 0x2B, 0x00000000, 0x00) {} - Processor(P02C, 0x2C, 0x00000000, 0x00) {} - Processor(P02D, 0x2D, 0x00000000, 0x00) {} - Processor(P02E, 0x2E, 0x00000000, 0x00) {} - Processor(P02F, 0x2F, 0x00000000, 0x00) {} - Alias (P000, CPU0) - Alias (P001, CPU1) - Alias (P002, CPU2) - Alias (P003, CPU3) - Alias (P004, CPU4) - Alias (P005, CPU5) - Alias (P006, CPU6) - Alias (P007, CPU7) - Alias (P008, CPU8) + Processor(C001, 0x01, 0x00000000, 0x00) {} + Processor(C002, 0x02, 0x00000000, 0x00) {} + Processor(C003, 0x03, 0x00000000, 0x00) {} + Processor(C004, 0x04, 0x00000000, 0x00) {} + Processor(C005, 0x05, 0x00000000, 0x00) {} + Processor(C006, 0x06, 0x00000000, 0x00) {} + Processor(C007, 0x07, 0x00000000, 0x00) {} + Processor(C008, 0x08, 0x00000000, 0x00) {} + Processor(C009, 0x09, 0x00000000, 0x00) {} + Processor(C00A, 0x0A, 0x00000000, 0x00) {} + Processor(C00B, 0x0B, 0x00000000, 0x00) {} + Processor(C00C, 0x0C, 0x00000000, 0x00) {} + Processor(C00D, 0x0D, 0x00000000, 0x00) {} + Processor(C00E, 0x0E, 0x00000000, 0x00) {} + Processor(C00F, 0x0F, 0x00000000, 0x00) {} + Processor(C010, 0x10, 0x00000000, 0x00) {} + Processor(C011, 0x11, 0x00000000, 0x00) {} + Processor(C012, 0x12, 0x00000000, 0x00) {} + Processor(C013, 0x13, 0x00000000, 0x00) {} + Processor(C014, 0x14, 0x00000000, 0x00) {} + Processor(C015, 0x15, 0x00000000, 0x00) {} + Processor(C016, 0x16, 0x00000000, 0x00) {} + Processor(C017, 0x17, 0x00000000, 0x00) {} + Processor(C018, 0x18, 0x00000000, 0x00) {} + Processor(C019, 0x19, 0x00000000, 0x00) {} + Processor(C01A, 0x1A, 0x00000000, 0x00) {} + Processor(C01B, 0x1B, 0x00000000, 0x00) {} + Processor(C01C, 0x1C, 0x00000000, 0x00) {} + Processor(C01D, 0x1D, 0x00000000, 0x00) {} + Processor(C01E, 0x1E, 0x00000000, 0x00) {} + Processor(C01F, 0x1F, 0x00000000, 0x00) {} + Processor(C020, 0x20, 0x00000000, 0x00) {} + Processor(C021, 0x21, 0x00000000, 0x00) {} + Processor(C022, 0x22, 0x00000000, 0x00) {} + Processor(C023, 0x23, 0x00000000, 0x00) {} + Processor(C024, 0x24, 0x00000000, 0x00) {} + Processor(C025, 0x25, 0x00000000, 0x00) {} + Processor(C026, 0x26, 0x00000000, 0x00) {} + Processor(C027, 0x27, 0x00000000, 0x00) {} + Processor(C028, 0x28, 0x00000000, 0x00) {} + Processor(C029, 0x29, 0x00000000, 0x00) {} + Processor(C02A, 0x2A, 0x00000000, 0x00) {} + Processor(C02B, 0x2B, 0x00000000, 0x00) {} + Processor(C02C, 0x2C, 0x00000000, 0x00) {} + Processor(C02D, 0x2D, 0x00000000, 0x00) {} + Processor(C02E, 0x2E, 0x00000000, 0x00) {} + Processor(C02F, 0x2F, 0x00000000, 0x00) {} + Alias (C000, CPU0) + Alias (C001, CPU1) + Alias (C002, CPU2) + Alias (C003, CPU3) + Alias (C004, CPU4) + Alias (C005, CPU5) + Alias (C006, CPU6) + Alias (C007, CPU7) + Alias (C008, CPU8) } /* End _PR scope */ /* PIC IRQ mapping registers, C00h-C01h */ [View Less]

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[Honest Request] Use Coreboot as BIOS for Server and Storage motherboard
by Kiran Patil 10 Apr '12

10 Apr '12

Kudos OCP experts, I am resending this mail, since earlier mail is rejected due to size issues. To make this project true "Open Compute Project", this Coreboot BIOS software on Motherboard is essential. I request you to consider using Coreboot (www.coreboot.org) as BIOS for Server and Storage motherboards used in Open Compute Project. Thanks, Kiran.

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Patch set updated for coreboot: 7f83ace Intel e7505: cleanups
by Kyösti Mälkki 10 Apr '12

10 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/883 -gerrit commit 7f83ace920173381d4a6316a375b685735d424fa Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 10 19:55:19 2012 +0300 Intel e7505: cleanups Fix delay loop comments. Time waited and the comments did not match in the origin (e7501), so delays currently "just work". Move reset detection to main raminit … [View More]and don't use generic sdram_initialize for now, as there are local debug functions I need to use. Fix AOpen respectively. Disable ecc scrub, until I have it fixed for cache-as-ram use. Change-Id: I0529297f43c565d30b5fb7d1836700278ac029c4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/aopen/dxplplusu/romstage.c | 2 - src/northbridge/intel/e7505/raminit.c | 89 +++++++++++++++-------------- src/northbridge/intel/e7505/reset_test.c | 18 ------ 3 files changed, 46 insertions(+), 63 deletions(-) diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 92ce896..573e0f1 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -62,8 +62,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif #include "northbridge/intel/e7505/raminit.c" -#include "northbridge/intel/e7505/reset_test.c" -#include "lib/generic_sdram.c" // This function MUST appear last (ROMCC limitation) BOARD_MAIN(unsigned long bist) diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 21ffba2..29eb42b 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -464,27 +464,25 @@ static const uint32_t pull_updown_offset_table[] = { Delay functions: -----------------------------------------------------------------------------*/ +/* Estimate that SLOW_DOWN_IO takes about 1 us */ #define SLOW_DOWN_IO inb(0x80) -//#define SLOW_DOWN_IO udelay(40); - - /* Estimate that SLOW_DOWN_IO takes about 50&76us */ - /* delay for 200us */ - -#if 1 -static void do_delay(void) +static inline void local_udelay(int i) { - int i; - for (i = 0; i < 16; i++) { + while (i--) { SLOW_DOWN_IO; } } -#define DO_DELAY do_delay() -#else -#define DO_DELAY \ - udelay(200) -#endif +static inline void local_mdelay(int i) +{ + i *= 1000; + while (i--) { + SLOW_DOWN_IO; + } +} +/* delay for 200us */ +#define DO_DELAY local_udelay(200) #define EXTRA_DELAY DO_DELAY /*----------------------------------------------------------------------------- @@ -913,8 +911,10 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) // RAM_COMMAND_NORMAL is an exception. // It affects only the memory controller and does not need to be "sent" to the DIMMs. - if (command == RAM_COMMAND_NORMAL) + if (command == RAM_COMMAND_NORMAL) { + EXTRA_DELAY; return; + } // NOTE: for mode select commands, some of the location address bits are part of the command // Map JEDEC mode bits to E7505 @@ -949,7 +949,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) dimm_start_64M_multiple = dimm_end_64M_multiple; } } - + EXTRA_DELAY; } /** @@ -1169,6 +1169,7 @@ static void configure_e7501_ram_addresses(const struct mem_controller * If we're configured to use ECC, initialize the SDRAM and clear the E7501's * ECC error flags. */ +#ifdef __ROMCC__ static void initialize_ecc(void) { uint32_t dram_controller_mode; @@ -1202,6 +1203,7 @@ static void initialize_ecc(void) } } +#endif /** * Program the DRAM Timing register (DRT) of the E7501 (except for CAS# @@ -1898,12 +1900,10 @@ Public interface: * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up * and running. * - * @param controllers Not used. * @param ctrl PCI addresses of memory controller functions, and SMBus * addresses of DIMM slots on the mainboard. */ -static void sdram_enable(int controllers, - const struct mem_controller *ctrl) +static void sdram_enable(const struct mem_controller *ctrl) { uint8_t dimm_mask = pci_read_config16(MCHDEV, SKPD); uint32_t dram_controller_mode; @@ -1921,12 +1921,10 @@ static void sdram_enable(int controllers, /* 3. Apply NOP */ RAM_DEBUG_MESSAGE("Ram Enable 3\n"); do_ram_command(RAM_COMMAND_NOP, 0); - EXTRA_DELAY; /* 4 Precharge all */ RAM_DEBUG_MESSAGE("Ram Enable 4\n"); do_ram_command(RAM_COMMAND_PRECHARGE, 0); - EXTRA_DELAY; /* wait until the all banks idle state... */ /* 5. Issue EMRS to enable DLL */ @@ -1934,7 +1932,6 @@ static void sdram_enable(int controllers, do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL); - EXTRA_DELAY; /* 6. Reset DLL */ RAM_DEBUG_MESSAGE("Ram Enable 6\n"); @@ -1949,33 +1946,17 @@ static void sdram_enable(int controllers, /* 7 Precharge all */ RAM_DEBUG_MESSAGE("Ram Enable 7\n"); do_ram_command(RAM_COMMAND_PRECHARGE, 0); - EXTRA_DELAY; /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */ - RAM_DEBUG_MESSAGE("Ram Enable 8\n"); - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - /* And for good luck 6 more CBRs */ - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; + RAM_DEBUG_MESSAGE("Ram Enable 8\n"); + int i; + for(i=0; i<8; i++) + do_ram_command(RAM_COMMAND_CBR, 0); /* 9 mode register set */ RAM_DEBUG_MESSAGE("Ram Enable 9\n"); set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL); - EXTRA_DELAY; /* 10 DDR Receive FIFO RE-Sync */ RAM_DEBUG_MESSAGE("Ram Enable 10\n"); @@ -1985,7 +1966,6 @@ static void sdram_enable(int controllers, /* 11 normal operation */ RAM_DEBUG_MESSAGE("Ram Enable 11\n"); do_ram_command(RAM_COMMAND_NORMAL, 0); - EXTRA_DELAY; // Reconfigure the row boundaries and Top of Low Memory // to match the true size of the DIMMs @@ -1996,7 +1976,11 @@ static void sdram_enable(int controllers, dram_controller_mode |= (1 << 29); pci_write_config32(MCHDEV, DRC, dram_controller_mode); EXTRA_DELAY; + +#ifdef __ROMCC__ + /* Problems with cache-as-ram, disable for now */ initialize_ecc(); +#endif dram_controller_mode = pci_read_config32(MCHDEV, DRC); /* FCS_EN */ dram_controller_mode |= (1 << 17); // NOTE: undocumented reserved bit @@ -2069,3 +2053,22 @@ static void sdram_set_registers(const struct mem_controller *ctrl) ram_handle_d060_2(); } +/** + * + * + */ +void sdram_initialize(int controllers, const struct mem_controller *memctrl) +{ + RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); + DUMPNORTH(); + + sdram_set_registers(memctrl); + sdram_set_spd_registers(memctrl); + sdram_enable(memctrl); +} + +static int bios_reset_detected(void) +{ + uint32_t dword = pci_read_config32(MCHDEV, DRC); + return !!(dword & DRC_DONE); +} diff --git a/src/northbridge/intel/e7505/reset_test.c b/src/northbridge/intel/e7505/reset_test.c deleted file mode 100644 index 1c0dad5..0000000 --- a/src/northbridge/intel/e7505/reset_test.c +++ /dev/null @@ -1,18 +0,0 @@ -/* Convert to C by yhlu */ -#define MCH_DRC 0x7c -#define DRC_DONE (1 << 29) - /* If I have already booted once skip a bunch of initialization */ - /* To see if I have already booted I check to see if memory - * has been enabled. - */ -static int bios_reset_detected(void) { - uint32_t dword; - - dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC); - - if( (dword & DRC_DONE) != 0 ) { - return 1; - } - - return 0; -} [View Less]

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New patch to review for coreboot: 3fdf815 Intel e7505: cleanups
by Kyösti Mälkki 10 Apr '12

10 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/883 -gerrit commit 3fdf815578294f606fe3e3d8918c56f8726ec135 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 10 18:46:14 2012 +0300 Intel e7505: cleanups Fix delay loop comments. Time waited and the comments did not match in the origin (e7501), so delays currently "just work". Move reset detection to main raminit … [View More]and don't use generic sdram_initialize for now, as there are local debug functions I need to use. Fix AOpen respectively. Disable ecc scrub, until I have it fixed for cache-as-ram use. Change-Id: I0529297f43c565d30b5fb7d1836700278ac029c4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/aopen/dxplplusu/romstage.c | 2 - src/northbridge/intel/e7505/raminit.c | 87 +++++++++++++++--------------- src/northbridge/intel/e7505/reset_test.c | 18 ------ 3 files changed, 44 insertions(+), 63 deletions(-) diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 92ce896..573e0f1 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -62,8 +62,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #endif #include "northbridge/intel/e7505/raminit.c" -#include "northbridge/intel/e7505/reset_test.c" -#include "lib/generic_sdram.c" // This function MUST appear last (ROMCC limitation) BOARD_MAIN(unsigned long bist) diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 21ffba2..9eaaa92 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -464,27 +464,25 @@ static const uint32_t pull_updown_offset_table[] = { Delay functions: -----------------------------------------------------------------------------*/ +/* Estimate that SLOW_DOWN_IO takes about 1 us */ #define SLOW_DOWN_IO inb(0x80) -//#define SLOW_DOWN_IO udelay(40); - - /* Estimate that SLOW_DOWN_IO takes about 50&76us */ - /* delay for 200us */ - -#if 1 -static void do_delay(void) +static inline void local_udelay(int i) { - int i; - for (i = 0; i < 16; i++) { + while (i--) { SLOW_DOWN_IO; } } -#define DO_DELAY do_delay() -#else -#define DO_DELAY \ - udelay(200) -#endif +static inline void local_mdelay(int i) +{ + i *= 1000; + while (i--) { + SLOW_DOWN_IO; + } +} +/* delay for 200us */ +#define DO_DELAY local_udelay(200) #define EXTRA_DELAY DO_DELAY /*----------------------------------------------------------------------------- @@ -913,8 +911,10 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) // RAM_COMMAND_NORMAL is an exception. // It affects only the memory controller and does not need to be "sent" to the DIMMs. - if (command == RAM_COMMAND_NORMAL) + if (command == RAM_COMMAND_NORMAL) { + EXTRA_DELAY; return; + } // NOTE: for mode select commands, some of the location address bits are part of the command // Map JEDEC mode bits to E7505 @@ -949,7 +949,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) dimm_start_64M_multiple = dimm_end_64M_multiple; } } - + EXTRA_DELAY; } /** @@ -1898,12 +1898,10 @@ Public interface: * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up * and running. * - * @param controllers Not used. * @param ctrl PCI addresses of memory controller functions, and SMBus * addresses of DIMM slots on the mainboard. */ -static void sdram_enable(int controllers, - const struct mem_controller *ctrl) +static void sdram_enable(const struct mem_controller *ctrl) { uint8_t dimm_mask = pci_read_config16(MCHDEV, SKPD); uint32_t dram_controller_mode; @@ -1921,12 +1919,10 @@ static void sdram_enable(int controllers, /* 3. Apply NOP */ RAM_DEBUG_MESSAGE("Ram Enable 3\n"); do_ram_command(RAM_COMMAND_NOP, 0); - EXTRA_DELAY; /* 4 Precharge all */ RAM_DEBUG_MESSAGE("Ram Enable 4\n"); do_ram_command(RAM_COMMAND_PRECHARGE, 0); - EXTRA_DELAY; /* wait until the all banks idle state... */ /* 5. Issue EMRS to enable DLL */ @@ -1934,7 +1930,6 @@ static void sdram_enable(int controllers, do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL); - EXTRA_DELAY; /* 6. Reset DLL */ RAM_DEBUG_MESSAGE("Ram Enable 6\n"); @@ -1949,33 +1944,17 @@ static void sdram_enable(int controllers, /* 7 Precharge all */ RAM_DEBUG_MESSAGE("Ram Enable 7\n"); do_ram_command(RAM_COMMAND_PRECHARGE, 0); - EXTRA_DELAY; /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */ - RAM_DEBUG_MESSAGE("Ram Enable 8\n"); - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - /* And for good luck 6 more CBRs */ - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; - do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY; + RAM_DEBUG_MESSAGE("Ram Enable 8\n"); + int i; + for(i=0; i<8; i++) + do_ram_command(RAM_COMMAND_CBR, 0); /* 9 mode register set */ RAM_DEBUG_MESSAGE("Ram Enable 9\n"); set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL); - EXTRA_DELAY; /* 10 DDR Receive FIFO RE-Sync */ RAM_DEBUG_MESSAGE("Ram Enable 10\n"); @@ -1985,7 +1964,6 @@ static void sdram_enable(int controllers, /* 11 normal operation */ RAM_DEBUG_MESSAGE("Ram Enable 11\n"); do_ram_command(RAM_COMMAND_NORMAL, 0); - EXTRA_DELAY; // Reconfigure the row boundaries and Top of Low Memory // to match the true size of the DIMMs @@ -1996,7 +1974,11 @@ static void sdram_enable(int controllers, dram_controller_mode |= (1 << 29); pci_write_config32(MCHDEV, DRC, dram_controller_mode); EXTRA_DELAY; + +#if 0 + /* Problems with cache-as-ram, disable for now */ initialize_ecc(); +#endif dram_controller_mode = pci_read_config32(MCHDEV, DRC); /* FCS_EN */ dram_controller_mode |= (1 << 17); // NOTE: undocumented reserved bit @@ -2069,3 +2051,22 @@ static void sdram_set_registers(const struct mem_controller *ctrl) ram_handle_d060_2(); } +/** + * + * + */ +void sdram_initialize(int controllers, const struct mem_controller *memctrl) +{ + RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); + DUMPNORTH(); + + sdram_set_registers(memctrl); + sdram_set_spd_registers(memctrl); + sdram_enable(memctrl); +} + +static int bios_reset_detected(void) +{ + uint32_t dword = pci_read_config32(MCHDEV, DRC); + return !!(dword & DRC_DONE); +} diff --git a/src/northbridge/intel/e7505/reset_test.c b/src/northbridge/intel/e7505/reset_test.c deleted file mode 100644 index 1c0dad5..0000000 --- a/src/northbridge/intel/e7505/reset_test.c +++ /dev/null @@ -1,18 +0,0 @@ -/* Convert to C by yhlu */ -#define MCH_DRC 0x7c -#define DRC_DONE (1 << 29) - /* If I have already booted once skip a bunch of initialization */ - /* To see if I have already booted I check to see if memory - * has been enabled. - */ -static int bios_reset_detected(void) { - uint32_t dword; - - dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC); - - if( (dword & DRC_DONE) != 0 ) { - return 1; - } - - return 0; -} [View Less]

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Re: [coreboot] Patch merged into coreboot/master: c35c461 Invalidate cache before first jump
by Bao, Zheng 10 Apr '12

10 Apr '12

Hi, It is unstable. In most cases, it hangs at this wbinvd. Once it pass that instruction, it will hang at when AP cores are launched. Joe > -----Original Message----- > From: Marc Jones [mailto:marcj303@gmail.com] > Sent: Friday, April 06, 2012 11:27 PM > To: Bao, Zheng > Cc: coreboot(a)coreboot.org; Marc Jones > Subject: Re: [coreboot] Patch merged into coreboot/master: c35c461 > Invalidate cache before first jump > > Can you be more descriptive to how it fails? … [View More]

3 3

ASUS M2V problems
by G 10 Apr '12

10 Apr '12

Hi, I'm trying to get coreboot onto my old ASUS M2V (rev. 1.01g) motherboard, but so far I've had no luck. I'm currently trying to get the coreinfo payload running, as that seems like the simplest test case (I've also tried seabios, and failed). After flashing, when I boot, nothing happens. No beeps, the monitor remains in power-save mode, the keyboard doesn't respond to any keypresses (not even holding down several keys for a long time generates any beeps), no blinking status LEDs, nothing … [View More]

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New patch to review for coreboot: ddfe8df Intel e7505: renames only
by Kyösti Mälkki 10 Apr '12

10 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/882 -gerrit commit ddfe8df0d5fa6466be8cb908aaaf5f08ad0293bc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 10 16:11:53 2012 +0300 Intel e7505: renames only Drop maybe-prefix in registers and tables. Have a name in place of PCI_DEV(x,y,z) to avoid confusion. Change-Id: I88f51b50d7fd83294aa14455a83418630e1bab85 … [View More] Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/e7505/e7505.h | 78 +++++---- src/northbridge/intel/e7505/northbridge.c | 2 +- src/northbridge/intel/e7505/raminit.c | 266 +++++++++++++++-------------- 3 files changed, 178 insertions(+), 168 deletions(-) diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index e20c5bc..3fd3aae 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -24,56 +24,62 @@ /************ D0:F0 ************/ // Register offsets -#define MAYBE_SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? (if similar to 855PM) */ -#define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */ -#define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */ -#define DRB_ROW_1 0x61 -#define DRB_ROW_2 0x62 -#define DRB_ROW_3 0x63 -#define DRB_ROW_4 0x64 -#define DRB_ROW_5 0x65 -#define DRB_ROW_6 0x66 -#define DRB_ROW_7 0x67 +#define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */ +#define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */ -#define DRA 0x70 /* DRAM Row Attributes registers, 4 x 8 bit */ -#define DRT 0x78 /* DRAM Timing register, 32 bit */ -#define DRC 0x7C /* DRAM Controller Mode register, 32 bit */ -#define MAYBE_DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */ -#define CKDIS 0x8C /* Clock disable register, 8 bit */ -#define TOLM 0xC4 /* Top of Low Memory register, 16 bit */ -#define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */ -#define REMAPLIMIT 0xC8 /* Remap Limit Address register, 16 bit */ -#define SKPD 0xDE /* Scratchpad register, 16 bit */ -#define MAYBE_MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */ +#define PAM_0 0x59 + +#define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */ +#define DRB_ROW_1 0x61 +#define DRB_ROW_2 0x62 +#define DRB_ROW_3 0x63 +#define DRB_ROW_4 0x64 +#define DRB_ROW_5 0x65 +#define DRB_ROW_6 0x66 +#define DRB_ROW_7 0x67 + +#define DRA 0x70 /* DRAM Row Attributes registers, 4 x 8 bit */ +#define DRT 0x78 /* DRAM Timing register, 32 bit */ +#define DRC 0x7C /* DRAM Controller Mode register, 32 bit */ +#define DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */ +#define CKDIS 0x8C /* Clock disable register, 8 bit */ +#define TOLM 0xC4 /* Top of Low Memory register, 16 bit */ +#define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */ +#define REMAPLIMIT 0xC8 /* Remap Limit Address register, 16 bit */ +#define SKPD 0xDE /* Scratchpad register, 16 bit */ +#define DVNP 0xE0 /* Device Not Present, 16 bit */ +#define MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */ // CAS# Latency bits in the DRAM Timing (DRT) register #define DRT_CAS_2_5 (0<<4) #define DRT_CAS_2_0 (1<<4) -#define DRT_CAS_MASK (3<<4) +#define DRT_CAS_MASK (3<<4) // Mode Select (SMS) bits in the DRAM Controller Mode (DRC) register -#define RAM_COMMAND_NOP (1<<4) +#define RAM_COMMAND_NOP (1<<4) #define RAM_COMMAND_PRECHARGE (2<<4) -#define RAM_COMMAND_MRS (3<<4) -#define RAM_COMMAND_EMRS (4<<4) -#define RAM_COMMAND_CBR (6<<4) -#define RAM_COMMAND_NORMAL (7<<4) +#define RAM_COMMAND_MRS (3<<4) +#define RAM_COMMAND_EMRS (4<<4) +#define RAM_COMMAND_CBR (6<<4) +#define RAM_COMMAND_NORMAL (7<<4) +#define DRC_DONE (1 << 29) // RCOMP Memory Map offsets // Conjecture based on apparent similarity between E7501 and 855PM // Intel doc. 252613-003 describes these for 855PM -#define MAYBE_SMRCTL 0x20 /* System Memory RCOMP Control Register? */ -#define MAYBE_DQCMDSTR 0x30 /* Strength control for DQ and CMD signal groups? */ -#define MAYBE_CKESTR 0x31 /* Strength control for CKE signal group? */ -#define MAYBE_CSBSTR 0x32 /* Strength control for CS# signal group? */ -#define MAYBE_CKSTR 0x33 /* Strength control for CK signal group? */ -#define MAYBE_RCVENSTR 0x34 /* Strength control for RCVEnOut# signal group? */ +#define SMRCTL 0x20 /* System Memory RCOMP Control Register? */ +#define DQCMDSTR 0x30 /* Strength control for DQ and CMD signal groups? */ +#define CKESTR 0x31 /* Strength control for CKE signal group? */ +#define CSBSTR 0x32 /* Strength control for CS# signal group? */ +#define CKSTR 0x33 /* Strength control for CK signal group? */ +#define RCVENSTR 0x34 /* Strength control for RCVEnOut# signal group? */ /************ D0:F1 ************/ // Register offsets -#define FERR_GLOBAL 0x40 /* First global error register, 32 bits */ -#define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ -#define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ -#define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ +#define FERR_GLOBAL 0x40 /* First global error register, 32 bits */ +#define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ +#define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ +#define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 1ea3ce9..6a533cd 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -38,7 +38,7 @@ static void pci_domain_set_resources(device_t dev) * the physical memory. The units are ticks of 64MB * i.e. 1 means 64MB. */ - tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16; + tomk = ((unsigned long)pci_read_config8(mc_dev, DRB_ROW_7)) << 16; /* Compute the top of Low memory */ tolmk = pci_tolm >> 10; if (tolmk >= tomk) { diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 46c1903..21ffba2 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -30,7 +30,7 @@ Definitions: #define RAM_DEBUG_MESSAGE(x) print_debug(x) #define RAM_DEBUG_HEX32(x) print_debug_hex32(x) #define RAM_DEBUG_HEX8(x) print_debug_hex8(x) -#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) +#define DUMPNORTH() dump_pci_device(MCHDEV) #else #define RAM_DEBUG_MESSAGE(x) #define RAM_DEBUG_HEX32(x) @@ -41,6 +41,10 @@ Definitions: #define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4) #define SPD_ERROR "Error reading SPD info\n" +#define MCHDEV PCI_DEV(0,0,0) +#define RASDEV PCI_DEV(0,0,1) +#define D060DEV PCI_DEV(0,6,0) + // NOTE: This used to be 0x100000. // That doesn't work on systems where A20M# is asserted, because // attempts to access 0x1000NN end up accessing 0x0000NN. @@ -438,20 +442,20 @@ static const long constant_register_values[] = { /* DDR RECOMP tables */ #if 0 // Slew table for 1x drive? -static const uint32_t maybe_1x_slew_table[] = { +static const uint32_t 1x_slew_table[] = { 0x44332211, 0xc9776655, 0xffffffff, 0xffffffff, 0x22111111, 0x55444332, 0xfffca876, 0xffffffff, }; #endif // Slew table for 2x drive? -static const uint32_t maybe_2x_slew_table[] = { +static const uint32_t slew_2x[] = { 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff, 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff, }; // Pull Up / Pull Down offset table, if analogous to IXP2800? -static const uint32_t maybe_pull_updown_offset_table[] = { +static const uint32_t pull_updown_offset_table[] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x88888888, 0x88888888, 0x88888888, 0x88888888, }; @@ -494,17 +498,17 @@ static void ram_handle_d060_1(void) { uint32_t dword; - dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST); + dword = pci_read_config32(MCHDEV, MCHTST); dword |= 0x02; - pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword); + pci_write_config32(MCHDEV, MCHTST, dword); - dword = pci_read_config32(PCI_DEV(0,6,0), 0xf0); + dword = pci_read_config32(D060DEV, 0xf0); dword |= 0x04; - pci_write_config32(PCI_DEV(0,6,0), 0xf0, dword); + pci_write_config32(D060DEV, 0xf0, dword); - dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST); + dword = pci_read_config32(MCHDEV, MCHTST); dword &= ~0x02; - pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword); + pci_write_config32(MCHDEV, MCHTST, dword); } /** @@ -515,19 +519,19 @@ static void ram_handle_d060_2(void) uint32_t dword; uint8_t revision; - revision = pci_read_config8(PCI_DEV(0,0,0), 0x08); + revision = pci_read_config8(MCHDEV, 0x08); if (revision >= 3) { - dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST); + dword = pci_read_config32(MCHDEV, MCHTST); dword |= 0x02; - pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword); + pci_write_config32(MCHDEV, MCHTST, dword); - dword = pci_read_config32(PCI_DEV(0,6,0), 0xf0); + dword = pci_read_config32(D060DEV, 0xf0); dword |= 0x18000000; - pci_write_config32(PCI_DEV(0,6,0), 0xf0, dword); + pci_write_config32(D060DEV, 0xf0, dword); - dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST); + dword = pci_read_config32(MCHDEV, MCHTST); dword &= ~0x02; - pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword); + pci_write_config32(MCHDEV, MCHTST, dword); } } @@ -902,10 +906,10 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) uint8_t i; // Configure the RAM command - dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); + dram_controller_mode = pci_read_config32(MCHDEV, DRC); dram_controller_mode &= 0xFFFFFF8F; dram_controller_mode |= command; - pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); + pci_write_config32(MCHDEV, DRC, dram_controller_mode); // RAM_COMMAND_NORMAL is an exception. // It affects only the memory controller and does not need to be "sent" to the DIMMs. @@ -935,7 +939,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) { - uint8_t dimm_end_64M_multiple = pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i); + uint8_t dimm_end_64M_multiple = pci_read_config8(MCHDEV, DRB_ROW_0 + i); if (dimm_end_64M_multiple > dimm_start_64M_multiple) { dimm_start_address &= 0x3ffffff; @@ -962,7 +966,7 @@ static void set_ram_mode(uint16_t jedec_mode_bits) ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK)); uint32_t dram_cas_latency = - pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK; + pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK; switch (dram_cas_latency) { case DRT_CAS_2_5: @@ -1024,7 +1028,7 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29)); // Configure the boundary address for the row on side 1 - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (dimm_index << 1), + pci_write_config8(MCHDEV, DRB_ROW_0 + (dimm_index << 1), total_dram_64M_multiple); // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair @@ -1034,16 +1038,16 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits (1 << (dimm_log2_num_bits.side2 - 29)); // Configure the boundary address for the row (if any) on side 2 - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (dimm_index << 1), + pci_write_config8(MCHDEV, DRB_ROW_1 + (dimm_index << 1), total_dram_64M_multiple); // Update boundaries for rows subsequent to these. // These settings will be overridden by a subsequent call if a populated physical slot exists for (i = dimm_index + 1; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (i << 1), + pci_write_config8(MCHDEV, DRB_ROW_0 + (i << 1), total_dram_64M_multiple); - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (i << 1), + pci_write_config8(MCHDEV, DRB_ROW_1 + (i << 1), total_dram_64M_multiple); } @@ -1068,8 +1072,8 @@ static void configure_e7501_ram_addresses(const struct mem_controller // Configure the E7501's DRAM row boundaries // Start by zeroing out the temporary initial configuration - pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_0, 0); - pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_4, 0); + pci_write_config32(MCHDEV, DRB_ROW_0, 0); + pci_write_config32(MCHDEV, DRB_ROW_4, 0); for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { @@ -1127,7 +1131,7 @@ static void configure_e7501_ram_addresses(const struct mem_controller uint16_t top_of_low_memory = total_dram_128M_multiple << 11; - pci_write_config16(PCI_DEV(0, 0, 0), TOLM, + pci_write_config16(MCHDEV, TOLM, top_of_low_memory); } else { @@ -1140,7 +1144,7 @@ static void configure_e7501_ram_addresses(const struct mem_controller // Put TOLM at 3 GB - pci_write_config16(PCI_DEV(0, 0, 0), TOLM, 0xc000); + pci_write_config16(MCHDEV, TOLM, 0xc000); // Define a remap window to make the RAM that would appear from 3 GB - 4 GB // visible just beyond 4 GB or the end of physical memory, whichever is larger @@ -1154,9 +1158,9 @@ static void configure_e7501_ram_addresses(const struct mem_controller 0x40 + (total_dram_64M_multiple - 0x30) - 1; } - pci_write_config16(PCI_DEV(0, 0, 0), REMAPBASE, + pci_write_config16(MCHDEV, REMAPBASE, remap_base); - pci_write_config16(PCI_DEV(0, 0, 0), REMAPLIMIT, + pci_write_config16(MCHDEV, REMAPLIMIT, remap_limit); } } @@ -1170,31 +1174,31 @@ static void initialize_ecc(void) uint32_t dram_controller_mode; /* Test to see if ECC support is enabled */ - dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); + dram_controller_mode = pci_read_config32(MCHDEV, DRC); dram_controller_mode >>= 20; dram_controller_mode &= 3; if (dram_controller_mode == 2) { uint8_t byte; RAM_DEBUG_MESSAGE("Initializing ECC state...\n"); - pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x01); + pci_write_config8(MCHDEV, MCHCFGNS, 0x01); // Wait for scrub cycle to complete do { byte = - pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS); + pci_read_config8(MCHDEV, MCHCFGNS); } while ((byte & 0x08) == 0); - pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, (byte & 0xfc) | 0x04); + pci_write_config8(MCHDEV, MCHCFGNS, (byte & 0xfc) | 0x04); RAM_DEBUG_MESSAGE("ECC state initialized.\n"); /* Clear the ECC error bits */ - pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03); - pci_write_config8(PCI_DEV(0, 0, 1), DRAM_NERR, 0x03); + pci_write_config8(RASDEV, DRAM_FERR, 0x03); + pci_write_config8(RASDEV, DRAM_NERR, 0x03); // Clear DRAM Interface error bits (write-one-clear) - pci_write_config32(PCI_DEV(0, 0, 1), FERR_GLOBAL, 1 << 18); - pci_write_config32(PCI_DEV(0, 0, 1), NERR_GLOBAL, 1 << 18); + pci_write_config32(RASDEV, FERR_GLOBAL, 1 << 18); + pci_write_config32(RASDEV, NERR_GLOBAL, 1 << 18); } } @@ -1218,7 +1222,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, uint8_t slowest_ras_cas_delay = 0; uint8_t slowest_active_to_precharge_delay = 0; uint32_t current_cas_latency = - pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK; + pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK; // CAS# latency must be programmed beforehand ASSERT((current_cas_latency == DRT_CAS_2_0) @@ -1267,7 +1271,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, // At 133 MHz, 1 clock == 7.52 ns /* Read the initial state */ - dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT); + dram_timing = pci_read_config32(MCHDEV, DRT); /* Trp */ @@ -1326,7 +1330,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, if (current_cas_latency == DRT_CAS_2_0) dram_timing |= (1 << 28); // 4 clocks - pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing); + pci_write_config32(MCHDEV, DRT, dram_timing); return; @@ -1348,7 +1352,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, int i; int value; uint32_t dram_timing; - uint16_t maybe_dram_read_timing; + uint16_t dram_read_timing; uint32_t dword; // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format @@ -1430,20 +1434,20 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, * cas latency I can use. */ - dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT); + dram_timing = pci_read_config32(MCHDEV, DRT); dram_timing &= ~(DRT_CAS_MASK); - maybe_dram_read_timing = - pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL); - maybe_dram_read_timing &= 0xF000; + dram_read_timing = + pci_read_config16(MCHDEV, DRDCTL); + dram_read_timing &= 0xF000; if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) { dram_timing |= DRT_CAS_2_0; - maybe_dram_read_timing |= 0x0222; + dram_read_timing |= 0x0222; } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) { uint32_t dram_row_attributes = - pci_read_config32(PCI_DEV(0, 0, 0), DRA); + pci_read_config32(MCHDEV, DRA); dram_timing |= DRT_CAS_2_5; @@ -1456,32 +1460,32 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, && (dram_row_attributes & 0xff000000)) { // All slots populated - maybe_dram_read_timing |= 0x0882; + dram_read_timing |= 0x0882; } else { // Some unpopulated slots - maybe_dram_read_timing |= 0x0662; + dram_read_timing |= 0x0662; } } else die("No CAS# latencies compatible with all DIMMs!!\n"); - pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing); + pci_write_config32(MCHDEV, DRT, dram_timing); /* set master DLL reset */ - dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); + dword = pci_read_config32(MCHDEV, 0x88); dword |= (1 << 26); - pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); + pci_write_config32(MCHDEV, 0x88, dword); /* patch try register 88 is undocumented tnz */ dword &= 0x0ca17fff; dword |= 0xd14a5000; - pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); + pci_write_config32(MCHDEV, 0x88, dword); - pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL, - maybe_dram_read_timing); + pci_write_config16(MCHDEV, DRDCTL, + dram_read_timing); /* clear master DLL reset */ - dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); + dword = pci_read_config32(MCHDEV, 0x88); dword &= ~(1 << 26); - pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); + pci_write_config32(MCHDEV, 0x88, dword); return; @@ -1506,7 +1510,7 @@ static void configure_e7501_dram_controller_mode(const struct // Initial settings uint32_t controller_mode = - pci_read_config32(PCI_DEV(0, 0, 0), DRC); + pci_read_config32(MCHDEV, DRC); uint32_t system_refresh_mode = (controller_mode >> 8) & 7; // Code below assumes that most aggressive settings are in @@ -1592,7 +1596,7 @@ static void configure_e7501_dram_controller_mode(const struct controller_mode |= (system_refresh_mode << 8); // Configure the E7501 - pci_write_config32(PCI_DEV(0, 0, 0), DRC, controller_mode); + pci_write_config32(MCHDEV, DRC, controller_mode); } /** @@ -1645,7 +1649,7 @@ static void configure_e7501_row_attributes(const struct mem_controller } /* Write the new row attributes register */ - pci_write_config32(PCI_DEV(0, 0, 0), DRA, row_attributes); + pci_write_config32(MCHDEV, DRA, row_attributes); } /* @@ -1657,9 +1661,9 @@ static void configure_e7501_row_attributes(const struct mem_controller static void enable_e7501_clocks(uint8_t dimm_mask) { int i; - uint8_t clock_disable = pci_read_config8(PCI_DEV(0, 0, 0), CKDIS); + uint8_t clock_disable = pci_read_config8(MCHDEV, CKDIS); - pci_write_config8(PCI_DEV(0,0,0), 0x8e, 0xb0); + pci_write_config8(MCHDEV, 0x8e, 0xb0); for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { @@ -1671,7 +1675,7 @@ static void enable_e7501_clocks(uint8_t dimm_mask) clock_disable |= socket_mask; // DIMM absent, disable clock } - pci_write_config8(PCI_DEV(0, 0, 0), CKDIS, clock_disable); + pci_write_config8(MCHDEV, CKDIS, clock_disable); } /* DIMM-dedependent configuration functions */ @@ -1682,13 +1686,13 @@ static void enable_e7501_clocks(uint8_t dimm_mask) static void RAM_RESET_DDR_PTR(void) { uint8_t byte; - byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88); + byte = pci_read_config8(MCHDEV, 0x88); byte |= (1 << 4); - pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte); + pci_write_config8(MCHDEV, 0x88, byte); - byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88); + byte = pci_read_config8(MCHDEV, 0x88); byte &= ~(1 << 4); - pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte); + pci_write_config8(MCHDEV, 0x88, byte); } /** @@ -1723,11 +1727,11 @@ static void ram_set_d0f0_regs(void) ASSERT((bits_to_mask & bits_to_set) == 0); register_value = - pci_read_config32(PCI_DEV(0, 0, 0), register_offset); + pci_read_config32(MCHDEV, register_offset); register_value &= bits_to_mask; register_value |= bits_to_set; - pci_write_config32(PCI_DEV(0, 0, 0), register_offset, + pci_write_config32(MCHDEV, register_offset, register_value); } } @@ -1761,87 +1765,87 @@ static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr) static void ram_set_rcomp_regs(void) { uint32_t dword; - uint8_t maybe_strength_control, revision; + uint8_t strength_control, revision; RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n"); /*enable access to the rcomp bar */ - dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST); + dword = pci_read_config32(MCHDEV, MCHTST); dword |= (1 << 22); - pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword); + pci_write_config32(MCHDEV, MCHTST, dword); // Set the RCOMP MMIO base address - pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO); + pci_write_config32(MCHDEV, SMRBASE, RCOMP_MMIO); // Block RCOMP updates while we configure the registers - dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); + dword = read32(RCOMP_MMIO + SMRCTL); dword |= (1 << 9); - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); + write32(RCOMP_MMIO + SMRCTL, dword); /* Begin to write the RCOMP registers */ write8(RCOMP_MMIO + 0x2c, 0x0); // Set CMD and DQ/DQS strength to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88; - maybe_strength_control |= 0x40; - write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control); - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80); + strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0x88; + strength_control |= 0x40; + write8(RCOMP_MMIO + DQCMDSTR, strength_control); + write_8dwords(slew_2x, RCOMP_MMIO + 0x80); write16(RCOMP_MMIO + 0x42, 0); // Set CMD and DQ/DQS strength to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0xF8; - maybe_strength_control |= 0x04; - write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control); - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x60); + strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0xF8; + strength_control |= 0x04; + write8(RCOMP_MMIO + DQCMDSTR, strength_control); + write_8dwords(slew_2x, RCOMP_MMIO + 0x60); write16(RCOMP_MMIO + 0x40, 0); // Set RCVEnOut# strength to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8; - maybe_strength_control |= 0x04; - write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control); - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0); + strength_control = read8(RCOMP_MMIO + RCVENSTR) & 0xF8; + strength_control |= 0x04; + write8(RCOMP_MMIO + RCVENSTR, strength_control); + write_8dwords(slew_2x, RCOMP_MMIO + 0x1c0); write16(RCOMP_MMIO + 0x50, 0); // Set CS# strength for x4 SDRAM to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0x88; - maybe_strength_control |= 0x04; - write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control); - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140); + strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x88; + strength_control |= 0x04; + write8(RCOMP_MMIO + CSBSTR, strength_control); + write_8dwords(slew_2x, RCOMP_MMIO + 0x140); write16(RCOMP_MMIO + 0x48, 0); // Set CS# strength for x4 SDRAM to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0x8F; - maybe_strength_control |= 0x40; - write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control); - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x160); + strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x8F; + strength_control |= 0x40; + write8(RCOMP_MMIO + CSBSTR, strength_control); + write_8dwords(slew_2x, RCOMP_MMIO + 0x160); write16(RCOMP_MMIO + 0x4a, 0); // Set CKE strength for x4 SDRAM to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0x88; - maybe_strength_control |= 0x04; - write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control); - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0); + strength_control = read8(RCOMP_MMIO + CKESTR) & 0x88; + strength_control |= 0x04; + write8(RCOMP_MMIO + CKESTR, strength_control); + write_8dwords(slew_2x, RCOMP_MMIO + 0xa0); write16(RCOMP_MMIO + 0x44, 0); // Set CKE strength for x4 SDRAM to 2x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0x8F; - maybe_strength_control |= 0x40; - write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control); - write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xc0); + strength_control = read8(RCOMP_MMIO + CKESTR) & 0x8F; + strength_control |= 0x40; + write8(RCOMP_MMIO + CKESTR, strength_control); + write_8dwords(slew_2x, RCOMP_MMIO + 0xc0); write16(RCOMP_MMIO + 0x46, 0); // Set CK strength for x4 SDRAM to 1x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0x88; - maybe_strength_control |= 0x01; - write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control); - write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180); + strength_control = read8(RCOMP_MMIO + CKSTR) & 0x88; + strength_control |= 0x01; + write8(RCOMP_MMIO + CKSTR, strength_control); + write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x180); write16(RCOMP_MMIO + 0x4c, 0); // Set CK strength for x4 SDRAM to 1x (?) - maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0x8F; - maybe_strength_control |= 0x10; - write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control); - write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x1a0); + strength_control = read8(RCOMP_MMIO + CKSTR) & 0x8F; + strength_control |= 0x10; + write8(RCOMP_MMIO + CKSTR, strength_control); + write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x1a0); write16(RCOMP_MMIO + 0x4e, 0); @@ -1855,33 +1859,33 @@ static void ram_set_rcomp_regs(void) ram_handle_d060_1(); - dword = pci_read_config32(PCI_DEV(0,0,0), MAYBE_MCHTST); + dword = pci_read_config32(MCHDEV, MCHTST); dword &= 0x3fffffff; - pci_write_config32(PCI_DEV(0,0,0), MAYBE_MCHTST, dword); + pci_write_config32(MCHDEV, MCHTST, dword); - revision = pci_read_config8(PCI_DEV(0,0,0), 0x08); + revision = pci_read_config8(MCHDEV, 0x08); if (revision >= 3) { - dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); + dword = read32(RCOMP_MMIO + SMRCTL); dword &= ~0x100; - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); - dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); + write32(RCOMP_MMIO + SMRCTL, dword); + dword = read32(RCOMP_MMIO + SMRCTL); dword |= 0x500; - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); + write32(RCOMP_MMIO + SMRCTL, dword); } - dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); + dword = read32(RCOMP_MMIO + SMRCTL); dword &= ~0x203; dword |= 0x401; - write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); + write32(RCOMP_MMIO + SMRCTL, dword); /* Wait 40 usec */ SLOW_DOWN_IO; // Clear the RCOMP MMIO base address - pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, 0); + pci_write_config32(MCHDEV, SMRBASE, 0); /*disable access to the rcomp bar */ - dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST); + dword = pci_read_config32(MCHDEV, MCHTST); dword &= ~(1 << 22); - pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword); + pci_write_config32(MCHDEV, MCHTST, dword); } @@ -1901,7 +1905,7 @@ Public interface: static void sdram_enable(int controllers, const struct mem_controller *ctrl) { - uint8_t dimm_mask = pci_read_config16(PCI_DEV(0, 0, 0), SKPD); + uint8_t dimm_mask = pci_read_config16(MCHDEV, SKPD); uint32_t dram_controller_mode; if (dimm_mask == 0) @@ -1988,15 +1992,15 @@ static void sdram_enable(int controllers, configure_e7501_ram_addresses(ctrl, dimm_mask); /* Finally enable refresh */ - dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); + dram_controller_mode = pci_read_config32(MCHDEV, DRC); dram_controller_mode |= (1 << 29); - pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); + pci_write_config32(MCHDEV, DRC, dram_controller_mode); EXTRA_DELAY; initialize_ecc(); - dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); /* FCS_EN */ + dram_controller_mode = pci_read_config32(MCHDEV, DRC); /* FCS_EN */ dram_controller_mode |= (1 << 17); // NOTE: undocumented reserved bit - pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); + pci_write_config32(MCHDEV, DRC, dram_controller_mode); RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n"); DUMPNORTH(); @@ -2045,7 +2049,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) * configure_e7501_ram_addresses() without having to regenerate the bitmask * of usable DIMMs. */ - pci_write_config16(PCI_DEV(0, 0, 0), SKPD, dimm_mask); + pci_write_config16(MCHDEV, SKPD, dimm_mask); } /** [View Less]

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Patch set updated for coreboot: a3650b6 Add Southbridge support for S3.
by Zheng Bao 10 Apr '12

10 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/621 -gerrit commit a3650b6cd356973f8b89c955533137be5cfa4b47 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 5 13:18:49 2012 +0800 Add Southbridge support for S3. 1. Add some CIMX call for S3. 2. Detect sleep type. Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-… [View More]off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/Makefile.inc | 11 +++++ src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 3 + src/southbridge/amd/cimx/sb800/cfg.c | 61 +++++++++++++++++++++++---- src/southbridge/amd/cimx/sb800/early.c | 8 ++++ src/southbridge/amd/cimx/sb800/late.c | 19 ++++++++ src/southbridge/amd/cimx/sb800/lpc.c | 4 +- src/southbridge/amd/cimx/sb800/lpc.h | 1 - src/southbridge/amd/cimx/sb800/sb_cimx.h | 4 ++ 8 files changed, 100 insertions(+), 11 deletions(-) diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 65e4729..2cdca29 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -15,3 +15,14 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx +$(obj)/s3.rom: + echo " S3 NVRAM 0xffff0000 (S3 storage area)" + echo -ne '\xFF' > $@ + for ((i=0;i<20479;i++)) do echo -ne '\xFF' >> $@ ; done + +ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) +cbfs-files-y += s3nv +s3nv-file := $(obj)/s3.rom +s3nv-position := 0xffff0000 +s3nv-type := raw +endif diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 25aba95..7dc752a 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -162,4 +162,7 @@ typedef union _PCI_ADDR { #include "spi.h" #endif +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 + #endif // _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index a9e35bc..2b73155 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -17,10 +17,52 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#include <console/console.h> #include "SBPLATFORM.h" #include "cfg.h" +#include "OEM.h" +#include <cbmem.h> + +#include <arch/io.h> +#include <arch/acpi.h> + +#if CONFIG_HAVE_ACPI_RESUME == 1 +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(PM1_CNT_BLK_ADDRESS); + tmp = ((tmp & (7 << 10)) >> 10); + printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); + return (int)tmp; +} +#endif + +#ifndef __PRE_RAM__ +void set_cbmem_toc(struct cbmem_entry *toc) +{ + u32 dword = (u32) toc; + int nvram_pos = 0xf8, i; /* temp */ + printk(BIOS_DEBUG, "dword=%x\n", dword); + for (i = 0; i<4; i++) { + printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} +#endif +struct cbmem_entry *get_cbmem_toc(void) +{ + u32 xdata = 0; + int xnvram_pos = 0xf8, xi; + for (xi = 0; xi<4; xi++) { + outb(xnvram_pos, BIOSRAM_INDEX); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(BIOSRAM_DATA) << (xi *8); + xnvram_pos++; + } + return (struct cbmem_entry *) xdata; +} /** * @brief South Bridge CIMx configuration @@ -30,10 +72,13 @@ */ void sb800_cimx_config(AMDSBCFG *sb_config) { - if (!sb_config) { + if (!sb_config) return; - } - //memset(sb_config, 0, sizeof(AMDSBCFG)); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_get_sleep_type() == 3) + sb_config->S3Resume = 1; +#endif /* header */ sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; @@ -75,19 +120,19 @@ void sb800_cimx_config(AMDSBCFG *sb_config) /* USB */ sb_config->USBMODE.UsbModeReg = USB_CONFIG; - sb_config->SbUsbPll = 0; + sb_config->SbUsbPll = 0; /* SATA */ sb_config->SataClass = SATA_MODE; sb_config->SataIdeMode = SATA_IDE_MODE; sb_config->SataPortMultCap = SATA_PORT_MULT_CAP_RESERVED; - sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; + sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. //TODO: set to secondary not take effect. sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE; sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE; - /* Azalia HDA */ + /* Azalia HDA */ sb_config->AzaliaController = AZALIA_CONTROLLER; sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN; @@ -97,7 +142,6 @@ void sb800_cimx_config(AMDSBCFG *sb_config) #else sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL; #endif - /* LPC */ /* SuperIO hardware monitor register access */ sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM; @@ -132,4 +176,3 @@ void sb800_cimx_config(AMDSBCFG *sb_config) } #endif //!__PRE_RAM__ } - diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 9d49a52..f692897 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -23,9 +23,11 @@ #include <device/pci_ids.h> #include <arch/io.h> /* inl, outl */ #include <arch/romcc_io.h> /* device_t */ +#include <arch/acpi.h> #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ +#include "cbmem.h" #if CONFIG_RAMINIT_SYSINFO == 1 @@ -80,3 +82,9 @@ void sb800_clk_output_48Mhz(void) *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ } +#if CONFIG_HAVE_ACPI_RESUME == 1 +int acpi_is_wakeup_early(void) +{ + return (acpi_get_sleep_type() == 3); +} +#endif diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 8c7abdb..c69782b 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -24,6 +24,7 @@ #include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <console/console.h> /* printk */ +#include <arch/acpi.h> #include "lpc.h" /* lpc_read_resources */ #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ #include "cfg.h" /* sb800 Cimx configuration */ @@ -351,6 +352,17 @@ void sb_Late_Post(void) AmdSbDispatcher(sb_config); } +void sb_Before_Pci_Restore_Init(void) +{ + sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT; + AmdSbDispatcher(sb_config); +} + +void sb_After_Pci_Restore_Init(void) +{ + sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT; + AmdSbDispatcher(sb_config); +} /** * @brief SB Cimx entry point sbBeforePciInit wrapper @@ -468,7 +480,14 @@ static void sb800_enable(device_t dev) /* call the CIMX entry at the last sb800 device, * so make sure the mainboard devicetree is complete */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) + sb_Before_Pci_Init(); + else + sb_Before_Pci_Restore_Init(); +#else sb_Before_Pci_Init(); +#endif break; default: diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index bc643b5..472817d 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -20,7 +20,9 @@ #include <console/console.h> #include <device/pci.h> #include "lpc.h" - +#include <bitops.h> +#include <arch/io.h> +#include <cbmem.h> void lpc_read_resources(device_t dev) { diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index 7b165f8..3d6a17a 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -20,7 +20,6 @@ #ifndef _SB800_LPC_H_ #define _SB800_LPC_H_ - #define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ void lpc_read_resources(device_t dev); diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h index 42a7ba9..5e510de 100644 --- a/src/southbridge/amd/cimx/sb800/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h @@ -29,6 +29,10 @@ void sb_Before_Pci_Init(void); void sb_After_Pci_Init(void); void sb_Mid_Post_Init(void); void sb_Late_Post(void); +void sb_Before_Pci_Restore_Init(void); +void sb_After_Pci_Restore_Init(void); + +int acpi_is_wakeup_early(void); /** * CIMX not set the clock to 48Mhz until sbBeforePciInit, [View Less]

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Patch set updated for coreboot: 9d1ff9f S3 code in coreboot public folder.
by Zheng Bao 10 Apr '12

10 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/623 -gerrit commit 9d1ff9fa00287975317bd101020c343f254f7a26 Author: zbao <fishbaozi(a)gmail.com> Date: Tue Apr 10 16:56:04 2012 +0800 S3 code in coreboot public folder. 1. Move the Stack to high memory. 2. Restore the MTRR before Coreboot jump to the wakeup vector. Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a Signed-off-by: … [View More]Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/Kconfig | 4 + src/arch/x86/boot/tables.c | 1 + src/cpu/amd/agesa/Makefile.inc | 2 + src/cpu/amd/agesa/cache_as_ram.inc | 7 + src/cpu/amd/agesa/family14/Kconfig | 5 + src/cpu/amd/agesa/family14/model_14_init.c | 125 +++++---- src/cpu/amd/agesa/s3_resume.c | 326 ++++++++++++++++++++++ src/cpu/amd/agesa/s3_resume.h | 42 +++ src/include/cbmem.h | 10 +- src/lib/cbmem.c | 1 + src/northbridge/amd/agesa/Kconfig | 4 + src/northbridge/amd/agesa/family14/northbridge.c | 77 ++++-- 12 files changed, 529 insertions(+), 75 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index b0261d9..149568a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -222,6 +222,10 @@ config HAVE_INIT_TIMER default n if UDELAY_IO default y +config HIGH_SCRATCH_MEMORY_SIZE + hex + default 0x0 + config HAVE_MAINBOARD_RESOURCES bool default n diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index b7dc4fe..64dbc9d 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -237,6 +237,7 @@ struct lb_memory *write_tables(void) * the result right now. If it fails, ACPI resume will be disabled. */ cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); + cbmem_add(CBMEM_ID_SCRATCH_AGESA, CONFIG_HIGH_SCRATCH_MEMORY_SIZE); #endif #if CONFIG_MULTIBOOT diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index fb536dd..696173d 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -21,5 +21,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15 +romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c ramstage-y += apic_timer.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index f328db4..2124bf3 100755 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -86,6 +86,13 @@ disable_cache_as_ram: /* Save return stack */ movd %esp, %xmm0 + /* Disable cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + invd + AMD_DISABLE_STACK /* Restore the return stack */ diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 702270c..6713660 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -67,3 +67,8 @@ config HAVE_INIT_TIMER default y depends on CPU_AMD_AGESA_FAMILY14 +config HIGH_SCRATCH_MEMORY_SIZE + hex + # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) + default 0x71000 + depends on CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 577da1b..d90695a 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -32,6 +32,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam14.h> +#include <arch/acpi.h> +#include <cpu/amd/agesa/s3_resume.h> #define MCI_STATUS 0x401 @@ -57,69 +59,84 @@ void wrmsr_amd(u32 index, msr_t msr) static void model_14_init(device_t dev) { - printk(BIOS_DEBUG, "Model 14 Init.\n"); - - u8 i; - msr_t msr; - int msrno; + u32 i; + msr_t msr; #if CONFIG_LOGICAL_CPUS == 1 - u32 siblings; + u32 siblings; +#endif + printk(BIOS_DEBUG, "Model 14 Init.\n"); + + disable_cache (); + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14. + * TODO: + * amd_setup_mtrrs(); + */ + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + /* Set shadow WB, RdMEM, WrMEM */ + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.hi = msr.lo = 0x1e1e1e1e; + wrmsr(0x250, msr); + wrmsr(0x258, msr); + for (i = 0x268; i <= 0x26f; i++) + wrmsr(i, msr); + + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type == 3) + restore_mtrr(); #endif - disable_cache (); - /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - - // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs - msr.lo = msr.hi = 0; - wrmsr (0x259, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); - - /* disable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - enable_cache (); - - /* zero the machine check error status registers */ - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < 6; i++) { - wrmsr(MCI_STATUS + (i * 4), msr); - } - - /* Enable the local cpu apics */ - setup_lapic(); + x86_mtrr_check(); + x86_enable_cache(); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + /* Enable the local cpu apics */ + setup_lapic(); #if CONFIG_LOGICAL_CPUS == 1 - siblings = cpuid_ecx(0x80000008) & 0xff; - - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } #endif - /* DisableCf8ExtCfg */ - msr = rdmsr(NB_CFG_MSR); - msr.hi &= ~(1 << (46 - 32)); - wrmsr(NB_CFG_MSR, msr); + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); - /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); + printk(BIOS_SPEW, "%s done.\n", __func__); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c new file mode 100644 index 0000000..c844efa --- /dev/null +++ b/src/cpu/amd/agesa/s3_resume.c @@ -0,0 +1,326 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/x86/cache.h> +#if CONFIG_WRITE_HIGH_TABLES +#include <cbmem.h> +#endif +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <string.h> +#include "Porting.h" +#include "BiosCallOuts.h" +#include "s3_resume.h" +#include "agesawrapper.h" + +#ifndef __PRE_RAM__ +#include "spi.h" +#endif + +void restore_mtrr(void) +{ + u32 msr; + volatile UINT32 *msrPtr = (volatile UINT32 *)S3_DATA_MTRR_POS; + msr_t msr_data; + + printk(BIOS_SPEW, "%s\n", __func__); + + disable_cache(); + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Now restore the Fixed MTRRs */ + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x250, msr_data); + + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x258, msr_data); + + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x259, msr_data); + + for (msr = 0x268; msr <= 0x26F; msr++) { + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(msr, msr_data); + } + + /* Disable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Restore the Variable MTRRs */ + for (msr = 0x200; msr <= 0x20F; msr++) { + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(msr, msr_data); + } + + /* Restore SYSCFG MTRR */ + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(SYS_CFG, msr_data); +} + +inline void *backup_resume(void) +{ + unsigned long high_ram_base; + void *resume_backup_memory; + + /* Start address of high memory tables */ + high_ram_base = (u32) get_cbmem_toc(); + + /* + * printk(BIOS_DEBUG, "CBMEM TOC is at: %x\n", (u32_t)high_ram_base); + * printk(BIOS_DEBUG, "CBMEM TOC 0-size:%x\n ",(u32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); + */ + + cbmem_reinit((u64) high_ram_base); + + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (((u32) resume_backup_memory == 0) + || ((u32) resume_backup_memory == -1)) { + printk(BIOS_ERR, "Error: resume_backup_memory: %x\n", + (u32) resume_backup_memory); + for (;;) ; + } + + return resume_backup_memory; +} + +void move_stack_high_mem(void) +{ + void *high_stack; + + high_stack = cbmem_find(CBMEM_ID_SCRATCH_AGESA); + memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE)); + + __asm__ + volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" + (high_stack - BSP_STACK_BASE_ADDR) + :); +} + +void OemAgesaSaveMtrr(void) +{ +#ifndef __PRE_RAM__ + u32 spi_address; + msr_t msr_data; + device_t dev; + u32 nvram_pos = S3_DATA_MTRR_POS; + u32 i; + + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Fixed MTRRs */ + msr_data = rdmsr(0x250); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + msr_data = rdmsr(0x258); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + msr_data = rdmsr(0x259); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + for (i = 0x268; i < 0x270; i++) { + msr_data = rdmsr(i); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + } + + /* Disable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Variable MTRRs */ + for (i = 0x200; i < 0x210; i++) { + msr_data = rdmsr(i); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + } + + /* SYS_CFG */ + msr_data = rdmsr(0xC0010010); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + /* TOM */ + msr_data = rdmsr(0xC001001A); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + /* TOM2 */ + msr_data = rdmsr(0xC001001D); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + +#endif +} + +void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data) +{ + AMD_CONFIG_PARAMS StdHeader; + if (S3DataType == S3DataTypeNonVolatile) { + *Data = (void *)S3_DATA_NONVOLATILE_POS; + *DataSize = *(UINTN *) (*Data); + *Data += 4; + } else { + *DataSize = *(UINTN *) S3_DATA_VOLATILE_POS; + *Data = (void *) GetHeapBase(&StdHeader); + memcpy((void *)(*Data), (void *)(S3_DATA_VOLATILE_POS + 4), *DataSize); + } +} + +#ifndef __PRE_RAM__ +u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) +{ + + u32 pos = S3_DATA_VOLATILE_POS; + u32 spi_address, data; + u32 nvram_pos; + device_t dev; + + if (S3DataType == S3DataTypeNonVolatile) { + pos = S3_DATA_NONVOLATILE_POS; + } else { /* S3DataTypeVolatile */ + pos = S3_DATA_VOLATILE_POS; + } + + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + + /* printk(BIOS_DEBUG, "spi_address=%x\n", spi_address); */ + read_spi_id((u8 *) spi_address); + write_spi_status((u8 *)spi_address, 0); + if (S3DataType == S3DataTypeNonVolatile) { + sector_erase_spi((u8 *) spi_address, S3_DATA_NONVOLATILE_POS); + } else { + sector_erase_spi((u8 *) spi_address, S3_DATA_VOLATILE_POS); + sector_erase_spi((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x1000); + sector_erase_spi((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x2000); + sector_erase_spi((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x3000); + } + + nvram_pos = 0; + dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos, DataSize); + + for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { + data = *(u32 *) (Data + nvram_pos); + dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos + 4, + *(u32 *) (Data + nvram_pos)); + } + + return AGESA_SUCCESS; +} +#endif + +void set_resume_cache(void) +{ + msr_t msr; + + /* disable fixed mtrr for now, it will be enabled by mtrr restore */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); + wrmsr(SYSCFG_MSR, msr); + + /* Enable caching for 0 - coreboot ram using variable mtrr */ + msr.lo = 0 | MTRR_TYPE_WRBACK; + msr.hi = 0; + wrmsr(MTRRphysBase_MSR(0), msr); + msr.lo = ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid; + msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; + wrmsr(MTRRphysMask_MSR(0), msr); + + /* Set the default memory type and disable fixed and enable variable MTRRs */ + msr.hi = 0; + msr.lo = (1 << 11); + wrmsr(MTRRdefType_MSR, msr); + + enable_cache(); +} + +void s3_resume(void) +{ + int status; + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + status = agesawrapper_amds3laterestore(); + if (status) + printk(BIOS_DEBUG, "error level: %x \n", (u32) status); + else + printk(BIOS_DEBUG, "passed.\n"); +} diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h new file mode 100644 index 0000000..22a7271 --- /dev/null +++ b/src/cpu/amd/agesa/s3_resume.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef S3_RESUME_H +#define S3_RESUME_H + +#define S3_DATA_NONVOLATILE_POS 0xFFFF4000 +#define S3_DATA_VOLATILE_POS 0xFFFF0000 +#define S3_DATA_MTRR_POS 0xFFFF3100 + +typedef enum { + S3DataTypeNonVolatile=0, ///< NonVolatile Data Type + S3DataTypeVolatile ///< Volatile Data Type +} S3_DATA_TYPE; + +void restore_mtrr(void); +void s3_resume(void); +inline void *backup_resume(void); +void set_resume_cache(void); +void move_stack_high_mem(void); + +u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data); +void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data); +void OemAgesaSaveMtrr (void); + +#endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index c55a7ca..4ea6a5f 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -28,17 +28,18 @@ #endif #if CONFIG_HAVE_ACPI_RESUME -#define HIGH_MEMORY_SIZE ((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE) -#define HIGH_MEMORY_SAVE ( HIGH_MEMORY_SIZE - HIGH_MEMORY_DEF_SIZE ) +#define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) +#define HIGH_MEMORY_SIZE (HIGH_MEMORY_SAVE + CONFIG_HIGH_SCRATCH_MEMORY_SIZE + HIGH_MEMORY_DEF_SIZE) /* Delegation of resume backup memory so we don't have to * (slowly) handle backing up OS memory in romstage.c */ #define CBMEM_BOOT_MODE 0x610 #define CBMEM_RESUME_BACKUP 0x614 -#else + +#else /* CONFIG_HAVE_ACPI_RESUME */ #define HIGH_MEMORY_SIZE HIGH_MEMORY_DEF_SIZE -#endif +#endif /* CONFIG_HAVE_ACPI_RESUME */ #define CBMEM_ID_FREESPACE 0x46524545 #define CBMEM_ID_GDT 0x4c474454 @@ -47,6 +48,7 @@ #define CBMEM_ID_PIRQ 0x49525154 #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_RESUME 0x5245534d +#define CBMEM_ID_SCRATCH_AGESA 0x53435254 #define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_MRCDATA 0x4d524344 diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index b09b070..9d8230e 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -254,6 +254,7 @@ void cbmem_list(void) case CBMEM_ID_PIRQ: printk(BIOS_DEBUG, "IRQ TABLE "); break; case CBMEM_ID_MPTABLE: printk(BIOS_DEBUG, "SMP TABLE "); break; case CBMEM_ID_RESUME: printk(BIOS_DEBUG, "ACPI RESUME"); break; + case CBMEM_ID_SCRATCH_AGESA: printk(BIOS_DEBUG, "ACPISCRATCH"); break; case CBMEM_ID_SMBIOS: printk(BIOS_DEBUG, "SMBIOS "); break; case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break; case CBMEM_ID_CONSOLE: printk(BIOS_DEBUG, "CONSOLE "); break; diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 2ee921b..ebdda38 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -27,6 +27,10 @@ config CONSOLE_VGA_MULTI bool default n +config S3_VGA_ROM_RUN + bool + default n + source src/northbridge/amd/agesa/family10/Kconfig source src/northbridge/amd/agesa/family12/Kconfig source src/northbridge/amd/agesa/family14/Kconfig diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 15efe12..2647814 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -745,20 +745,46 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(device_t dev) { +extern u8 acpi_slp_type; + +static void domain_enable_resources(device_t dev) +{ u32 val; #if CONFIG_AMD_SB_CIMX + #if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + sb_After_Pci_Init(); + sb_Mid_Post_Init(); + } else { + sb_After_Pci_Restore_Init(); + } + #else sb_After_Pci_Init(); sb_Mid_Post_Init(); + #endif #endif /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n"); - val = agesawrapper_amdinitmid(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); + +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); } +#else + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); +#endif printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); } @@ -788,24 +814,41 @@ static void cpu_bus_set_resources(device_t dev) { pci_dev_set_resources(dev); } -static void cpu_bus_init(device_t dev) { - struct device_path cpu_path; +static u32 cpu_bus_scan(device_t dev, u32 max) +{ device_t cpu; - int apic_id; + struct device_path cpu_path; + int apic_id, cores_found; - initialize_cpus(dev->link_list); + /* There is only one node for fam14, but there may be multiple cores. */ + cpu = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (!cpu) + printk(BIOS_ERR, "ERROR: %02x:%02x.0 not found", 0, 0x18); - /* Build the AP cpu device path(s) */ - for (apic_id = 1; apic_id < CONFIG_MAX_CPUS; apic_id++) { + cores_found = (pci_read_config32(dev_find_slot(0,PCI_DEVFN(0x18,0x3)), 0xe8) >> 12) & 3; + printk(BIOS_DEBUG, " AP siblings=%d\n", cores_found); + + + for (apic_id = 0; apic_id <= cores_found; apic_id++) { cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = apic_id; - cpu = alloc_dev(dev->link_list, &cpu_path); - if (!cpu) - return; - cpu->enabled = 1; - cpu->path.apic.node_id = 0; - cpu->path.apic.core_id = apic_id; + cpu = alloc_find_dev(dev->link_list, &cpu_path); + if (cpu) { + cpu->enabled = 1; + cpu->path.apic.node_id = 0; + cpu->path.apic.core_id = apic_id; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } else { + cpu->enabled = 0; + } } + return max; +} + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); } /* North Bridge Structures */ @@ -844,7 +887,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = cpu_bus_set_resources, .enable_resources = NULL, .init = cpu_bus_init, - .scan_bus = NULL, + .scan_bus = cpu_bus_scan, }; static void root_complex_enable_dev(struct device *dev) { [View Less]

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Patch set updated for coreboot: f820756 S3 code in the mainboard.
by Zheng Bao 10 Apr '12

10 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/624 -gerrit commit f8207561e5f09b974fbb9afd55ae722771c420cc Author: zbao <fishbaozi(a)gmail.com> Date: Tue Apr 10 16:56:36 2012 +0800 S3 code in the mainboard. Persimmon is the demo board. Tested by Linux and Windows 7. Change-Id: I5ded942b51e63ebeb08ace0b202b4ed239b0c14c Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-… [View More]by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/persimmon/BiosCallOuts.c | 40 +++--- src/mainboard/amd/persimmon/BiosCallOuts.h | 4 +- src/mainboard/amd/persimmon/Kconfig | 1 + src/mainboard/amd/persimmon/PlatformGnbPcie.c | 2 +- .../amd/persimmon/PlatformGnbPcieComplex.h | 1 + src/mainboard/amd/persimmon/agesawrapper.c | 160 +++++++++++++++++++- src/mainboard/amd/persimmon/agesawrapper.h | 5 + src/mainboard/amd/persimmon/buildOpts.c | 6 +- src/mainboard/amd/persimmon/get_bus_conf.c | 21 ++- src/mainboard/amd/persimmon/mainboard.c | 16 ++- src/mainboard/amd/persimmon/romstage.c | 90 +++++++++-- 11 files changed, 296 insertions(+), 50 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 7323832..52eb9dd 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -119,8 +119,10 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams->BufferPointer = NULL; AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + printk(BIOS_SPEW, "%s BiosHeapBaseAddr: %x\n", __func__, (u32) BiosHeapBaseAddr); if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { /* First allocation */ @@ -229,26 +231,26 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_BUFFER_NODE *PrevNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *NextNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + /* Find target node to deallocate in list of allocated nodes. - Return AGESA_BOUNDS_CHK if the BufferHandle is not found + Return AGESA_BOUNDS_CHK if the BufferHandle is not found */ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); @@ -355,8 +357,8 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index d9e4497..071c73c 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -23,8 +23,8 @@ #include "Porting.h" #include "AGESA.h" -#define BIOS_HEAP_START_ADDRESS 0x00010000 -#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ +#define BIOS_HEAP_SIZE 0x20000 +#define BSP_STACK_BASE_ADDR 0x30000 typedef struct _BIOS_HEAP_MANAGER { //UINT32 AvailableSize; diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 9212e20..27e27a5 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES + select HAVE_ACPI_RESUME select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index 5e37f51..bdfcb66 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -23,6 +23,7 @@ #include "heapManager.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include "BiosCallOuts.h" #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -165,4 +166,3 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; } - diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index b50cb1a..a49be62 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -23,6 +23,7 @@ #include "Porting.h" #include "AGESA.h" #include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 6e9997f..16d90a3 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -33,10 +33,13 @@ #include "cpuLateInit.h" #include "Dispatcher.h" #include "cpuCacheInit.h" +#include "heapManager.h" #include "amdlib.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" #include <arch/io.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cbmem.h> #define FILECODE UNASSIGNED_FILE_FILECODE @@ -209,7 +212,7 @@ agesawrapper_amdinitreset ( if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); return (UINT32)status; - } +} UINT32 agesawrapper_amdinitearly ( @@ -243,6 +246,17 @@ agesawrapper_amdinitearly ( return (UINT32)status; } +UINT32 GetHeapBase( + AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 high_heap; + + high_heap = (UINT32)cbmem_find(CBMEM_ID_SCRATCH_AGESA) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* base + high_stack_size */ + + return high_heap; +} + UINT32 agesawrapper_amdinitpost ( VOID @@ -272,7 +286,7 @@ agesawrapper_amdinitpost ( AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ - BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader); HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { @@ -496,6 +510,148 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } +#if CONFIG_HAVE_ACPI_RESUME == 1 +UINT32 +agesawrapper_amdinitresume ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amds3laterestore ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdS3LateParams, + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + + AmdCreateStruct (&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +#ifndef __PRE_RAM__ +UINT32 +agesawrapper_amdS3Save ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdInterfaceParams, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save (AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + S3DataType = S3DataTypeNonVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage + ); + } + + OemAgesaSaveMtrr(); + AmdReleaseStruct (&AmdInterfaceParams); + + return (UINT32)Status; +} +#endif /* #ifndef __PRE_RAM__ */ +#endif /* CONFIG_HAVE_ACPI_RESUME */ + UINT32 agesawrapper_amdlaterunaptask ( UINT32 Func, diff --git a/src/mainboard/amd/persimmon/agesawrapper.h b/src/mainboard/amd/persimmon/agesawrapper.h index 7bed570..7babd58 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.h +++ b/src/mainboard/amd/persimmon/agesawrapper.h @@ -84,7 +84,12 @@ UINT32 agesawrapper_amdreadeventlog (void); UINT32 agesawrapper_amdinitcpuio (void); UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdinitresume (void); +UINT32 agesawrapper_amdS3Save (void); +UINT32 agesawrapper_amds3laterestore (void); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); void *agesawrapper_getlateinitptr (int pick); +UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); + #endif diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 3e5b14e..389e1d4 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -120,8 +120,8 @@ #define AGESA_ENTRY_INIT_LATE TRUE #define AGESA_ENTRY_INIT_S3SAVE TRUE #define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -169,7 +169,7 @@ //#define BLDCFG_USE_HT_ASSIST TRUE //#define BLDCFG_USE_ATM_MODE TRUE //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE +#define BLDCFG_S3_LATE_RESTORE TRUE //#define BLDCFG_USE_32_BYTE_REFRESH FALSE //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE //#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 0142762..4c094ae 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -51,6 +51,9 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +#endif void get_bus_conf(void) { @@ -80,11 +83,20 @@ void get_bus_conf(void) * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + status = agesawrapper_amdS3Save(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } +#else status = agesawrapper_amdinitlate(); - if(status) { + if(status) printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - +#endif sbdn_sb800 = 0; for (i = 0; i < 3; i++) { @@ -124,7 +136,8 @@ void get_bus_conf(void) for (j = bus_sb800[2]; j < bus_isa; j++) bus_type[j] = 1; - /* I/O APICs: APIC ID Version State Address */ + + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 3b181a1..9a8428e 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -23,10 +23,13 @@ #include <arch/io.h> #include <boot/tables.h> #include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -//#include <southbridge/amd/sb800/sb800.h> +#include <southbridge/amd/sb800/sb800.h> +#include <arch/acpi.h> #include "chip.h" +#include "BiosCallOuts.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/amd/mtrr.h> void set_pcie_reset(void); void set_pcie_dereset(void); @@ -56,6 +59,14 @@ static void persimmon_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); +/* + * The mainboard is the first place that we get control in ramstage. Check + * for S3 resume and call the approriate AGESA/CIMx resume functions. + */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + acpi_slp_type = acpi_get_sleep_type(); +#endif + #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; uint32_t sys_mem; @@ -110,6 +121,7 @@ int add_mainboard_resources(struct lb_memory *mem) #endif return 0; } + struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = persimmon_enable, diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index dfb1aca..f1d1b2a 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -35,9 +35,14 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "pc80/i8254.c" #include "pc80/i8259.c" +#include <cpu/x86/cache.h> #include "sb_cimx.h" #include "SBPLATFORM.h" +#include "cbmem.h" +#include "cpu/amd/mtrr.h" +#include "cpu/amd/agesa/s3_resume.h" +void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) @@ -46,6 +51,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; +#if CONFIG_HAVE_ACPI_RESUME == 1 + void *resume_backup_memory; +#endif + /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) @@ -98,28 +107,75 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - post_code(0x40); - printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); - val = agesawrapper_amdinitpost (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); - - post_code(0x41); - printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); - val = agesawrapper_amdinitenv (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ +#endif + post_code(0x40); + printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); + val = agesawrapper_amdinitpost (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x42); + printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); + val = agesawrapper_amdinitenv (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); + val = agesawrapper_amdinitresume(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + val = agesawrapper_amds3laterestore (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x61); + printk(BIOS_DEBUG, "Find resume memory location\n"); + resume_backup_memory = backup_resume(); + + post_code(0x62); + printk(BIOS_DEBUG, "Move CAR stack.\n"); + move_stack_high_mem(); + printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); + + post_code(0x63); + disable_cache_as_ram(); + printk(BIOS_DEBUG, "CAR disabled.\n"); + set_resume_cache(); + + /* + * Copy the system memory that is in the ramstage area to the + * reserved area. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); + + printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + } +#endif /* Initialize i8259 pic */ - post_code(0x41); + post_code(0x43); setup_i8259 (); /* Initialize i8254 timers */ - post_code(0x42); + post_code(0x44); setup_i8254 (); post_code(0x50); [View Less]

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Patch set updated for coreboot: f8300b4 S3 code in vendorcode folder.
by Zheng Bao 10 Apr '12

10 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/622 -gerrit commit f8300b4e154e265ae2e281b61761428f487774b3 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 5 13:20:50 2012 +0800 S3 code in vendorcode folder. Change the ExecuteFinalHltInstruction to assembly code. so we can make sure the code can run stackless. Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d Signed-off-by: … [View More]Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/family14/Makefile.inc | 1 + src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h | 10 +- src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c | 141 +------------- src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S | 203 ++++++++++++++++++++ .../amd/agesa/f14/Proc/Common/AmdS3Save.c | 2 +- .../amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c | 10 +- src/vendorcode/amd/agesa/f14/gcccar.inc | 192 ++++++++++--------- 7 files changed, 325 insertions(+), 234 deletions(-) diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 774d401..b08ceeb 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -113,6 +113,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtMidPost.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnPciTables.c diff --git a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h index 58438b9..5ce3ee3 100644 --- a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h @@ -305,7 +305,9 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr0, %[value]" - : [value] "=a" (value)); + : [value] "=a" (value) + : + : "memory"); return value; } @@ -379,6 +381,7 @@ static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long D "mov %%eax, %%cr0" : : "a" (Data) + : "memory" ); } @@ -508,13 +511,16 @@ static __inline__ __attribute__((always_inline)) void __debugbreak(void) __asm__ __volatile__ ("int3"); } +static __inline__ __attribute__((always_inline)) void __invd(void) +{ + __asm__ __volatile__ ("invd"); +} static __inline__ __attribute__((always_inline)) void __wbinvd(void) { __asm__ __volatile__ ("wbinvd"); } - static __inline__ __attribute__((always_inline)) void __lidt(void *Source) { __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source)); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c index ae9f3c7..938300a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c @@ -106,149 +106,16 @@ ExecuteWbinvdInstruction ( */ -//---------------------------------------------------------------------------- - -STATIC -VOID -PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) - { - UINT64 data; - UINT32 msrno; - // Configure the MTRRs on the AP so - // when it runs remote code it will execute - // out of RAM instead of ROM. - // Disable MTRRs and turn on modification enable bit - - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data &= ~(1 << 18); // MtrrFixDramEn - data &= ~(1 << 20); // MtrrVarDramEn - data |= (1 << 19); // MtrrFixDramModEn - data |= (1 << 17); // SysUcLockEn - - - __writemsr (0xC0010010, data); - - // Set 7FFFh-00000h and 9FFFFh-80000h as WB DRAM - __writemsr (0x250, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX64k_00000 - __writemsr (0x258, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX16k_80000 - - // Set BFFFFh-A0000h, DFFFFh-C0000h as Uncacheable Memory-mapped IO - __writemsr (0x259, 0); // AMD_AP_MTRR_FIX16k_A0000 - __writemsr (0x268, 0); // AMD_MTRR_FIX4k_C0000 - __writemsr (0x269, 0); // AMD_MTRR_FIX4k_C8000 - __writemsr (0x26A, 0); // AMD_MTRR_FIX4k_D0000 - __writemsr (0x26B, 0); // AMD_MTRR_FIX4k_D8000 - - // Set FFFFFh-E0000h as Uncacheable Memory - for (msrno = 0x26C; msrno <= 0x26F; msrno++) - __writemsr (msrno, 0x1818181818181818); - - // If IBV provided settings for Fixed-Sized MTRRs, - // overwrite the default settings. - if ((uintptr_t) ApMtrrSettingsList != 0 && (uintptr_t) ApMtrrSettingsList != 0xFFFFFFFF) - { - int index; - for (index = 0; ApMtrrSettingsList [index].MsrAddr != CPU_LIST_TERMINAL; index++) - __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); - } - - // restore variable MTTR6 and MTTR7 to default states - for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared - __writemsr (msrno, 0); - - // Enable fixed-range and variable-range MTRRs - // Set Fixed-Range Enable (FE) and MTRR Enable (E) bits - __writemsr (0x2FF, __readmsr (0x2FF) | 0xC00); - - // Enable Top-of-Memory setting - // Enable use of RdMem/WrMem bits attributes - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data |= (1 << 18); // MtrrFixDramEn - data |= (1 << 20); // MtrrVarDramEn - data &= ~(1 << 19); // MtrrFixDramModEn - __writemsr (0xC0010010, data); - } - -//---------------------------------------------------------------------------- - +/* see cahaltasm.S VOID ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, + IN UINT32 HaltFlags, IN AP_MTRR_SETTINGS *ApMtrrSettingsList, IN AMD_CONFIG_PARAMS *StdHeader ) { - int abcdRegs [4]; - UINT32 cr0val; - UINT64 data; - - cr0val = __readcr0 (); - if (SharedCore & 2) - { - // set CombineCr0Cd and enable cache in CR0 - __writemsr (MSR_CU_CFG3, __readmsr (MSR_CU_CFG3) | 1ULL << 49); - __writecr0 (cr0val & ~0x60000000); - } - else - __writecr0 (cr0val | 0x60000000); - - if (SharedCore & 1) PrimaryCoreFunctions (ApMtrrSettingsList); - - // Make sure not to touch any Shared MSR from this point on - - // Restore settings that were temporarily overridden for the cache as ram phase - data = __readmsr (0xC0011022); // MSR_DC_CFG - data &= ~(1 << 4); // DC_DIS_SPEC_TLB_RLD - data &= ~(1 << 8); // DIS_CLR_WBTOL2_SMC_HIT - data &= ~(1 << 13); // DIS_HW_PF - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); // MSR_IC_CFG - C001_1021 - data &= ~(1 << 9); // IC_DIS_SPEC_TLB_RLD - __writemsr (0xC0011021, data); - - // AMD_DISABLE_STACK_FAMILY_HOOK - __cpuid (abcdRegs, 1); - if ((abcdRegs [0] >> 20) == 1) //-----family 10h (Hydra) only----- - { - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1 << 8); - data &= ~(1 << 13); - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 14); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC001102A); - data &= ~(1 << 15); - data &= ~(1ull << 35); - __writemsr (0xC001102A, data); - } - else if ((abcdRegs [0] >> 20) == 6) //-----family 15h (Orochi) only----- - { - data = __readmsr (0xC0011020); - data &= ~(1 << 28); - __writemsr (0xC0011020, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1l << 13); - __writemsr (0xC0011022, data); - } - - for (;;) - { - _disable (); - __halt (); - } - } +} +*/ //---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S new file mode 100644 index 0000000..48ee5d0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +.include "src/vendorcode/amd/agesa/f14/gcccar.inc" + +.code32 +.align 4 +.globl ExecuteFinalHltInstruction + .type ExecuteFinalHltInstruction, @function +/* ExecuteFinalHltInstruction ( + IN UINT32 HaltFlags, + IN AP_MTRR_SETTINGS *ApMtrrSettingsList, + IN AMD_CONFIG_PARAMS *StdHeader + ) +*/ + +/* This function disables CAR. We don't care about the stack on this CPU */ +ExecuteFinalHltInstruction: + movl 4(%esp), %esi /* HaltFlags*/ + movl 8(%esp), %edi /* ApMtrrSettingList */ + +/* Do these special steps in case if the core is part of a compute unit + * Note: The following bits are family specific flags, that gets set during build time, + * and indicates things like "family cache control methodology", etc. + * esi bit0 = 0 -> not a Primary core + * esi bit0 = 1 -> Primary core + * esi bit1 = 0 -> Cache disable + * esi bit1 = 1 -> Cache enable + */ + + bt $1, %esi /* .if (esi & 2h) */ + jz 0f + /* Set CombineCr0Cd bit */ + movl $CU_CFG3, %ecx + rdmsr + bts $(COMBINE_CR0_CD - 32), %edx + wrmsr + /* Clear the CR0.CD bit */ + movl %cr0, %eax /* Make sure cache is enabled for all APs */ + btr $CR0_CD, %eax + btr $CR0_NW, %eax + mov %eax, %cr0 /* Write back to CR0 */ + jmp 1f /* .else */ +0: + movl %cr0, %eax /* Make sure cache is disabled for all APs */ + bts $CR0_CD, %eax /* Disable cache */ + bts $CR0_NW, %eax + movl %eax, %cr0 /* Write back to CR0 */ +1: /* .endif */ + + bt $0, %esi /* .if (esi & 1h) */ + jz 2f + /* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */ + movl %edi, %esi /* Get ApMtrrSettingList */ + + /* Configure the MTRRs on the AP so + * when it runs remote code it will execute + * out of RAM instead of ROM. + */ + + /* Disable MTRRs and turn on modification enable bit */ + movl $MTRR_SYS_CFG, %ecx + rdmsr + btr $MTRR_VAR_DRAM_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_MOD_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_EN, %eax /* Disable */ + bts $SYS_UC_LOCK_EN, %eax + wrmsr + + /* Setup default values for Fixed-Sized MTRRs */ + /* Set 7FFFh-00000h as WB */ + movl $AMD_AP_MTRR_FIX64k_00000, %ecx + movl $0x1E1E1E1E, %eax + movl %eax, %edx + wrmsr + + /* Set 9FFFFh-80000h also as WB */ + movl $AMD_AP_MTRR_FIX16k_80000, %ecx + wrmsr + + /* Set BFFFFh-A0000h as Uncacheable Memory-mapped IO */ + movl $AMD_AP_MTRR_FIX16k_A0000, %ecx + xorl %eax, %eax + xorl %edx, %edx + wrmsr + + /* Set DFFFFh-C0000h as Uncacheable Memory-mapped IO */ + xorl %eax, %eax + xorl %edx, %edx + movl $AMD_AP_MTRR_FIX4k_C0000, %ecx + +CDLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_D8000, %ecx + jbe CDLoop + + /* Set FFFFFh-E0000h as Uncacheable Memory */ + movl $0x18181818, %eax + movl %eax, %edx + + mov $AMD_AP_MTRR_FIX4k_E0000, %ecx + +EFLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_F8000, %ecx + jbe EFLoop + + /* If IBV provided settings for Fixed-Sized MTRRs, + * overwrite the default settings. */ + cmp $0, %esi /*.if ((esi != 0) && (esi != 0FFFFFFFFh)) */ + jz 4f + cmp $0xFFFFFFFF, %esi + jz 4f + 5: + mov (%esi), %ecx /* (AP_MTRR_SETTINGS ptr [esi]).MsrAddr */ + /* While we are not at the end of the list */ + cmp $CPU_LIST_TERMINAL, %ecx /* .while (ecx != CPU_LIST_TERMINAL)*/ + je 4f + /* TODO - coreboot isn't checking for valid data. + * Ensure that the MSR address is valid for Fixed-Sized MTRRs */ + /*.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \ + (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || \ + (ecx == AMD_AP_MTRR_FIX16k_A0000)) + */ + mov 4(%esi), %eax /* MsrData */ + mov 8(%esi), %edx /* MsrData */ + wrmsr + /* .endif */ + add $12, %esi /* sizeof (AP_MTRR_SETTINGS) */ + jmp 5b /* .endw */ + 4: /* .endif */ + + /* restore variable MTTR6 and MTTR7 to default states */ + movl $AMD_MTRR_VARIABLE_BASE6, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ + xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */ + xor %edx, %edx + cmp $10, %ecx /* .while (cl < 010h) */ + jge 6f + wrmsr + inc %ecx + 6: /* .endw */ + + /* Enable fixed-range and variable-range MTRRs */ + mov $AMD_MTRR_DEFTYPE, %ecx + rdmsr + bts $MTRR_DEF_TYPE_EN, %eax /* MtrrDefTypeEn */ + bts $MTRR_DEF_TYPE_FIX_EN, %eax /* MtrrDefTypeFixEn */ + wrmsr + + /* Enable Top-of-Memory setting */ + /* Enable use of RdMem/WrMem bits attributes */ + mov $MTRR_SYS_CFG, %ecx + rdmsr + bts $MTRR_VAR_DRAM_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_MOD_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_EN, %eax /* Enable */ + wrmsr + + bts $FLAG_IS_PRIMARY, %esi + jmp 3f /* .else ; end if primary core */ + 2: + xor %esi, %esi + 3: /* .endif*/ + + /* Make sure not to touch any Shared MSR from this point on */ + + AMD_DISABLE_STACK_FAMILY_HOOK + + xor %eax, %eax + +7: + cli + hlt + jmp 7b /* ExecuteHltInstruction */ + + .size ExecuteFinalHltInstruction, .-ExecuteFinalHltInstruction diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c index f994c87..448d0f9 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c @@ -245,7 +245,7 @@ AmdS3Save ( HeapStatus = AmdS3SaveParams->StdHeader.HeapStatus; AmdS3SaveParams->StdHeader.HeapStatus = HEAP_S3_RESUME; - AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT64) HeapPtr; + AmdS3SaveParams->StdHeader.HeapBasePtr = (VOID *) HeapPtr; for (i = 0; i < S3LATE_TABLE_SIZE; i++) { if (HeapPtrs[i] != NULL) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c index df2071f..eee9804 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c @@ -259,30 +259,30 @@ MemFS3GetDeviceList ( (*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize; // Copy device list on the stack to the heap. - BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr; + BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) (UINT32) AllocHeapParams.BufferPtr; for (Die = 0; Die < DieCount; Die ++) { for (i = PRESELFREF; i <= POSTSELFREF; i ++) { // Copy PCI device descriptor to the heap if it exists. if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR); } // Copy conditional PCI device descriptor to the heap if it exists. if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); } // Copy MSR device descriptor to the heap if it exists. if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR); } // Copy conditional MSR device descriptor to the heap if it exists. if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); } diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 8743919..d81b6af 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -37,99 +37,113 @@ .altmacro -BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ -BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ -CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ -CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ -CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ -CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ - -APIC_BASE_ADDRESS = 0x0000001B - APIC_BSC = 8 /* Boot Strap Core */ - -AMD_MTRR_VARIABLE_BASE0 = 0x0200 -AMD_MTRR_VARIABLE_BASE6 = 0x020C -AMD_MTRR_FIX64k_00000 = 0x0250 -AMD_MTRR_FIX16k_80000 = 0x0258 -AMD_MTRR_FIX16k_A0000 = 0x0259 -AMD_MTRR_FIX4k_C0000 = 0x0268 -AMD_MTRR_FIX4k_C8000 = 0x0269 -AMD_MTRR_FIX4k_D0000 = 0x026A -AMD_MTRR_FIX4k_D8000 = 0x026B -AMD_MTRR_FIX4k_E0000 = 0x026C -AMD_MTRR_FIX4k_E8000 = 0x026D -AMD_MTRR_FIX4k_F0000 = 0x026E -AMD_MTRR_FIX4k_F8000 = 0x026F - -AMD_MTRR_DEFTYPE = 0x02FF - WB_DRAM_TYPE = 0x1E /* MemType - memory type */ - MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ - MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ - -HWCR = 0x0C0010015 /* Hardware Configuration */ - INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ - -IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ - /* uses 16h - 19h */ -TOP_MEM = 0x0C001001A /* Top of Memory */ -TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ - -LS_CFG = 0x0C0011020 /* Load-Store Configuration */ - DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ - DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ - -IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ - IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ - DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ - DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ - -DC_CFG = 0x0C0011022 /* Data Cache Configuration */ - DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ - DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ - DIS_HW_PF = 13 /* Hardware prefetches bit */ - -DE_CFG = 0x0C0011029 /* Decode Configuration */ - CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ - -BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ -CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ - F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ - IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ - -CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ - COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ - - +BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ +BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ +CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ +CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ +CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ +CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ + +APIC_BASE_ADDRESS = 0x0000001B + APIC_BSC = 8 /* Boot Strap Core */ + +AMD_MTRR_VARIABLE_BASE0 = 0x0200 +AMD_MTRR_VARIABLE_BASE6 = 0x020C +AMD_MTRR_FIX64k_00000 = 0x0250 +AMD_MTRR_FIX16k_80000 = 0x0258 +AMD_MTRR_FIX16k_A0000 = 0x0259 +AMD_MTRR_FIX4k_C0000 = 0x0268 +AMD_MTRR_FIX4k_C8000 = 0x0269 +AMD_MTRR_FIX4k_D0000 = 0x026A +AMD_MTRR_FIX4k_D8000 = 0x026B +AMD_MTRR_FIX4k_E0000 = 0x026C +AMD_MTRR_FIX4k_E8000 = 0x026D +AMD_MTRR_FIX4k_F0000 = 0x026E +AMD_MTRR_FIX4k_F8000 = 0x026F + +/* Reproduced from AGESA.h */ +AMD_AP_MTRR_FIX64k_00000 = 0x00000250 +AMD_AP_MTRR_FIX16k_80000 = 0x00000258 +AMD_AP_MTRR_FIX16k_A0000 = 0x00000259 +AMD_AP_MTRR_FIX4k_C0000 = 0x00000268 +AMD_AP_MTRR_FIX4k_C8000 = 0x00000269 +AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A +AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B +AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C +AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D +AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E +AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F +CPU_LIST_TERMINAL = 0xFFFFFFFF + +AMD_MTRR_DEFTYPE = 0x02FF + WB_DRAM_TYPE = 0x1E /* MemType - memory type */ + MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ + MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ + +HWCR = 0x0C0010015 /* Hardware Configuration */ + INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ + +IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ + /* uses 16h - 19h */ +TOP_MEM = 0x0C001001A /* Top of Memory */ +TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ + +LS_CFG = 0x0C0011020 /* Load-Store Configuration */ + DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ + DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ + +IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ + IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ + DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ + DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ + +DC_CFG = 0x0C0011022 /* Data Cache Configuration */ + DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ + DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ + DIS_HW_PF = 13 /* Hardware prefetches bit */ + +DE_CFG = 0x0C0011029 /* Decode Configuration */ + CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ + +BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ +CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ + F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ + IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ + +CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ + COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ + + CR0_PE = 1 # Protection Enable CR0_NW = 29 # Not Write-through CR0_CD = 30 # Cache Disable CR0_PG = 31 # Paging Enable - -/* CPUID Functions */ - -CPUID_MODEL = 1 -AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ - -NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ - INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ - -MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ - CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ - SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ - MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ - MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ - MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ - MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ - -PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ - PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ - PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ - CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ - CONFIG_EVENT_H = 4 /* Increment count by number of event */ - /* occured in clock cycle */ - EVENT_ENABLE = 22 /* Enable the event */ -PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ + +/* CPUID Functions */ + +CPUID_MODEL = 1 +AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ +AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ + +NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ + INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ + +MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ + CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ + SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ + MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ + MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ + MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ + MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ + +PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ + PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ + PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ + CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ + CONFIG_EVENT_H = 4 /* Increment count by number of event */ + /* occured in clock cycle */ + EVENT_ENABLE = 22 /* Enable the event */ +PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ # Local use flags, in upper most byte if ESI FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized [View Less]

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Patch set updated for coreboot: f10e257 Add multicore support to coreboot
by Ronald G. Minnich 09 Apr '12

09 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/877 -gerrit commit f10e25754cc2650417500d629aa788a6e3384707 Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 23:51:18 2012 -0700 Add multicore support to coreboot This set of changes supports the ability for multicore support in coreboot. To give people a chance to examine the structure, and to make bisecting for bugs easier,… [View More] we are implementing the patch in 3 stages. This first stage introduces the basic mechanism but does not make any visible change in behavior. The APs, instead of being immediately spun down, are asked to run one debug print function and then spun down. The means by which APs are tasked was implemented in the NIX operating system in 2011, see: http://code.google.com/p/nix-os/ The APs come alive and spin on a memory location, contained in a per-AP structure. Tasking is accomplished by setting parameters into an argument array and then writing a function pointer into the memory location. The AP indicates completion by writing zero to the memory location. The BSP can wait for the AP to finish (synchronous) or going off to do other work (asynchronous). Wait times are in units of microseconds. This way of tasking APs is incredibly cheap and fast: in the minimal case, one memory write suffices to launch an AP into doing work. This code has been tested on a sandybridge system (chromebook) and on another 4-core sandybridge system. Take the opportunity to remove the macro definition whose origins few people remember. Change-Id: I19f8587562fd499e98457aa9f11b52400c105697 Signed-off-by: Ron Minnich <rminnich(a)gmail.com> --- src/arch/x86/include/arch/cpu.h | 5 + src/arch/x86/lib/cpu.c | 28 ++++++- src/cpu/x86/lapic/lapic_cpu_init.c | 147 ++++++++++++++++++++++++++++++++---- src/cpu/x86/lapic/secondary.S | 2 + src/include/cpu/cpu.h | 8 ++- 5 files changed, 169 insertions(+), 21 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 604abde..34d0856 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -157,9 +157,14 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); +typedef u32 (*workfunc)(u32, u32, u32); + struct cpu_info { device_t cpu; unsigned long index; + workfunc work; + u32 params[3]; + u32 result; }; static inline struct cpu_info *cpu_info(void) diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 98ede06..29ccccc 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -234,7 +234,7 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } -void cpu_initialize(void) +void cpu_initialize(struct cpu_info *info) { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -242,12 +242,9 @@ void cpu_initialize(void) * disabled. */ struct device *cpu; - struct cpu_info *info; struct cpuinfo_x86 c; - info = cpu_info(); - - printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index); + printk(BIOS_INFO, "cpu_initialize: CPU #%ld\n", info->index); cpu = info->cpu; if (!cpu) { @@ -289,3 +286,24 @@ void cpu_initialize(void) return; } +void cpu_work(struct cpu_info *info) +{ + workfunc f; + volatile workfunc *ptr = &info->work; + volatile u32 *params = info->params; + + printk(BIOS_INFO, "CPU #%ld ready to work\n", info->index); + + while (!*ptr) + ; + f = *ptr; + + printk(BIOS_SPEW, "CPU #%ld is asked to do %p\n", info->index, f); + info->result = f(params[0], params[1], params[2]); + + printk(BIOS_SPEW, "CPU #%ld finishes %p, mark %p\n", info->index, f, ptr); + *ptr = 0; + + printk(BIOS_INFO, "CPU #%ld leaving cpu_work()\n", info->index); +} + diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 2ac9093..227cb06 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -17,6 +17,20 @@ #include <cpu/intel/speedstep.h> #if CONFIG_SMP == 1 + +/* We do not want this struct to be visible outside this file. + * The external interface is via functions. + */ + +struct apcore { + u32 stack[4096 - sizeof(struct cpu_info)]; + struct cpu_info info; +}; + +#define TOS(x) (&apcores[(x)].stack[ARRAY_SIZE(apcores[x].stack)-1]) + +struct apcore apcores[CONFIG_MAX_CPUS]; + /* This is a lot more paranoid now, since Linux can NOT handle * being told there is a CPU when none exists. So any errors * will return 0, meaning no CPU. @@ -221,19 +235,22 @@ static atomic_t active_cpus = ATOMIC_INIT(1); * start_cpu returns. */ +/* N.B. if we move to serial smp init we don't need this spin lock. + * Consider for the future. + */ + static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; -static unsigned last_cpu_index = 0; -volatile unsigned long secondary_stack; +static unsigned int last_cpu_index = 0; +volatile unsigned long secondary_stack, secondary_cpu_info; int start_cpu(device_t cpu) { - extern unsigned char _estack[]; struct cpu_info *info; unsigned long stack_end; unsigned long apicid; - unsigned long index; unsigned long count; int result; + unsigned int index = last_cpu_index + 1; spin_lock(&start_cpu_lock); @@ -241,19 +258,27 @@ int start_cpu(device_t cpu) apicid = cpu->path.apic.apic_id; /* Get an index for the new processor */ - index = ++last_cpu_index; + if (index >= CONFIG_MAX_CPUS){ + printk(BIOS_ERR, "CONFIG_MAX_CPUS(%d) too small!\n", CONFIG_MAX_CPUS); + spin_unlock(&start_cpu_lock); + return 0; + } + + last_cpu_index = index; /* Find end of the new processors stack */ - stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); + stack_end = (unsigned long) TOS(index); /* Record the index and which cpu structure we are using */ - info = (struct cpu_info *)stack_end; + info = &apcores[index].info; info->index = index; info->cpu = cpu; /* Advertise the new stack to start_cpu */ secondary_stack = stack_end; - + secondary_cpu_info = (unsigned long) info; + printk(BIOS_SPEW, "start_cpu CPU %d secondary_stack %#lx info %p\n", + index, secondary_stack, info); /* Until the cpu starts up report the cpu is not enabled */ cpu->enabled = 0; cpu->initialized = 0; @@ -381,7 +406,7 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat #endif /* C entry point of secondary cpus */ -void secondary_cpu_init(void) +void secondary_cpu_init(struct cpu_info *info) { atomic_inc(&active_cpus); #if CONFIG_SERIAL_CPU_INIT == 1 @@ -398,11 +423,11 @@ void secondary_cpu_init(void) cr4_val |= (1 << 9 | 1 << 10); writecr4(cr4_val); #endif - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SERIAL_CPU_INIT == 1 spin_unlock(&start_cpu_lock); #endif - + cpu_work(info); atomic_dec(&active_cpus); stop_this_cpu(); @@ -476,8 +501,6 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } -#else /* CONFIG_SMP */ -#define initialize_other_cpus(root) do {} while(0) #endif /* CONFIG_SMP */ void initialize_cpus(struct bus *cpu_bus) @@ -522,7 +545,7 @@ void initialize_cpus(struct bus *cpu_bus) #endif /* Initialize the bootstrap processor */ - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SMP == 1 #if CONFIG_SERIAL_CPU_INIT == 1 @@ -534,3 +557,99 @@ void initialize_cpus(struct bus *cpu_bus) #endif } +#if CONFIG_SMP == 1 +/* work primitives */ + +/* start_work is only intended to be called by the bsp. */ +/* A built in assumption of this code is that you know what + * you're doing. This is firmware, not pthreads. You should + * not call this function for a core if: + * - the core does not exist + * - the core is not initialized + * - the core is busy + * Any of these return a -1, else the core is started and + * 0 is returned. + */ +static int start_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c) +{ + struct cpu_info *info; + volatile workfunc *ptr; + volatile u32 *params; + + if (core >= CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + if (*ptr){ + printk(BIOS_EMERG, "start_work: core is busy %d\n", core); + return -1; + } + params = (u32 *)&info->params; + params[0] = a; + params[1] = b; + params[2] = c; + + printk(BIOS_INFO, "BSP starts work on core %d\n", core); + + /* This interface depends on arguments being written, + * then the function pointer being written. + */ + barrier(); + *ptr = f; + return 0; +} + +/* wait for the work to finish and return the result. Wait at + * most maxusec microseconds. + */ +static int wait_work(unsigned int core, u32 *retval, unsigned int maxusec) +{ + unsigned int usec; + struct cpu_info *info; + volatile workfunc *ptr; + u32 result; + + if (core >= CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + for(usec = 0; usec < maxusec && *ptr; usec++) + udelay(1); + + /* N.B. since only the BSP starts cores, there is not + * problem checking the pointer since access to it is + * serialized by the single-threaded BSP code. + */ + if (*ptr){ + printk(BIOS_INFO, "core %d still running after %d microseconds\n", + core, usec); + return -1; + } + result = info->result; + printk(BIOS_INFO, "Result is %#x\n", result); + if (retval) + *retval = result; + return 0; +} + +/* start the work and wait for it to finish */ +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout) +{ + if (start_work(core, f, a, b, c)) + return -1; + return wait_work(core, retval, timeout); +} +#endif /* CONFIG_SMP == 1 */ diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index dc00b08..84e0c6e 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -42,6 +42,8 @@ _secondary_start: xorl %eax, %eax movl secondary_stack, %esp movl %eax, secondary_stack + movl secondary_cpu_info, %eax + pushl %eax call secondary_cpu_init 1: hlt diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index cca2be1..362c53c 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -5,9 +5,13 @@ struct device; struct bus; #include <arch/cpu.h> -void cpu_initialize(void); +void cpu_initialize(struct cpu_info *info); void initialize_cpus(struct bus *cpu_bus); -void secondary_cpu_init(void); +void secondary_cpu_init(struct cpu_info *info); +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout); +void cpu_work(struct cpu_info *info); + #if !CONFIG_WAIT_BEFORE_CPUS_INIT #define cpus_ready_for_init() do {} while(0) [View Less]

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Re: [coreboot] coccinelle project for i915 graphics driver for coreboot
by Peter Stuge 09 Apr '12

09 Apr '12

ron minnich wrote: > What I'm thinking to do is submit a commit for this tool in its > nascent state and let people take a look. Or, share the code, which > may be better. I think it's a good approach. I would like having separate repositories for our tools, but for now adding one more is not making the problem worse I guess. //Peter

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Re: [coreboot] coccinelle project for i915 graphics driver for coreboot
by Paul Menzel 09 Apr '12

09 Apr '12

Dear Ron, Am Montag, den 09.04.2012, 11:30 -0700 schrieb ron minnich: > I'm trying an experiment and I welcome anyone who wants to help. > > It's a simple idea motivated by a very hard problem. The problem is > that we have unending problems with binary video bioses. We'd like to > get to a source based video bios on, e.g., chromebook. […] > The simple idea is to use coccinelle to extract the init code from the > linux driver to create a standalone piece of C code . I'… [View More]

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New patch to review for coreboot: a928a36 Removed repeated sections of code in header file
by Vikram Narayanan 09 Apr '12

09 Apr '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/881 -gerrit commit a928a367944580ed22a27ad5ad9de1ae2a17abde Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Feb 11 21:44:10 2012 +0530 Removed repeated sections of code in header file Change-Id: Ia25e554dc2b4885b0470d250efb8b71671e47adb Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/include/cpu/amd/… [View More]

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coccinelle project for i915 graphics driver for coreboot
by ron minnich 09 Apr '12

09 Apr '12

I'm trying an experiment and I welcome anyone who wants to help. It's a simple idea motivated by a very hard problem. The problem is that we have unending problems with binary video bioses. We'd like to get to a source based video bios on, e.g., chromebook. The linux driver for the intel i915 series can in fact turn on hardware without the vbios having run. This is great; one reason we boot the chromebook so fast (as some of you saw last week) is that we don't bother running the video bios. … [View More]

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Patch set updated for coreboot: 83d27ab Add multicore support to coreboot
by Ronald G. Minnich 09 Apr '12

09 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/877 -gerrit commit 83d27ab81445e3f9cc88ed77ec52800c5c7b4321 Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 23:51:18 2012 -0700 Add multicore support to coreboot This set of changes supports the ability for multicore support in coreboot. To give people a chance to examine the structure, and to make bisecting for bugs easier,… [View More] we are implementing the patch in 3 stages. This first stage introduces the basic mechanism but does not make any visible change in behavior. The APs, instead of being immediately spun down, are asked to run one debug print function and then spun down. The means by which APs are tasked was implemented in the NIX operating system in 2011, see: http://code.google.com/p/nix-os/ The APs come alive and spin on a memory location, contained in a per-AP structure. Tasking is accomplished by setting parameters into an argument array and then writing a function pointer into the memory location. The AP indicates completion by writing zero to the memory location. The BSP can wait for the AP to finish (synchronous) or going off to do other work (asynchronous). Wait times are in units of microseconds. This way of tasking APs is incredibly cheap and fast: in the minimal case, one memory write suffices to launch an AP into doing work. This code has been tested on a sandybridge system (chromebook) and on another 4-core sandybridge system. Take the opportunity to remove the macro definition whose origins few people remember. Change-Id: I19f8587562fd499e98457aa9f11b52400c105697 Signed-off-by: Ron Minnich <rminnich(a)gmail.com> --- src/arch/x86/include/arch/cpu.h | 5 ++ src/arch/x86/lib/cpu.c | 30 +++++++-- src/cpu/x86/lapic/lapic_cpu_init.c | 137 +++++++++++++++++++++++++++++++++--- src/include/cpu/cpu.h | 10 ++- 4 files changed, 165 insertions(+), 17 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 604abde..34d0856 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -157,9 +157,14 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); +typedef u32 (*workfunc)(u32, u32, u32); + struct cpu_info { device_t cpu; unsigned long index; + workfunc work; + u32 params[3]; + u32 result; }; static inline struct cpu_info *cpu_info(void) diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 98ede06..ad028e3 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -234,7 +234,7 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } -void cpu_initialize(void) +void cpu_initialize(struct cpu_info *info) { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -242,12 +242,9 @@ void cpu_initialize(void) * disabled. */ struct device *cpu; - struct cpu_info *info; struct cpuinfo_x86 c; - info = cpu_info(); - - printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index); + printk(BIOS_INFO, "cpu_initialize: CPU #%ld\n", info->index); cpu = info->cpu; if (!cpu) { @@ -289,3 +286,26 @@ void cpu_initialize(void) return; } +void cpu_work(struct cpu_info *info) +{ + workfunc f; + volatile workfunc *ptr = &info->work; + volatile u32 *params = info->params; + + printk(BIOS_INFO, "CPU #%ld ready to work\n", info->index); + + while (!*ptr) + ; + f = *ptr; + + printk(BIOS_SPEW, "CPU #%ld is asked to do %p\n", info->index, f); + f(params[0], params[1], params[2]); + + printk(BIOS_SPEW, "CPU #%ld finishes %p, mark %p\n", info->index, f, ptr); + *ptr = 0; + + printk(BIOS_INFO, "CPU #%ld leaving cpu_work()\n", info->index); + + return; +} + diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 2ac9093..f54f07c 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -17,6 +17,21 @@ #include <cpu/intel/speedstep.h> #if CONFIG_SMP == 1 + +/* we do not want this struct visible outside this file. + * The external interface is via functions. + */ + +struct apcore { + u32 stack[1024 - sizeof(struct cpu_info)]; + struct cpu_info info; +}; + +#define TOS(x) (&apcores[(x)].stack[ARRAY_SIZE(apcores[x].stack)-1]) +typedef struct apcore apcore_t; + +apcore_t apcores[CONFIG_MAX_CPUS]; + /* This is a lot more paranoid now, since Linux can NOT handle * being told there is a CPU when none exists. So any errors * will return 0, meaning no CPU. @@ -221,13 +236,16 @@ static atomic_t active_cpus = ATOMIC_INIT(1); * start_cpu returns. */ +/* N.B. if we move to serial smp init we don't need this spin lock. + * Consider for the future. + */ + static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; static unsigned last_cpu_index = 0; volatile unsigned long secondary_stack; int start_cpu(device_t cpu) { - extern unsigned char _estack[]; struct cpu_info *info; unsigned long stack_end; unsigned long apicid; @@ -241,19 +259,26 @@ int start_cpu(device_t cpu) apicid = cpu->path.apic.apic_id; /* Get an index for the new processor */ + if ((last_cpu_index+1) >= CONFIG_MAX_CPUS){ + printk(BIOS_ERR, "CONFIG_MAX_CPUS(%d) too small!\n", CONFIG_MAX_CPUS); + spin_unlock(&start_cpu_lock); + return 0; + } + index = ++last_cpu_index; /* Find end of the new processors stack */ - stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); + stack_end = (unsigned long) TOS(index); /* Record the index and which cpu structure we are using */ - info = (struct cpu_info *)stack_end; + info = &apcores[index].info; info->index = index; info->cpu = cpu; /* Advertise the new stack to start_cpu */ secondary_stack = stack_end; - + printk(BIOS_SPEW, "start_cpu CPU %ld secondary_stack %#lx info %p\n", + index, secondary_stack, info); /* Until the cpu starts up report the cpu is not enabled */ cpu->enabled = 0; cpu->initialized = 0; @@ -381,8 +406,11 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat #endif /* C entry point of secondary cpus */ -void secondary_cpu_init(void) +void secondary_cpu_init(u32 infoptr) { + /* note: we tried (((u32 *)&infoptr)[1]) but that failed. Compiler? */ + struct cpu_info *info = (struct cpu_info *)(((u8*)&infoptr)+sizeof(u32)); + atomic_inc(&active_cpus); #if CONFIG_SERIAL_CPU_INIT == 1 spin_lock(&start_cpu_lock); @@ -398,11 +426,11 @@ void secondary_cpu_init(void) cr4_val |= (1 << 9 | 1 << 10); writecr4(cr4_val); #endif - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SERIAL_CPU_INIT == 1 spin_unlock(&start_cpu_lock); #endif - + cpu_work(info); atomic_dec(&active_cpus); stop_this_cpu(); @@ -476,8 +504,6 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } -#else /* CONFIG_SMP */ -#define initialize_other_cpus(root) do {} while(0) #endif /* CONFIG_SMP */ void initialize_cpus(struct bus *cpu_bus) @@ -505,6 +531,7 @@ void initialize_cpus(struct bus *cpu_bus) info->cpu = alloc_find_dev(cpu_bus, &cpu_path); #if CONFIG_SMP == 1 + memset(apcores, 0, sizeof(*apcores)); copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif @@ -522,7 +549,7 @@ void initialize_cpus(struct bus *cpu_bus) #endif /* Initialize the bootstrap processor */ - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SMP == 1 #if CONFIG_SERIAL_CPU_INIT == 1 @@ -534,3 +561,93 @@ void initialize_cpus(struct bus *cpu_bus) #endif } +#if CONFIG_SMP == 1 +/* work primitives */ + +/* start_work is only intended to be called by the bsp. */ +/* A built in assumption of this code is that you know what + * you're doing. This is firmware, not pthreads. You should + * not call this function for a core if: + * - the core does not exist + * - the core is not initialized + * - the core is busy + * Any of these return a -1, else the core is started and + * 0 is returned. + */ +int start_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c) +{ + struct cpu_info *info; + volatile workfunc *ptr; + volatile u32 *params; + + if (core >= CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + if (*ptr){ + printk(BIOS_EMERG, "start_work: core is busy %d\n", core); + return -1; + } + params = (u32 *)&info->params; + params[0] = a; + params[1] = b; + params[2] = c; + printk(BIOS_INFO, "BSP starts work on core %d\n", core); + *ptr = f; + return 0; +} + +/* wait for the work to finish and return the result. Wait at + * most maxusec microseconds. + */ +int wait_work(unsigned int core, u32 *retval, unsigned int maxusec) +{ + unsigned int usec; + struct cpu_info *info; + volatile workfunc *ptr; + volatile u32 *result; + + if (core >= CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + for(usec = 0; usec < maxusec && *ptr; usec++) + udelay(1); + + /* N.B. since only the BSP starts cores, there is not + * problem checking the pointer since access to it is + * serialized by the single-threaded BSP code. + */ + if (*ptr){ + printk(BIOS_INFO, "core %d still running after %d microseconds\n", + core, usec); + return -1; + } + result = &info->result; + printk(BIOS_INFO, "info->work after result is %#lx\n", (unsigned long)*result); + if (retval) + *retval = *result; + return 0; +} + +/* start the work and wait for it to finish */ +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout) +{ + if (start_work(core, f, a, b, c)) + return -1; + return wait_work(core, retval, timeout); +} +#endif /* CONFIG_SMP == 1 */ diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index cca2be1..0b7a748 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -5,9 +5,15 @@ struct device; struct bus; #include <arch/cpu.h> -void cpu_initialize(void); +void cpu_initialize(struct cpu_info *info); void initialize_cpus(struct bus *cpu_bus); -void secondary_cpu_init(void); +void secondary_cpu_init(u32 unused); +int start_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c); +int wait_work(unsigned int core, u32 *retval, unsigned int maxusec); +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout); +void cpu_work(struct cpu_info *info); + #if !CONFIG_WAIT_BEFORE_CPUS_INIT #define cpus_ready_for_init() do {} while(0) [View Less]

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Patch set updated for coreboot: 7ebde20 Add multicore support to coreboot
by Ronald G. Minnich 09 Apr '12

09 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/877 -gerrit commit 7ebde200d7acc1409b952b738c41be28ddf9a4e7 Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 23:51:18 2012 -0700 Add multicore support to coreboot This set of changes supports the ability for multicore support in coreboot. To give people a chance to examine the structure, and to make bisecting for bugs easier,… [View More] we are implementing the patch in 3 stages. This first stage introduces the basic mechanism but does not make any visible change in behavior. The APs, instead of being immediately spun down, are asked to run one debug print function and then spun down. The means by which APs are tasked was implemented in the NIX operating system in 2011, see: http://code.google.com/p/nix-os/ The APs come alive and spin on a memory location, contained in a per-AP structure. Tasking is accomplished by setting parameters into an argument array and then writing a function pointer into the memory location. The AP indicates completion by writing zero to the memory location. The BSP can wait for the AP to finish (synchronous) or going off to do other work (asynchronous). Wait times are in units of microseconds. This way of tasking APs is incredibly cheap and fast: in the minimal case, one memory write suffices to launch an AP into doing work. This code has been tested on a sandybridge system (chromebook) and on another 4-core sandybridge system. Take the opportunity to remove the macro definition whose origins few people remember. Change-Id: I19f8587562fd499e98457aa9f11b52400c105697 Signed-off-by: Ron Minnich <rminnich(a)gmail.com> --- src/arch/x86/include/arch/cpu.h | 5 ++ src/arch/x86/lib/cpu.c | 30 +++++++-- src/cpu/x86/lapic/lapic_cpu_init.c | 132 +++++++++++++++++++++++++++++++++--- src/include/cpu/cpu.h | 10 ++- 4 files changed, 160 insertions(+), 17 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 604abde..34d0856 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -157,9 +157,14 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); +typedef u32 (*workfunc)(u32, u32, u32); + struct cpu_info { device_t cpu; unsigned long index; + workfunc work; + u32 params[3]; + u32 result; }; static inline struct cpu_info *cpu_info(void) diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 98ede06..ad028e3 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -234,7 +234,7 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } -void cpu_initialize(void) +void cpu_initialize(struct cpu_info *info) { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -242,12 +242,9 @@ void cpu_initialize(void) * disabled. */ struct device *cpu; - struct cpu_info *info; struct cpuinfo_x86 c; - info = cpu_info(); - - printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index); + printk(BIOS_INFO, "cpu_initialize: CPU #%ld\n", info->index); cpu = info->cpu; if (!cpu) { @@ -289,3 +286,26 @@ void cpu_initialize(void) return; } +void cpu_work(struct cpu_info *info) +{ + workfunc f; + volatile workfunc *ptr = &info->work; + volatile u32 *params = info->params; + + printk(BIOS_INFO, "CPU #%ld ready to work\n", info->index); + + while (!*ptr) + ; + f = *ptr; + + printk(BIOS_SPEW, "CPU #%ld is asked to do %p\n", info->index, f); + f(params[0], params[1], params[2]); + + printk(BIOS_SPEW, "CPU #%ld finishes %p, mark %p\n", info->index, f, ptr); + *ptr = 0; + + printk(BIOS_INFO, "CPU #%ld leaving cpu_work()\n", info->index); + + return; +} + diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 2ac9093..aca429a 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -17,6 +17,21 @@ #include <cpu/intel/speedstep.h> #if CONFIG_SMP == 1 + +/* we do not want this struct visible outside this file. + * The external interface is via functions. + */ + +struct apcore { + u32 stack[1024 - sizeof(struct cpu_info)]; + struct cpu_info info; +}; + +#define TOS(x) (&apcores[(x)].stack[ARRAY_SIZE(apcores[x].stack)-1]) +typedef struct apcore apcore_t; + +apcore_t apcores[CONFIG_MAX_CPUS]; + /* This is a lot more paranoid now, since Linux can NOT handle * being told there is a CPU when none exists. So any errors * will return 0, meaning no CPU. @@ -227,7 +242,6 @@ volatile unsigned long secondary_stack; int start_cpu(device_t cpu) { - extern unsigned char _estack[]; struct cpu_info *info; unsigned long stack_end; unsigned long apicid; @@ -241,19 +255,25 @@ int start_cpu(device_t cpu) apicid = cpu->path.apic.apic_id; /* Get an index for the new processor */ + if (last_cpu_index >= CONFIG_MAX_CPUS){ + printk(BIOS_ERR, "CONFIG_MAX_CPUS(%d) too small!\n", CONFIG_MAX_CPUS); + return 0; + } + index = ++last_cpu_index; /* Find end of the new processors stack */ - stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); + stack_end = (unsigned long) TOS(index); /* Record the index and which cpu structure we are using */ - info = (struct cpu_info *)stack_end; + info = &apcores[index].info; info->index = index; info->cpu = cpu; /* Advertise the new stack to start_cpu */ secondary_stack = stack_end; - + printk(BIOS_SPEW, "start_cpu CPU %ld secondary_stack %#lx info %p\n", + index, secondary_stack, info); /* Until the cpu starts up report the cpu is not enabled */ cpu->enabled = 0; cpu->initialized = 0; @@ -381,8 +401,11 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat #endif /* C entry point of secondary cpus */ -void secondary_cpu_init(void) +void secondary_cpu_init(u32 infoptr) { + /* note: we tried (((u32 *)&infoptr)[1]) but that failed. Compiler? */ + struct cpu_info *info = (struct cpu_info *)(((u8*)&infoptr)+sizeof(u32)); + atomic_inc(&active_cpus); #if CONFIG_SERIAL_CPU_INIT == 1 spin_lock(&start_cpu_lock); @@ -398,11 +421,11 @@ void secondary_cpu_init(void) cr4_val |= (1 << 9 | 1 << 10); writecr4(cr4_val); #endif - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SERIAL_CPU_INIT == 1 spin_unlock(&start_cpu_lock); #endif - + cpu_work(info); atomic_dec(&active_cpus); stop_this_cpu(); @@ -476,8 +499,6 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } -#else /* CONFIG_SMP */ -#define initialize_other_cpus(root) do {} while(0) #endif /* CONFIG_SMP */ void initialize_cpus(struct bus *cpu_bus) @@ -505,6 +526,7 @@ void initialize_cpus(struct bus *cpu_bus) info->cpu = alloc_find_dev(cpu_bus, &cpu_path); #if CONFIG_SMP == 1 + memset(apcores, 0, sizeof(*apcores)); copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif @@ -522,7 +544,7 @@ void initialize_cpus(struct bus *cpu_bus) #endif /* Initialize the bootstrap processor */ - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SMP == 1 #if CONFIG_SERIAL_CPU_INIT == 1 @@ -534,3 +556,93 @@ void initialize_cpus(struct bus *cpu_bus) #endif } +#if CONFIG_SMP == 1 +/* work primitives */ + +/* start_work is only intended to be called by the bsp. */ +/* A built in assumption of this code is that you know what + * you're doing. This is firmware, not pthreads. You should + * not call this function for a core if: + * - the core does not exist + * - the core is not initialized + * - the core is busy + * Any of these return a -1, else the core is started and + * 0 is returned. + */ +int start_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c) +{ + struct cpu_info *info; + volatile workfunc *ptr; + volatile u32 *params; + + if (core >= CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + if (*ptr){ + printk(BIOS_EMERG, "start_work: core is busy %d\n", core); + return -1; + } + params = (u32 *)&info->params; + params[0] = a; + params[1] = b; + params[2] = c; + printk(BIOS_INFO, "BSP starts work on core %d\n", core); + *ptr = f; + return 0; +} + +/* wait for the work to finish and return the result. Wait at + * most maxusec microseconds. + */ +int wait_work(unsigned int core, u32 *retval, unsigned int maxusec) +{ + unsigned int usec; + struct cpu_info *info; + volatile workfunc *ptr; + volatile u32 *result; + + if (core >= CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + for(usec = 0; usec < maxusec && *ptr; usec++) + udelay(1); + + /* N.B. since only the BSP starts cores, there is not + * problem checking the pointer since access to it is + * serialized by the single-threaded BSP code. + */ + if (*ptr){ + printk(BIOS_INFO, "core %d still running after %d microseconds\n", + core, usec); + return -1; + } + result = &info->result; + printk(BIOS_INFO, "info->work after result is %#lx\n", (unsigned long)*result); + if (retval) + *retval = *result; + return 0; +} + +/* start the work and wait for it to finish */ +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout) +{ + if (start_work(core, f, a, b, c)) + return -1; + return wait_work(core, retval, timeout); +} +#endif /* CONFIG_SMP == 1 */ diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index cca2be1..0b7a748 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -5,9 +5,15 @@ struct device; struct bus; #include <arch/cpu.h> -void cpu_initialize(void); +void cpu_initialize(struct cpu_info *info); void initialize_cpus(struct bus *cpu_bus); -void secondary_cpu_init(void); +void secondary_cpu_init(u32 unused); +int start_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c); +int wait_work(unsigned int core, u32 *retval, unsigned int maxusec); +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout); +void cpu_work(struct cpu_info *info); + #if !CONFIG_WAIT_BEFORE_CPUS_INIT #define cpus_ready_for_init() do {} while(0) [View Less]

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Trac reminder: list of new ticket(s)
by coreboot tracker 09 Apr '12

09 Apr '12

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Patch merged into coreboot/master: b55e2f4 Actually return %ebx value from cpuid_ebx()
by gerrit＠coreboot.org 08 Apr '12

08 Apr '12

the following patch was just integrated into master: commit b55e2f4611720891e645c719b1ec040ae00f88b0 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Sun Apr 8 11:32:34 2012 -0500 Actually return %ebx value from cpuid_ebx() Change-Id: I75f8f942950cad94439a10e389490ecfdd9272fe Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Build-Tested: build bot (Jenkins) at Sun Apr 8 18:51:51 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.… [View More]

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New patch to review for coreboot: b55e2f4 Actually return %ebx value from cpuid_ebx()
by Jonathan A. Kollasch 08 Apr '12

08 Apr '12

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/880 -gerrit commit b55e2f4611720891e645c719b1ec040ae00f88b0 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Sun Apr 8 11:32:34 2012 -0500 Actually return %ebx value from cpuid_ebx() Change-Id: I75f8f942950cad94439a10e389490ecfdd9272fe Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/arch/x86/… [View More]

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Patch set updated for coreboot: 39764b7 Add multicore support to coreboot
by Ronald G. Minnich 08 Apr '12

08 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/877 -gerrit commit 39764b7b5f5f997928ffca01fd89469d95016f4e Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 23:51:18 2012 -0700 Add multicore support to coreboot This set of changes supports the ability for multicore support in coreboot. To give people a chance to examine the structure, and to make bisecting for bugs easier,… [View More] we are implementing the patch in 3 stages. This first stage introduces the basic mechanism but does not make any visible change in behavior. The APs, instead of being immediately spun down, are asked to run one debug print function and then spun down. The means by which APs are tasked was implemented in the NIX operating system in 2011, see: http://code.google.com/p/nix-os/ The APs come alive and spin on a memory location, contained in a per-AP structure. Tasking is accomplished by setting parameters into an argument array and then writing a function pointer into the memory location. The AP indicates completion by writing zero to the memory location. The BSP can wait for the AP to finish (synchronous) or going off to do other work (asynchronous). This way of tasking APs is incredibly cheap and fast: in the minimal case, one memory write suffices to launch an AP into doing work. This code has been tested on a sandybridge system (chromebook) and on another 4-core sandybridge system. Change-Id: I19f8587562fd499e98457aa9f11b52400c105697 Signed-off-by: Ron Minnich <rminnich(a)gmail.com> --- src/arch/x86/include/arch/cpu.h | 5 ++ src/arch/x86/lib/cpu.c | 30 ++++++++-- src/cpu/x86/lapic/lapic_cpu_init.c | 110 +++++++++++++++++++++++++++++++++--- src/include/cpu/cpu.h | 10 +++- 4 files changed, 140 insertions(+), 15 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 604abde..34d0856 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -157,9 +157,14 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); +typedef u32 (*workfunc)(u32, u32, u32); + struct cpu_info { device_t cpu; unsigned long index; + workfunc work; + u32 params[3]; + u32 result; }; static inline struct cpu_info *cpu_info(void) diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 98ede06..ad028e3 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -234,7 +234,7 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } -void cpu_initialize(void) +void cpu_initialize(struct cpu_info *info) { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -242,12 +242,9 @@ void cpu_initialize(void) * disabled. */ struct device *cpu; - struct cpu_info *info; struct cpuinfo_x86 c; - info = cpu_info(); - - printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index); + printk(BIOS_INFO, "cpu_initialize: CPU #%ld\n", info->index); cpu = info->cpu; if (!cpu) { @@ -289,3 +286,26 @@ void cpu_initialize(void) return; } +void cpu_work(struct cpu_info *info) +{ + workfunc f; + volatile workfunc *ptr = &info->work; + volatile u32 *params = info->params; + + printk(BIOS_INFO, "CPU #%ld ready to work\n", info->index); + + while (!*ptr) + ; + f = *ptr; + + printk(BIOS_SPEW, "CPU #%ld is asked to do %p\n", info->index, f); + f(params[0], params[1], params[2]); + + printk(BIOS_SPEW, "CPU #%ld finishes %p, mark %p\n", info->index, f, ptr); + *ptr = 0; + + printk(BIOS_INFO, "CPU #%ld leaving cpu_work()\n", info->index); + + return; +} + diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 2ac9093..e425884 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -17,6 +17,21 @@ #include <cpu/intel/speedstep.h> #if CONFIG_SMP == 1 + +/* we do not want this struct visible outside this file. + * The external interface is via functions. + */ + +struct apcore { + u32 stack[1024 - sizeof(struct cpu_info)]; + struct cpu_info info; +}; + +#define TOS(x) (&apcores[(x)].stack[ARRAY_SIZE(apcores[x].stack)-1]) +typedef struct apcore apcore_t; + +apcore_t apcores[CONFIG_MAX_CPUS]; + /* This is a lot more paranoid now, since Linux can NOT handle * being told there is a CPU when none exists. So any errors * will return 0, meaning no CPU. @@ -227,7 +242,6 @@ volatile unsigned long secondary_stack; int start_cpu(device_t cpu) { - extern unsigned char _estack[]; struct cpu_info *info; unsigned long stack_end; unsigned long apicid; @@ -241,19 +255,24 @@ int start_cpu(device_t cpu) apicid = cpu->path.apic.apic_id; /* Get an index for the new processor */ + /* N.B. No checking against MAX_CPUS here. + * This function gets called if all those + * checks have been passed. + */ index = ++last_cpu_index; /* Find end of the new processors stack */ - stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); + stack_end = (unsigned long) TOS(index); /* Record the index and which cpu structure we are using */ - info = (struct cpu_info *)stack_end; + info = &apcores[index].info; info->index = index; info->cpu = cpu; /* Advertise the new stack to start_cpu */ secondary_stack = stack_end; - + printk(BIOS_SPEW, "start_cpu CPU %ld secondary_stack %#lx info %p\n", + index, secondary_stack, info); /* Until the cpu starts up report the cpu is not enabled */ cpu->enabled = 0; cpu->initialized = 0; @@ -381,8 +400,11 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat #endif /* C entry point of secondary cpus */ -void secondary_cpu_init(void) +void secondary_cpu_init(u32 infoptr) { + /* note: we tried (((u32 *)&infoptr)[1]) but that failed. Compiler? */ + struct cpu_info *info = (struct cpu_info *)(((u8*)&infoptr)+sizeof(u32)); + atomic_inc(&active_cpus); #if CONFIG_SERIAL_CPU_INIT == 1 spin_lock(&start_cpu_lock); @@ -398,11 +420,11 @@ void secondary_cpu_init(void) cr4_val |= (1 << 9 | 1 << 10); writecr4(cr4_val); #endif - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SERIAL_CPU_INIT == 1 spin_unlock(&start_cpu_lock); #endif - + cpu_work(info); atomic_dec(&active_cpus); stop_this_cpu(); @@ -505,6 +527,7 @@ void initialize_cpus(struct bus *cpu_bus) info->cpu = alloc_find_dev(cpu_bus, &cpu_path); #if CONFIG_SMP == 1 + memset(apcores, 0, sizeof(*apcores)); copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif @@ -522,7 +545,7 @@ void initialize_cpus(struct bus *cpu_bus) #endif /* Initialize the bootstrap processor */ - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SMP == 1 #if CONFIG_SERIAL_CPU_INIT == 1 @@ -534,3 +557,74 @@ void initialize_cpus(struct bus *cpu_bus) #endif } +#if CONFIG_SMP == 1 +/* work primitives */ +int start_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c) +{ + struct cpu_info *info; + volatile workfunc *ptr; + volatile u32 *params; + + if (core >= CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + if (*ptr){ + printk(BIOS_EMERG, "start_work: core is busy %d\n", core); + return -1; + } + params = (u32 *)&info->params; + params[0] = a; + params[1] = b; + params[2] = c; + printk(BIOS_INFO, "BSP starts work on core %d\n", core); + *ptr = f; + return 0; +} + +int wait_work(unsigned int core, u32 *retval, unsigned int maxwait) +{ + int i = 0; + struct cpu_info *info; + volatile workfunc *ptr; + volatile u32 *result; + + if (core >= CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + while (i++ < maxwait && *ptr) + if (i%100000 == 0) printk(BIOS_SPEW, "still waiting on %p at %d\n", + ptr, i); + if (*ptr){ + printk(BIOS_INFO, "core %d still running after %d iterations\n", + core, i); + return -1; + } + result = &info->result; + printk(BIOS_INFO, "info->work after result is %#lx\n", (unsigned long)*result); + if (retval) + *retval = *result; + return 0; +} + +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout) +{ + if (start_work(core, f, a, b, c)) + return -1; + return wait_work(core, retval, timeout); +} +#endif /* CONFIG_SMP == 1 */ diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index cca2be1..39f2fa2 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -5,9 +5,15 @@ struct device; struct bus; #include <arch/cpu.h> -void cpu_initialize(void); +void cpu_initialize(struct cpu_info *info); void initialize_cpus(struct bus *cpu_bus); -void secondary_cpu_init(void); +void secondary_cpu_init(u32 unused); +int start_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c); +int wait_work(unsigned int core, u32 *retval, unsigned int maxwait); +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout); +void cpu_work(struct cpu_info *info); + #if !CONFIG_WAIT_BEFORE_CPUS_INIT #define cpus_ready_for_init() do {} while(0) [View Less]

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Re: [coreboot] [RFC] Re-thinking the stages
by Carl-Daniel Hailfinger 07 Apr '12

07 Apr '12

Am 06.04.2012 22:38 schrieb ron minnich: > On Fri, Apr 6, 2012 at 11:12 AM, Marc Jones <marcj303(a)gmail.com> wrote: > >>> One such a nice app would be zmodem download of raminit. >> This is an interesting thought, but really a debug/development >> feature. > We even talked about this in v3. But it never got done, seems there is > no interest. I think it didn't get done for the same reason we had to abandon v3: lack of manpower. A few highly motivated … [View More]developers spent pretty much all of their time on v3, but bringing a completely new design and codebase from zero to production was simply too big of a task, yielding stable Qemu and GeodeLX ports but not much for other hardware. At the same time, v2 was moving along and getting new hardware support all the time. In the end, it was decided that the v2 codebase should get some of the designs proven in v3, and thus v4 was born. There is still some stuff I would love to prototype in v3 and then move to v4, and downloading raminit is one of those features. However, I won't have sufficient spare time this year to attempt that. >> I am not convinced of the value of earlier serial console. It adds >> complexity where things should be simple. I hesitate to continue >> moving more code before CAR. We have had a long standing goal to >> reduce code before CAR. > CAR is fragile! I agree. It should be reduced as much as possible. > > You may want to look at what we did in v3, it has some similarities to > your ideas. And, we dropped it :-) We already have multiple pre-CAR serial consoles if you want to build them: llshell, SerialICE and a few others. The trick is to integrate them into the coreboot execution flow in a way which lets the boot continue automatically in the normal case, and allow console access when you need it. >>> This also has a CAR and RAM environment (GCC-build) that can execute XIP >>> stages from Flash ROM or decompress stages to CAR/RAM from Flash ROM. >> >> At least with AMD processors, you can't execute code out of the data >> cache. The only way to get instructions cached is with a code fetch, >> which doesn't hit the data cache. By the way, if you're into really weird stuff, you could try to work around the apparent "data writes hit dcache, not icache" limitation by running the downloaded code in x86emu in CAR because for x86emu the emulated instructions are data. You'll need flameproof underwear if you plan to submit such a patch, though. Regards, Carl-Daniel -- http://www.hailfinger.org/ [View Less]

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Patch set updated for coreboot: 9f3f266 Add multicore support to coreboot
by Ronald G. Minnich 07 Apr '12

07 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/877 -gerrit commit 9f3f26668c3332aaeb0bde1b6cda80d363496da2 Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 23:51:18 2012 -0700 Add multicore support to coreboot This set of changes supports the ability for multicore support in coreboot. To give people a chance to examine the structure, and to make bisecting for bugs easier,… [View More] we are implementing the patch in 3 stages. This first stage introduces the basic mechanism but does not make any visible change in behavior. The APs, instead of being immediately spun down, are asked to run one debug print function and then spun down. The means by which APs are tasked was implemented in the NIX operating system in 2011, see: http://code.google.com/p/nix-os/ The APs come alive and spin on a memory location, contained in a per-AP structure. Tasking is accomplished by setting parameters into an argument array and then writing a function pointer into the memory location. The AP indicates completion by writing zero to the memory location. The BSP can wait for the AP to finish (synchronous) or going off to do other work (asynchronous). This way of tasking APs is incredibly cheap and fast: in the minimal case, one memory write suffices to launch an AP into doing work. This code has been tested on a sandybridge system (chromebook) and on another 4-core sandybridge system. Change-Id: I19f8587562fd499e98457aa9f11b52400c105697 Signed-off-by: Ron Minnich <rminnich(a)gmail.com> --- src/arch/x86/include/arch/cpu.h | 5 ++ src/arch/x86/lib/cpu.c | 30 ++++++++-- src/cpu/x86/lapic/lapic_cpu_init.c | 108 +++++++++++++++++++++++++++++++++--- src/include/cpu/cpu.h | 10 +++- 4 files changed, 137 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 604abde..34d0856 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -157,9 +157,14 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); +typedef u32 (*workfunc)(u32, u32, u32); + struct cpu_info { device_t cpu; unsigned long index; + workfunc work; + u32 params[3]; + u32 result; }; static inline struct cpu_info *cpu_info(void) diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 98ede06..ad028e3 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -234,7 +234,7 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } -void cpu_initialize(void) +void cpu_initialize(struct cpu_info *info) { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -242,12 +242,9 @@ void cpu_initialize(void) * disabled. */ struct device *cpu; - struct cpu_info *info; struct cpuinfo_x86 c; - info = cpu_info(); - - printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index); + printk(BIOS_INFO, "cpu_initialize: CPU #%ld\n", info->index); cpu = info->cpu; if (!cpu) { @@ -289,3 +286,26 @@ void cpu_initialize(void) return; } +void cpu_work(struct cpu_info *info) +{ + workfunc f; + volatile workfunc *ptr = &info->work; + volatile u32 *params = info->params; + + printk(BIOS_INFO, "CPU #%ld ready to work\n", info->index); + + while (!*ptr) + ; + f = *ptr; + + printk(BIOS_SPEW, "CPU #%ld is asked to do %p\n", info->index, f); + f(params[0], params[1], params[2]); + + printk(BIOS_SPEW, "CPU #%ld finishes %p, mark %p\n", info->index, f, ptr); + *ptr = 0; + + printk(BIOS_INFO, "CPU #%ld leaving cpu_work()\n", info->index); + + return; +} + diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 2ac9093..108bb66 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -17,6 +17,21 @@ #include <cpu/intel/speedstep.h> #if CONFIG_SMP == 1 + +/* we do not want this struct visible outside this file. + * The external interface is via functions. + */ + +struct apcore { + u32 stack[1024 - sizeof(struct cpu_info)]; + struct cpu_info info; +}; + +#define TOS(x) (&apcores[(x)].stack[ARRAY_SIZE(apcores[x].stack)-1]) +typedef struct apcore apcore_t; + +apcore_t apcores[CONFIG_MAX_CPUS]; + /* This is a lot more paranoid now, since Linux can NOT handle * being told there is a CPU when none exists. So any errors * will return 0, meaning no CPU. @@ -227,7 +242,6 @@ volatile unsigned long secondary_stack; int start_cpu(device_t cpu) { - extern unsigned char _estack[]; struct cpu_info *info; unsigned long stack_end; unsigned long apicid; @@ -244,16 +258,17 @@ int start_cpu(device_t cpu) index = ++last_cpu_index; /* Find end of the new processors stack */ - stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); + stack_end = (unsigned long) TOS(index); /* Record the index and which cpu structure we are using */ - info = (struct cpu_info *)stack_end; + info = &apcores[index].info; info->index = index; info->cpu = cpu; /* Advertise the new stack to start_cpu */ secondary_stack = stack_end; - + printk(BIOS_SPEW, "start_cpu CPU %ld secondary_stack %#lx info %p\n", + index, secondary_stack, info); /* Until the cpu starts up report the cpu is not enabled */ cpu->enabled = 0; cpu->initialized = 0; @@ -381,8 +396,11 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat #endif /* C entry point of secondary cpus */ -void secondary_cpu_init(void) -{ +void secondary_cpu_init(u32 infoptr) + { + /* note: we tried (((u32 *)&infoptr)[1]) but that failed. Compiler? */ + struct cpu_info *info = (struct cpu_info *)(((u8*)&infoptr)+sizeof(u32)); + atomic_inc(&active_cpus); #if CONFIG_SERIAL_CPU_INIT == 1 spin_lock(&start_cpu_lock); @@ -398,11 +416,11 @@ void secondary_cpu_init(void) cr4_val |= (1 << 9 | 1 << 10); writecr4(cr4_val); #endif - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SERIAL_CPU_INIT == 1 spin_unlock(&start_cpu_lock); #endif - + cpu_work(info); atomic_dec(&active_cpus); stop_this_cpu(); @@ -505,6 +523,7 @@ void initialize_cpus(struct bus *cpu_bus) info->cpu = alloc_find_dev(cpu_bus, &cpu_path); #if CONFIG_SMP == 1 + memset(apcores, 0, sizeof(*apcores)); copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif @@ -522,7 +541,7 @@ void initialize_cpus(struct bus *cpu_bus) #endif /* Initialize the bootstrap processor */ - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SMP == 1 #if CONFIG_SERIAL_CPU_INIT == 1 @@ -534,3 +553,74 @@ void initialize_cpus(struct bus *cpu_bus) #endif } +#if CONFIG_SMP == 1 +/* work primitives */ +int start_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c) +{ + struct cpu_info *info; + volatile workfunc *ptr; + volatile u32 *params; + + if (core > CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + if (*ptr){ + printk(BIOS_EMERG, "start_work: core is busy %d\n", core); + return -1; + } + params = (u32 *)&info->params; + params[0] = a; + params[1] = b; + params[2] = c; + printk(BIOS_INFO, "BSP starts work on core %d\n", core); + *ptr = f; + return 0; +} + +int wait_work(unsigned int core, u32 *retval, unsigned int maxwait) +{ + int i = 0; + struct cpu_info *info; + volatile workfunc *ptr; + volatile u32 *result; + + if (core > CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + while (i++ < maxwait && *ptr) + if (i%100000 == 0) printk(BIOS_SPEW, "still waiting on %p at %d\n", + ptr, i); + if (*ptr){ + printk(BIOS_INFO, "core %d still running after %d iterations\n", + core, i); + return -1; + } + result = &info->result; + printk(BIOS_INFO, "info->work after result is %#lx\n", (unsigned long)*result); + if (retval) + *retval = *result; + return 0; +} + +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout) +{ + if (start_work(core, f, a, b, c)) + return -1; + return wait_work(core, retval, timeout); +} +#endif /* CONFIG_SMP == 1 */ diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index cca2be1..39f2fa2 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -5,9 +5,15 @@ struct device; struct bus; #include <arch/cpu.h> -void cpu_initialize(void); +void cpu_initialize(struct cpu_info *info); void initialize_cpus(struct bus *cpu_bus); -void secondary_cpu_init(void); +void secondary_cpu_init(u32 unused); +int start_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c); +int wait_work(unsigned int core, u32 *retval, unsigned int maxwait); +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout); +void cpu_work(struct cpu_info *info); + #if !CONFIG_WAIT_BEFORE_CPUS_INIT #define cpus_ready_for_init() do {} while(0) [View Less]

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Patch set updated for coreboot: e3f939c Add multicore support to coreboot
by Ronald G. Minnich 07 Apr '12

07 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/877 -gerrit commit e3f939c617fd9eced19ccc2f8bfd6f9012c232f3 Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 23:51:18 2012 -0700 Add multicore support to coreboot This set of changes supports the ability for multicore support in coreboot. To give people a chance to examine the structure, and to make bisecting for bugs easier,… [View More] we are implementing the patch in 3 stages. This first stage introduces the basic mechanism but does not make any visible change in behavior. The APs, instead of being immediately spun down, are asked to run one debug print function and then spun down. The means by which APs are tasked was implemented in the NIX operating system in 2011, see: http://code.google.com/p/nix-os/ The APs come alive and spin on a memory location, contained in a per-AP structure. Tasking is accomplished by setting parameters into an argument array and then writing a function pointer into the memory location. The AP indicates completion by writing zero to the memory location. The BSP can wait for the AP to finish (synchronous) or going off to do other work (asynchronous). This way of tasking APs is incredibly cheap and fast: in the minimal case, one memory write suffices to launch an AP into doing work. This code has been tested on a sandybridge system (chromebook) and on another 4-core sandybridge system. Change-Id: I19f8587562fd499e98457aa9f11b52400c105697 Signed-off-by: Ron Minnich <rminnich(a)gmail.com> --- src/arch/x86/include/arch/cpu.h | 5 ++ src/arch/x86/lib/cpu.c | 30 ++++++++-- src/cpu/x86/lapic/lapic_cpu_init.c | 108 +++++++++++++++++++++++++++++++++--- src/include/cpu/cpu.h | 10 +++- 4 files changed, 137 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 604abde..34d0856 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -157,9 +157,14 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); +typedef u32 (*workfunc)(u32, u32, u32); + struct cpu_info { device_t cpu; unsigned long index; + workfunc work; + u32 params[3]; + u32 result; }; static inline struct cpu_info *cpu_info(void) diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 98ede06..ad028e3 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -234,7 +234,7 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } -void cpu_initialize(void) +void cpu_initialize(struct cpu_info *info) { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -242,12 +242,9 @@ void cpu_initialize(void) * disabled. */ struct device *cpu; - struct cpu_info *info; struct cpuinfo_x86 c; - info = cpu_info(); - - printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index); + printk(BIOS_INFO, "cpu_initialize: CPU #%ld\n", info->index); cpu = info->cpu; if (!cpu) { @@ -289,3 +286,26 @@ void cpu_initialize(void) return; } +void cpu_work(struct cpu_info *info) +{ + workfunc f; + volatile workfunc *ptr = &info->work; + volatile u32 *params = info->params; + + printk(BIOS_INFO, "CPU #%ld ready to work\n", info->index); + + while (!*ptr) + ; + f = *ptr; + + printk(BIOS_SPEW, "CPU #%ld is asked to do %p\n", info->index, f); + f(params[0], params[1], params[2]); + + printk(BIOS_SPEW, "CPU #%ld finishes %p, mark %p\n", info->index, f, ptr); + *ptr = 0; + + printk(BIOS_INFO, "CPU #%ld leaving cpu_work()\n", info->index); + + return; +} + diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index ed9940c..a1a2097 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -16,6 +16,21 @@ #include <cpu/cpu.h> #if CONFIG_SMP == 1 + +/* we do not want this struct visible outside this file. + * The external interface is via functions. + */ + +struct apcore { + u32 stack[1024 - sizeof(struct cpu_info)]; + struct cpu_info info; +}; + +#define TOS(x) (&apcores[(x)].stack[ARRAY_SIZE(apcores[x].stack)-1]) +typedef struct apcore apcore_t; + +apcore_t apcores[CONFIG_MAX_CPUS]; + /* This is a lot more paranoid now, since Linux can NOT handle * being told there is a CPU when none exists. So any errors * will return 0, meaning no CPU. @@ -226,7 +241,6 @@ volatile unsigned long secondary_stack; int start_cpu(device_t cpu) { - extern unsigned char _estack[]; struct cpu_info *info; unsigned long stack_end; unsigned long apicid; @@ -243,16 +257,17 @@ int start_cpu(device_t cpu) index = ++last_cpu_index; /* Find end of the new processors stack */ - stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); + stack_end = (unsigned long) TOS(index); /* Record the index and which cpu structure we are using */ - info = (struct cpu_info *)stack_end; + info = &apcores[index].info; info->index = index; info->cpu = cpu; /* Advertise the new stack to start_cpu */ secondary_stack = stack_end; - + printk(BIOS_SPEW, "start_cpu CPU %ld secondary_stack %#lx info %p\n", + index, secondary_stack, info); /* Until the cpu starts up report the cpu is not enabled */ cpu->enabled = 0; cpu->initialized = 0; @@ -380,8 +395,11 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat #endif /* C entry point of secondary cpus */ -void secondary_cpu_init(void) -{ +void secondary_cpu_init(u32 infoptr) + { + /* note: we tried (((u32 *)&infoptr)[1]) but that failed. Compiler? */ + struct cpu_info *info = (struct cpu_info *)(((u8*)&infoptr)+sizeof(u32)); + atomic_inc(&active_cpus); #if CONFIG_SERIAL_CPU_INIT == 1 spin_lock(&start_cpu_lock); @@ -397,11 +415,11 @@ void secondary_cpu_init(void) cr4_val |= (1 << 9 | 1 << 10); writecr4(cr4_val); #endif - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SERIAL_CPU_INIT == 1 spin_unlock(&start_cpu_lock); #endif - + cpu_work(info); atomic_dec(&active_cpus); stop_this_cpu(); @@ -498,6 +516,7 @@ void initialize_cpus(struct bus *cpu_bus) info->cpu = alloc_find_dev(cpu_bus, &cpu_path); #if CONFIG_SMP == 1 + memset(apcores, 0, sizeof(*apcores)); copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif @@ -515,7 +534,7 @@ void initialize_cpus(struct bus *cpu_bus) #endif /* Initialize the bootstrap processor */ - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SMP == 1 #if CONFIG_SERIAL_CPU_INIT == 1 @@ -527,3 +546,74 @@ void initialize_cpus(struct bus *cpu_bus) #endif } +#if CONFIG_SMP == 1 +/* work primitives */ +int start_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c) +{ + struct cpu_info *info; + volatile workfunc *ptr; + volatile u32 *params; + + if (core > CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + if (*ptr){ + printk(BIOS_EMERG, "start_work: core is busy %d\n", core); + return -1; + } + params = (u32 *)&info->params; + params[0] = a; + params[1] = b; + params[2] = c; + printk(BIOS_INFO, "BSP starts work on core %d\n", core); + *ptr = f; + return 0; +} + +int wait_work(unsigned int core, u32 *retval, unsigned int maxwait) +{ + int i = 0; + struct cpu_info *info; + volatile workfunc *ptr; + volatile u32 *result; + + if (core > CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + while (i++ < maxwait && *ptr) + if (i%100000 == 0) printk(BIOS_SPEW, "still waiting on %p at %d\n", + ptr, i); + if (*ptr){ + printk(BIOS_INFO, "core %d still running after %d iterations\n", + core, i); + return -1; + } + result = &info->result; + printk(BIOS_INFO, "info->work after result is %#lx\n", (unsigned long)*result); + if (retval) + *retval = *result; + return 0; +} + +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout) +{ + if (start_work(core, f, a, b, c)) + return -1; + return wait_work(core, retval, timeout); +} +#endif /* CONFIG_SMP == 1 */ diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index cca2be1..39f2fa2 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -5,9 +5,15 @@ struct device; struct bus; #include <arch/cpu.h> -void cpu_initialize(void); +void cpu_initialize(struct cpu_info *info); void initialize_cpus(struct bus *cpu_bus); -void secondary_cpu_init(void); +void secondary_cpu_init(u32 unused); +int start_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c); +int wait_work(unsigned int core, u32 *retval, unsigned int maxwait); +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout); +void cpu_work(struct cpu_info *info); + #if !CONFIG_WAIT_BEFORE_CPUS_INIT #define cpus_ready_for_init() do {} while(0) [View Less]

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Patch set updated for coreboot: 543e247 drivers/i2c: Add description in Kconfig file
by Vikram Narayanan 07 Apr '12

07 Apr '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/879 -gerrit commit 543e24732a2742716b0d2c6c4984718afdcbd002 Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 7 16:47:06 2012 +0530 drivers/i2c: Add description in Kconfig file Change-Id: Ibf44a0e1c44bae11febf7cfc503582e4a1033c02 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/drivers/i2c/adm1026/… [View More]Kconfig | 3 +++ src/drivers/i2c/adm1027/Kconfig | 3 +++ src/drivers/i2c/adt7463/Kconfig | 3 +++ src/drivers/i2c/i2cmux/Kconfig | 3 +++ src/drivers/i2c/i2cmux2/Kconfig | 3 +++ src/drivers/i2c/lm63/Kconfig | 3 +++ src/drivers/i2c/w83795/Kconfig | 3 +++ 7 files changed, 21 insertions(+), 0 deletions(-) diff --git a/src/drivers/i2c/adm1026/Kconfig b/src/drivers/i2c/adm1026/Kconfig index 8168b29..84a1c73 100644 --- a/src/drivers/i2c/adm1026/Kconfig +++ b/src/drivers/i2c/adm1026/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_ADM1026 bool + default n + help + Support for ADM1026-Thermal System Management Fan Controller IC diff --git a/src/drivers/i2c/adm1027/Kconfig b/src/drivers/i2c/adm1027/Kconfig index c135726..19aa338 100644 --- a/src/drivers/i2c/adm1027/Kconfig +++ b/src/drivers/i2c/adm1027/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_ADM1027 bool + default n + help + Support for ADM1027-Remote Thermal Controller and Voltage Monitor diff --git a/src/drivers/i2c/adt7463/Kconfig b/src/drivers/i2c/adt7463/Kconfig index b942341..c3990bf 100644 --- a/src/drivers/i2c/adt7463/Kconfig +++ b/src/drivers/i2c/adt7463/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_ADT7463 bool + default n + help + Support for ADT7463-Remote Thermal Controller and Voltage Monitor diff --git a/src/drivers/i2c/i2cmux/Kconfig b/src/drivers/i2c/i2cmux/Kconfig index 57bb278..ea43d91 100644 --- a/src/drivers/i2c/i2cmux/Kconfig +++ b/src/drivers/i2c/i2cmux/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_I2CMUX bool + default n + help + Support for PCA9556 SMBus IC diff --git a/src/drivers/i2c/i2cmux2/Kconfig b/src/drivers/i2c/i2cmux2/Kconfig index 0213e55..5a7adef 100644 --- a/src/drivers/i2c/i2cmux2/Kconfig +++ b/src/drivers/i2c/i2cmux2/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_I2CMUX2 bool + default n + help + Support for PCA9554 SMBus IC diff --git a/src/drivers/i2c/lm63/Kconfig b/src/drivers/i2c/lm63/Kconfig index 120ee0d..2211649 100644 --- a/src/drivers/i2c/lm63/Kconfig +++ b/src/drivers/i2c/lm63/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_LM63 bool + default n + help + Support for National Semiconductor LM63 diff --git a/src/drivers/i2c/w83795/Kconfig b/src/drivers/i2c/w83795/Kconfig index 80856e2..5232121 100644 --- a/src/drivers/i2c/w83795/Kconfig +++ b/src/drivers/i2c/w83795/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_W83795 bool + default n + help + Support for Nuvoton W83795G [View Less]

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Patch merged into coreboot/master: 65aff4f hexdump: fix compiler warning
by gerrit＠coreboot.org 07 Apr '12

07 Apr '12

the following patch was just integrated into master: commit 65aff4f8d15fec36023e22a25a1f48b331a9353e Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 7 16:28:26 2012 +0530 hexdump: fix compiler warning Fixed "warning: format not a string literal and no format arguments" Change-Id: If752a37f268c90f782c6e831e5477ea804e48026 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Apr 7 13:17:23 2012, … [View More]

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New patch to review for coreboot: ae30789 drivers/i2c: Add description in Kconfig file
by Vikram Narayanan 07 Apr '12

07 Apr '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/879 -gerrit commit ae307898e74c38a5a065b0a1983d69084d00ccfd Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 7 16:47:06 2012 +0530 drivers/i2c: Add description in Kconfig file Change-Id: Ibf44a0e1c44bae11febf7cfc503582e4a1033c02 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/drivers/i2c/adm1026/… [View More]Kconfig | 5 ++++- src/drivers/i2c/adm1027/Kconfig | 5 ++++- src/drivers/i2c/adt7463/Kconfig | 5 ++++- src/drivers/i2c/i2cmux/Kconfig | 5 ++++- src/drivers/i2c/i2cmux2/Kconfig | 5 ++++- src/drivers/i2c/lm63/Kconfig | 5 ++++- src/drivers/i2c/w83795/Kconfig | 5 ++++- 7 files changed, 28 insertions(+), 7 deletions(-) diff --git a/src/drivers/i2c/adm1026/Kconfig b/src/drivers/i2c/adm1026/Kconfig index 8168b29..141766c 100644 --- a/src/drivers/i2c/adm1026/Kconfig +++ b/src/drivers/i2c/adm1026/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_ADM1026 - bool + bool "ADM1026" + default n + help + Support for ADM1026-Thermal System Management Fan Controller IC diff --git a/src/drivers/i2c/adm1027/Kconfig b/src/drivers/i2c/adm1027/Kconfig index c135726..f77fdd8 100644 --- a/src/drivers/i2c/adm1027/Kconfig +++ b/src/drivers/i2c/adm1027/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_ADM1027 - bool + bool "ADM1027" + default n + help + Support for ADM1027-Remote Thermal Controller and Voltage Monitor diff --git a/src/drivers/i2c/adt7463/Kconfig b/src/drivers/i2c/adt7463/Kconfig index b942341..70d6a25 100644 --- a/src/drivers/i2c/adt7463/Kconfig +++ b/src/drivers/i2c/adt7463/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_ADT7463 - bool + bool "ADT7463" + default n + help + Support for ADT7463-Remote Thermal Controller and Voltage Monitor diff --git a/src/drivers/i2c/i2cmux/Kconfig b/src/drivers/i2c/i2cmux/Kconfig index 57bb278..4a08c77 100644 --- a/src/drivers/i2c/i2cmux/Kconfig +++ b/src/drivers/i2c/i2cmux/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_I2CMUX - bool + bool "PCA9556 SMBus mux" + default n + help + Support for PCA9556 SMBus IC diff --git a/src/drivers/i2c/i2cmux2/Kconfig b/src/drivers/i2c/i2cmux2/Kconfig index 0213e55..a37a80e 100644 --- a/src/drivers/i2c/i2cmux2/Kconfig +++ b/src/drivers/i2c/i2cmux2/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_I2CMUX2 - bool + bool "PCA9554 SMBus mux" + default n + help + Support for PCA9554 SMBus IC diff --git a/src/drivers/i2c/lm63/Kconfig b/src/drivers/i2c/lm63/Kconfig index 120ee0d..433fe37 100644 --- a/src/drivers/i2c/lm63/Kconfig +++ b/src/drivers/i2c/lm63/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_LM63 - bool + bool "LM63" + default n + help + Support for National Semiconductor LM63 diff --git a/src/drivers/i2c/w83795/Kconfig b/src/drivers/i2c/w83795/Kconfig index 80856e2..bdaf2b6 100644 --- a/src/drivers/i2c/w83795/Kconfig +++ b/src/drivers/i2c/w83795/Kconfig @@ -1,2 +1,5 @@ config DRIVERS_I2C_W83795 - bool + bool "W83795" + default n + help + Support for Nuvoton W83795G [View Less]

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New patch to review for coreboot: 65aff4f hexdump: fix compiler warning
by Vikram Narayanan 07 Apr '12

07 Apr '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/878 -gerrit commit 65aff4f8d15fec36023e22a25a1f48b331a9353e Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 7 16:28:26 2012 +0530 hexdump: fix compiler warning Fixed "warning: format not a string literal and no format arguments" Change-Id: If752a37f268c90f782c6e831e5477ea804e48026 Signed-off-by: Vikram Narayanan &… [View More]lt;vikram186(a)gmail.com> --- util/nvramtool/hexdump.c | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/util/nvramtool/hexdump.c b/util/nvramtool/hexdump.c index 4d13963..e6d9faf 100644 --- a/util/nvramtool/hexdump.c +++ b/util/nvramtool/hexdump.c @@ -83,10 +83,10 @@ void hexdump(const void *mem, int bytes, uint64_t addrprint_start, bytes_left >= format->bytes_per_line; bytes_left -= format->bytes_per_line) { /* print start address for current line */ - fprintf(outfile, format->indent); + fprintf(outfile, "%s", format->indent); addrprint(outfile, addrprint_start + index, format->addrprint_width); - fprintf(outfile, format->sep1); + fprintf(outfile, "%s", format->sep1); /* display the bytes in hex */ for (i = 0;;) { @@ -95,11 +95,11 @@ void hexdump(const void *mem, int bytes, uint64_t addrprint_start, if (++i >= format->bytes_per_line) break; - fprintf(outfile, format->sep2); + fprintf(outfile, "%s", format->sep2); } index -= format->bytes_per_line; - fprintf(outfile, format->sep3); + fprintf(outfile, "%s", format->sep3); /* display the bytes as characters */ for (i = 0; i < format->bytes_per_line; i++, index++) @@ -112,14 +112,14 @@ void hexdump(const void *mem, int bytes, uint64_t addrprint_start, return; /* print start address for last line */ - fprintf(outfile, format->indent); + fprintf(outfile, "%s", format->indent); addrprint(outfile, addrprint_start + index, format->addrprint_width); - fprintf(outfile, format->sep1); + fprintf(outfile, "%s", format->sep1); /* display bytes for last line in hex */ for (i = 0; i < bytes_left; i++) { fprintf(outfile, "%02x", p[index++]); - fprintf(outfile, format->sep2); + fprintf(outfile, "%s", format->sep2); } index -= bytes_left; @@ -131,10 +131,10 @@ void hexdump(const void *mem, int bytes, uint64_t addrprint_start, if (++i >= format->bytes_per_line) break; - fprintf(outfile, format->sep2); + fprintf(outfile, "%s", format->sep2); } - fprintf(outfile, format->sep3); + fprintf(outfile, "%s", format->sep3); /* display bytes for last line as characters */ for (i = 0; i < bytes_left; i++) [View Less]

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Patch set updated for coreboot: 1c810f1 Fixes and Sandybridge support for lapic cpu init
by Stefan Reinauer 06 Apr '12

06 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/871 -gerrit commit 1c810f17a1a3e9c5433e9eee4a18175d64698be2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:17:11 2012 -0700 Fixes and Sandybridge support for lapic cpu init - preprocessor macros should not use defined(CONFIG_*) but just CONFIG_* - drop AMD CPU model 14XXX config variable use. Those do … [View More]not exist. - skip some delays on Sandybridge systems - Count how long we're waiting for each AP to stop - Skip speedstep specific CPU entries Change-Id: I13db384ba4e28acbe7f0f8c9cd169954b39f167d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/lapic/lapic_cpu_init.c | 15 +++++++++++---- src/include/cpu/intel/speedstep.h | 3 +++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index ed9940c..2ac9093 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -14,6 +14,7 @@ #include <smp/atomic.h> #include <smp/spinlock.h> #include <cpu/cpu.h> +#include <cpu/intel/speedstep.h> #if CONFIG_SMP == 1 /* This is a lot more paranoid now, since Linux can NOT handle @@ -108,7 +109,7 @@ static int lapic_start_cpu(unsigned long apicid) } return 0; } -#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) +#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX mdelay(10); #endif @@ -136,7 +137,7 @@ static int lapic_start_cpu(unsigned long apicid) start_eip = get_valid_start_eip((unsigned long)_secondary_start); -#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) +#if !CONFIG_CPU_AMD_MODEL_10XXX num_starts = 2; #else num_starts = 1; @@ -269,7 +270,7 @@ int start_cpu(device_t cpu) break; } udelay(10); - } + } } secondary_stack = 0; spin_unlock(&start_cpu_lock); @@ -446,6 +447,8 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) { device_t cpu; int old_active_count, active_count; + long loopcount = 0; + /* Now loop until the other cpus have finished initializing */ old_active_count = 1; active_count = atomic_read(&active_cpus); @@ -456,17 +459,21 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) } udelay(10); active_count = atomic_read(&active_cpus); + loopcount++; } for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { if (cpu->path.type != DEVICE_PATH_APIC) { continue; } + if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) { + continue; + } if (!cpu->initialized) { printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n", cpu->path.apic.apic_id); } } - printk(BIOS_DEBUG, "All AP CPUs stopped\n"); + printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } #else /* CONFIG_SMP */ diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 0fa5244..00a5b9b 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -19,6 +19,9 @@ * MA 02110-1301 USA */ +/* Magic value used to locate speedstep configuration in the device tree */ +#define SPEEDSTEP_APIC_MAGIC 0xACAC + /* MWAIT coordination I/O base address. This must match * the \_PR_.CPU0 PM base address. */ [View Less]

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Patch merged into coreboot/master: e35b393 Remove Dell s1850
by gerrit＠coreboot.org 06 Apr '12

06 Apr '12

the following patch was just integrated into master: commit e35b393caad3c74efc8c06c1d13a9608cd316618 Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 20:25:38 2012 -0700 Remove Dell s1850 It's almost 10 years old. It never worked. It's a soldered in FLASH, so mistakes are fatal. It's got no redeeming features. Remove the dell directory. In 12 years of trying to work with Dell we have not had much interest. It's misleading to have it there. … [View More]

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Patch set updated for coreboot: e35b393 Remove Dell s1850
by Ronald G. Minnich 06 Apr '12

06 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/876 -gerrit commit e35b393caad3c74efc8c06c1d13a9608cd316618 Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 20:25:38 2012 -0700 Remove Dell s1850 It's almost 10 years old. It never worked. It's a soldered in FLASH, so mistakes are fatal. It's got no redeeming features. Remove the dell directory. In 12 years of trying … [View More]to work with Dell we have not had much interest. It's misleading to have it there. Change-Id: I83ff009bd7a6d5289229ca39608789ae5c33710b --- src/mainboard/Kconfig | 3 - src/mainboard/dell/Kconfig | 17 -- src/mainboard/dell/s1850/Kconfig | 44 ---- src/mainboard/dell/s1850/Makefile.inc | 1 - src/mainboard/dell/s1850/chip.h | 3 - src/mainboard/dell/s1850/cmos.layout | 80 -------- src/mainboard/dell/s1850/debug.c | 289 --------------------------- src/mainboard/dell/s1850/devicetree.cb | 72 ------- src/mainboard/dell/s1850/irq_tables.c | 53 ----- src/mainboard/dell/s1850/mainboard.c | 7 - src/mainboard/dell/s1850/mptable.c | 160 --------------- src/mainboard/dell/s1850/reset.c | 16 -- src/mainboard/dell/s1850/romstage.c | 324 ------------------------------- src/mainboard/dell/s1850/s1850_fixups.c | 60 ------ src/mainboard/dell/s1850/watchdog.c | 57 ------ 15 files changed, 0 insertions(+), 1186 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 051ae45..64ae1d6 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -44,8 +44,6 @@ config VENDOR_BROADCOM bool "Broadcom" config VENDOR_COMPAQ bool "Compaq" -config VENDOR_DELL - bool "Dell" config VENDOR_DIGITALLOGIC bool "DIGITAL-LOGIC" config VENDOR_EAGLELION @@ -149,7 +147,6 @@ source "src/mainboard/bifferos/Kconfig" source "src/mainboard/biostar/Kconfig" source "src/mainboard/broadcom/Kconfig" source "src/mainboard/compaq/Kconfig" -source "src/mainboard/dell/Kconfig" source "src/mainboard/digitallogic/Kconfig" source "src/mainboard/eaglelion/Kconfig" source "src/mainboard/ecs/Kconfig" diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig deleted file mode 100644 index fb665c4..0000000 --- a/src/mainboard/dell/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -if VENDOR_DELL - -choice - prompt "Mainboard model" - -config BOARD_DELL_S1850 - bool "PowerEdge 1850" - -endchoice - -source "src/mainboard/dell/s1850/Kconfig" - -config MAINBOARD_VENDOR - string - default "Dell" - -endif # VENDOR_DELL diff --git a/src/mainboard/dell/s1850/Kconfig b/src/mainboard/dell/s1850/Kconfig deleted file mode 100644 index cd4a6a9..0000000 --- a/src/mainboard/dell/s1850/Kconfig +++ /dev/null @@ -1,44 +0,0 @@ -if BOARD_DELL_S1850 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select ARCH_X86 - select CPU_INTEL_SOCKET_MPGA604 - select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801EX - select SOUTHBRIDGE_INTEL_PXHD - select SUPERIO_NSC_PC8374 - select ROMCC - select HAVE_OPTION_TABLE - select BOARD_HAS_HARD_RESET - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select USE_WATCHDOG_ON_BOOT - select BOARD_ROMSIZE_KB_1024 - select UDELAY_TSC - -config MAINBOARD_DIR - string - default dell/s1850 - -config MAINBOARD_PART_NUMBER - string - default "PowerEdge 1850" - -config MAX_CPUS - int - default 4 - -config MAX_PHYSICAL_CPUS - int - default 1 - -config IRQ_SLOT_COUNT - int - default 9 - -config DIMM_MAP_LOGICAL - hex - default 0x2841 - -endif # BOARD_DELL_S1850 diff --git a/src/mainboard/dell/s1850/Makefile.inc b/src/mainboard/dell/s1850/Makefile.inc deleted file mode 100644 index 0f285cd..0000000 --- a/src/mainboard/dell/s1850/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=p4 -O2 diff --git a/src/mainboard/dell/s1850/chip.h b/src/mainboard/dell/s1850/chip.h deleted file mode 100644 index d138e51..0000000 --- a/src/mainboard/dell/s1850/chip.h +++ /dev/null @@ -1,3 +0,0 @@ -extern struct chip_operations mainboard_ops; - -struct mainboard_config {}; diff --git a/src/mainboard/dell/s1850/cmos.layout b/src/mainboard/dell/s1850/cmos.layout deleted file mode 100644 index 81f1a69..0000000 --- a/src/mainboard/dell/s1850/cmos.layout +++ /dev/null @@ -1,80 +0,0 @@ -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 2 hyper_threading -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM - -checksums - -checksum 392 983 984 - - diff --git a/src/mainboard/dell/s1850/debug.c b/src/mainboard/dell/s1850/debug.c deleted file mode 100644 index 7904c06..0000000 --- a/src/mainboard/dell/s1850/debug.c +++ /dev/null @@ -1,289 +0,0 @@ -#include <spd.h> - -static void print_reg(unsigned char index) -{ - unsigned char data; - - outb(index, 0x2e); - data = inb(0x2f); - print_debug("0x"); - print_debug_hex8(index); - print_debug(": 0x"); - print_debug_hex8(data); - print_debug("\n"); - return; -} - -static void xbus_en(void) -{ - /* select the XBUS function in the SIO */ - outb(0x07, 0x2e); - outb(0x0f, 0x2f); - outb(0x30, 0x2e); - outb(0x01, 0x2f); - return; -} - -static void setup_func(unsigned char func) -{ - /* select the function in the SIO */ - outb(0x07, 0x2e); - outb(func, 0x2f); - /* print out the regs */ - print_reg(0x30); - print_reg(0x60); - print_reg(0x61); - print_reg(0x62); - print_reg(0x63); - print_reg(0x70); - print_reg(0x71); - print_reg(0x74); - print_reg(0x75); - return; -} - -static void siodump(void) -{ - int i; - unsigned char data; - - print_debug("\n*** SERVER I/O REGISTERS ***\n"); - for (i=0x10; i<=0x2d; i++) { - print_reg((unsigned char)i); - } -#if 0 - print_debug("\n*** XBUS REGISTERS ***\n"); - setup_func(0x0f); - for (i=0xf0; i<=0xff; i++) { - print_reg((unsigned char)i); - } - - print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); - setup_func(0x03); - print_reg(0xf0); - - print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); - setup_func(0x02); - print_reg(0xf0); - -#endif - print_debug("\n*** GPIO REGISTERS ***\n"); - setup_func(0x07); - for (i=0xf0; i<=0xf8; i++) { - print_reg((unsigned char)i); - } - print_debug("\n*** GPIO VALUES ***\n"); - data = inb(0x68a); - print_debug("\nGPDO 4: 0x"); - print_debug_hex8(data); - data = inb(0x68b); - print_debug("\nGPDI 4: 0x"); - print_debug_hex8(data); - print_debug("\n"); - -#if 0 - - print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); - setup_func(0x0a); - print_reg(0xf0); - - print_debug("\n*** FAN CONTROL REGISTERS ***\n"); - setup_func(0x09); - print_reg(0xf0); - print_reg(0xf1); - - print_debug("\n*** RTC REGISTERS ***\n"); - setup_func(0x10); - print_reg(0xf0); - print_reg(0xf1); - print_reg(0xf3); - print_reg(0xf6); - print_reg(0xf7); - print_reg(0xfe); - print_reg(0xff); - - print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); - setup_func(0x14); - print_reg(0xf0); -#endif - return; -} - -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} - -static void print_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - print_debug("\n"); - } -} - -static void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - print_debug("\n"); - - for(i = 0; i <= 255; i++) { - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); - print_debug_char(' '); - print_debug_hex8(val); - if ((i & 0x0f) == 0x0f) { - print_debug("\n"); - } - } -} - -static void dump_bar14(unsigned dev) -{ - int i; - unsigned long bar; - - print_debug("BAR 14 Dump\n"); - - bar = pci_read_config32(dev, 0x14); - for(i = 0; i <= 0x300; i+=4) { -#if 0 - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); -#endif - if((i%4)==0) { - print_debug("\n"); - print_debug_hex16(i); - print_debug_char(' '); - } - print_debug_hex32(read32(bar + i)); - print_debug_char(' '); - } - print_debug("\n"); -} - -static void dump_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - -void dump_spd_registers(void) -{ - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); - print_debug_hex8(device); - - for(i = 0; (i < 256) ; i++) { - unsigned char byte; - if ((i % 16) == 0) { - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device: "); - print_debug_hex8(-status); - print_debug("\n"); - break; - } - print_debug_hex8(status); - print_debug_char(' '); - } - device++; - print_debug("\n"); - } -} - -void show_dram_slots(void) -{ - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); - print_debug_hex8(device); - - status = smbus_read_byte(device, 0); - if (status < 0) { - print_debug("bad device: "); - } else { - print_debug("present: "); - } - print_debug_hex8(status); - print_debug("\n"); - device++; - print_debug("\n"); - } -} - -void dump_ipmi_registers(void) -{ - unsigned device; - device = 0x42; - while(device <= 0x42) { - int status = 0; - int i; - print_debug("\n"); - print_debug("ipmi "); - print_debug_hex8(device); - - for(i = 0; (i < 8) ; i++) { - unsigned char byte; - status = smbus_read_byte(device, 2); - if (status < 0) { - print_debug("bad device: "); - print_debug_hex8(-status); - print_debug("\n"); - break; - } - print_debug_hex8(status); - print_debug_char(' '); - } - device++; - print_debug("\n"); - } -} diff --git a/src/mainboard/dell/s1850/devicetree.cb b/src/mainboard/dell/s1850/devicetree.cb deleted file mode 100644 index c56fd37..0000000 --- a/src/mainboard/dell/s1850/devicetree.cb +++ /dev/null @@ -1,72 +0,0 @@ -chip northbridge/intel/e7520 # mch - device pci_domain 0 on - subsystemid 0x15d9 0x5580 inherit - chip southbridge/intel/i82801ex # i82801er - # USB ports - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.7 on end - - # -> Bridge - device pci 1e.0 on end - - # -> ISA - device pci 1f.0 on - chip superio/nsc/pc8374 - device pnp 2e.0 off end - device pnp 2e.1 off end - device pnp 2e.2 off end - device pnp 2e.3 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.6 off end - device pnp 2e.7 off end - device pnp 2e.8 off end - end - end - # -> IDE - device pci 1f.1 on end - # -> SATA - device pci 1f.2 on end - device pci 1f.3 on end - - register "pirq_a_d" = "0x8a07030b" - register "pirq_e_h" = "0x85808080" - end - device pci 00.0 on end - device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # pxhd1 - # Bus bridges and ioapics usually bus 1 - device pci 0.0 on - # On board gig e1000 - chip drivers/generic/generic - device pci 03.0 on end - device pci 03.1 on end - end - end - device pci 0.1 on end - device pci 0.2 on end - device pci 0.3 on end - end - end - device pci 04.0 on end - device pci 06.0 on end - end - device lapic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu 0 - device lapic 0 on end - end - chip cpu/intel/socket_mPGA604 # cpu 1 - device lapic 6 on end - end - end - register "intrline" = "0x00070100" -end - diff --git a/src/mainboard/dell/s1850/irq_tables.c b/src/mainboard/dell/s1850/irq_tables.c deleted file mode 100644 index e6073c7..0000000 --- a/src/mainboard/dell/s1850/irq_tables.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) by the coreboot pirq tool. - * This file was programatically generated. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/pirq_routing.h> - -const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x11 << 3) | 0x0, /* Interrupt router device */ - 0xc20, /* IRQs devoted exclusively to PCI usage */ - 0x1106, /* Vendor */ - 0x596, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x66, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0}, - {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x4, 0x0}, - {0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr); -} diff --git a/src/mainboard/dell/s1850/mainboard.c b/src/mainboard/dell/s1850/mainboard.c deleted file mode 100644 index 3d22f2d..0000000 --- a/src/mainboard/dell/s1850/mainboard.c +++ /dev/null @@ -1,7 +0,0 @@ -#include <device/device.h> -#include "chip.h" - -struct chip_operations mainboard_ops = { - CHIP_NAME("Dell S1850 Mainboard") -}; - diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c deleted file mode 100644 index 0c7562c..0000000 --- a/src/mainboard/dell/s1850/mptable.c +++ /dev/null @@ -1,160 +0,0 @@ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - unsigned char bus_pxhd_1; - unsigned char bus_pxhd_2; - unsigned char bus_pxhd_3; - unsigned char bus_pxhd_4; - unsigned char bus_ich5r_1; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - { - device_t dev; - - /* ich5r */ - dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); - if (dev) { - bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); - bus_ich5r_1 = 7; - } - /* pxhd-1 */ - dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); - if (dev) { - bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n"); - bus_pxhd_1 = 2; - } - /* pxhd-2 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); - if (dev) { - bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n"); - bus_pxhd_2 = 3; - } - - /* pxhd-3 */ - dev = dev_find_slot(0, PCI_DEVFN(0x4,0)); - if (dev) { - bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n"); - bus_pxhd_3 = 5; - } - /* pxhd-4 */ - dev = dev_find_slot(0, PCI_DEVFN(0x06,0)); - if (dev) { - bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n"); - bus_pxhd_4 = 6; - } - - } - - mptable_write_buses(mc, NULL, &bus_isa); - - /* IOAPIC handling */ - - smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - { - struct resource *res; - device_t dev; - /* pxhd apic 3 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x03, 0x20, res->base); - } - } - else { - printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n"); - } - /* pxhd apic 4 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x04, 0x20, res->base); - } - } - else { - printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); - } - } - - mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x74, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x76, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x77, 0x02, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x75, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x74, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x7c, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x7d, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x08, 0x03, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x0c, 0x03, 0x06); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x0d, 0x03, 0x07); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_2, 0x08, 0x04, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_ich5r_1, 0x04, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_4, 0x00, 0x02, 0x10); -#if 0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - (bus_isa - 1), 0x04, 0x02, 0x10); -#endif - /* Standard local interrupt assignments */ -#if 0 - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - bus_isa, 0x00, MP_APIC_ALL, 0x00); -#endif - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - bus_isa, 0x00, MP_APIC_ALL, 0x01); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} - diff --git a/src/mainboard/dell/s1850/reset.c b/src/mainboard/dell/s1850/reset.c deleted file mode 100644 index 745f187..0000000 --- a/src/mainboard/dell/s1850/reset.c +++ /dev/null @@ -1,16 +0,0 @@ -#include <arch/io.h> -#include <reset.h> -#if defined (__PRE_RAM__) -#include <arch/romcc_io.h> -#endif - -void soft_reset(void) -{ - outb(0x04, 0xcf9); -} - -void hard_reset(void) -{ - outb(0x02, 0xcf9); - outb(0x06, 0xcf9); -} diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c deleted file mode 100644 index e636986..0000000 --- a/src/mainboard/dell/s1850/romstage.c +++ /dev/null @@ -1,324 +0,0 @@ -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include <stdlib.h> -#include <console/console.h> -#include "southbridge/intel/i82801ex/early_smbus.c" -#include "northbridge/intel/e7520/raminit.h" -#include "superio/nsc/pc8374/early_init.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "debug.c" -#include "watchdog.c" -// Remove comment if resets in this file are actually used. -// #include "reset.c" -#include "s1850_fixups.c" -#include "northbridge/intel/e7520/memory_initialized.c" -#include "cpu/x86/bist.h" -#include <spd.h> - -#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1) - -#define DEVPRES_CONFIG ( \ - DEVPRES_D0F0 | \ - DEVPRES_D1F0 | \ - DEVPRES_D2F0 | \ - DEVPRES_D3F0 | \ - DEVPRES_D4F0 | \ - DEVPRES_D6F0 | \ - 0 ) -#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/e7520/raminit.c" -#include "lib/generic_sdram.c" - -/* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere - */ - -#define nftransport 0xc - -#define OBF 0 -#define IBF 1 - -#define ipmidata 0xca0 -#define ipmicsr 0xca4 - -static inline void ibfzero(void) -{ - while(inb(ipmicsr) & (1<<IBF)) - ; -} -static inline void clearobf(void) -{ - (void) inb(ipmidata); -} - -static inline void waitobf(void) -{ - while((inb(ipmicsr) & (1<<OBF)) == 0) - ; -} - -/* quite possibly the stupidest interface ever designed. */ -static inline void first_cmd_byte(unsigned char byte) -{ - ibfzero(); - clearobf(); - outb(0x61, ipmicsr); - ibfzero(); - clearobf(); - outb(byte, ipmidata); -} - -static inline void next_cmd_byte(unsigned char byte) -{ - - ibfzero(); - clearobf(); - outb(byte, ipmidata); -} - -static inline void last_cmd_byte(unsigned char byte) -{ - outb(0x62, ipmicsr); - - ibfzero(); - clearobf(); - outb(byte, ipmidata); -} - -static inline void read_response_byte(void) -{ - int val = -1; - if ((inb(ipmicsr)>>6) != 1) - return; - - ibfzero(); - waitobf(); - val = inb(ipmidata); - outb(0x68, ipmidata); - - /* see if it is done */ - if ((inb(ipmicsr)>>6) != 1){ - /* wait for the dummy read. Which describes this protocol */ - waitobf(); - (void)inb(ipmidata); - } -} - -static inline void ipmidelay(void) -{ - int i; - for(i = 0; i < 1000; i++) { - inb(0x80); - } -} - -static inline void bmc_foad(void) -{ - unsigned char c; - /* be safe; make sure it is really ready */ - while ((inb(ipmicsr)>>6)) { - outb(0x60, ipmicsr); - inb(ipmidata); - } - first_cmd_byte(nftransport << 2); - ipmidelay(); - next_cmd_byte(0x12); - ipmidelay(); - next_cmd_byte(2); - ipmidelay(); - last_cmd_byte(3); - ipmidelay(); -} - -/* end IPMI garbage */ - -#include "arch/x86/lib/stages.c" - -static void main(unsigned long bist) -{ - u8 b; - u16 w; - u32 l; - int do_reset; - - static const struct mem_controller mch[] = { - { - .node_id = 0, - /* the wiring on this part is really messed up */ - /* this is my best guess so far */ - .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, }, - .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, }, - } - }; - - /* superio setup */ - /* observed from serialice */ - static const u8 earlyinit[] = { - 0x21, 0x11, 0x11, - 0x22, 1, 1, - 0x23, 05, 05, - 0x24, 0x81, 0x81, - 0x26, 0, 0, - 0, - }; - - /* using SerialICE, we've seen this basic reset sequence on the dell. - * we don't understand it as it uses undocumented registers, but - * we're going to clone it. - */ - /* enable a hidden device. */ - b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - b |= 0x8; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - - /* read-write lock in CMOS on LPC bridge on ICH5 */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4); - - /* operate on undocumented device */ - l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4); - l |= 0x1000; - pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l); - - l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c); - l |= 0x8000; - pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l); - - /* disable undocumented device */ - b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - b &= ~0x8; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - - /* set up LPC bridge bits, some of which reply on undocumented - * registers - */ - - b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8); - b |= 4; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b); - - b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4); - b |= 2; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b); - - /* ACPI base address */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800); - - /* Enable specific ACPI features */ - b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44); - b |= 0x10; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b); - - /* ACPI control */ - w = inw(0x868); - outw(w|0x800, 0x868); - w = inw(0x866); - outw(w|2, 0x866); - -#if 0 - /*seriaice shows - dell does this so leave it here so I don't forget - */ - /* SMBUS */ - pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0); - - /* unknown */ - b = inb(0x8c2); - outb(0xdf, 0x8c2); -#endif - - /* another device enable? */ - b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - b |= 2; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - - /* ?? */ - l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0); - do_reset = l & 0x8000000; - l |= 0x8000000; - pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l); - - if (! do_reset) { - outb(2, 0xcf9); - outb(6, 0xcf9); - } - if (bist == 0) { - /* Skip this if there was a built in self test failure */ - early_mtrr_init(); - if (memory_initialized()) - skip_romstage(); - } - /* Setup the console */ - mainboard_set_ich5(); - //bmc_foad(); - pc8374_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* stuff we seem to need */ - pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0); - - /* GPIOs */ - pc8374_enable_dev(PNP_DEV(0x2e, PC8374_GPIO), 0xc20); - - /* keep this in mind. - SerialICE-hlp: outb 002e <= 23 - SerialICE-hlp: inb 002f => 05 - SerialICE-hlp: outb 002f <= 05 - SerialICE-hlp: outb 002e <= 24 - SerialICE-hlp: inb 002f => c1 - SerialICE-hlp: outb 002f <= c1 - */ - - /* Halt if there was a built in self test failure */ -// report_bist_failure(bist); - - /* MOVE ME TO A BETTER LOCATION !!! */ - /* config LPC decode for flash memory access */ - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) { - die("Missing ich5?"); - } - pci_write_config32(dev, 0xe8, 0x00000000); - pci_write_config8(dev, 0xf0, 0x00); - -#if 0 - display_cpuid_update_microcode(); -#endif -#if 1 - print_pci_devices(); -#endif -#if 1 - enable_smbus(); -#endif -#if 0 -// dump_spd_registers(&cpu[0]); - int i; - for(i = 0; i < 1; i++) - dump_spd_registers(); -#endif -#if 1 - show_dram_slots(); -#endif - disable_watchdogs(); -// dump_ipmi_registers(); - mainboard_set_e7520_leds(); - - sdram_initialize(ARRAY_SIZE(mch), mch); -#if 0 - dump_pci_devices(); -#endif -#if 1 - dump_pci_device(PCI_DEV(0, 0x00, 0)); -// dump_bar14(PCI_DEV(0, 0x00, 0)); -#endif -} diff --git a/src/mainboard/dell/s1850/s1850_fixups.c b/src/mainboard/dell/s1850/s1850_fixups.c deleted file mode 100644 index 7ef9ce1..0000000 --- a/src/mainboard/dell/s1850/s1850_fixups.c +++ /dev/null @@ -1,60 +0,0 @@ -#include <arch/romcc_io.h> - -static void mch_reset(void) -{ - return; -} - - - -static void mainboard_set_e7520_pll(unsigned bits) -{ - return; -} - - -static void mainboard_set_e7520_leds(void) -{ - return; -} - -static void mainboard_set_ich5(void) -{ - /* coma is 0x3f8 , comb is 0x2f8*/ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe0, 0x10); - /* enable decoding of various devices */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xe6, 0x140f); - /* 1M flash */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe3, 0xc0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xf0, 0x0); - /* disable certain devices -- see data sheet -- this is from - * dell settings via lspci - * Note that they leave SMBUS disabled -- 8f6f. - * we leave it enabled and visible in config space -- 8f66 - */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xf2, 0x8f66); - /* GPIOs -- needed, possibly, for SPD */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x58, 0x881); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x5c, 0x10); - - /* now the fun begins ... enable the GPIOs as done on factory */ - /* factory config from IO ports - * It has a few more things enabled than default! - */ - outl(0x1ae0f183, 0x880); - outl(0x1b00ffff, 0x884); - outl(0x131f0000, 0x88c); - outl(0x00000000, 0x894); - outl(0x00040000, 0x898); - outl(0x00000000, 0x8a4); - outl(0x00000000, 0x8a8); - outl(0x000031c0, 0x8ac); - outl(0x00000007, 0x8b0); - outl(0x00000304, 0x8b4); - outl(0x00030303, 0x8b8); - -} - - - - diff --git a/src/mainboard/dell/s1850/watchdog.c b/src/mainboard/dell/s1850/watchdog.c deleted file mode 100644 index 43f4029..0000000 --- a/src/mainboard/dell/s1850/watchdog.c +++ /dev/null @@ -1,57 +0,0 @@ -#include <device/pnp_def.h> - -#define NSC_WD_DEV PNP_DEV(0x2e, 0xa) -#define NSC_WDBASE 0x600 -#define ICH5_WDBASE 0x400 -#define ICH5_GPIOBASE 0x500 - -static void disable_sio_watchdog(device_t dev) -{ -#if 0 - /* FIXME move me somewhere more appropriate */ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); - pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE); - /* disable the sio watchdog */ - outb(0, NSC_WDBASE + 0); - pnp_set_enable(dev, 0); -#endif -} - -static void disable_ich5_watchdog(void) -{ - /* FIXME move me somewhere more appropriate */ - device_t dev; - unsigned long value, base; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) { - die("Missing ich5?"); - } - /* Enable I/O space */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - - /* Set and enable acpibase */ - pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); - pci_write_config8(dev, 0x44, 0x10); - base = ICH5_WDBASE + 0x60; - - /* Set bit 11 in TCO1_CNT */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - - /* Clear TCO timeout status */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); -} - - -static void disable_watchdogs(void) -{ -// disable_sio_watchdog(NSC_WD_DEV); - disable_ich5_watchdog(); - print_debug("Watchdogs disabled\n"); -} - [View Less]

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Re: [coreboot] [RFC] Re-thinking the stages
by ron minnich 06 Apr '12

06 Apr '12

On Fri, Apr 6, 2012 at 11:12 AM, Marc Jones <marcj303(a)gmail.com> wrote: >> 3. Microcode updates >> >> The "tiny" bootblock doesn't seem like the correct place for microcode >> updates. >> > > Does microcode have to be this early? Before CAR? Yes. Some history. We started out doing microcode updates in linux. Then it moved to the end of the ram stage. Then the start. Then it turned out it had to happen before CAR. So be careful! Sure, it may not … [View More]

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Patch set updated for coreboot: 4159696 Remove Dell s1850
by Ronald G. Minnich 06 Apr '12

06 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/876 -gerrit commit 4159696eabb8bb7aae741e19962fe00aed03329e Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 20:25:38 2012 -0700 Remove Dell s1850 It's almost 10 years old. It never worked. It's a soldered in FLASH, so mistakes are fatal. It's got no redeeming features. Remove the dell directory. In 12 years of trying … [View More]to work with Dell we have not had much interest. It's misleading to have it there. Change-Id: I83ff009bd7a6d5289229ca39608789ae5c33710b --- src/mainboard/dell/Kconfig | 17 -- src/mainboard/dell/s1850/Kconfig | 44 ---- src/mainboard/dell/s1850/Makefile.inc | 1 - src/mainboard/dell/s1850/chip.h | 3 - src/mainboard/dell/s1850/cmos.layout | 80 -------- src/mainboard/dell/s1850/debug.c | 289 --------------------------- src/mainboard/dell/s1850/devicetree.cb | 72 ------- src/mainboard/dell/s1850/irq_tables.c | 53 ----- src/mainboard/dell/s1850/mainboard.c | 7 - src/mainboard/dell/s1850/mptable.c | 160 --------------- src/mainboard/dell/s1850/reset.c | 16 -- src/mainboard/dell/s1850/romstage.c | 324 ------------------------------- src/mainboard/dell/s1850/s1850_fixups.c | 60 ------ src/mainboard/dell/s1850/watchdog.c | 57 ------ 14 files changed, 0 insertions(+), 1183 deletions(-) diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig deleted file mode 100644 index fb665c4..0000000 --- a/src/mainboard/dell/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -if VENDOR_DELL - -choice - prompt "Mainboard model" - -config BOARD_DELL_S1850 - bool "PowerEdge 1850" - -endchoice - -source "src/mainboard/dell/s1850/Kconfig" - -config MAINBOARD_VENDOR - string - default "Dell" - -endif # VENDOR_DELL diff --git a/src/mainboard/dell/s1850/Kconfig b/src/mainboard/dell/s1850/Kconfig deleted file mode 100644 index cd4a6a9..0000000 --- a/src/mainboard/dell/s1850/Kconfig +++ /dev/null @@ -1,44 +0,0 @@ -if BOARD_DELL_S1850 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select ARCH_X86 - select CPU_INTEL_SOCKET_MPGA604 - select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801EX - select SOUTHBRIDGE_INTEL_PXHD - select SUPERIO_NSC_PC8374 - select ROMCC - select HAVE_OPTION_TABLE - select BOARD_HAS_HARD_RESET - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select USE_WATCHDOG_ON_BOOT - select BOARD_ROMSIZE_KB_1024 - select UDELAY_TSC - -config MAINBOARD_DIR - string - default dell/s1850 - -config MAINBOARD_PART_NUMBER - string - default "PowerEdge 1850" - -config MAX_CPUS - int - default 4 - -config MAX_PHYSICAL_CPUS - int - default 1 - -config IRQ_SLOT_COUNT - int - default 9 - -config DIMM_MAP_LOGICAL - hex - default 0x2841 - -endif # BOARD_DELL_S1850 diff --git a/src/mainboard/dell/s1850/Makefile.inc b/src/mainboard/dell/s1850/Makefile.inc deleted file mode 100644 index 0f285cd..0000000 --- a/src/mainboard/dell/s1850/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=p4 -O2 diff --git a/src/mainboard/dell/s1850/chip.h b/src/mainboard/dell/s1850/chip.h deleted file mode 100644 index d138e51..0000000 --- a/src/mainboard/dell/s1850/chip.h +++ /dev/null @@ -1,3 +0,0 @@ -extern struct chip_operations mainboard_ops; - -struct mainboard_config {}; diff --git a/src/mainboard/dell/s1850/cmos.layout b/src/mainboard/dell/s1850/cmos.layout deleted file mode 100644 index 81f1a69..0000000 --- a/src/mainboard/dell/s1850/cmos.layout +++ /dev/null @@ -1,80 +0,0 @@ -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 2 hyper_threading -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM - -checksums - -checksum 392 983 984 - - diff --git a/src/mainboard/dell/s1850/debug.c b/src/mainboard/dell/s1850/debug.c deleted file mode 100644 index 7904c06..0000000 --- a/src/mainboard/dell/s1850/debug.c +++ /dev/null @@ -1,289 +0,0 @@ -#include <spd.h> - -static void print_reg(unsigned char index) -{ - unsigned char data; - - outb(index, 0x2e); - data = inb(0x2f); - print_debug("0x"); - print_debug_hex8(index); - print_debug(": 0x"); - print_debug_hex8(data); - print_debug("\n"); - return; -} - -static void xbus_en(void) -{ - /* select the XBUS function in the SIO */ - outb(0x07, 0x2e); - outb(0x0f, 0x2f); - outb(0x30, 0x2e); - outb(0x01, 0x2f); - return; -} - -static void setup_func(unsigned char func) -{ - /* select the function in the SIO */ - outb(0x07, 0x2e); - outb(func, 0x2f); - /* print out the regs */ - print_reg(0x30); - print_reg(0x60); - print_reg(0x61); - print_reg(0x62); - print_reg(0x63); - print_reg(0x70); - print_reg(0x71); - print_reg(0x74); - print_reg(0x75); - return; -} - -static void siodump(void) -{ - int i; - unsigned char data; - - print_debug("\n*** SERVER I/O REGISTERS ***\n"); - for (i=0x10; i<=0x2d; i++) { - print_reg((unsigned char)i); - } -#if 0 - print_debug("\n*** XBUS REGISTERS ***\n"); - setup_func(0x0f); - for (i=0xf0; i<=0xff; i++) { - print_reg((unsigned char)i); - } - - print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); - setup_func(0x03); - print_reg(0xf0); - - print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); - setup_func(0x02); - print_reg(0xf0); - -#endif - print_debug("\n*** GPIO REGISTERS ***\n"); - setup_func(0x07); - for (i=0xf0; i<=0xf8; i++) { - print_reg((unsigned char)i); - } - print_debug("\n*** GPIO VALUES ***\n"); - data = inb(0x68a); - print_debug("\nGPDO 4: 0x"); - print_debug_hex8(data); - data = inb(0x68b); - print_debug("\nGPDI 4: 0x"); - print_debug_hex8(data); - print_debug("\n"); - -#if 0 - - print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); - setup_func(0x0a); - print_reg(0xf0); - - print_debug("\n*** FAN CONTROL REGISTERS ***\n"); - setup_func(0x09); - print_reg(0xf0); - print_reg(0xf1); - - print_debug("\n*** RTC REGISTERS ***\n"); - setup_func(0x10); - print_reg(0xf0); - print_reg(0xf1); - print_reg(0xf3); - print_reg(0xf6); - print_reg(0xf7); - print_reg(0xfe); - print_reg(0xff); - - print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); - setup_func(0x14); - print_reg(0xf0); -#endif - return; -} - -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} - -static void print_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - print_debug("\n"); - } -} - -static void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - print_debug("\n"); - - for(i = 0; i <= 255; i++) { - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); - print_debug_char(' '); - print_debug_hex8(val); - if ((i & 0x0f) == 0x0f) { - print_debug("\n"); - } - } -} - -static void dump_bar14(unsigned dev) -{ - int i; - unsigned long bar; - - print_debug("BAR 14 Dump\n"); - - bar = pci_read_config32(dev, 0x14); - for(i = 0; i <= 0x300; i+=4) { -#if 0 - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); -#endif - if((i%4)==0) { - print_debug("\n"); - print_debug_hex16(i); - print_debug_char(' '); - } - print_debug_hex32(read32(bar + i)); - print_debug_char(' '); - } - print_debug("\n"); -} - -static void dump_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - -void dump_spd_registers(void) -{ - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); - print_debug_hex8(device); - - for(i = 0; (i < 256) ; i++) { - unsigned char byte; - if ((i % 16) == 0) { - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device: "); - print_debug_hex8(-status); - print_debug("\n"); - break; - } - print_debug_hex8(status); - print_debug_char(' '); - } - device++; - print_debug("\n"); - } -} - -void show_dram_slots(void) -{ - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); - print_debug_hex8(device); - - status = smbus_read_byte(device, 0); - if (status < 0) { - print_debug("bad device: "); - } else { - print_debug("present: "); - } - print_debug_hex8(status); - print_debug("\n"); - device++; - print_debug("\n"); - } -} - -void dump_ipmi_registers(void) -{ - unsigned device; - device = 0x42; - while(device <= 0x42) { - int status = 0; - int i; - print_debug("\n"); - print_debug("ipmi "); - print_debug_hex8(device); - - for(i = 0; (i < 8) ; i++) { - unsigned char byte; - status = smbus_read_byte(device, 2); - if (status < 0) { - print_debug("bad device: "); - print_debug_hex8(-status); - print_debug("\n"); - break; - } - print_debug_hex8(status); - print_debug_char(' '); - } - device++; - print_debug("\n"); - } -} diff --git a/src/mainboard/dell/s1850/devicetree.cb b/src/mainboard/dell/s1850/devicetree.cb deleted file mode 100644 index c56fd37..0000000 --- a/src/mainboard/dell/s1850/devicetree.cb +++ /dev/null @@ -1,72 +0,0 @@ -chip northbridge/intel/e7520 # mch - device pci_domain 0 on - subsystemid 0x15d9 0x5580 inherit - chip southbridge/intel/i82801ex # i82801er - # USB ports - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.7 on end - - # -> Bridge - device pci 1e.0 on end - - # -> ISA - device pci 1f.0 on - chip superio/nsc/pc8374 - device pnp 2e.0 off end - device pnp 2e.1 off end - device pnp 2e.2 off end - device pnp 2e.3 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.6 off end - device pnp 2e.7 off end - device pnp 2e.8 off end - end - end - # -> IDE - device pci 1f.1 on end - # -> SATA - device pci 1f.2 on end - device pci 1f.3 on end - - register "pirq_a_d" = "0x8a07030b" - register "pirq_e_h" = "0x85808080" - end - device pci 00.0 on end - device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # pxhd1 - # Bus bridges and ioapics usually bus 1 - device pci 0.0 on - # On board gig e1000 - chip drivers/generic/generic - device pci 03.0 on end - device pci 03.1 on end - end - end - device pci 0.1 on end - device pci 0.2 on end - device pci 0.3 on end - end - end - device pci 04.0 on end - device pci 06.0 on end - end - device lapic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu 0 - device lapic 0 on end - end - chip cpu/intel/socket_mPGA604 # cpu 1 - device lapic 6 on end - end - end - register "intrline" = "0x00070100" -end - diff --git a/src/mainboard/dell/s1850/irq_tables.c b/src/mainboard/dell/s1850/irq_tables.c deleted file mode 100644 index e6073c7..0000000 --- a/src/mainboard/dell/s1850/irq_tables.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) by the coreboot pirq tool. - * This file was programatically generated. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/pirq_routing.h> - -const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x11 << 3) | 0x0, /* Interrupt router device */ - 0xc20, /* IRQs devoted exclusively to PCI usage */ - 0x1106, /* Vendor */ - 0x596, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x66, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0}, - {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x4, 0x0}, - {0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr); -} diff --git a/src/mainboard/dell/s1850/mainboard.c b/src/mainboard/dell/s1850/mainboard.c deleted file mode 100644 index 3d22f2d..0000000 --- a/src/mainboard/dell/s1850/mainboard.c +++ /dev/null @@ -1,7 +0,0 @@ -#include <device/device.h> -#include "chip.h" - -struct chip_operations mainboard_ops = { - CHIP_NAME("Dell S1850 Mainboard") -}; - diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c deleted file mode 100644 index 0c7562c..0000000 --- a/src/mainboard/dell/s1850/mptable.c +++ /dev/null @@ -1,160 +0,0 @@ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - unsigned char bus_pxhd_1; - unsigned char bus_pxhd_2; - unsigned char bus_pxhd_3; - unsigned char bus_pxhd_4; - unsigned char bus_ich5r_1; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - { - device_t dev; - - /* ich5r */ - dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); - if (dev) { - bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); - bus_ich5r_1 = 7; - } - /* pxhd-1 */ - dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); - if (dev) { - bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n"); - bus_pxhd_1 = 2; - } - /* pxhd-2 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); - if (dev) { - bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n"); - bus_pxhd_2 = 3; - } - - /* pxhd-3 */ - dev = dev_find_slot(0, PCI_DEVFN(0x4,0)); - if (dev) { - bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n"); - bus_pxhd_3 = 5; - } - /* pxhd-4 */ - dev = dev_find_slot(0, PCI_DEVFN(0x06,0)); - if (dev) { - bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n"); - bus_pxhd_4 = 6; - } - - } - - mptable_write_buses(mc, NULL, &bus_isa); - - /* IOAPIC handling */ - - smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - { - struct resource *res; - device_t dev; - /* pxhd apic 3 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x03, 0x20, res->base); - } - } - else { - printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n"); - } - /* pxhd apic 4 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x04, 0x20, res->base); - } - } - else { - printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); - } - } - - mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x74, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x76, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x77, 0x02, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x75, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x74, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x7c, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x7d, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x08, 0x03, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x0c, 0x03, 0x06); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x0d, 0x03, 0x07); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_2, 0x08, 0x04, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_ich5r_1, 0x04, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_4, 0x00, 0x02, 0x10); -#if 0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - (bus_isa - 1), 0x04, 0x02, 0x10); -#endif - /* Standard local interrupt assignments */ -#if 0 - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - bus_isa, 0x00, MP_APIC_ALL, 0x00); -#endif - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - bus_isa, 0x00, MP_APIC_ALL, 0x01); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} - diff --git a/src/mainboard/dell/s1850/reset.c b/src/mainboard/dell/s1850/reset.c deleted file mode 100644 index 745f187..0000000 --- a/src/mainboard/dell/s1850/reset.c +++ /dev/null @@ -1,16 +0,0 @@ -#include <arch/io.h> -#include <reset.h> -#if defined (__PRE_RAM__) -#include <arch/romcc_io.h> -#endif - -void soft_reset(void) -{ - outb(0x04, 0xcf9); -} - -void hard_reset(void) -{ - outb(0x02, 0xcf9); - outb(0x06, 0xcf9); -} diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c deleted file mode 100644 index e636986..0000000 --- a/src/mainboard/dell/s1850/romstage.c +++ /dev/null @@ -1,324 +0,0 @@ -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include <stdlib.h> -#include <console/console.h> -#include "southbridge/intel/i82801ex/early_smbus.c" -#include "northbridge/intel/e7520/raminit.h" -#include "superio/nsc/pc8374/early_init.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "debug.c" -#include "watchdog.c" -// Remove comment if resets in this file are actually used. -// #include "reset.c" -#include "s1850_fixups.c" -#include "northbridge/intel/e7520/memory_initialized.c" -#include "cpu/x86/bist.h" -#include <spd.h> - -#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1) - -#define DEVPRES_CONFIG ( \ - DEVPRES_D0F0 | \ - DEVPRES_D1F0 | \ - DEVPRES_D2F0 | \ - DEVPRES_D3F0 | \ - DEVPRES_D4F0 | \ - DEVPRES_D6F0 | \ - 0 ) -#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/e7520/raminit.c" -#include "lib/generic_sdram.c" - -/* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere - */ - -#define nftransport 0xc - -#define OBF 0 -#define IBF 1 - -#define ipmidata 0xca0 -#define ipmicsr 0xca4 - -static inline void ibfzero(void) -{ - while(inb(ipmicsr) & (1<<IBF)) - ; -} -static inline void clearobf(void) -{ - (void) inb(ipmidata); -} - -static inline void waitobf(void) -{ - while((inb(ipmicsr) & (1<<OBF)) == 0) - ; -} - -/* quite possibly the stupidest interface ever designed. */ -static inline void first_cmd_byte(unsigned char byte) -{ - ibfzero(); - clearobf(); - outb(0x61, ipmicsr); - ibfzero(); - clearobf(); - outb(byte, ipmidata); -} - -static inline void next_cmd_byte(unsigned char byte) -{ - - ibfzero(); - clearobf(); - outb(byte, ipmidata); -} - -static inline void last_cmd_byte(unsigned char byte) -{ - outb(0x62, ipmicsr); - - ibfzero(); - clearobf(); - outb(byte, ipmidata); -} - -static inline void read_response_byte(void) -{ - int val = -1; - if ((inb(ipmicsr)>>6) != 1) - return; - - ibfzero(); - waitobf(); - val = inb(ipmidata); - outb(0x68, ipmidata); - - /* see if it is done */ - if ((inb(ipmicsr)>>6) != 1){ - /* wait for the dummy read. Which describes this protocol */ - waitobf(); - (void)inb(ipmidata); - } -} - -static inline void ipmidelay(void) -{ - int i; - for(i = 0; i < 1000; i++) { - inb(0x80); - } -} - -static inline void bmc_foad(void) -{ - unsigned char c; - /* be safe; make sure it is really ready */ - while ((inb(ipmicsr)>>6)) { - outb(0x60, ipmicsr); - inb(ipmidata); - } - first_cmd_byte(nftransport << 2); - ipmidelay(); - next_cmd_byte(0x12); - ipmidelay(); - next_cmd_byte(2); - ipmidelay(); - last_cmd_byte(3); - ipmidelay(); -} - -/* end IPMI garbage */ - -#include "arch/x86/lib/stages.c" - -static void main(unsigned long bist) -{ - u8 b; - u16 w; - u32 l; - int do_reset; - - static const struct mem_controller mch[] = { - { - .node_id = 0, - /* the wiring on this part is really messed up */ - /* this is my best guess so far */ - .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, }, - .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, }, - } - }; - - /* superio setup */ - /* observed from serialice */ - static const u8 earlyinit[] = { - 0x21, 0x11, 0x11, - 0x22, 1, 1, - 0x23, 05, 05, - 0x24, 0x81, 0x81, - 0x26, 0, 0, - 0, - }; - - /* using SerialICE, we've seen this basic reset sequence on the dell. - * we don't understand it as it uses undocumented registers, but - * we're going to clone it. - */ - /* enable a hidden device. */ - b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - b |= 0x8; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - - /* read-write lock in CMOS on LPC bridge on ICH5 */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4); - - /* operate on undocumented device */ - l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4); - l |= 0x1000; - pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l); - - l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c); - l |= 0x8000; - pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l); - - /* disable undocumented device */ - b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - b &= ~0x8; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - - /* set up LPC bridge bits, some of which reply on undocumented - * registers - */ - - b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8); - b |= 4; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b); - - b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4); - b |= 2; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b); - - /* ACPI base address */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800); - - /* Enable specific ACPI features */ - b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44); - b |= 0x10; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b); - - /* ACPI control */ - w = inw(0x868); - outw(w|0x800, 0x868); - w = inw(0x866); - outw(w|2, 0x866); - -#if 0 - /*seriaice shows - dell does this so leave it here so I don't forget - */ - /* SMBUS */ - pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0); - - /* unknown */ - b = inb(0x8c2); - outb(0xdf, 0x8c2); -#endif - - /* another device enable? */ - b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - b |= 2; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - - /* ?? */ - l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0); - do_reset = l & 0x8000000; - l |= 0x8000000; - pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l); - - if (! do_reset) { - outb(2, 0xcf9); - outb(6, 0xcf9); - } - if (bist == 0) { - /* Skip this if there was a built in self test failure */ - early_mtrr_init(); - if (memory_initialized()) - skip_romstage(); - } - /* Setup the console */ - mainboard_set_ich5(); - //bmc_foad(); - pc8374_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* stuff we seem to need */ - pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0); - - /* GPIOs */ - pc8374_enable_dev(PNP_DEV(0x2e, PC8374_GPIO), 0xc20); - - /* keep this in mind. - SerialICE-hlp: outb 002e <= 23 - SerialICE-hlp: inb 002f => 05 - SerialICE-hlp: outb 002f <= 05 - SerialICE-hlp: outb 002e <= 24 - SerialICE-hlp: inb 002f => c1 - SerialICE-hlp: outb 002f <= c1 - */ - - /* Halt if there was a built in self test failure */ -// report_bist_failure(bist); - - /* MOVE ME TO A BETTER LOCATION !!! */ - /* config LPC decode for flash memory access */ - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) { - die("Missing ich5?"); - } - pci_write_config32(dev, 0xe8, 0x00000000); - pci_write_config8(dev, 0xf0, 0x00); - -#if 0 - display_cpuid_update_microcode(); -#endif -#if 1 - print_pci_devices(); -#endif -#if 1 - enable_smbus(); -#endif -#if 0 -// dump_spd_registers(&cpu[0]); - int i; - for(i = 0; i < 1; i++) - dump_spd_registers(); -#endif -#if 1 - show_dram_slots(); -#endif - disable_watchdogs(); -// dump_ipmi_registers(); - mainboard_set_e7520_leds(); - - sdram_initialize(ARRAY_SIZE(mch), mch); -#if 0 - dump_pci_devices(); -#endif -#if 1 - dump_pci_device(PCI_DEV(0, 0x00, 0)); -// dump_bar14(PCI_DEV(0, 0x00, 0)); -#endif -} diff --git a/src/mainboard/dell/s1850/s1850_fixups.c b/src/mainboard/dell/s1850/s1850_fixups.c deleted file mode 100644 index 7ef9ce1..0000000 --- a/src/mainboard/dell/s1850/s1850_fixups.c +++ /dev/null @@ -1,60 +0,0 @@ -#include <arch/romcc_io.h> - -static void mch_reset(void) -{ - return; -} - - - -static void mainboard_set_e7520_pll(unsigned bits) -{ - return; -} - - -static void mainboard_set_e7520_leds(void) -{ - return; -} - -static void mainboard_set_ich5(void) -{ - /* coma is 0x3f8 , comb is 0x2f8*/ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe0, 0x10); - /* enable decoding of various devices */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xe6, 0x140f); - /* 1M flash */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe3, 0xc0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xf0, 0x0); - /* disable certain devices -- see data sheet -- this is from - * dell settings via lspci - * Note that they leave SMBUS disabled -- 8f6f. - * we leave it enabled and visible in config space -- 8f66 - */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xf2, 0x8f66); - /* GPIOs -- needed, possibly, for SPD */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x58, 0x881); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x5c, 0x10); - - /* now the fun begins ... enable the GPIOs as done on factory */ - /* factory config from IO ports - * It has a few more things enabled than default! - */ - outl(0x1ae0f183, 0x880); - outl(0x1b00ffff, 0x884); - outl(0x131f0000, 0x88c); - outl(0x00000000, 0x894); - outl(0x00040000, 0x898); - outl(0x00000000, 0x8a4); - outl(0x00000000, 0x8a8); - outl(0x000031c0, 0x8ac); - outl(0x00000007, 0x8b0); - outl(0x00000304, 0x8b4); - outl(0x00030303, 0x8b8); - -} - - - - diff --git a/src/mainboard/dell/s1850/watchdog.c b/src/mainboard/dell/s1850/watchdog.c deleted file mode 100644 index 43f4029..0000000 --- a/src/mainboard/dell/s1850/watchdog.c +++ /dev/null @@ -1,57 +0,0 @@ -#include <device/pnp_def.h> - -#define NSC_WD_DEV PNP_DEV(0x2e, 0xa) -#define NSC_WDBASE 0x600 -#define ICH5_WDBASE 0x400 -#define ICH5_GPIOBASE 0x500 - -static void disable_sio_watchdog(device_t dev) -{ -#if 0 - /* FIXME move me somewhere more appropriate */ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); - pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE); - /* disable the sio watchdog */ - outb(0, NSC_WDBASE + 0); - pnp_set_enable(dev, 0); -#endif -} - -static void disable_ich5_watchdog(void) -{ - /* FIXME move me somewhere more appropriate */ - device_t dev; - unsigned long value, base; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) { - die("Missing ich5?"); - } - /* Enable I/O space */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - - /* Set and enable acpibase */ - pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); - pci_write_config8(dev, 0x44, 0x10); - base = ICH5_WDBASE + 0x60; - - /* Set bit 11 in TCO1_CNT */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - - /* Clear TCO timeout status */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); -} - - -static void disable_watchdogs(void) -{ -// disable_sio_watchdog(NSC_WD_DEV); - disable_ich5_watchdog(); - print_debug("Watchdogs disabled\n"); -} - [View Less]

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New patch to review for coreboot: d8f2b2f Add multicore support to coreboot.
by Ronald G. Minnich 06 Apr '12

06 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/877 -gerrit commit d8f2b2f51ab249977430685dec0093b8e0256106 Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 23:51:18 2012 -0700 Add multicore support to coreboot. This set of changes supports the ability for multicore support in coreboot. To give people a chance to examine the structure, and to make bisecting for bugs … [View More]easier, we are implementing the patch in 3 stages. This first stage introduces the basic mechanism but does not make any visible change in behavior. The APs, instead of being immediately spun down, are asked to run one debug print function and then spun down. The means by which APs are tasked was implemented in the NIX operating system in 2011, see: http://code.google.com/p/nix-os/ The APs come alive and spin on a memory location, contained in a per-AP structure. Tasking is accomplished by setting parameters into an argument array and then writing a function pointer into the memory location. The AP indicates completion by writing zero to the memory location. The BSP can wait for the AP to finish (synchronous) or going off to do other work (asynchronous). This way of tasking APs is incredibly cheap and fast: in the minimal case, one memory write suffices to launch an AP into doing work. This code has been tested on a sandybridge system (chromebook) and on another 4-core sandybridge system. Change-Id: I19f8587562fd499e98457aa9f11b52400c105697 --- src/arch/x86/include/arch/cpu.h | 5 ++ src/arch/x86/lib/cpu.c | 30 ++++++++-- src/cpu/x86/lapic/lapic_cpu_init.c | 117 +++++++++++++++++++++++++++++++++--- src/include/cpu/cpu.h | 10 +++- 4 files changed, 146 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 604abde..34d0856 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -157,9 +157,14 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); +typedef u32 (*workfunc)(u32, u32, u32); + struct cpu_info { device_t cpu; unsigned long index; + workfunc work; + u32 params[3]; + u32 result; }; static inline struct cpu_info *cpu_info(void) diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 98ede06..5e2683e 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -234,7 +234,7 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } -void cpu_initialize(void) +void cpu_initialize(struct cpu_info *info) { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -242,12 +242,9 @@ void cpu_initialize(void) * disabled. */ struct device *cpu; - struct cpu_info *info; struct cpuinfo_x86 c; - info = cpu_info(); - - printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index); + printk(BIOS_INFO, "cpu_initialize: CPU #%ld, info %p\n", info->index, info); cpu = info->cpu; if (!cpu) { @@ -289,3 +286,26 @@ void cpu_initialize(void) return; } +void cpu_work(struct cpu_info *info) +{ + workfunc f; + volatile workfunc *ptr = &info->work; + volatile u32 *params = info->params; + + printk(BIOS_INFO, "CPU #%ld ready to work\n", info->index); + + while (!*ptr) + ; + f = *ptr; + + printk(BIOS_SPEW, "CPU #%ld is asked to do %p\n", info->index, f); + f(params[0], params[1], params[2]); + + printk(BIOS_SPEW, "CPU #%ld finishes %p, mark %p\n", info->index, f, ptr); + *ptr = 0; + + printk(BIOS_INFO, "CPU #%ld leaving cpu_work()\n", info->index); + + return; +} + diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index ed9940c..02924e2 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -16,6 +16,21 @@ #include <cpu/cpu.h> #if CONFIG_SMP == 1 + +/* we do not want this struct visible outside this file. + * The external interface is via functions. + */ + +struct apcore { + u32 stack[1024 - sizeof(struct cpu_info)]; + struct cpu_info info; +}; + +#define TOS(x) (&apcores[(x)].stack[ARRAY_SIZE(apcores[x].stack)-1]) +typedef struct apcore apcore_t; + +apcore_t apcores[CONFIG_MAX_CPUS]; + /* This is a lot more paranoid now, since Linux can NOT handle * being told there is a CPU when none exists. So any errors * will return 0, meaning no CPU. @@ -224,9 +239,11 @@ static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; static unsigned last_cpu_index = 0; volatile unsigned long secondary_stack; +static void testfunc(u32 a, u32 b, u32 c){ + printk(a, "testfunc: %s %d\n", (char *)b, (int)c); +} int start_cpu(device_t cpu) { - extern unsigned char _estack[]; struct cpu_info *info; unsigned long stack_end; unsigned long apicid; @@ -243,16 +260,17 @@ int start_cpu(device_t cpu) index = ++last_cpu_index; /* Find end of the new processors stack */ - stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); + stack_end = (unsigned long) TOS(index); /* Record the index and which cpu structure we are using */ - info = (struct cpu_info *)stack_end; + info = &apcores[index].info; info->index = index; info->cpu = cpu; /* Advertise the new stack to start_cpu */ secondary_stack = stack_end; - + printk(BIOS_SPEW, "start_cpu CPU %ld secondary_stack %#lx info %p\n", + index, secondary_stack, info); /* Until the cpu starts up report the cpu is not enabled */ cpu->enabled = 0; cpu->initialized = 0; @@ -273,6 +291,12 @@ int start_cpu(device_t cpu) } secondary_stack = 0; spin_unlock(&start_cpu_lock); + if (result) { /* test work */ + printk(BIOS_SPEW, "BSP tests work\n"); + run_work(index, (workfunc)testfunc, BIOS_SPEW, + (u32)"Hello; run_work works", 555, NULL, 5000000); + printk(BIOS_SPEW, "Done core %ld\n", index); + } return result; } @@ -380,8 +404,11 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat #endif /* C entry point of secondary cpus */ -void secondary_cpu_init(void) -{ +void secondary_cpu_init(u32 x) + { + /* note: we tried (((u32 *)&x)[1]) but that failed. Compiler? */ + struct cpu_info *info = (struct cpu_info *)(((u8*)&x)+4); + atomic_inc(&active_cpus); #if CONFIG_SERIAL_CPU_INIT == 1 spin_lock(&start_cpu_lock); @@ -397,11 +424,11 @@ void secondary_cpu_init(void) cr4_val |= (1 << 9 | 1 << 10); writecr4(cr4_val); #endif - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SERIAL_CPU_INIT == 1 spin_unlock(&start_cpu_lock); #endif - + cpu_work(info); atomic_dec(&active_cpus); stop_this_cpu(); @@ -498,6 +525,7 @@ void initialize_cpus(struct bus *cpu_bus) info->cpu = alloc_find_dev(cpu_bus, &cpu_path); #if CONFIG_SMP == 1 + memset(apcores, 0, sizeof(*apcores)); copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif @@ -515,7 +543,7 @@ void initialize_cpus(struct bus *cpu_bus) #endif /* Initialize the bootstrap processor */ - cpu_initialize(); + cpu_initialize(info); #if CONFIG_SMP == 1 #if CONFIG_SERIAL_CPU_INIT == 1 @@ -527,3 +555,74 @@ void initialize_cpus(struct bus *cpu_bus) #endif } +#if CONFIG_SMP == 1 +/* work primitives */ +int start_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c) +{ + struct cpu_info *info; + volatile workfunc *ptr; + volatile u32 *params; + + if (core > CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + if (*ptr){ + printk(BIOS_EMERG, "start_work: core is busy %d\n", core); + return -1; + } + params = (u32 *)&info->params; + params[0] = a; + params[1] = b; + params[2] = c; + printk(BIOS_INFO, "BSP starts work on core %d\n", core); + *ptr = f; + return 0; +} + +int wait_work(unsigned int core, u32 *retval, unsigned int maxwait) +{ + int i = 0; + struct cpu_info *info; + volatile workfunc *ptr; + volatile u32 *result; + + if (core > CONFIG_MAX_CPUS){ + printk(BIOS_EMERG, "start_work: invalid core %d\n", core); + return -1; + } + info = &apcores[core].info; + if (! info->cpu->initialized){ + printk(BIOS_EMERG, "start_work: core not initialized %d\n", core); + return -1; + } + ptr = &info->work; + while (i++ < maxwait && *ptr) + if (i%100000 == 0) printk(BIOS_SPEW, "still waiting on %p at %d\n", + ptr, i); + if (*ptr){ + printk(BIOS_INFO, "core %d still running after %d iterations\n", + core, i); + return -1; + } + result = &info->result; + printk(BIOS_INFO, "info->work after result is %#lx\n", (unsigned long)*result); + if (retval) + *retval = *result; + return 0; +} + +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout) +{ + if (start_work(core, f, a, b, c)) + return -1; + return wait_work(core, retval, timeout); +} +#endif /* CONFIG_SMP == 1 */ diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index cca2be1..39f2fa2 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -5,9 +5,15 @@ struct device; struct bus; #include <arch/cpu.h> -void cpu_initialize(void); +void cpu_initialize(struct cpu_info *info); void initialize_cpus(struct bus *cpu_bus); -void secondary_cpu_init(void); +void secondary_cpu_init(u32 unused); +int start_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c); +int wait_work(unsigned int core, u32 *retval, unsigned int maxwait); +int run_work(unsigned int core, workfunc f, u32 a, u32 b, u32 c, u32 *retval, + unsigned int timeout); +void cpu_work(struct cpu_info *info); + #if !CONFIG_WAIT_BEFORE_CPUS_INIT #define cpus_ready_for_init() do {} while(0) [View Less]

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Re: [coreboot] [RFC] Re-thinking the stages
by Patrick Georgi 06 Apr '12

06 Apr '12

Am 06.04.2012 20:12, schrieb Marc Jones: > There is a lot of assumed configuration ownership in the vendor code, > and coreboot may need to adjust to that. Something else to consider as > you design these stages. Reminds me: can we get rid of platform_cfg.h on AGESA boards, please? Patrick

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Patch merged into coreboot/master: a6dfe8c Add support for SMSC MEC1308/1310 SuperI/O EC
by gerrit＠coreboot.org 06 Apr '12

06 Apr '12

the following patch was just integrated into master: commit a6dfe8c5be076c93b6a3540aa015f51cfbca4c2d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:12:22 2012 -0700 Add support for SMSC MEC1308/1310 SuperI/O EC Change-Id: If7921a66bab35f72c8455d5f0befc32a514ab417 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Apr 6 20:48:48 2012, … [View More]

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Patch merged into coreboot/master: 14eecf4 Add initial support for SMSC SIO1007 SuperI/O chip
by gerrit＠coreboot.org 06 Apr '12

06 Apr '12

the following patch was just integrated into master: commit 14eecf45d0570a231425254fb09e99a51e254107 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:10:07 2012 -0700 Add initial support for SMSC SIO1007 SuperI/O chip early_serial and some ACPI needed for compilation Change-Id: I5dd970676488697156e0630392884f31149ac85b Signed-off-by: Gabe Black <gabeblack(a)google.com> Build-Tested: build bot (Jenkins) at Fri Apr 6 21:07:35 2012, … [View More]

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Patch merged into coreboot/master: ba45bea Add support for SMSC LPC47N207 SuperI/O chip
by gerrit＠coreboot.org 06 Apr '12

06 Apr '12

the following patch was just integrated into master: commit ba45bea96cc244284e13f74e7a4d760952904938 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:06:04 2012 -0700 Add support for SMSC LPC47N207 SuperI/O chip This includes only early serial support for now. Change-Id: I9a2a439e1d17a989428033fdb4a4b813553dab6d Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> … [View More]

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Re: [coreboot] Patch merged into coreboot/master: c35c461 Invalidate cache before first jump
by Patrick Georgi 06 Apr '12

06 Apr '12

Am 06.04.2012 17:27, schrieb Marc Jones: > Can you be more descriptive to how it fails? Does it hang on that > instruction? That change might also break on future CPUs (if they finally manage to make the TPM stuff secure, so that's a big if) Patrick

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[RFC] Re-thinking the stages
by Kyösti Mälkki 06 Apr '12

06 Apr '12

Hi! Looking at some of the changes proposed with the new support of Intel Sandybridge and Ivybridge, combined with my previous design choices made with support of Intel Hyper-Threading for NetBurst architectures and SMP generally, made me share my thoughts of the Coreboot stage -layout. So there is currently bootblock, romstage, ramstage and payload, in that specific order. I have identified a few issues that would need to be worked on. 1. Built-in-self test failures On (Intel) SMP system … [View More]only BSP CPU failure is detected and possibly reported. I think architecture allows that BSP CPU is not the same physical core across power-cycles. One should consistently either be redundant or die on single CPU failure. 2. Serial console This is initialized in romstage and requires working cache to work. If due to a BIST failure or bad cache-as-ram init code, cache fails to work, there is no console. 3. Microcode updates The "tiny" bootblock doesn't seem like the correct place for microcode updates. 4. Cache coherency MTRR setup should be consistent across all CPUs. If all CPUs are started for microcode updates before ramstage, they should fix their MTRRs too. Even then, pre-ram spinlocks may be impossible to implement, so pre-ram SMP operation is very, very restricted. 5. XIP alignment If 4 variable MTRRs were used in pre-ram execution environment for XIP, there would be no alignment requirement on the placement of XIP romstage in Flash ROM. Such runtime MTRR setup code is around 512 bytes and cache footprint would extend at most 30% over the actual romstage size. A single MTRR setup may reserve almost twice the actual size of a romstage in both flash and cache memory. 6. Bypassing raminit One may want to start his Coreboot conversion job from something less complex than raminit, like setting up PCI device tree. With the amount of cache on modern CPUs, one could probably run libpayload -apps from cache. One such a nice app would be zmodem download of raminit. 7. CPU max physical address MTRR physical mask should be set correctly for the time of romstage too, just in case memory over 4GB is tested. Should first auto-detect and then provide work-arounds for CPU errata. Counting all the above together, I would like to start some discussion whether the current 4 stage model is the best design choice. I am thinking about some changes in the layout as a fix: 1. Bootblock No real change. Must guarantee access to all of Flash ROM and operational PCI configuration cycles for following stages. Contains boot vector for any AP CPUs. Exits in protected mode to Stageloader. 2. Stageloader A new stage. This has a pre-CAR environment (ROMCC-build) to enable early serial console and control MTRR setup to enable cache-as-ram. Pre-CAR environment can execute stages from Flash ROM with XIP. This also has a CAR and RAM environment (GCC-build) that can execute XIP stages from Flash ROM or decompress stages to CAR/RAM from Flash ROM. 3. CPU init A new stage built with ROMCC. Checks BIST of AP CPUs, executes microcode updates and handles the issue of shared Cache-Disable bit on hyper-threading Intel CPUs. 4. RAM init Old romstage built with GCC. Returns to Stageloader after DRAM is functional, but before any DRAM is written. 5. DEV init Old ramstage built with GCC. Only change is that microcode update and SMP setup is already taken care of. 6. Payload No changes required. I would be interested in working on some of these topics and I think I can also test most of the suggested changes on older SMP hardware. Thanks, Kyösti Mälkki <kyosti.malkki(a)gmail.com> [View Less]

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Patch set updated for coreboot: a6dfe8c Add support for SMSC MEC1308/1310 SuperI/O EC
by Stefan Reinauer 06 Apr '12

06 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/825 -gerrit commit a6dfe8c5be076c93b6a3540aa015f51cfbca4c2d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:12:22 2012 -0700 Add support for SMSC MEC1308/1310 SuperI/O EC Change-Id: If7921a66bab35f72c8455d5f0befc32a514ab417 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan … [View More]Reinauer <reinauer(a)google.com> --- src/superio/smsc/Kconfig | 2 + src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/mec1308/Makefile.inc | 20 +++ src/superio/smsc/mec1308/acpi/superio.asl | 261 +++++++++++++++++++++++++++++ src/superio/smsc/mec1308/chip.h | 33 ++++ src/superio/smsc/mec1308/mec1308.h | 27 +++ src/superio/smsc/mec1308/superio.c | 121 +++++++++++++ 7 files changed, 465 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 224376b..8d66fc5 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -40,6 +40,8 @@ config SUPERIO_SMSC_SIO1007 bool config SUPERIO_SMSC_KBC1100 bool +config SUPERIO_SMSC_MEC1308 + bool config SUPERIO_SMSC_SMSCSUPERIO bool config SUPERIO_SMSC_SIO1036 diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index bb4bf1d..8ebdf05 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -29,6 +29,7 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += sio1007 subdirs-y += kbc1100 +subdirs-y += mec1308 subdirs-y += smscsuperio subdirs-y += sio1036 subdirs-y += sch4037 diff --git a/src/superio/smsc/mec1308/Makefile.inc b/src/superio/smsc/mec1308/Makefile.inc new file mode 100644 index 0000000..b2b7baa --- /dev/null +++ b/src/superio/smsc/mec1308/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_MEC1308) += superio.c diff --git a/src/superio/smsc/mec1308/acpi/superio.asl b/src/superio/smsc/mec1308/acpi/superio.asl new file mode 100644 index 0000000..96f2ef8 --- /dev/null +++ b/src/superio/smsc/mec1308/acpi/superio.asl @@ -0,0 +1,261 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) { + OperationRegion (SIOA, SystemIO, 0x2E, 0x02) + Field (SIOA, ByteAcc, NoLock, Preserve) + { + SI2E, 8, + SI2F, 8, + } + + IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + SLDN, 8, /* Logical Device Number */ + Offset (0x30), + SACT, 8, /* Activate */ + Offset (0x60), + IO0H, 8, /* Base Address 0 MSB */ + IO0L, 8, /* Base Address 0 LSB */ + Offset (0x62), + IO1H, 8, /* Base Address 1 MSB */ + IO1L, 8, /* Base Address 1 LSB */ + Offset (0x70), + IQ00, 8, /* Interrupt Select */ + } + + Name (LPM1, 1) /* ACPI PM1 */ + Name (LEC1, 2) /* EC 1 */ + Name (LEC2, 3) /* EC 2 */ + Name (LSP1, 4) /* Serial Port */ + Name (LKBC, 7) /* Keyboard */ + Name (LEC0, 8) /* EC 0 */ + Name (LMBX, 9) /* Mailbox */ + + Method (ENTR, 0, NotSerialized) + { + Store (0x55, SI2E) + } + + Method (EXIT, 0, NotSerialized) + { + Store (0xaa, SI2E) + } + + /* Parse activate register for an LDN */ + Method (ISEN, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (SACT, Local0) + EXIT () + + /* Check if it exists */ + If (LEqual (Local0, 0xFF)) + { + Return (0x00) + } + + /* Check if activated */ + If (LEqual (Local0, One)) + { + Return (0x0F) + } + Else + { + Return (0x0D) + } + } + + /* Enable an LDN via the activate register */ + Method (SENA, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (One, SACT) + EXIT () + } + + /* Disable an LDN via the activate register */ + Method (SDIS, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (Zero, SACT) + EXIT () + } + +#ifdef SIO_ENABLE_SPM1 + Device (SPM1) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LPM1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08) + }) + } +#endif + +#ifdef SIO_ENABLE_SEC1 + Device (SEC1) { + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 2) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LEC1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04) + }) + } +#endif + +#ifdef SIO_ENABLE_SEC2 + Device (SEC2) { + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 3) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LEC2)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04) + }) + } +#endif + +#ifdef SIO_ENABLE_SSP1 + Device (SSP1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 4) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LSP1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08) + IRQNoFlags () {SIO_SSP1_IRQ} + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08) + IRQNoFlags () {SIO_SSP1_IRQ} + }) + } +#endif + +#ifdef SIO_ENABLE_SKBC + Device (SKBC) // Keyboard + { + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LKBC)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + } +#endif + +#ifdef SIO_ENABLE_SEC0 + Device (SEC0) { + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 8) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LEC0)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04) + }) + } +#endif + +#ifdef SIO_ENABLE_SMBX + Device (SMBX) // Mailbox + { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 9) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LMBX)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34) + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34) + }) + } +#endif +} diff --git a/src/superio/smsc/mec1308/chip.h b/src/superio/smsc/mec1308/chip.h new file mode 100644 index 0000000..3826888 --- /dev/null +++ b/src/superio/smsc/mec1308/chip.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SMSC_MEC1308_CHIP_H +#define SUPERIO_SMSC_MEC1308_CHIP_H + +#include <pc80/keyboard.h> +#include <uart8250.h> + +struct chip_operations; +extern struct chip_operations superio_smsc_mec1308_ops; + +struct superio_smsc_mec1308_config { + struct pc_keyboard keyboard; +}; + +#endif diff --git a/src/superio/smsc/mec1308/mec1308.h b/src/superio/smsc/mec1308/mec1308.h new file mode 100644 index 0000000..2b61234 --- /dev/null +++ b/src/superio/smsc/mec1308/mec1308.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define MEC1308_PM1 1 +#define MEC1308_EC1 2 +#define MEC1308_EC2 3 +#define MEC1308_UART 4 +#define MEC1308_KBC 7 +#define MEC1308_EC0 8 +#define MEC1308_MBX 9 + diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c new file mode 100644 index 0000000..070871d --- /dev/null +++ b/src/superio/smsc/mec1308/superio.c @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC MEC1308 Super I/O chip */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <device/smbus.h> +#include <string.h> +#include <bitops.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include "chip.h" +#include "mec1308.h" +#if CONFIG_HAVE_ACPI_RESUME +#include <arch/acpi.h> +#endif + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} + +static void mec1308_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void mec1308_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void mec1308_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void mec1308_init(device_t dev) +{ + struct superio_smsc_mec1308_config *conf = dev->chip_info; + + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + case MEC1308_KBC: +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type == 3) + return; +#endif + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = mec1308_pnp_set_resources, + .enable_resources = mec1308_pnp_enable_resources, + .enable = mec1308_pnp_enable, + .init = mec1308_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, MEC1308_PM1, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_EC1, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_EC2, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_UART, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, MEC1308_KBC, PNP_IRQ0, { 0, 0 } /* IO Fixed at 0x60/0x64 */ }, + { &ops, MEC1308_EC0, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_MBX, PNP_IO0, { 0x7ff, 0 } }, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_smsc_mec1308_ops = { + CHIP_NAME("SMSC MEC1308 EC SuperIO Interface") + .enable_dev = enable_dev +}; + [View Less]

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Patch set updated for coreboot: 2cf9f47 Remove Dell s1850
by Ronald G. Minnich 06 Apr '12

06 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/876 -gerrit commit 2cf9f473b6aea64419c1f0ca536ed5c11ca5fb41 Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 20:25:38 2012 -0700 Remove Dell s1850 It's almost 10 years old. It never worked. It's a soldered in FLASH, so mistakes are fatal. It's got no redeeming features. Change-Id: … [View More]I83ff009bd7a6d5289229ca39608789ae5c33710b --- src/mainboard/dell/Kconfig | 5 - src/mainboard/dell/s1850/Kconfig | 44 ---- src/mainboard/dell/s1850/Makefile.inc | 1 - src/mainboard/dell/s1850/chip.h | 3 - src/mainboard/dell/s1850/cmos.layout | 80 -------- src/mainboard/dell/s1850/debug.c | 289 --------------------------- src/mainboard/dell/s1850/devicetree.cb | 72 ------- src/mainboard/dell/s1850/irq_tables.c | 53 ----- src/mainboard/dell/s1850/mainboard.c | 7 - src/mainboard/dell/s1850/mptable.c | 160 --------------- src/mainboard/dell/s1850/reset.c | 16 -- src/mainboard/dell/s1850/romstage.c | 324 ------------------------------- src/mainboard/dell/s1850/s1850_fixups.c | 60 ------ src/mainboard/dell/s1850/watchdog.c | 57 ------ 14 files changed, 0 insertions(+), 1171 deletions(-) diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig index fb665c4..c4bd673 100644 --- a/src/mainboard/dell/Kconfig +++ b/src/mainboard/dell/Kconfig @@ -3,13 +3,8 @@ if VENDOR_DELL choice prompt "Mainboard model" -config BOARD_DELL_S1850 - bool "PowerEdge 1850" - endchoice -source "src/mainboard/dell/s1850/Kconfig" - config MAINBOARD_VENDOR string default "Dell" diff --git a/src/mainboard/dell/s1850/Kconfig b/src/mainboard/dell/s1850/Kconfig deleted file mode 100644 index cd4a6a9..0000000 --- a/src/mainboard/dell/s1850/Kconfig +++ /dev/null @@ -1,44 +0,0 @@ -if BOARD_DELL_S1850 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select ARCH_X86 - select CPU_INTEL_SOCKET_MPGA604 - select NORTHBRIDGE_INTEL_E7520 - select SOUTHBRIDGE_INTEL_I82801EX - select SOUTHBRIDGE_INTEL_PXHD - select SUPERIO_NSC_PC8374 - select ROMCC - select HAVE_OPTION_TABLE - select BOARD_HAS_HARD_RESET - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select USE_WATCHDOG_ON_BOOT - select BOARD_ROMSIZE_KB_1024 - select UDELAY_TSC - -config MAINBOARD_DIR - string - default dell/s1850 - -config MAINBOARD_PART_NUMBER - string - default "PowerEdge 1850" - -config MAX_CPUS - int - default 4 - -config MAX_PHYSICAL_CPUS - int - default 1 - -config IRQ_SLOT_COUNT - int - default 9 - -config DIMM_MAP_LOGICAL - hex - default 0x2841 - -endif # BOARD_DELL_S1850 diff --git a/src/mainboard/dell/s1850/Makefile.inc b/src/mainboard/dell/s1850/Makefile.inc deleted file mode 100644 index 0f285cd..0000000 --- a/src/mainboard/dell/s1850/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=p4 -O2 diff --git a/src/mainboard/dell/s1850/chip.h b/src/mainboard/dell/s1850/chip.h deleted file mode 100644 index d138e51..0000000 --- a/src/mainboard/dell/s1850/chip.h +++ /dev/null @@ -1,3 +0,0 @@ -extern struct chip_operations mainboard_ops; - -struct mainboard_config {}; diff --git a/src/mainboard/dell/s1850/cmos.layout b/src/mainboard/dell/s1850/cmos.layout deleted file mode 100644 index 81f1a69..0000000 --- a/src/mainboard/dell/s1850/cmos.layout +++ /dev/null @@ -1,80 +0,0 @@ -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 2 hyper_threading -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -728 256 h 0 user_data -984 16 h 0 check_sum -# Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved - - - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM - -checksums - -checksum 392 983 984 - - diff --git a/src/mainboard/dell/s1850/debug.c b/src/mainboard/dell/s1850/debug.c deleted file mode 100644 index 7904c06..0000000 --- a/src/mainboard/dell/s1850/debug.c +++ /dev/null @@ -1,289 +0,0 @@ -#include <spd.h> - -static void print_reg(unsigned char index) -{ - unsigned char data; - - outb(index, 0x2e); - data = inb(0x2f); - print_debug("0x"); - print_debug_hex8(index); - print_debug(": 0x"); - print_debug_hex8(data); - print_debug("\n"); - return; -} - -static void xbus_en(void) -{ - /* select the XBUS function in the SIO */ - outb(0x07, 0x2e); - outb(0x0f, 0x2f); - outb(0x30, 0x2e); - outb(0x01, 0x2f); - return; -} - -static void setup_func(unsigned char func) -{ - /* select the function in the SIO */ - outb(0x07, 0x2e); - outb(func, 0x2f); - /* print out the regs */ - print_reg(0x30); - print_reg(0x60); - print_reg(0x61); - print_reg(0x62); - print_reg(0x63); - print_reg(0x70); - print_reg(0x71); - print_reg(0x74); - print_reg(0x75); - return; -} - -static void siodump(void) -{ - int i; - unsigned char data; - - print_debug("\n*** SERVER I/O REGISTERS ***\n"); - for (i=0x10; i<=0x2d; i++) { - print_reg((unsigned char)i); - } -#if 0 - print_debug("\n*** XBUS REGISTERS ***\n"); - setup_func(0x0f); - for (i=0xf0; i<=0xff; i++) { - print_reg((unsigned char)i); - } - - print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); - setup_func(0x03); - print_reg(0xf0); - - print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); - setup_func(0x02); - print_reg(0xf0); - -#endif - print_debug("\n*** GPIO REGISTERS ***\n"); - setup_func(0x07); - for (i=0xf0; i<=0xf8; i++) { - print_reg((unsigned char)i); - } - print_debug("\n*** GPIO VALUES ***\n"); - data = inb(0x68a); - print_debug("\nGPDO 4: 0x"); - print_debug_hex8(data); - data = inb(0x68b); - print_debug("\nGPDI 4: 0x"); - print_debug_hex8(data); - print_debug("\n"); - -#if 0 - - print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); - setup_func(0x0a); - print_reg(0xf0); - - print_debug("\n*** FAN CONTROL REGISTERS ***\n"); - setup_func(0x09); - print_reg(0xf0); - print_reg(0xf1); - - print_debug("\n*** RTC REGISTERS ***\n"); - setup_func(0x10); - print_reg(0xf0); - print_reg(0xf1); - print_reg(0xf3); - print_reg(0xf6); - print_reg(0xf7); - print_reg(0xfe); - print_reg(0xff); - - print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); - setup_func(0x14); - print_reg(0xf0); -#endif - return; -} - -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} - -static void print_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - print_debug("\n"); - } -} - -static void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - print_debug("\n"); - - for(i = 0; i <= 255; i++) { - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); - print_debug_char(' '); - print_debug_hex8(val); - if ((i & 0x0f) == 0x0f) { - print_debug("\n"); - } - } -} - -static void dump_bar14(unsigned dev) -{ - int i; - unsigned long bar; - - print_debug("BAR 14 Dump\n"); - - bar = pci_read_config32(dev, 0x14); - for(i = 0; i <= 0x300; i+=4) { -#if 0 - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); -#endif - if((i%4)==0) { - print_debug("\n"); - print_debug_hex16(i); - print_debug_char(' '); - } - print_debug_hex32(read32(bar + i)); - print_debug_char(' '); - } - print_debug("\n"); -} - -static void dump_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -} - -void dump_spd_registers(void) -{ - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); - print_debug_hex8(device); - - for(i = 0; (i < 256) ; i++) { - unsigned char byte; - if ((i % 16) == 0) { - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device: "); - print_debug_hex8(-status); - print_debug("\n"); - break; - } - print_debug_hex8(status); - print_debug_char(' '); - } - device++; - print_debug("\n"); - } -} - -void show_dram_slots(void) -{ - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); - print_debug_hex8(device); - - status = smbus_read_byte(device, 0); - if (status < 0) { - print_debug("bad device: "); - } else { - print_debug("present: "); - } - print_debug_hex8(status); - print_debug("\n"); - device++; - print_debug("\n"); - } -} - -void dump_ipmi_registers(void) -{ - unsigned device; - device = 0x42; - while(device <= 0x42) { - int status = 0; - int i; - print_debug("\n"); - print_debug("ipmi "); - print_debug_hex8(device); - - for(i = 0; (i < 8) ; i++) { - unsigned char byte; - status = smbus_read_byte(device, 2); - if (status < 0) { - print_debug("bad device: "); - print_debug_hex8(-status); - print_debug("\n"); - break; - } - print_debug_hex8(status); - print_debug_char(' '); - } - device++; - print_debug("\n"); - } -} diff --git a/src/mainboard/dell/s1850/devicetree.cb b/src/mainboard/dell/s1850/devicetree.cb deleted file mode 100644 index c56fd37..0000000 --- a/src/mainboard/dell/s1850/devicetree.cb +++ /dev/null @@ -1,72 +0,0 @@ -chip northbridge/intel/e7520 # mch - device pci_domain 0 on - subsystemid 0x15d9 0x5580 inherit - chip southbridge/intel/i82801ex # i82801er - # USB ports - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.7 on end - - # -> Bridge - device pci 1e.0 on end - - # -> ISA - device pci 1f.0 on - chip superio/nsc/pc8374 - device pnp 2e.0 off end - device pnp 2e.1 off end - device pnp 2e.2 off end - device pnp 2e.3 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.6 off end - device pnp 2e.7 off end - device pnp 2e.8 off end - end - end - # -> IDE - device pci 1f.1 on end - # -> SATA - device pci 1f.2 on end - device pci 1f.3 on end - - register "pirq_a_d" = "0x8a07030b" - register "pirq_e_h" = "0x85808080" - end - device pci 00.0 on end - device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # pxhd1 - # Bus bridges and ioapics usually bus 1 - device pci 0.0 on - # On board gig e1000 - chip drivers/generic/generic - device pci 03.0 on end - device pci 03.1 on end - end - end - device pci 0.1 on end - device pci 0.2 on end - device pci 0.3 on end - end - end - device pci 04.0 on end - device pci 06.0 on end - end - device lapic_cluster 0 on - chip cpu/intel/socket_mPGA604 # cpu 0 - device lapic 0 on end - end - chip cpu/intel/socket_mPGA604 # cpu 1 - device lapic 6 on end - end - end - register "intrline" = "0x00070100" -end - diff --git a/src/mainboard/dell/s1850/irq_tables.c b/src/mainboard/dell/s1850/irq_tables.c deleted file mode 100644 index e6073c7..0000000 --- a/src/mainboard/dell/s1850/irq_tables.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) by the coreboot pirq tool. - * This file was programatically generated. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/pirq_routing.h> - -const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x11 << 3) | 0x0, /* Interrupt router device */ - 0xc20, /* IRQs devoted exclusively to PCI usage */ - 0x1106, /* Vendor */ - 0x596, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x66, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0}, - {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x4, 0x0}, - {0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr); -} diff --git a/src/mainboard/dell/s1850/mainboard.c b/src/mainboard/dell/s1850/mainboard.c deleted file mode 100644 index 3d22f2d..0000000 --- a/src/mainboard/dell/s1850/mainboard.c +++ /dev/null @@ -1,7 +0,0 @@ -#include <device/device.h> -#include "chip.h" - -struct chip_operations mainboard_ops = { - CHIP_NAME("Dell S1850 Mainboard") -}; - diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c deleted file mode 100644 index 0c7562c..0000000 --- a/src/mainboard/dell/s1850/mptable.c +++ /dev/null @@ -1,160 +0,0 @@ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - unsigned char bus_pxhd_1; - unsigned char bus_pxhd_2; - unsigned char bus_pxhd_3; - unsigned char bus_pxhd_4; - unsigned char bus_ich5r_1; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - { - device_t dev; - - /* ich5r */ - dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); - if (dev) { - bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); - bus_ich5r_1 = 7; - } - /* pxhd-1 */ - dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); - if (dev) { - bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n"); - bus_pxhd_1 = 2; - } - /* pxhd-2 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); - if (dev) { - bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n"); - bus_pxhd_2 = 3; - } - - /* pxhd-3 */ - dev = dev_find_slot(0, PCI_DEVFN(0x4,0)); - if (dev) { - bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n"); - bus_pxhd_3 = 5; - } - /* pxhd-4 */ - dev = dev_find_slot(0, PCI_DEVFN(0x06,0)); - if (dev) { - bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n"); - bus_pxhd_4 = 6; - } - - } - - mptable_write_buses(mc, NULL, &bus_isa); - - /* IOAPIC handling */ - - smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - { - struct resource *res; - device_t dev; - /* pxhd apic 3 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x03, 0x20, res->base); - } - } - else { - printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n"); - } - /* pxhd apic 4 */ - dev = dev_find_slot(1, PCI_DEVFN(0x00,3)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x04, 0x20, res->base); - } - } - else { - printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); - } - } - - mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x74, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x76, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x77, 0x02, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x75, 0x02, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x74, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x7c, 0x02, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x00, 0x7d, 0x02, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x08, 0x03, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x0c, 0x03, 0x06); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_1, 0x0d, 0x03, 0x07); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_2, 0x08, 0x04, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_ich5r_1, 0x04, 0x02, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pxhd_4, 0x00, 0x02, 0x10); -#if 0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - (bus_isa - 1), 0x04, 0x02, 0x10); -#endif - /* Standard local interrupt assignments */ -#if 0 - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - bus_isa, 0x00, MP_APIC_ALL, 0x00); -#endif - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - bus_isa, 0x00, MP_APIC_ALL, 0x01); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} - diff --git a/src/mainboard/dell/s1850/reset.c b/src/mainboard/dell/s1850/reset.c deleted file mode 100644 index 745f187..0000000 --- a/src/mainboard/dell/s1850/reset.c +++ /dev/null @@ -1,16 +0,0 @@ -#include <arch/io.h> -#include <reset.h> -#if defined (__PRE_RAM__) -#include <arch/romcc_io.h> -#endif - -void soft_reset(void) -{ - outb(0x04, 0xcf9); -} - -void hard_reset(void) -{ - outb(0x02, 0xcf9); - outb(0x06, 0xcf9); -} diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c deleted file mode 100644 index e636986..0000000 --- a/src/mainboard/dell/s1850/romstage.c +++ /dev/null @@ -1,324 +0,0 @@ -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <arch/romcc_io.h> -#include <cpu/x86/lapic.h> -#include <stdlib.h> -#include <console/console.h> -#include "southbridge/intel/i82801ex/early_smbus.c" -#include "northbridge/intel/e7520/raminit.h" -#include "superio/nsc/pc8374/early_init.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "debug.c" -#include "watchdog.c" -// Remove comment if resets in this file are actually used. -// #include "reset.c" -#include "s1850_fixups.c" -#include "northbridge/intel/e7520/memory_initialized.c" -#include "cpu/x86/bist.h" -#include <spd.h> - -#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1) - -#define DEVPRES_CONFIG ( \ - DEVPRES_D0F0 | \ - DEVPRES_D1F0 | \ - DEVPRES_D2F0 | \ - DEVPRES_D3F0 | \ - DEVPRES_D4F0 | \ - DEVPRES_D6F0 | \ - 0 ) -#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/e7520/raminit.c" -#include "lib/generic_sdram.c" - -/* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere - */ - -#define nftransport 0xc - -#define OBF 0 -#define IBF 1 - -#define ipmidata 0xca0 -#define ipmicsr 0xca4 - -static inline void ibfzero(void) -{ - while(inb(ipmicsr) & (1<<IBF)) - ; -} -static inline void clearobf(void) -{ - (void) inb(ipmidata); -} - -static inline void waitobf(void) -{ - while((inb(ipmicsr) & (1<<OBF)) == 0) - ; -} - -/* quite possibly the stupidest interface ever designed. */ -static inline void first_cmd_byte(unsigned char byte) -{ - ibfzero(); - clearobf(); - outb(0x61, ipmicsr); - ibfzero(); - clearobf(); - outb(byte, ipmidata); -} - -static inline void next_cmd_byte(unsigned char byte) -{ - - ibfzero(); - clearobf(); - outb(byte, ipmidata); -} - -static inline void last_cmd_byte(unsigned char byte) -{ - outb(0x62, ipmicsr); - - ibfzero(); - clearobf(); - outb(byte, ipmidata); -} - -static inline void read_response_byte(void) -{ - int val = -1; - if ((inb(ipmicsr)>>6) != 1) - return; - - ibfzero(); - waitobf(); - val = inb(ipmidata); - outb(0x68, ipmidata); - - /* see if it is done */ - if ((inb(ipmicsr)>>6) != 1){ - /* wait for the dummy read. Which describes this protocol */ - waitobf(); - (void)inb(ipmidata); - } -} - -static inline void ipmidelay(void) -{ - int i; - for(i = 0; i < 1000; i++) { - inb(0x80); - } -} - -static inline void bmc_foad(void) -{ - unsigned char c; - /* be safe; make sure it is really ready */ - while ((inb(ipmicsr)>>6)) { - outb(0x60, ipmicsr); - inb(ipmidata); - } - first_cmd_byte(nftransport << 2); - ipmidelay(); - next_cmd_byte(0x12); - ipmidelay(); - next_cmd_byte(2); - ipmidelay(); - last_cmd_byte(3); - ipmidelay(); -} - -/* end IPMI garbage */ - -#include "arch/x86/lib/stages.c" - -static void main(unsigned long bist) -{ - u8 b; - u16 w; - u32 l; - int do_reset; - - static const struct mem_controller mch[] = { - { - .node_id = 0, - /* the wiring on this part is really messed up */ - /* this is my best guess so far */ - .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, }, - .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, }, - } - }; - - /* superio setup */ - /* observed from serialice */ - static const u8 earlyinit[] = { - 0x21, 0x11, 0x11, - 0x22, 1, 1, - 0x23, 05, 05, - 0x24, 0x81, 0x81, - 0x26, 0, 0, - 0, - }; - - /* using SerialICE, we've seen this basic reset sequence on the dell. - * we don't understand it as it uses undocumented registers, but - * we're going to clone it. - */ - /* enable a hidden device. */ - b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - b |= 0x8; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - - /* read-write lock in CMOS on LPC bridge on ICH5 */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4); - - /* operate on undocumented device */ - l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4); - l |= 0x1000; - pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l); - - l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c); - l |= 0x8000; - pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l); - - /* disable undocumented device */ - b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - b &= ~0x8; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - - /* set up LPC bridge bits, some of which reply on undocumented - * registers - */ - - b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8); - b |= 4; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b); - - b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4); - b |= 2; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b); - - /* ACPI base address */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800); - - /* Enable specific ACPI features */ - b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44); - b |= 0x10; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b); - - /* ACPI control */ - w = inw(0x868); - outw(w|0x800, 0x868); - w = inw(0x866); - outw(w|2, 0x866); - -#if 0 - /*seriaice shows - dell does this so leave it here so I don't forget - */ - /* SMBUS */ - pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0); - - /* unknown */ - b = inb(0x8c2); - outb(0xdf, 0x8c2); -#endif - - /* another device enable? */ - b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); - b |= 2; - pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); - - /* ?? */ - l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0); - do_reset = l & 0x8000000; - l |= 0x8000000; - pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l); - - if (! do_reset) { - outb(2, 0xcf9); - outb(6, 0xcf9); - } - if (bist == 0) { - /* Skip this if there was a built in self test failure */ - early_mtrr_init(); - if (memory_initialized()) - skip_romstage(); - } - /* Setup the console */ - mainboard_set_ich5(); - //bmc_foad(); - pc8374_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* stuff we seem to need */ - pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0); - - /* GPIOs */ - pc8374_enable_dev(PNP_DEV(0x2e, PC8374_GPIO), 0xc20); - - /* keep this in mind. - SerialICE-hlp: outb 002e <= 23 - SerialICE-hlp: inb 002f => 05 - SerialICE-hlp: outb 002f <= 05 - SerialICE-hlp: outb 002e <= 24 - SerialICE-hlp: inb 002f => c1 - SerialICE-hlp: outb 002f <= c1 - */ - - /* Halt if there was a built in self test failure */ -// report_bist_failure(bist); - - /* MOVE ME TO A BETTER LOCATION !!! */ - /* config LPC decode for flash memory access */ - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) { - die("Missing ich5?"); - } - pci_write_config32(dev, 0xe8, 0x00000000); - pci_write_config8(dev, 0xf0, 0x00); - -#if 0 - display_cpuid_update_microcode(); -#endif -#if 1 - print_pci_devices(); -#endif -#if 1 - enable_smbus(); -#endif -#if 0 -// dump_spd_registers(&cpu[0]); - int i; - for(i = 0; i < 1; i++) - dump_spd_registers(); -#endif -#if 1 - show_dram_slots(); -#endif - disable_watchdogs(); -// dump_ipmi_registers(); - mainboard_set_e7520_leds(); - - sdram_initialize(ARRAY_SIZE(mch), mch); -#if 0 - dump_pci_devices(); -#endif -#if 1 - dump_pci_device(PCI_DEV(0, 0x00, 0)); -// dump_bar14(PCI_DEV(0, 0x00, 0)); -#endif -} diff --git a/src/mainboard/dell/s1850/s1850_fixups.c b/src/mainboard/dell/s1850/s1850_fixups.c deleted file mode 100644 index 7ef9ce1..0000000 --- a/src/mainboard/dell/s1850/s1850_fixups.c +++ /dev/null @@ -1,60 +0,0 @@ -#include <arch/romcc_io.h> - -static void mch_reset(void) -{ - return; -} - - - -static void mainboard_set_e7520_pll(unsigned bits) -{ - return; -} - - -static void mainboard_set_e7520_leds(void) -{ - return; -} - -static void mainboard_set_ich5(void) -{ - /* coma is 0x3f8 , comb is 0x2f8*/ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe0, 0x10); - /* enable decoding of various devices */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xe6, 0x140f); - /* 1M flash */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe3, 0xc0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xf0, 0x0); - /* disable certain devices -- see data sheet -- this is from - * dell settings via lspci - * Note that they leave SMBUS disabled -- 8f6f. - * we leave it enabled and visible in config space -- 8f66 - */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xf2, 0x8f66); - /* GPIOs -- needed, possibly, for SPD */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x58, 0x881); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x5c, 0x10); - - /* now the fun begins ... enable the GPIOs as done on factory */ - /* factory config from IO ports - * It has a few more things enabled than default! - */ - outl(0x1ae0f183, 0x880); - outl(0x1b00ffff, 0x884); - outl(0x131f0000, 0x88c); - outl(0x00000000, 0x894); - outl(0x00040000, 0x898); - outl(0x00000000, 0x8a4); - outl(0x00000000, 0x8a8); - outl(0x000031c0, 0x8ac); - outl(0x00000007, 0x8b0); - outl(0x00000304, 0x8b4); - outl(0x00030303, 0x8b8); - -} - - - - diff --git a/src/mainboard/dell/s1850/watchdog.c b/src/mainboard/dell/s1850/watchdog.c deleted file mode 100644 index 43f4029..0000000 --- a/src/mainboard/dell/s1850/watchdog.c +++ /dev/null @@ -1,57 +0,0 @@ -#include <device/pnp_def.h> - -#define NSC_WD_DEV PNP_DEV(0x2e, 0xa) -#define NSC_WDBASE 0x600 -#define ICH5_WDBASE 0x400 -#define ICH5_GPIOBASE 0x500 - -static void disable_sio_watchdog(device_t dev) -{ -#if 0 - /* FIXME move me somewhere more appropriate */ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); - pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE); - /* disable the sio watchdog */ - outb(0, NSC_WDBASE + 0); - pnp_set_enable(dev, 0); -#endif -} - -static void disable_ich5_watchdog(void) -{ - /* FIXME move me somewhere more appropriate */ - device_t dev; - unsigned long value, base; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) { - die("Missing ich5?"); - } - /* Enable I/O space */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - - /* Set and enable acpibase */ - pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); - pci_write_config8(dev, 0x44, 0x10); - base = ICH5_WDBASE + 0x60; - - /* Set bit 11 in TCO1_CNT */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - - /* Clear TCO timeout status */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); -} - - -static void disable_watchdogs(void) -{ -// disable_sio_watchdog(NSC_WD_DEV); - disable_ich5_watchdog(); - print_debug("Watchdogs disabled\n"); -} - [View Less]

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Patch merged into coreboot/master: 1c810f1 Fixes and Sandybridge support for lapic cpu init
by gerrit＠coreboot.org 06 Apr '12

06 Apr '12

the following patch was just integrated into master: commit 1c810f17a1a3e9c5433e9eee4a18175d64698be2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:17:11 2012 -0700 Fixes and Sandybridge support for lapic cpu init - preprocessor macros should not use defined(CONFIG_*) but just CONFIG_* - drop AMD CPU model 14XXX config variable use. Those do not exist. - skip some delays on Sandybridge systems - Count how long we're waiting for each … [View More]

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New patch to review for coreboot: da94856 Remove Dell s1850
by Ronald G. Minnich 06 Apr '12

06 Apr '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/876 -gerrit commit da948569bff18ceb397652d3d547377b43f3263f Author: Ron Minnich <rminnich(a)gmail.com> Date: Thu Apr 5 20:25:38 2012 -0700 Remove Dell s1850 It's almost 10 years old. It never worked. It's a soldered in FLASH, so mistakes are fatal. It's got no redeeming features. Change-Id: … [View More]

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Patch merged into coreboot/master: c35c461 Invalidate cache before first jump
by gerrit＠coreboot.org 06 Apr '12

06 Apr '12

the following patch was just integrated into master: commit c35c461bb2146ab949062f22e265406deef178d2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:09:46 2012 -0700 Invalidate cache before first jump Some CPUs (Sandybridge) seem to require this, and it does not hurt on other CPUs. Change-Id: I4fdb281b2b684ab5fea999aae28ca08dce24da4d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Thu … [View More]

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New patch to review for coreboot: beca17b amdfam10: add phenom II as known cpu
by Bernhard Urban 06 Apr '12

06 Apr '12

Bernhard Urban (lewurm(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/864 -gerrit commit beca17b9dc211fa2c8424083724c28c5f37d52bf Author: Bernhard Urban <lewurm(a)gmail.com> Date: Thu Apr 5 17:13:27 2012 +0200 amdfam10: add phenom II as known cpu Change-Id: I84a0f9e8e7a15c0aac8dc380de3ddf70b1decbd7 Signed-off-by: Bernhard Urban <lewurm(a)gmail.com> --- src/northbridge/amd/amdfam10/raminit_amdmct.c | 3 +… [View More]

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Re: [coreboot] GSoC project ideas
by Peter Stuge 06 Apr '12

06 Apr '12

Paul Geraedts wrote: > >> I will try to make my VHDL cores so they will be compatible with > >> both types of boards. I plan to start with UART over USB support > >> for the currently available Papilio boards. > > > > UART is stoneage idiotic useless. It's 2012, so please aim higher. > > Yet another opinion I guess; It's a bit more than opinion. > at the end of the day opinions should not matter. What a nice way to say that you reject my … [View More]input. > >> Basically flashrom SPI access, POST code access and serial console > >> access. This 'playground' should eventually give me enough insight > >> in an optimal implementation when targeting future boards. > > > > Don't invent yet another packet protocol on top of a serial stream, > > do this right the first time. You're planning on implementing three > > different functions, and they really do need to use different > > interfaces. > > Do not worry. No need for assumptions. I was not planning to. SPI, port 80, and 16550 are the three functions you list, and which I refer to. These are good features, that's not the point, the point is that they are distinct features, so it makes sense to have them fall out the other side of the FPGA as such. > I will write a number of VHDL cores that plug in to a Wishbone > interface that will also be connected to a USB controller. Wishbone to some degree and USB for certain takes a lot of logic space, and I think they're both way overkill for this simple FPGA design. USB MAC core can make good sense if high speed is required, but that's not the case for either of these functions. Optimizing for design size allows cheaper and simpler implementation, ideally the LPC slave can even be made to fit into a CPLD. > In the first version that controller will be a (circuit-switched) > UART over USB controller (switched either manually or by means of > routing an extra GPIO pin of the FT2232D to the FPGA). You overlook or ignore my earlier point. Use something more structured than UART right from the start. > Future boards is expected to contain improved USB hardware in several > flavors ranging from a USB transceiver-only approach with USB stack in > FPGA, to an FT232H in MPSSE mode, to a dedicated microprocesser with > build-in USB and anything in between. Right, I've talked with Jack about these things quite a bit. > It should not matter what kind of hardware is used It matters a lot for implementability, design size and thus manufacturability based on possible usable parts. > as long as it contains a similar Wishbone interface it will be > transparant to the rest of the Wishbone cores. I don't see the need for Wishbone in this design. > > For the SPI flash emulator, suggest use IS61WV20488BLL-10TLI. > > The first prototype will not contain SRAM, but merely act as an SPI > master mux. Due to its complexity, cost and GPIO pin count, I will > only consider SRAM if absolutely necessary. SRAM is trivial to interface, but it does need lots of pins! It is in any case quite neccessary for the design to be useful for development and testing; I believe the third usecase you listed originally. Please tell some more about your background? Thanks //Peter [View Less]

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Re: [coreboot] New patch to review for coreboot: dc63ffb Fill out ChromeOS specific coreboot table extensions
by Peter Stuge 05 Apr '12

05 Apr '12

ron minnich wrote: > > Maybe it should be made clear also in the names that these tags are > > chromeos specific? > > I don't think we should. I am hoping that some other vendor will > figure out how neat these things are and use them too. It's good to collaborate on design rather than just run with something? //Peter

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Patch merged into coreboot/master: d9462c6 Fix support for RAM-less multi-processor init
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit d9462c6dca942bed9a609cc40572912bb33f0558 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 6 04:03:50 2012 +0300 Fix support for RAM-less multi-processor init Fix regression after commit: 7dfe32c5408916b6cb23f1ec48e473e1c728d300 Only align 16-bit entry on platforms that really require it, indicated by selecting SIPI_VECTOR_IN_ROM in CPU Kconfig. Disable assertion test of … [View More]

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New patch to review for coreboot: d9462c6 Fix support for RAM-less multi-processor init
by Kyösti Mälkki 05 Apr '12

05 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/875 -gerrit commit d9462c6dca942bed9a609cc40572912bb33f0558 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 6 04:03:50 2012 +0300 Fix support for RAM-less multi-processor init Fix regression after commit: 7dfe32c5408916b6cb23f1ec48e473e1c728d300 Only align 16-bit entry on platforms that really require it, … [View More]indicated by selecting SIPI_VECTOR_IN_ROM in CPU Kconfig. Disable assertion test of AP_SIPI_VECTOR for platforms not depending on this feature. Build of romstage should be fixed to get the vector address from bootblock build automatically. Change-Id: Ide470833c0254df1a9ff708369ab1c095ccfb98d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Kconfig | 7 +++++++ src/arch/x86/init/ldscript_failover.lb | 14 +++++++++----- src/cpu/intel/socket_mPGA604/Kconfig | 1 + 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index f49d09b..6d56ec6 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -8,6 +8,13 @@ config AP_IN_SIPI_WAIT default n depends on ARCH_X86 +# Aligns 16bit entry code in bootblock so that hyper-threading CPUs +# can boot AP CPUs to enable their shared caches. +config SIPI_VECTOR_IN_ROM + bool + default n + depends on ARCH_X86 + config RAMBASE hex default 0x100000 diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 61c3d2a..d6940ee 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -30,10 +30,11 @@ TARGET(binary) SECTIONS { /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs - * with Startup IPI message without RAM. + * with Startup IPI message without RAM. Align .rom to next 4 byte + * boundary anyway, so no pad byte appears between _rom and _start. */ .bogus ROMLOC_MIN : { - . = ALIGN(4096); + . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4); ROMLOC = .; } >rom = 0xff @@ -52,11 +53,14 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096; + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - + (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); /* Post-check proper SIPI vector. */ - _bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment"); - _bogus = ASSERT((ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), "Address mismatch on AP_SIPI_VECTOR"); + _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0), + "Bad SIPI vector alignment"); + _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), + "Address mismatch on AP_SIPI_VECTOR"); /DISCARD/ : { *(.comment) diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 4fa7569..0d4d45f 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -11,6 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select MMX select SSE select UDELAY_TSC + select SIPI_VECTOR_IN_ROM # mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on [View Less]

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Re: [coreboot] GSoC project ideas
by Peter Stuge 05 Apr '12

05 Apr '12

Paul Geraedts wrote: > My hardware target is the Papilio platform in general For the SPI flash emulator, suggest use IS61WV20488BLL-10TLI. //Peter

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Re: [coreboot] GSoC project ideas
by Paul Geraedts 05 Apr '12

05 Apr '12

Hi Svetoslav, On Wed Apr 4 23:17:46 CEST 2012, Svetoslav Trochev wrote: >>> - Flash ICE device with SPI support. >>> - Flash ICE device with LPC/FWH support. >>> - Serial emulation for LPC buses on a configurable I/O port with USB >>> output on the other side. >>> - Dual serial emulation for two LPC buses either on the same device or >>> with two identical devices and a fast bus in between. >>> - Serial emulation for PCI buses (i.… [View More]

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Patch set updated for coreboot: ba45bea Add support for SMSC LPC47N207 SuperI/O chip
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/823 -gerrit commit ba45bea96cc244284e13f74e7a4d760952904938 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:06:04 2012 -0700 Add support for SMSC LPC47N207 SuperI/O chip This includes only early serial support for now. Change-Id: I9a2a439e1d17a989428033fdb4a4b813553dab6d Signed-off-by: Vadim … [View More]Bendebury <vbendeb(a)chromium.org> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/superio/smsc/lpc47n207/early_serial.c | 97 +++++++++++++++++++++++++++++ src/superio/smsc/lpc47n207/lpc47n207.h | 25 ++++++++ 2 files changed, 122 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c new file mode 100644 index 0000000..e2ae49d --- /dev/null +++ b/src/superio/smsc/lpc47n207/early_serial.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * This code tries to discover the SMSC LPC47N207 superio chip which can be + * connected over an LPC dongle. The chip could be bootstrap mapped to one of + * four LPC addresses: 0x2e, 0x4e, 0x162e, and 0x164e. + * + * Initializing the UART requires accesses to a few control registers. This + * structure includes the register offset and the value to write (along with + * the mask). + */ +typedef struct { + u8 conf_reg; + u8 value; + u8 mask; +} uart_conf; + +/* All regs/values to write to initialize the LPC47N207 UART */ +static const uart_conf uart_conf_data [] = { + {2, (1 << 3), (1 << 3)}, /* cr02, enable Primary UART power */ + {0xc, (1 << 6), (1 << 6)}, /* cr0c, enable Primary UART high speed */ + {0x24, (CONFIG_TTYS0_BASE >> 3) << 1, 0xff}, /* cr24, base addr */ +}; + +void try_enabling_LPC47N207_uart(void) +{ + u8 reg_value; + const uart_conf* conf_item; + u16 lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e}; + u16 lpc_port; + int i, j; + +#define CONFIG_ENABLE 0x55 +#define CONFIG_DISABLE 0xaa + + for (j = 0; j < ARRAY_SIZE(lpc_ports); j++) { + lpc_port = lpc_ports[j]; + + /* enable CONFIG mode */ + outb(CONFIG_ENABLE, lpc_port); + reg_value=inb(lpc_port); + if (reg_value != CONFIG_ENABLE) { + continue; /* There is no LPC device at this address */ + } + + do { + /* + * Registers 12 and 13 hold config address, look for a + * match. + */ + outb(0x12, lpc_port); + reg_value=inb(lpc_port + 1); + if (reg_value != (lpc_port & 0xff)) + break; + + outb(0x13, lpc_port); + reg_value=inb(lpc_port + 1); + if (reg_value != (lpc_port >> 8)) + break; + + /* This must be the SMSC LPC 47N207, enable the UART. */ + for (i = 0; i < ARRAY_SIZE(uart_conf_data); i++) { + u8 reg, value, mask; + + conf_item = uart_conf_data + i; + + reg = conf_item->conf_reg; + value = conf_item->value; + mask = conf_item->mask; + + outb(reg, lpc_port); + reg_value = inb(lpc_port + 1); + reg_value &= ~mask; + reg_value |= (value & mask); + outb(reg_value, lpc_port + 1); + } + } while (0); + outb(CONFIG_DISABLE, lpc_port); + } +} diff --git a/src/superio/smsc/lpc47n207/lpc47n207.h b/src/superio/smsc/lpc47n207/lpc47n207.h new file mode 100644 index 0000000..69689a4 --- /dev/null +++ b/src/superio/smsc/lpc47n207/lpc47n207.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SMSC_LPC47N207_LPC47N207_H +#define SUPERIO_SMSC_LPC47N207_LPC47N207_H + +extern void try_enabling_LPC47N207_uart(void); + +#endif [View Less]

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Patch merged into coreboot/master: b16b60f Add Sandybridge/Cougar Point support to SMM relocation handler
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit b16b60fd585a776063526ccf589d6b21480ea174 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Apr 5 15:59:33 2012 -0700 Add Sandybridge/Cougar Point support to SMM relocation handler Previously this part of smmrelocate.S had to be omitted because the CONFIG_ options for those components did not exist yet. Add them back. Change-Id: I6ac94ca804e03062724401a08d1d174adac5e830 Signed-off-by: … [View More]

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Patch merged into coreboot/master: 6cacede Cache 8MB flash instead of 4MB
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit 6cacede10e33019d6cbf2486f51f11ecaf3a797b Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:24:37 2012 -0700 Cache 8MB flash instead of 4MB Also fix the MTRR check to use the total_mtrrs variable instead of a hardcoded 8. Change-Id: I2c5ceb3910cd949f43ecf5b8aff857d6ffe0b1a5 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Build-Tested: build bot (Jenkins) at Fri Apr 6 … [View More]

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Patch merged into coreboot/master: 2196604 Factor out function to find driver for a CPU
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit 21966043fe2519e1b48809a40bf407c7e653d094 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:07:56 2012 -0700 Factor out function to find driver for a CPU This function can be used outside of the normal CPU setup Change-Id: I810c63b8aff868a6f69d5b992bea1cfae5a5996b Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com… [View More]

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Patch set updated for coreboot: 1bd74b4 Add initial support for SMSC SIO1007 SuperI/O chip
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/824 -gerrit commit 1bd74b430fe3917da5497a1342f2a946ca87aaf4 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:10:07 2012 -0700 Add initial support for SMSC SIO1007 SuperI/O chip early_serial and some ACPI needed for compilation Change-Id: I5dd970676488697156e0630392884f31149ac85b Signed-off-by: Gabe … [View More]Black <gabeblack(a)google.com> --- src/superio/smsc/Kconfig | 2 + src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/sio1007/acpi/superio.asl | 299 +++++++++++++++++++++++++++++ src/superio/smsc/sio1007/early_serial.c | 64 ++++++ 4 files changed, 366 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index d4f07ec..224376b 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -36,6 +36,8 @@ config SUPERIO_SMSC_LPC47N227 bool config SUPERIO_SMSC_SIO10N268 bool +config SUPERIO_SMSC_SIO1007 + bool config SUPERIO_SMSC_KBC1100 bool config SUPERIO_SMSC_SMSCSUPERIO diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index d07afea..bb4bf1d 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -27,6 +27,7 @@ subdirs-y += lpc47m15x subdirs-y += lpc47n217 subdirs-y += lpc47n227 subdirs-y += sio10n268 +subdirs-y += sio1007 subdirs-y += kbc1100 subdirs-y += smscsuperio subdirs-y += sio1036 diff --git a/src/superio/smsc/sio1007/acpi/superio.asl b/src/superio/smsc/sio1007/acpi/superio.asl new file mode 100644 index 0000000..5bb45fa --- /dev/null +++ b/src/superio/smsc/sio1007/acpi/superio.asl @@ -0,0 +1,299 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) { + Name (_ADR, 0x2E) + OperationRegion (SIOA, SystemIO, 0x2E, 0x02) + Field (SIOA, ByteAcc, NoLock, Preserve) + { + SI2E, 8, + SI2F, 8, + } + + IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + SCNT, 8, /* Configure Control */ + Offset (0x07), + SLDN, 8, /* Logical Device Number */ + Offset (0x30), + SACT, 8, /* Activate */ + Offset (0x60), + IO0H, 8, /* Base Address 0 MSB */ + IO0L, 8, /* Base Address 0 LSB */ + Offset (0x62), + IO1H, 8, /* Base Address 1 MSB */ + IO1L, 8, /* Base Address 1 LSB */ + Offset (0x70), + IQ00, 8, /* Interrupt Select */ + } + + Name (SFDC, 0) /* Floppy Disk Controller */ + Name (SSP1, 1) /* Serial Port 1 */ + Name (SENV, 4) /* Environment Controller */ + Name (SKBC, 5) /* Keyboard */ + Name (SKBM, 6) /* Mouse */ + Name (SGPI, 7) /* GPIO */ + Name (SINF, 10) /* Consumer IR */ + + Method (ENTR, 0, NotSerialized) + { + Store (0x87, SI2E) + Store (0x01, SI2E) + Store (0x55, SI2E) + Store (0x55, SI2E) + } + + Method (EXIT, 0, NotSerialized) + { + Store (0x02, SCNT) + } + + /* Parse activate register for an LDN */ + Method (ISEN, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (SACT, Local0) + EXIT () + + /* Check if it exists */ + If (LEqual (Local0, 0xFF)) + { + Return (0x00) + } + + /* Check if activated */ + If (LEqual (Local0, One)) + { + Return (0x0F) + } + Else + { + Return (0x0D) + } + } + + /* Enable an LDN via the activate register */ + Method (SENA, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (One, SACT) + EXIT () + } + + /* Disable an LDN via the activate register */ + Method (SDIS, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (Zero, SACT) + EXIT () + } + +#ifdef SIO_ENABLE_ENVC + Device (ENVC) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 10) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SENV)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08) + IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08) + IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04) + }) + + OperationRegion (ECAP, SystemIO, SIO_ENVC_IO0, 0x07) + Field (ECAP, ByteAcc, NoLock, Preserve) + { + Offset (0x05), + ECAI, 8, // Address Index Register + ECAD, 8, // Address Data Register + } + + // Registers for thermal zone implementations + IndexField (ECAI, ECAD, ByteAcc, NoLock, Preserve) + { + Offset (0x29), + TIN1, 8, // TMPIN1 Reading + TIN2, 8, // TMPIN2 Reading + TIN3, 8, // TMPIN3 Reading + Offset (0x6b), + F2PS, 8, // FAN2 PWM Setting + Offset (0x73), + F3PS, 8, // FAN3 PWM Setting + } + } +#endif + +#ifdef SIO_ENABLE_GPIO + Device (GPIO) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 11) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01) + IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01) + IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08) + }) + } +#endif + +#ifdef SIO_ENABLE_COM1 + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SSP1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + } +#endif + +#ifdef SIO_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SKBC)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + } +#endif + +#ifdef SIO_ENABLE_PS2M + Device (PS2M) // Mouse + { + Name (_HID, EISAID("PNP0F13")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SKBM)) + } + + Name (_CRS, ResourceTemplate() + { + IRQNoFlags () {12} + }) + + Name (_PRS, ResourceTemplate() + { + IRQNoFlags () {12} + }) + } +#endif + +#ifdef SIO_ENABLE_FDC0 + Device (FDC0) // Floppy controller + { + Name (_HID, EISAID ("PNP0700")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SFDC)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + } +#endif + +#ifdef SIO_ENABLE_INFR + Device (INFR) // Infrared controller + { + Name (_HID, EISAID ("PNP0510")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SINF)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08) + IRQNoFlags () { SIO_INFR_IRQ } + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08) + IRQNoFlags () { SIO_INFR_IRQ } + }) + } +#endif +} diff --git a/src/superio/smsc/sio1007/early_serial.c b/src/superio/smsc/sio1007/early_serial.c new file mode 100644 index 0000000..859e351 --- /dev/null +++ b/src/superio/smsc/sio1007/early_serial.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * The chip could be bootstrap mapped to one of four LPC addresses: + * 0x2e, 0x4e, 0x162e, and 0x164e. + */ +const u16 sio1007_lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e}; + +static void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask) +{ + u8 reg_value; + + outb(reg, lpc_port); + reg_value = inb(lpc_port + 1); + reg_value &= ~mask; + reg_value |= (value & mask); + outb(reg_value, lpc_port + 1); +} + +static int sio1007_enable_uart_at(u16 port) +{ + /* Enable config mode. */ + outb(0x55, port); + if (inb(port) != 0x55) + return 0; /* There is no LPC device at this address. */ + + /* Registers 12 and 13 hold config address, look for a match. */ + outb(0x12, port); + if (inb(port + 1) != (port & 0xff)) + return 0; + + outb(0x13, port); + if (inb(port + 1) != (port >> 8)) + return 0; + + /* This must be the sio1007, enable the UART. */ + /* turn on power */ + sio1007_setreg(port, 0x2, 1 << 3, 1 << 3); + /* enable high speed */ + sio1007_setreg(port, 0xc, 1 << 6, 1 << 6); + /* set the base address */ + sio1007_setreg(port, 0x24, CONFIG_TTYS0_BASE >> 2, 0xff); + + /* Disable config mode. */ + outb(0xaa, port); + return 1; +} [View Less]

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Patch set updated for coreboot: cadb0e4 Add support for SMSC MEC1308/1310 SuperI/O EC
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/825 -gerrit commit cadb0e43529ea4ea2a8ae885403506ad1b8242fe Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:12:22 2012 -0700 Add support for SMSC MEC1308/1310 SuperI/O EC Change-Id: If7921a66bab35f72c8455d5f0befc32a514ab417 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan … [View More]Reinauer <reinauer(a)google.com> --- src/superio/smsc/Kconfig | 2 + src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/mec1308/Makefile.inc | 20 +++ src/superio/smsc/mec1308/acpi/superio.asl | 261 +++++++++++++++++++++++++++++ src/superio/smsc/mec1308/chip.h | 33 ++++ src/superio/smsc/mec1308/mec1308.h | 27 +++ src/superio/smsc/mec1308/superio.c | 121 +++++++++++++ 7 files changed, 465 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 224376b..8d66fc5 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -40,6 +40,8 @@ config SUPERIO_SMSC_SIO1007 bool config SUPERIO_SMSC_KBC1100 bool +config SUPERIO_SMSC_MEC1308 + bool config SUPERIO_SMSC_SMSCSUPERIO bool config SUPERIO_SMSC_SIO1036 diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index bb4bf1d..8ebdf05 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -29,6 +29,7 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += sio1007 subdirs-y += kbc1100 +subdirs-y += mec1308 subdirs-y += smscsuperio subdirs-y += sio1036 subdirs-y += sch4037 diff --git a/src/superio/smsc/mec1308/Makefile.inc b/src/superio/smsc/mec1308/Makefile.inc new file mode 100644 index 0000000..b2b7baa --- /dev/null +++ b/src/superio/smsc/mec1308/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_MEC1308) += superio.c diff --git a/src/superio/smsc/mec1308/acpi/superio.asl b/src/superio/smsc/mec1308/acpi/superio.asl new file mode 100644 index 0000000..96f2ef8 --- /dev/null +++ b/src/superio/smsc/mec1308/acpi/superio.asl @@ -0,0 +1,261 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) { + OperationRegion (SIOA, SystemIO, 0x2E, 0x02) + Field (SIOA, ByteAcc, NoLock, Preserve) + { + SI2E, 8, + SI2F, 8, + } + + IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + SLDN, 8, /* Logical Device Number */ + Offset (0x30), + SACT, 8, /* Activate */ + Offset (0x60), + IO0H, 8, /* Base Address 0 MSB */ + IO0L, 8, /* Base Address 0 LSB */ + Offset (0x62), + IO1H, 8, /* Base Address 1 MSB */ + IO1L, 8, /* Base Address 1 LSB */ + Offset (0x70), + IQ00, 8, /* Interrupt Select */ + } + + Name (LPM1, 1) /* ACPI PM1 */ + Name (LEC1, 2) /* EC 1 */ + Name (LEC2, 3) /* EC 2 */ + Name (LSP1, 4) /* Serial Port */ + Name (LKBC, 7) /* Keyboard */ + Name (LEC0, 8) /* EC 0 */ + Name (LMBX, 9) /* Mailbox */ + + Method (ENTR, 0, NotSerialized) + { + Store (0x55, SI2E) + } + + Method (EXIT, 0, NotSerialized) + { + Store (0xaa, SI2E) + } + + /* Parse activate register for an LDN */ + Method (ISEN, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (SACT, Local0) + EXIT () + + /* Check if it exists */ + If (LEqual (Local0, 0xFF)) + { + Return (0x00) + } + + /* Check if activated */ + If (LEqual (Local0, One)) + { + Return (0x0F) + } + Else + { + Return (0x0D) + } + } + + /* Enable an LDN via the activate register */ + Method (SENA, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (One, SACT) + EXIT () + } + + /* Disable an LDN via the activate register */ + Method (SDIS, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (Zero, SACT) + EXIT () + } + +#ifdef SIO_ENABLE_SPM1 + Device (SPM1) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LPM1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08) + }) + } +#endif + +#ifdef SIO_ENABLE_SEC1 + Device (SEC1) { + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 2) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LEC1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04) + }) + } +#endif + +#ifdef SIO_ENABLE_SEC2 + Device (SEC2) { + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 3) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LEC2)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04) + }) + } +#endif + +#ifdef SIO_ENABLE_SSP1 + Device (SSP1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 4) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LSP1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08) + IRQNoFlags () {SIO_SSP1_IRQ} + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08) + IRQNoFlags () {SIO_SSP1_IRQ} + }) + } +#endif + +#ifdef SIO_ENABLE_SKBC + Device (SKBC) // Keyboard + { + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LKBC)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + } +#endif + +#ifdef SIO_ENABLE_SEC0 + Device (SEC0) { + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 8) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LEC0)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04) + }) + } +#endif + +#ifdef SIO_ENABLE_SMBX + Device (SMBX) // Mailbox + { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 9) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (LMBX)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34) + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34) + }) + } +#endif +} diff --git a/src/superio/smsc/mec1308/chip.h b/src/superio/smsc/mec1308/chip.h new file mode 100644 index 0000000..3826888 --- /dev/null +++ b/src/superio/smsc/mec1308/chip.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SMSC_MEC1308_CHIP_H +#define SUPERIO_SMSC_MEC1308_CHIP_H + +#include <pc80/keyboard.h> +#include <uart8250.h> + +struct chip_operations; +extern struct chip_operations superio_smsc_mec1308_ops; + +struct superio_smsc_mec1308_config { + struct pc_keyboard keyboard; +}; + +#endif diff --git a/src/superio/smsc/mec1308/mec1308.h b/src/superio/smsc/mec1308/mec1308.h new file mode 100644 index 0000000..2b61234 --- /dev/null +++ b/src/superio/smsc/mec1308/mec1308.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define MEC1308_PM1 1 +#define MEC1308_EC1 2 +#define MEC1308_EC2 3 +#define MEC1308_UART 4 +#define MEC1308_KBC 7 +#define MEC1308_EC0 8 +#define MEC1308_MBX 9 + diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c new file mode 100644 index 0000000..070871d --- /dev/null +++ b/src/superio/smsc/mec1308/superio.c @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC MEC1308 Super I/O chip */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <device/smbus.h> +#include <string.h> +#include <bitops.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include "chip.h" +#include "mec1308.h" +#if CONFIG_HAVE_ACPI_RESUME +#include <arch/acpi.h> +#endif + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} + +static void mec1308_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void mec1308_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void mec1308_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void mec1308_init(device_t dev) +{ + struct superio_smsc_mec1308_config *conf = dev->chip_info; + + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + case MEC1308_KBC: +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type == 3) + return; +#endif + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = mec1308_pnp_set_resources, + .enable_resources = mec1308_pnp_enable_resources, + .enable = mec1308_pnp_enable, + .init = mec1308_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, MEC1308_PM1, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_EC1, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_EC2, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_UART, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, MEC1308_KBC, PNP_IRQ0, { 0, 0 } /* IO Fixed at 0x60/0x64 */ }, + { &ops, MEC1308_EC0, PNP_IO0, { 0x7ff, 0 } }, + { &ops, MEC1308_MBX, PNP_IO0, { 0x7ff, 0 } }, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_smsc_mec1308_ops = { + CHIP_NAME("SMSC MEC1308 EC SuperIO Interface") + .enable_dev = enable_dev +}; + [View Less]

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Patch set updated for coreboot: bf1ba52 Add support for SMSC LPC47N207 SuperI/O chip
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/823 -gerrit commit bf1ba5280ae594a549685453e7abf9d00b96baba Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 15:06:04 2012 -0700 Add support for SMSC LPC47N207 SuperI/O chip This includes only early serial support for now. Change-Id: I9a2a439e1d17a989428033fdb4a4b813553dab6d Signed-off-by: Vadim … [View More]Bendebury <vbendeb(a)chromium.org> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/superio/smsc/lpc47n207/early_serial.c | 99 +++++++++++++++++++++++++++++ src/superio/smsc/lpc47n207/lpc47n207.h | 25 +++++++ 2 files changed, 124 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c new file mode 100644 index 0000000..5532941 --- /dev/null +++ b/src/superio/smsc/lpc47n207/early_serial.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * This code tries to discover the SMSC LPC47N207 superio chip which can be + * connected over an LPC dongle. The chip could be bootstrap mapped to one of + * four LPC addresses: 0x2e, 0x4e, 0x162e, and 0x164e. + * + * Initializing the UART requires accesses to a few control registers. This + * structure includes the register offset and the value to write (along with + * the mask). + */ +typedef struct { + u8 conf_reg; + u8 value; + u8 mask; +} uart_conf; + +/* All regs/values to write to initialize the LPC47N207 UART */ +static const uart_conf uart_conf_data [] = { + {2, (1 << 3), (1 << 3)}, /* cr02, enable Primary UART power */ + {0xc, (1 << 6), (1 << 6)}, /* cr0c, enable Primary UART high speed */ + {0x24, (CONFIG_TTYS0_BASE >> 3) << 1, 0xff}, /* cr24, base addr */ +}; + +void try_enabling_LPC47N207_uart(void) +{ + u8 reg_value; + const uart_conf* conf_item; + u16 lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e}; + u16 lpc_port; + int i, j; + +#define CONFIG_ENABLE 0x55 +#define CONFIG_DISABLE 0xaa + + for (j = 0; j < ARRAY_SIZE(lpc_ports); j++) { + lpc_port = lpc_ports[j]; + + /* enable CONFIG mode */ + outb(CONFIG_ENABLE, lpc_port); + reg_value=inb(lpc_port); + if (reg_value != CONFIG_ENABLE) { + continue; /* There is no LPC device at this address */ + } + + do { + /* + * Registers 12 and 13 hold config address, look for a + * match. + */ + outb(0x12, lpc_port); + reg_value=inb(lpc_port + 1); + if (reg_value != (lpc_port & 0xff)) + break; + + outb(0x13, lpc_port); + reg_value=inb(lpc_port + 1); + if (reg_value != (lpc_port >> 8)) + break; + + /* This must be the SMSC LPC 47N207, enable the UART. */ + for (i = 0; i < ARRAY_SIZE(uart_conf_data); i++) { + u8 reg, value, mask; + + conf_item = uart_conf_data + i; + + reg = conf_item->conf_reg; + value = conf_item->value; + mask = conf_item->mask; + + outb(reg, lpc_port); + reg_value = inb(lpc_port + 1); + reg_value &= ~mask; + reg_value |= (value & mask); + outb(reg_value, lpc_port + 1); + } + /* Keep COMA UART enable bit on */ + saved_basic_config |= COMA_LPC_EN; + } while (0); + outb(CONFIG_DISABLE, lpc_port); + } +} diff --git a/src/superio/smsc/lpc47n207/lpc47n207.h b/src/superio/smsc/lpc47n207/lpc47n207.h new file mode 100644 index 0000000..69689a4 --- /dev/null +++ b/src/superio/smsc/lpc47n207/lpc47n207.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SMSC_LPC47N207_LPC47N207_H +#define SUPERIO_SMSC_LPC47N207_LPC47N207_H + +extern void try_enabling_LPC47N207_uart(void); + +#endif [View Less]

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New patch to review for coreboot: dc63ffb Fill out ChromeOS specific coreboot table extensions
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/866 -gerrit commit dc63ffbd1863337c3b61dd0ea784b4fd7c475a3d Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 5 21:22:02 2012 +0200 Fill out ChromeOS specific coreboot table extensions ChromeOS uses two extensions to the coreboot table: - ChromeOS specific GPIO description for onboard switches - position … [View More]of verified boot area in nvram Change-Id: I8c389feec54c00faf2770aafbfd2223ac9da1362 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/coreboot_table.c | 43 +++++++++++++++++++++++++++ src/arch/x86/include/arch/coreboot_tables.h | 2 + src/include/boot/coreboot_tables.h | 36 ++++++++++++++++++++++ 3 files changed, 81 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index a9ff6f0..219de7a 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -179,6 +179,39 @@ static void lb_framebuffer(struct lb_header *header) #endif } +#if CONFIG_CHROMEOS +static void lb_gpios(struct lb_header *header) +{ + struct lb_gpios *gpios; + gpios = (struct lb_gpios *)lb_new_record(header); + gpios->tag = LB_TAG_GPIO; + gpios->size = sizeof(*gpios); + gpios->count = 0; + fill_lb_gpios(gpios); +} + +static void lb_vdat(struct lb_header *header) +{ + struct lb_vdat* vdat; + + vdat = (struct lb_vdat *)lb_new_record(header); + vdat->tag = LB_TAG_VDAT; + vdat->size = sizeof(*vdat); + acpi_get_vdat_info(&vdat->vdat_addr, &vdat->vdat_size); +} + +static void lb_vbnv(struct lb_header *header) +{ + struct lb_vbnv* vbnv; + + vbnv = (struct lb_vbnv *)lb_new_record(header); + vbnv->tag = LB_TAG_VBNV; + vbnv->size = sizeof(*vbnv); + vbnv->vbnv_start = CONFIG_VBNV_OFFSET + 14; + vbnv->vbnv_size = CONFIG_VBNV_SIZE; +} +#endif + static void add_cbmem_pointers(struct lb_header *header) { /* @@ -654,6 +687,16 @@ unsigned long write_coreboot_table( /* Record our framebuffer */ lb_framebuffer(head); +#if CONFIG_CHROMEOS + /* Record our GPIO settings (ChromeOS specific) */ + lb_gpios(head); + + /* pass along the VDAT buffer adress */ + lb_vdat(head); + + /* pass along VBNV offsets in CMOS */ + lb_vbnv(head); +#endif add_cbmem_pointers(head); /* Remember where my valid memory ranges are */ diff --git a/src/arch/x86/include/arch/coreboot_tables.h b/src/arch/x86/include/arch/coreboot_tables.h index 773e053..b177949 100644 --- a/src/arch/x86/include/arch/coreboot_tables.h +++ b/src/arch/x86/include/arch/coreboot_tables.h @@ -20,4 +20,6 @@ struct lb_memory *get_lb_mem(void); int add_mainboard_resources(struct lb_memory *mem); int add_northbridge_resources(struct lb_memory *mem); +void fill_lb_gpios(struct lb_gpios *gpios); + #endif /* COREBOOT_TABLE_H */ diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 5535a38..5d5ca2c 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -195,6 +195,33 @@ struct lb_framebuffer { uint8_t reserved_mask_size; }; +#define LB_TAG_GPIO 0x0013 + +struct lb_gpio { + uint32_t port; + uint32_t polarity; + uint32_t value; +#define GPIO_MAX_NAME_LENGTH 16 + uint8_t name[GPIO_MAX_NAME_LENGTH]; +}; + +struct lb_gpios { + uint32_t tag; + uint32_t size; + + uint32_t count; + struct lb_gpio gpios[0]; +}; + +#define LB_TAG_VDAT 0x0015 +struct lb_vdat { + uint32_t tag; + uint32_t size; + + void *vdat_addr; + uint32_t vdat_size; +}; + #define LB_TAG_TIMESTAMPS 0x0016 #define LB_TAG_CBMEM_CONSOLE 0x0017 #define LB_TAG_MRC_CACHE 0x0018 @@ -205,6 +232,15 @@ struct lb_cbmem_ref { void *cbmem_addr; }; +#define LB_TAG_VBNV 0x0019 +struct lb_vbnv { + uint32_t tag; + uint32_t size; + + uint32_t vbnv_start; + uint32_t vbnv_size; +}; + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ [View Less]

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Patch set updated for coreboot: a529a47 Don't loop infinitely long on serial comm failures
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/826 -gerrit commit a529a4718a63f7e0853b4c9dd32ec1c77cc7bb2c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 16:19:31 2012 -0700 Don't loop infinitely long on serial comm failures If serial uart (8250/16x50) takes abnormally long to respond, give up on logging to serial console and instead let the system boot. … [View More] Also reference bit in LSR register with correct name. Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Ported from 9dd3ef165a1bf1bc404056d3e54337de1a15ac90 to uart8250mem.c: Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: Iaca4f57389c887110e6406d45053935891c96838 --- src/lib/uart8250mem.c | 32 +++++++++++++++++++++++--------- 1 files changed, 23 insertions(+), 9 deletions(-) diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index a38623e..b98cb0e 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -27,24 +27,34 @@ #if !defined(__SMM__) && !defined(__PRE_RAM__) #include <device/device.h> #endif +#include <delay.h> /* Should support 8250, 16450, 16550, 16550A type UARTs */ +/* Expected character delay at 1200bps is 9ms for a working UART + * and no flow-control. Assume UART as stuck if shift register + * or FIFO takes more than 50ms per character to appear empty. + */ +#define SINGLE_CHAR_TIMEOUT (50 * 1000) +#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) + static inline int uart8250_mem_can_tx_byte(unsigned base_port) { - return read8(base_port + UART_LSR) & UART_MSR_DSR; + return read8(base_port + UART_LSR) & UART_LSR_THRE; } static inline void uart8250_mem_wait_to_tx_byte(unsigned base_port) { - while(!uart8250_mem_can_tx_byte(base_port)) - ; + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while(i-- && !uart8250_mem_can_tx_byte(base_port)) + udelay(1); } static inline void uart8250_mem_wait_until_sent(unsigned base_port) { - while(!(read8(base_port + UART_LSR) & UART_LSR_TEMT)) - ; + unsigned long int i = FIFO_TIMEOUT; + while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT)) + udelay(1); } void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) @@ -65,9 +75,13 @@ int uart8250_mem_can_rx_byte(unsigned base_port) unsigned char uart8250_mem_rx_byte(unsigned base_port) { - while(!uart8250_mem_can_rx_byte(base_port)) - ; - return read8(base_port + UART_RBR); + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while(i-- && !uart8250_mem_can_rx_byte(base_port)) + udelay(1); + if (i) + return read8(base_port + UART_RBR); + else + return 0x0; } void uart8250_mem_init(unsigned base_port, unsigned divisor) @@ -83,7 +97,7 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor) /* DLAB on */ write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS); - /* Set Baud Rate Divisor. 12 ==> 115200 Baud */ + /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ write8(base_port + UART_DLL, divisor & 0xFF); write8(base_port + UART_DLM, (divisor >> 8) & 0xFF); [View Less]

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Patch set updated for coreboot: c5695eb Fixes and Sandybridge support for lapic cpu init
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/871 -gerrit commit c5695eb38966e6ed70ef3396cb541da6372e475f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:17:11 2012 -0700 Fixes and Sandybridge support for lapic cpu init - preprocessor macros should not use defined(CONFIG_*) but just CONFIG_* - skip some delays on Sandybridge systems - Count how … [View More]long we're waiting for each AP to stop - Skip speedstep specific CPU entries Change-Id: I13db384ba4e28acbe7f0f8c9cd169954b39f167d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/lapic/lapic_cpu_init.c | 15 +++++++++++---- src/include/cpu/intel/speedstep.h | 3 +++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index ed9940c..d650716 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -14,6 +14,7 @@ #include <smp/atomic.h> #include <smp/spinlock.h> #include <cpu/cpu.h> +#include <cpu/intel/speedstep.h> #if CONFIG_SMP == 1 /* This is a lot more paranoid now, since Linux can NOT handle @@ -108,7 +109,7 @@ static int lapic_start_cpu(unsigned long apicid) } return 0; } -#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) +#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_AMD_MODEL_14XXX && !CONFIG_CPU_INTEL_MODEL_206AX mdelay(10); #endif @@ -136,7 +137,7 @@ static int lapic_start_cpu(unsigned long apicid) start_eip = get_valid_start_eip((unsigned long)_secondary_start); -#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) +#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_AMD_MODEL_14XXX num_starts = 2; #else num_starts = 1; @@ -269,7 +270,7 @@ int start_cpu(device_t cpu) break; } udelay(10); - } + } } secondary_stack = 0; spin_unlock(&start_cpu_lock); @@ -446,6 +447,8 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) { device_t cpu; int old_active_count, active_count; + long loopcount = 0; + /* Now loop until the other cpus have finished initializing */ old_active_count = 1; active_count = atomic_read(&active_cpus); @@ -456,17 +459,21 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) } udelay(10); active_count = atomic_read(&active_cpus); + loopcount++; } for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { if (cpu->path.type != DEVICE_PATH_APIC) { continue; } + if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) { + continue; + } if (!cpu->initialized) { printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n", cpu->path.apic.apic_id); } } - printk(BIOS_DEBUG, "All AP CPUs stopped\n"); + printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } #else /* CONFIG_SMP */ diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 0fa5244..00a5b9b 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -19,6 +19,9 @@ * MA 02110-1301 USA */ +/* Magic value used to locate speedstep configuration in the device tree */ +#define SPEEDSTEP_APIC_MAGIC 0xACAC + /* MWAIT coordination I/O base address. This must match * the \_PR_.CPU0 PM base address. */ [View Less]

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New patch to review for coreboot: b16b60f Add Sandybridge/Cougar Point support to SMM relocation handler
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/874 -gerrit commit b16b60fd585a776063526ccf589d6b21480ea174 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Apr 5 15:59:33 2012 -0700 Add Sandybridge/Cougar Point support to SMM relocation handler Previously this part of smmrelocate.S had to be omitted because the CONFIG_ options for those components did not exist yet. … [View More]

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Asus M2N68-LA HP Narra 2
by Marc Dunivan 05 Apr '12

05 Apr '12

I have and old HP Pavillion with an Asus M2N68-LA Narra 2 mother board. Coreboot hasn't been ported to it. Not asking for it either. I just want to know the northbridge and southbridge it has.

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Patch set updated for coreboot: 6cacede Cache 8MB flash instead of 4MB
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/873 -gerrit commit 6cacede10e33019d6cbf2486f51f11ecaf3a797b Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:24:37 2012 -0700 Cache 8MB flash instead of 4MB Also fix the MTRR check to use the total_mtrrs variable instead of a hardcoded 8. Change-Id: I2c5ceb3910cd949f43ecf5b8aff857d6ffe0b1a5 Signed-… [View More]off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/mtrr/mtrr.c | 46 +++++++++++++++++++++------------------------- 1 files changed, 21 insertions(+), 25 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index ed7d93b..c310905 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -50,6 +50,24 @@ static unsigned int mtrr_msr[] = { MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, }; +/* 2 MTRRS are reserved for the operating system */ +#define BIOS_MTRRS 6 +#define OS_MTRRS 2 +#define MTRRS (BIOS_MTRRS + OS_MTRRS) + +static int total_mtrrs = MTRRS; +static int bios_mtrrs = BIOS_MTRRS; + +static void detect_var_mtrrs(void) +{ + msr_t msr; + + msr = rdmsr(MTRRcap_MSR); + + total_mtrrs = msr.lo & 0xff; + bios_mtrrs = total_mtrrs - OS_MTRRS; +} + void enable_fixed_mtrr(void) { msr_t msr; @@ -76,8 +94,8 @@ static void set_var_mtrr( msr_t base, mask; unsigned address_mask_high; - if (reg >= 8) - return; + if (reg >= total_mtrrs) + return; // it is recommended that we disable and enable cache when we // do this. @@ -169,28 +187,6 @@ static inline unsigned int fls(unsigned int x) * or a 156MB (128MB + 32MB - 4MB SMA) example: * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB) */ -/* 2 MTRRS are reserved for the operating system */ -#if 1 -#define BIOS_MTRRS 6 -#define OS_MTRRS 2 -#else -#define BIOS_MTRRS 8 -#define OS_MTRRS 0 -#endif -#define MTRRS (BIOS_MTRRS + OS_MTRRS) - -static int total_mtrrs = MTRRS; -static int bios_mtrrs = BIOS_MTRRS; - -static void detect_var_mtrrs(void) -{ - msr_t msr; - - msr = rdmsr(MTRRcap_MSR); - - total_mtrrs = msr.lo & 0xff; - bios_mtrrs = total_mtrrs - 2; -} static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type) { @@ -504,7 +500,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) * complete ROM now that we actually have RAM. */ if (boot_cpu() && (acpi_slp_type != 3)) { - set_var_mtrr(total_mtrrs-1, (4096-4)*1024, 4*1024, + set_var_mtrr(total_mtrrs - 1, (4096 - 8)*1024, 8 * 1024, MTRR_TYPE_WRPROT, address_bits); } #endif [View Less]

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Patch merged into coreboot/master: 5a596f7 Add constants for fast path resume copying
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit 5a596f7a8fb66d12c2888d8bb91ea883c2fceea0 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:21:04 2012 -0700 Add constants for fast path resume copying cache as ram does not usually cache the ram before it is up. Hence, if romstage.c backs up resume memory, the involved memcpy is always uncached. This makes resume very slow. On Sandybridge we copy the memory later, after enabling … [View More]

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Patch set updated for coreboot: ff29084 Fixes and Sandybridge support for lapic cpu init
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/871 -gerrit commit ff290840a59fd26c3f4da4095344e0429d402866 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:17:11 2012 -0700 Fixes and Sandybridge support for lapic cpu init - preprocessor macros should not use defined(CONFIG_*) but just CONFIG_* - skip some delays on Sandybridge systems - Count how … [View More]long we're waiting for each AP to stop - Skip speedstep specific CPU entries Change-Id: I13db384ba4e28acbe7f0f8c9cd169954b39f167d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/intel/speedstep/chip.h | 35 +++++++++++++++++++++++++++++++++++ src/cpu/x86/lapic/lapic_cpu_init.c | 13 ++++++++++--- 2 files changed, 45 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/speedstep/chip.h b/src/cpu/intel/speedstep/chip.h new file mode 100644 index 0000000..44f336a --- /dev/null +++ b/src/cpu/intel/speedstep/chip.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_intel_speedstep_ops; + +/* Magic value used to locate this chip in the device tree */ +#define SPEEDSTEP_APIC_MAGIC 0xACAC + +struct cpu_intel_speedstep_config { + u8 pstate_coord_type; /* Processor Coordination Type */ + + int c1_battery; /* CPU C-state for ACPI C1 on Battery Power */ + int c2_battery; /* CPU C-state for ACPI C2 on Battery Power */ + int c3_battery; /* CPU C-state for ACPI C3 on Battery Power */ + + int c1_acpower; /* CPU C-state for ACPI C1 on AC Power */ + int c2_acpower; /* CPU C-state for ACPI C2 on AC Power */ + int c3_acpower; /* CPU C-state for ACPI C3 on AC Power */ +}; diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index ed9940c..61a0f87 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -14,6 +14,7 @@ #include <smp/atomic.h> #include <smp/spinlock.h> #include <cpu/cpu.h> +#include <cpu/intel/speedstep/chip.h> #if CONFIG_SMP == 1 /* This is a lot more paranoid now, since Linux can NOT handle @@ -108,7 +109,7 @@ static int lapic_start_cpu(unsigned long apicid) } return 0; } -#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) +#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_AMD_MODEL_14XXX && !CONFIG_CPU_INTEL_MODEL_206AX mdelay(10); #endif @@ -136,7 +137,7 @@ static int lapic_start_cpu(unsigned long apicid) start_eip = get_valid_start_eip((unsigned long)_secondary_start); -#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) +#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_AMD_MODEL_14XXX num_starts = 2; #else num_starts = 1; @@ -446,6 +447,8 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) { device_t cpu; int old_active_count, active_count; + long loopcount = 0; + /* Now loop until the other cpus have finished initializing */ old_active_count = 1; active_count = atomic_read(&active_cpus); @@ -456,17 +459,21 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) } udelay(10); active_count = atomic_read(&active_cpus); + loopcount++; } for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { if (cpu->path.type != DEVICE_PATH_APIC) { continue; } + if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) { + continue; + } if (!cpu->initialized) { printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n", cpu->path.apic.apic_id); } } - printk(BIOS_DEBUG, "All AP CPUs stopped\n"); + printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } #else /* CONFIG_SMP */ [View Less]

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Patch set updated for coreboot: 2196604 Factor out function to find driver for a CPU
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/868 -gerrit commit 21966043fe2519e1b48809a40bf407c7e653d094 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:07:56 2012 -0700 Factor out function to find driver for a CPU This function can be used outside of the normal CPU setup Change-Id: I810c63b8aff868a6f69d5b992bea1cfae5a5996b Signed-off-by: Duncan … [View More]

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Patch merged into coreboot/master: 1a50b63 Fix timer frequency detection on Sandybridge
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit 1a50b63b220d62ad987e6c7882e8a83a8f3d680c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:11:02 2012 -0700 Fix timer frequency detection on Sandybridge Change-Id: Ide720bd91cde56a0afdd231d93500c371b1ffbe8 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Thu Apr 5 23:31:19 2012, … [View More]

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Patch merged into coreboot/master: beca17b amdfam10: add phenom II as known cpu
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit beca17b9dc211fa2c8424083724c28c5f37d52bf Author: Bernhard Urban <lewurm(a)gmail.com> Date: Thu Apr 5 17:13:27 2012 +0200 amdfam10: add phenom II as known cpu Change-Id: I84a0f9e8e7a15c0aac8dc380de3ddf70b1decbd7 Signed-off-by: Bernhard Urban <lewurm(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Apr 5 17:28:37 2012, giving +1 See http://review.coreboot.org/864 for details. -gerrit

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Patch merged into coreboot/master: 6e6e012 smbios: Don't fill out firmware version on ChromeOS
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit 6e6e0125ce79d04956ef818fcb247215aec04840 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:02:54 2012 -0700 smbios: Don't fill out firmware version on ChromeOS In ChromeOS we potentially have different payloads with different versions. Since the user land tools get information on which one of them is loaded, leave the string in smbios empty so we can fill it out in the payload. … [View More]

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Patch merged into coreboot/master: dc63ffb Fill out ChromeOS specific coreboot table extensions
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit dc63ffbd1863337c3b61dd0ea784b4fd7c475a3d Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 5 21:22:02 2012 +0200 Fill out ChromeOS specific coreboot table extensions ChromeOS uses two extensions to the coreboot table: - ChromeOS specific GPIO description for onboard switches - position of verified boot area in nvram Change-Id: I8c389feec54c00faf2770aafbfd2223ac9da1362 … [View More]

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Patch merged into coreboot/master: 5d5628a Update documentation in smmrelocate.S to mention TSEG
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit 5d5628a869a1369bb9640ffc25384a3618373bac Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 10:38:05 2012 -0700 Update documentation in smmrelocate.S to mention TSEG Change-Id: I392f5fc475b15b458fc015e176e45888e7de27fb Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Thu Apr 5 21:52:25 2012, giving +1 Reviewed-By: Stefan Reinauer <… [View More]

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New patch to review for coreboot: c72ad05 Cache 8MB flash instead of 4MB
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/873 -gerrit commit c72ad05e7b3e38f3366bf37f11adfcc6ce42c36f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:24:37 2012 -0700 Cache 8MB flash instead of 4MB Also fix the MTRR check to use the total_mtrrs variable instead of a hardcoded 8. Change-Id: I2c5ceb3910cd949f43ecf5b8aff857d6ffe0b1a5 Signed-… [View More]off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/mtrr/mtrr.c | 47 +++++++++++++++++++++-------------------------- 1 files changed, 21 insertions(+), 26 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index ed7d93b..faa0d93 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -37,7 +37,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> -#include <arch/cpu.h> #include <arch/acpi.h> #if CONFIG_GFXUMA @@ -50,6 +49,24 @@ static unsigned int mtrr_msr[] = { MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, }; +/* 2 MTRRS are reserved for the operating system */ +#define BIOS_MTRRS 6 +#define OS_MTRRS 2 +#define MTRRS (BIOS_MTRRS + OS_MTRRS) + +static int total_mtrrs = MTRRS; +static int bios_mtrrs = BIOS_MTRRS; + +static void detect_var_mtrrs(void) +{ + msr_t msr; + + msr = rdmsr(MTRRcap_MSR); + + total_mtrrs = msr.lo & 0xff; + bios_mtrrs = total_mtrrs - 2; +} + void enable_fixed_mtrr(void) { msr_t msr; @@ -76,8 +93,8 @@ static void set_var_mtrr( msr_t base, mask; unsigned address_mask_high; - if (reg >= 8) - return; + if (reg >= total_mtrrs) + return; // it is recommended that we disable and enable cache when we // do this. @@ -169,28 +186,6 @@ static inline unsigned int fls(unsigned int x) * or a 156MB (128MB + 32MB - 4MB SMA) example: * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB) */ -/* 2 MTRRS are reserved for the operating system */ -#if 1 -#define BIOS_MTRRS 6 -#define OS_MTRRS 2 -#else -#define BIOS_MTRRS 8 -#define OS_MTRRS 0 -#endif -#define MTRRS (BIOS_MTRRS + OS_MTRRS) - -static int total_mtrrs = MTRRS; -static int bios_mtrrs = BIOS_MTRRS; - -static void detect_var_mtrrs(void) -{ - msr_t msr; - - msr = rdmsr(MTRRcap_MSR); - - total_mtrrs = msr.lo & 0xff; - bios_mtrrs = total_mtrrs - 2; -} static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type) { @@ -504,7 +499,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) * complete ROM now that we actually have RAM. */ if (boot_cpu() && (acpi_slp_type != 3)) { - set_var_mtrr(total_mtrrs-1, (4096-4)*1024, 4*1024, + set_var_mtrr(total_mtrrs-1, (4096-8)*1024, 8*1024, MTRR_TYPE_WRPROT, address_bits); } #endif [View Less]

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New patch to review for coreboot: 5a596f7 Add constants for fast path resume copying
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/872 -gerrit commit 5a596f7a8fb66d12c2888d8bb91ea883c2fceea0 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:21:04 2012 -0700 Add constants for fast path resume copying cache as ram does not usually cache the ram before it is up. Hence, if romstage.c backs up resume memory, the involved memcpy is always … [View More]

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New patch to review for coreboot: 06f59dd Fixes and Sandybridge support for lapic cpu init
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/871 -gerrit commit 06f59ddf04321026f9a6794f2eadba6cab3f4508 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:17:11 2012 -0700 Fixes and Sandybridge support for lapic cpu init - preprocessor macros should not use defined(CONFIG_*) but just CONFIG_* - skip some delays on Sandybridge systems - Count how … [View More]long we're waiting for each AP to stop - Skip speedstep specific CPU entries Change-Id: I13db384ba4e28acbe7f0f8c9cd169954b39f167d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/lapic/lapic_cpu_init.c | 13 ++++++++++--- 1 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index ed9940c..61a0f87 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -14,6 +14,7 @@ #include <smp/atomic.h> #include <smp/spinlock.h> #include <cpu/cpu.h> +#include <cpu/intel/speedstep/chip.h> #if CONFIG_SMP == 1 /* This is a lot more paranoid now, since Linux can NOT handle @@ -108,7 +109,7 @@ static int lapic_start_cpu(unsigned long apicid) } return 0; } -#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) +#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_AMD_MODEL_14XXX && !CONFIG_CPU_INTEL_MODEL_206AX mdelay(10); #endif @@ -136,7 +137,7 @@ static int lapic_start_cpu(unsigned long apicid) start_eip = get_valid_start_eip((unsigned long)_secondary_start); -#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) +#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_AMD_MODEL_14XXX num_starts = 2; #else num_starts = 1; @@ -446,6 +447,8 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) { device_t cpu; int old_active_count, active_count; + long loopcount = 0; + /* Now loop until the other cpus have finished initializing */ old_active_count = 1; active_count = atomic_read(&active_cpus); @@ -456,17 +459,21 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) } udelay(10); active_count = atomic_read(&active_cpus); + loopcount++; } for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { if (cpu->path.type != DEVICE_PATH_APIC) { continue; } + if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) { + continue; + } if (!cpu->initialized) { printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n", cpu->path.apic.apic_id); } } - printk(BIOS_DEBUG, "All AP CPUs stopped\n"); + printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } #else /* CONFIG_SMP */ [View Less]

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New patch to review for coreboot: 1a50b63 Fix timer frequency detection on Sandybridge
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/870 -gerrit commit 1a50b63b220d62ad987e6c7882e8a83a8f3d680c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:11:02 2012 -0700 Fix timer frequency detection on Sandybridge Change-Id: Ide720bd91cde56a0afdd231d93500c371b1ffbe8 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan … [View More]Reinauer <reinauer(a)google.com> --- src/cpu/x86/lapic/apic_timer.c | 48 ++++++++++++++++++++++++++++++---------- 1 files changed, 36 insertions(+), 12 deletions(-) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 826f5b6..bb6cca7 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <delay.h> +#include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> @@ -27,14 +28,40 @@ * memory init. */ -#define FSB_CLOCK_STS 0xcd +static u32 timer_fsb = 0; -static u32 timer_fsb = 200; // default to 200MHz +static int set_timer_fsb(void) +{ + struct cpuinfo_x86 c; + int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; + int core2_fsb[8] = { 266, 133, 200, 166, -1, 100, -1, -1 }; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return -1; + + switch (c.x86_model) { + case 0xe: /* Core Solo/Duo */ + case 0x1c: /* Atom */ + timer_fsb = core_fsb[rdmsr(0xcd).lo & 7]; + break; + case 0xf: /* Core 2*/ + case 0x17: /* Enhanced Core */ + timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7]; + break; + case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ + timer_fsb = 100; + break; + default: + timer_fsb = 200; + break; + } + + return 0; +} void init_timer(void) { - msr_t fsb_clock_sts; - /* Set the apic timer to no interrupts and periodic mode */ lapic_write(LAPIC_LVTT, (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)); @@ -45,19 +72,16 @@ void init_timer(void) lapic_write(LAPIC_TMICT, 0xffffffff); /* Set FSB frequency to a reasonable value */ - fsb_clock_sts = rdmsr(FSB_CLOCK_STS); - switch ((fsb_clock_sts.lo >> 4) & 0x07) { - case 0: timer_fsb = 266; break; - case 1: timer_fsb = 133; break; - case 2: timer_fsb = 200; break; - case 3: timer_fsb = 166; break; - case 5: timer_fsb = 100; break; - } + set_timer_fsb(); } void udelay(u32 usecs) { u32 start, value, ticks; + + if (!timer_fsb) + init_timer(); + /* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz */ ticks = usecs * timer_fsb; start = lapic_read(LAPIC_TMCCT); [View Less]

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New patch to review for coreboot: c35c461 Invalidate cache before first jump
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/869 -gerrit commit c35c461bb2146ab949062f22e265406deef178d2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:09:46 2012 -0700 Invalidate cache before first jump Some CPUs (Sandybridge) seem to require this, and it does not hurt on other CPUs. Change-Id: I4fdb281b2b684ab5fea999aae28ca08dce24da4d … [View More]

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New patch to review for coreboot: 231c8fa Factor out function to find driver for a CPU
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/868 -gerrit commit 231c8fae7b5da973f70d9769e6076ea1885bc3e7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:07:56 2012 -0700 Factor out function to find driver for a CPU This function can be used outside of the normal CPU setup Change-Id: I810c63b8aff868a6f69d5b992bea1cfae5a5996b Signed-off-by: Duncan … [View More]

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New patch to review for coreboot: 6e6e012 smbios: Don't fill out firmware version on ChromeOS
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/867 -gerrit commit 6e6e0125ce79d04956ef818fcb247215aec04840 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:02:54 2012 -0700 smbios: Don't fill out firmware version on ChromeOS In ChromeOS we potentially have different payloads with different versions. Since the user land tools get information on which one … [View More]of them is loaded, leave the string in smbios empty so we can fill it out in the payload. Also fill out system version number and serial number with some constant values. Change-Id: Id1fed5a54b511c730975fa83347452f1274b8504 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/smbios.c | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 2bd00c4..f39bf04 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -29,6 +29,9 @@ #include <cpu/x86/name.h> #include <cbfs_core.h> #include <arch/byteorder.h> +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/gnvs.h> +#endif static u8 smbios_checksum(u8 *p, u32 length) { @@ -126,8 +129,18 @@ static int smbios_write_type0(unsigned long *current, int handle) t->length = len - 2; t->vendor = smbios_add_string(t->eos, "coreboot"); +#if !CONFIG_CHROMEOS t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE); t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION); +#else +#define SPACES \ + " " + t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE); + u32 version_offset = (u32)smbios_string_table_len(t->eos); + t->bios_version = smbios_add_string(t->eos, SPACES); + /* SMBIOS offsets start at 1 rather than 0 */ + vboot_data->vbt10 = (u32)t->eos + (version_offset - 1); +#endif if ((hdr = get_cbfs_header()) != (struct cbfs_header *)0xffffffff) t->bios_rom_size = (ntohl(hdr->romsize) / 65535) - 1; @@ -160,6 +173,8 @@ static int smbios_write_type1(unsigned long *current, int handle) t->length = len - 2; t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_PART_NUMBER); + t->serial_number = smbios_add_string(t->eos, "123456789"); + t->version = smbios_add_string(t->eos, "1.0"); len = t->length + smbios_string_table_len(t->eos); *current += len; return len; [View Less]

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Patch set updated for coreboot: 5d5628a Update documentation in smmrelocate.S to mention TSEG
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/861 -gerrit commit 5d5628a869a1369bb9640ffc25384a3618373bac Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 10:38:05 2012 -0700 Update documentation in smmrelocate.S to mention TSEG Change-Id: I392f5fc475b15b458fc015e176e45888e7de27fb Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/… [View More]cpu/x86/smm/smmrelocate.S | 19 +++++++++++-------- 1 files changed, 11 insertions(+), 8 deletions(-) diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index bc5b2da..18d668c 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -54,13 +54,22 @@ .code16 /** - * This trampoline code relocates SMBASE to 0xa0000 - ( lapicid * 0x400 ) + * When starting up, x86 CPUs have their SMBASE set to 0x30000. However, + * this is not a good place for the SMM handler to live, so it needs to + * be relocated. + * Traditionally SMM handlers used to live in the A segment (0xa0000). + * With growing SMM handlers, more CPU cores, etc. CPU vendors started + * allowing to relocate the handler to the end of physical memory, which + * they refer to as TSEG. + * This trampoline code relocates SMBASE to base address - ( lapicid * 0x400 ) * * Why 0x400? It is a safe value to cover the save state area per CPU. On * current AMD CPUs this area is _documented_ to be 0x200 bytes. On Intel * Core 2 CPUs the _documented_ parts of the save state area is 48 bytes * bigger, effectively sizing our data structures 0x300 bytes. * + * Example (with SMM handler living at 0xa0000): + * * LAPICID SMBASE SMM Entry SAVE STATE * 0 0xa0000 0xa8000 0xafd00 * 1 0x9fc00 0xa7c00 0xaf900 @@ -88,13 +97,7 @@ * at 0xa8000-0xa8100 (example for core 0). That is not enough. * * This means we're basically limited to 16 cpu cores before - * we need to use the TSEG/HSEG for the actual SMM handler plus stack. - * When we exceed 32 cores, we also need to put SMBASE to TSEG/HSEG. - * - * If we figure out the documented values above are safe to use, - * we could pack the structure above even more, so we could use the - * scheme to pack save state areas for 63 AMD CPUs or 58 Intel CPUs - * in the ASEG. + * we need to move the SMM handler to TSEG. * * Note: Some versions of Pentium M need their SMBASE aligned to 32k. * On those the above only works for up to 2 cores. But for now we only [View Less]

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Patch merged into coreboot/master: 5cc6cb3 Add support for Intel Sandybridge CPU
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit 5cc6cb3584fb6e662fcdf8a526ec2d289e248380 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 00:09:50 2012 +0200 Add support for Intel Sandybridge CPU Change-Id: I9f37e291c00c0640c6600d8fdd6dcc13c3e5b8d5 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Wed Apr 4 02:01:17 2012, … [View More]

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Patch merged into coreboot/master: ff8097a Add support for Intel Sandybridge CPU (northbridge part)
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit ff8097ac89d47349ad72417959efcd8b47c70a69 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 00:08:51 2012 +0200 Add support for Intel Sandybridge CPU (northbridge part) Change-Id: I06228ecf9cac931ad34e32871d5a4f2a4857b2ac Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Wed Apr … [View More]

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Patch merged into coreboot/master: 4aeb1c8 Ignore .exe files in whitespace test
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit 4aeb1c857b3819e115b39b67b1379fbd2c21892d Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Apr 5 11:18:23 2012 +0200 Ignore .exe files in whitespace test On windows, we sometimes require getopt executables, which end up in the source tree. These shouldn't break the whitespace test. Change-Id: Iaf86e38b94605bebb69a317e00f932eefcf468b9 Signed-off-by: Patrick Georgi <patrick.georgi(a)… [View More]

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Patch merged into coreboot/master: 5f92c27 Add getopt implementation to abuild
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit 5f92c27db7619359919470fc43da1d5e1dd831f1 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Apr 5 11:17:01 2012 +0200 Add getopt implementation to abuild Similar to buildgcc, abuild requires getopt(1). Provide an implementation for platforms without it (Win32) Change-Id: I2ae4d84e06dd34135c97b18819da2b49a89706ce Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> See … [View More]

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Re: [coreboot] [Honest Request] Use Coreboot as BIOS for Server and Storage motherboard
by Peter Stuge 05 Apr '12

05 Apr '12

Kiran Patil wrote: > To make this project true "Open Compute Project", this Coreboot > BIOS software on Motherboard is essential. > > I request you to consider using Coreboot (www.coreboot.org) as BIOS > for Server and Storage motherboards used in Open Compute Project. Note that BIOS refers to a very specific set of OS<->firmware interfaces which have evolved over 30 years with little to no formal specification. coreboot is a BIOS replacement. coreboot can be combined … [View More]

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[Honest Request] Use Coreboot as BIOS for Server and Storage motherboard
by Kiran Patil 05 Apr '12

05 Apr '12

Kudos OCP experts, To make this project true "Open Compute Project", this Coreboot BIOS software on Motherboard is essential. I request you to consider using Coreboot (www.coreboot.org) as BIOS for Server and Storage motherboards used in Open Compute Project. You are all "Men of honour". -- Thanks, Kiran Patil. [image: Inline image 1][image: Inline image 2]

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New patch to review for coreboot: 4aeb1c8 Ignore .exe files in whitespace test
by Patrick Georgi 05 Apr '12

05 Apr '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/863 -gerrit commit 4aeb1c857b3819e115b39b67b1379fbd2c21892d Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Apr 5 11:18:23 2012 +0200 Ignore .exe files in whitespace test On windows, we sometimes require getopt executables, which end up in the source tree. These shouldn't break the whitespace test. Change-Id: … [View More]

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New patch to review for coreboot: 5f92c27 Add getopt implementation to abuild
by Patrick Georgi 05 Apr '12

05 Apr '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/862 -gerrit commit 5f92c27db7619359919470fc43da1d5e1dd831f1 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Apr 5 11:17:01 2012 +0200 Add getopt implementation to abuild Similar to buildgcc, abuild requires getopt(1). Provide an implementation for platforms without it (Win32) Change-Id: … [View More]I2ae4d84e06dd34135c97b18819da2b49a89706ce Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- util/abuild/abuild | 4 +++ util/abuild/getopt.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+), 0 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 74d2908..5b8d73d 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -563,6 +563,10 @@ test -f util/sconfig/sconfig.l && ROOT=$( pwd ) test -f ../util/sconfig/sconfig.l && ROOT=$( cd ..; pwd ) test "$ROOT" = "" && ROOT=$( cd ../..; pwd ) +# Look if we have getopt. If not, build it. +export PATH=$PATH:util/abuild +getopt - > /dev/null 2>/dev/null || gcc -o util/abuild/getopt util/abuild/getopt.c + # parse parameters.. try to find out whether we're running GNU getopt getoptbrand="`getopt -V`" if [ "${getoptbrand:0:6}" == "getopt" ]; then diff --git a/util/abuild/getopt.c b/util/abuild/getopt.c new file mode 100644 index 0000000..8476285 --- /dev/null +++ b/util/abuild/getopt.c @@ -0,0 +1,64 @@ +/* +Copyright (c) 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 + The DragonFly Project. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. +3. Neither the name of The DragonFly Project nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific, prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, +BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. +*/ + +/* $FreeBSD: src/usr.bin/getopt/getopt.c,v 1.4.2.2 2001/07/30 10:16:38 dd Exp $ */ +/* $DragonFly: src/usr.bin/getopt/getopt.c,v 1.4 2004/10/23 13:33:36 eirikn Exp $ */ + +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> + +int +main(int argc, char **argv) +{ + int c; + int status = 0; + + optind = 2; /* Past the program name and the option letters. */ + while ((c = getopt(argc, argv, argv[1])) != -1) + switch (c) { + case '?': + status = 1; /* getopt routine gave message */ + break; + default: + if (optarg != NULL) + printf(" -%c %s", c, optarg); + else + printf(" -%c", c); + break; + } + printf(" --"); + for (; optind < argc; optind++) + printf(" %s", argv[optind]); + printf("\n"); + return(status); +} [View Less]

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Re: [coreboot] GSoC project ideas
by Peter Stuge 04 Apr '12

04 Apr '12

Paul Geraedts wrote: > > The OLS is not a good fit for installation into e.g. a laptop. This > > is one of the use cases for a QiProg; it's intended to be soldered > > into the target system, on top of, or very near, the flash chip. > > Can you please post a reference to this QiProg device? I would like to > read more about it and Google does not seem to know it. The information available so far is the USB protocol at http://stuge.se/qiprog_protocol.txt and beyond … [View More]

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Re: [coreboot] GSoC project ideas
by Peter Stuge 04 Apr '12

04 Apr '12

Paul Geraedts wrote: > My hardware target is the Papilio platform in general [1]; I have one as well, can try to help test. > All current Papilio implementations (to which I count the OLS) rely > on UART over USB. They rely on UART, not USB. FPGA on OLS as well as Papilio has no idea that there is a USB connection at all. > I will try to make my VHDL cores so they will be compatible with > both types of boards. I plan to start with UART over USB support > for the … [View More]

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Patch set updated for coreboot: 58f3030 Add Southbridge support for S3.
by Zheng Bao 04 Apr '12

04 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/621 -gerrit commit 58f3030964d6ae7d446bd84c4bd3bd97481061a8 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 5 13:18:49 2012 +0800 Add Southbridge support for S3. 1. Add some CIMX call for S3. 2. Detect sleep type. Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-… [View More]off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/Makefile.inc | 11 +++++ src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 3 + src/southbridge/amd/cimx/sb800/cfg.c | 61 +++++++++++++++++++++++---- src/southbridge/amd/cimx/sb800/early.c | 8 ++++ src/southbridge/amd/cimx/sb800/late.c | 19 ++++++++ src/southbridge/amd/cimx/sb800/lpc.c | 4 +- src/southbridge/amd/cimx/sb800/lpc.h | 1 - src/southbridge/amd/cimx/sb800/sb_cimx.h | 4 ++ 8 files changed, 100 insertions(+), 11 deletions(-) diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 65e4729..2cdca29 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -15,3 +15,14 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx +$(obj)/s3.rom: + echo " S3 NVRAM 0xffff0000 (S3 storage area)" + echo -ne '\xFF' > $@ + for ((i=0;i<20479;i++)) do echo -ne '\xFF' >> $@ ; done + +ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) +cbfs-files-y += s3nv +s3nv-file := $(obj)/s3.rom +s3nv-position := 0xffff0000 +s3nv-type := raw +endif diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 25aba95..7dc752a 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -162,4 +162,7 @@ typedef union _PCI_ADDR { #include "spi.h" #endif +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 + #endif // _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index a9e35bc..2b73155 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -17,10 +17,52 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#include <console/console.h> #include "SBPLATFORM.h" #include "cfg.h" +#include "OEM.h" +#include <cbmem.h> + +#include <arch/io.h> +#include <arch/acpi.h> + +#if CONFIG_HAVE_ACPI_RESUME == 1 +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(PM1_CNT_BLK_ADDRESS); + tmp = ((tmp & (7 << 10)) >> 10); + printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); + return (int)tmp; +} +#endif + +#ifndef __PRE_RAM__ +void set_cbmem_toc(struct cbmem_entry *toc) +{ + u32 dword = (u32) toc; + int nvram_pos = 0xf8, i; /* temp */ + printk(BIOS_DEBUG, "dword=%x\n", dword); + for (i = 0; i<4; i++) { + printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} +#endif +struct cbmem_entry *get_cbmem_toc(void) +{ + u32 xdata = 0; + int xnvram_pos = 0xf8, xi; + for (xi = 0; xi<4; xi++) { + outb(xnvram_pos, BIOSRAM_INDEX); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(BIOSRAM_DATA) << (xi *8); + xnvram_pos++; + } + return (struct cbmem_entry *) xdata; +} /** * @brief South Bridge CIMx configuration @@ -30,10 +72,13 @@ */ void sb800_cimx_config(AMDSBCFG *sb_config) { - if (!sb_config) { + if (!sb_config) return; - } - //memset(sb_config, 0, sizeof(AMDSBCFG)); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_get_sleep_type() == 3) + sb_config->S3Resume = 1; +#endif /* header */ sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; @@ -75,19 +120,19 @@ void sb800_cimx_config(AMDSBCFG *sb_config) /* USB */ sb_config->USBMODE.UsbModeReg = USB_CONFIG; - sb_config->SbUsbPll = 0; + sb_config->SbUsbPll = 0; /* SATA */ sb_config->SataClass = SATA_MODE; sb_config->SataIdeMode = SATA_IDE_MODE; sb_config->SataPortMultCap = SATA_PORT_MULT_CAP_RESERVED; - sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; + sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. //TODO: set to secondary not take effect. sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE; sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE; - /* Azalia HDA */ + /* Azalia HDA */ sb_config->AzaliaController = AZALIA_CONTROLLER; sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN; @@ -97,7 +142,6 @@ void sb800_cimx_config(AMDSBCFG *sb_config) #else sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL; #endif - /* LPC */ /* SuperIO hardware monitor register access */ sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM; @@ -132,4 +176,3 @@ void sb800_cimx_config(AMDSBCFG *sb_config) } #endif //!__PRE_RAM__ } - diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 9d49a52..f692897 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -23,9 +23,11 @@ #include <device/pci_ids.h> #include <arch/io.h> /* inl, outl */ #include <arch/romcc_io.h> /* device_t */ +#include <arch/acpi.h> #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ +#include "cbmem.h" #if CONFIG_RAMINIT_SYSINFO == 1 @@ -80,3 +82,9 @@ void sb800_clk_output_48Mhz(void) *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ } +#if CONFIG_HAVE_ACPI_RESUME == 1 +int acpi_is_wakeup_early(void) +{ + return (acpi_get_sleep_type() == 3); +} +#endif diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 8c7abdb..c69782b 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -24,6 +24,7 @@ #include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <console/console.h> /* printk */ +#include <arch/acpi.h> #include "lpc.h" /* lpc_read_resources */ #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ #include "cfg.h" /* sb800 Cimx configuration */ @@ -351,6 +352,17 @@ void sb_Late_Post(void) AmdSbDispatcher(sb_config); } +void sb_Before_Pci_Restore_Init(void) +{ + sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT; + AmdSbDispatcher(sb_config); +} + +void sb_After_Pci_Restore_Init(void) +{ + sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT; + AmdSbDispatcher(sb_config); +} /** * @brief SB Cimx entry point sbBeforePciInit wrapper @@ -468,7 +480,14 @@ static void sb800_enable(device_t dev) /* call the CIMX entry at the last sb800 device, * so make sure the mainboard devicetree is complete */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) + sb_Before_Pci_Init(); + else + sb_Before_Pci_Restore_Init(); +#else sb_Before_Pci_Init(); +#endif break; default: diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index bc643b5..472817d 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -20,7 +20,9 @@ #include <console/console.h> #include <device/pci.h> #include "lpc.h" - +#include <bitops.h> +#include <arch/io.h> +#include <cbmem.h> void lpc_read_resources(device_t dev) { diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index 7b165f8..3d6a17a 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -20,7 +20,6 @@ #ifndef _SB800_LPC_H_ #define _SB800_LPC_H_ - #define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ void lpc_read_resources(device_t dev); diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h index 42a7ba9..5e510de 100644 --- a/src/southbridge/amd/cimx/sb800/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h @@ -29,6 +29,10 @@ void sb_Before_Pci_Init(void); void sb_After_Pci_Init(void); void sb_Mid_Post_Init(void); void sb_Late_Post(void); +void sb_Before_Pci_Restore_Init(void); +void sb_After_Pci_Restore_Init(void); + +int acpi_is_wakeup_early(void); /** * CIMX not set the clock to 48Mhz until sbBeforePciInit, [View Less]

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Patch set updated for coreboot: f677488 S3 code in coreboot public folder.
by Zheng Bao 04 Apr '12

04 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/623 -gerrit commit f677488bf475eaceec69953ddb348baa8d443338 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 5 13:22:06 2012 +0800 S3 code in coreboot public folder. 1. Move the Stack to high memory. 2. Restore the MTRR before Coreboot jump to the wakeup vector. Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a Signed-off-by: … [View More]Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/Kconfig | 4 + src/arch/x86/boot/tables.c | 2 +- src/cpu/amd/agesa/Makefile.inc | 2 + src/cpu/amd/agesa/cache_as_ram.inc | 7 + src/cpu/amd/agesa/family14/Kconfig | 5 + src/cpu/amd/agesa/family14/model_14_init.c | 125 +++++---- src/cpu/amd/agesa/s3_resume.c | 323 ++++++++++++++++++++++ src/cpu/amd/agesa/s3_resume.h | 42 +++ src/include/cbmem.h | 8 +- src/northbridge/amd/agesa/Kconfig | 4 + src/northbridge/amd/agesa/family14/northbridge.c | 77 ++++-- 11 files changed, 523 insertions(+), 76 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index b0261d9..149568a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -222,6 +222,10 @@ config HAVE_INIT_TIMER default n if UDELAY_IO default y +config HIGH_SCRATCH_MEMORY_SIZE + hex + default 0x0 + config HAVE_MAINBOARD_RESOURCES bool default n diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index b7dc4fe..c90a01b 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -236,7 +236,7 @@ struct lb_memory *write_tables(void) * it begin there during reboot time. We don't need the pointer, nor * the result right now. If it fails, ACPI resume will be disabled. */ - cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); + cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE + CONFIG_HIGH_SCRATCH_MEMORY_SIZE); #endif #if CONFIG_MULTIBOOT diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index fb536dd..696173d 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -21,5 +21,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15 +romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c ramstage-y += apic_timer.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index f328db4..2124bf3 100755 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -86,6 +86,13 @@ disable_cache_as_ram: /* Save return stack */ movd %esp, %xmm0 + /* Disable cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + invd + AMD_DISABLE_STACK /* Restore the return stack */ diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 702270c..6713660 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -67,3 +67,8 @@ config HAVE_INIT_TIMER default y depends on CPU_AMD_AGESA_FAMILY14 +config HIGH_SCRATCH_MEMORY_SIZE + hex + # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) + default 0x71000 + depends on CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 577da1b..d90695a 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -32,6 +32,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam14.h> +#include <arch/acpi.h> +#include <cpu/amd/agesa/s3_resume.h> #define MCI_STATUS 0x401 @@ -57,69 +59,84 @@ void wrmsr_amd(u32 index, msr_t msr) static void model_14_init(device_t dev) { - printk(BIOS_DEBUG, "Model 14 Init.\n"); - - u8 i; - msr_t msr; - int msrno; + u32 i; + msr_t msr; #if CONFIG_LOGICAL_CPUS == 1 - u32 siblings; + u32 siblings; +#endif + printk(BIOS_DEBUG, "Model 14 Init.\n"); + + disable_cache (); + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14. + * TODO: + * amd_setup_mtrrs(); + */ + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + /* Set shadow WB, RdMEM, WrMEM */ + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.hi = msr.lo = 0x1e1e1e1e; + wrmsr(0x250, msr); + wrmsr(0x258, msr); + for (i = 0x268; i <= 0x26f; i++) + wrmsr(i, msr); + + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type == 3) + restore_mtrr(); #endif - disable_cache (); - /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - - // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs - msr.lo = msr.hi = 0; - wrmsr (0x259, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); - - /* disable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - enable_cache (); - - /* zero the machine check error status registers */ - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < 6; i++) { - wrmsr(MCI_STATUS + (i * 4), msr); - } - - /* Enable the local cpu apics */ - setup_lapic(); + x86_mtrr_check(); + x86_enable_cache(); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + /* Enable the local cpu apics */ + setup_lapic(); #if CONFIG_LOGICAL_CPUS == 1 - siblings = cpuid_ecx(0x80000008) & 0xff; - - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } #endif - /* DisableCf8ExtCfg */ - msr = rdmsr(NB_CFG_MSR); - msr.hi &= ~(1 << (46 - 32)); - wrmsr(NB_CFG_MSR, msr); + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); - /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); + printk(BIOS_SPEW, "%s done.\n", __func__); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c new file mode 100644 index 0000000..59e7bc6 --- /dev/null +++ b/src/cpu/amd/agesa/s3_resume.c @@ -0,0 +1,323 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/x86/cache.h> +#if CONFIG_WRITE_HIGH_TABLES +#include <cbmem.h> +#endif +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <string.h> +#include "Porting.h" +#include "BiosCallOuts.h" +#include "s3_resume.h" +#include "agesawrapper.h" + +#ifndef __PRE_RAM__ +#include "spi.h" +#endif + +void restore_mtrr(void) +{ + u32 msr; + volatile UINT32 *msrPtr = (volatile UINT32 *)S3_DATA_MTRR_POS; + msr_t msr_data; + + printk(BIOS_SPEW, "%s\n", __func__); + + disable_cache(); + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Now restore the Fixed MTRRs */ + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x250, msr_data); + + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x258, msr_data); + + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x259, msr_data); + + for (msr = 0x268; msr <= 0x26F; msr++) { + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(msr, msr_data); + } + + /* Disable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Restore the Variable MTRRs */ + for (msr = 0x200; msr <= 0x20F; msr++) { + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(msr, msr_data); + } + + /* Restore SYSCFG MTRR */ + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(SYS_CFG, msr_data); +} + +inline void *backup_resume(void) +{ + unsigned long high_ram_base; + void *resume_backup_memory; + + /* Start address of high memory tables */ + high_ram_base = (u32) get_cbmem_toc(); + + /* + * printk(BIOS_DEBUG, "CBMEM TOC is at: %x\n", (u32_t)high_ram_base); + * printk(BIOS_DEBUG, "CBMEM TOC 0-size:%x\n ",(u32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); + */ + + cbmem_reinit((u64) high_ram_base); + + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (((u32) resume_backup_memory == 0) + || ((u32) resume_backup_memory == -1)) { + printk(BIOS_ERR, "Error: resume_backup_memory: %x\n", + (u32) resume_backup_memory); + for (;;) ; + } + + return resume_backup_memory; +} + +void move_stack_high_mem(void *resume_backup_memory) +{ + memcpy(resume_backup_memory, (void *)BSP_STACK_BASE_ADDR, + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE)); + + __asm__ + volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" + (resume_backup_memory - BSP_STACK_BASE_ADDR) + :); +} + +void OemAgesaSaveMtrr(void) +{ +#ifndef __PRE_RAM__ + u32 spi_address; + msr_t msr_data; + device_t dev; + u32 nvram_pos = S3_DATA_MTRR_POS; + u32 i; + + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Fixed MTRRs */ + msr_data = rdmsr(0x250); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + msr_data = rdmsr(0x258); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + msr_data = rdmsr(0x259); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + for (i = 0x268; i < 0x270; i++) { + msr_data = rdmsr(i); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + } + + /* Disable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Variable MTRRs */ + for (i = 0x200; i < 0x210; i++) { + msr_data = rdmsr(i); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + } + + /* SYS_CFG */ + msr_data = rdmsr(0xC0010010); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + /* TOM */ + msr_data = rdmsr(0xC001001A); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + /* TOM2 */ + msr_data = rdmsr(0xC001001D); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + +#endif +} + +void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data) +{ + AMD_CONFIG_PARAMS StdHeader; + if (S3DataType == S3DataTypeNonVolatile) { + *Data = (void *)S3_DATA_NONVOLATILE_POS; + *DataSize = *(UINTN *) (*Data); + *Data += 4; + } else { + *DataSize = *(UINTN *) S3_DATA_VOLATILE_POS; + *Data = (void *) GetHeapBase(&StdHeader); + memcpy((void *)(*Data), (void *)(S3_DATA_VOLATILE_POS + 4), *DataSize); + } +} + +#ifndef __PRE_RAM__ +u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) +{ + + u32 pos = S3_DATA_VOLATILE_POS; + u32 spi_address, data; + u32 nvram_pos; + device_t dev; + + if (S3DataType == S3DataTypeNonVolatile) { + pos = S3_DATA_NONVOLATILE_POS; + } else { /* S3DataTypeVolatile */ + pos = S3_DATA_VOLATILE_POS; + } + + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + + /* printk(BIOS_DEBUG, "spi_address=%x\n", spi_address); */ + read_spi_id((u8 *) spi_address); + write_spi_status((u8 *)spi_address, 0); + if (S3DataType == S3DataTypeNonVolatile) { + sector_erase_spi((u8 *) spi_address, S3_DATA_NONVOLATILE_POS); + } else { + sector_erase_spi((u8 *) spi_address, S3_DATA_VOLATILE_POS); + sector_erase_spi((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x1000); + sector_erase_spi((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x2000); + sector_erase_spi((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x3000); + } + + nvram_pos = 0; + dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos, DataSize); + + for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { + data = *(u32 *) (Data + nvram_pos); + dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos + 4, + *(u32 *) (Data + nvram_pos)); + } + + return AGESA_SUCCESS; +} +#endif + +void set_resume_cache(void) +{ + msr_t msr; + + /* disable fixed mtrr for now, it will be enabled by mtrr restore */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); + wrmsr(SYSCFG_MSR, msr); + + /* Enable caching for 0 - coreboot ram using variable mtrr */ + msr.lo = 0 | MTRR_TYPE_WRBACK; + msr.hi = 0; + wrmsr(MTRRphysBase_MSR(0), msr); + msr.lo = ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid; + msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; + wrmsr(MTRRphysMask_MSR(0), msr); + + /* Set the default memory type and disable fixed and enable variable MTRRs */ + msr.hi = 0; + msr.lo = (1 << 11); + wrmsr(MTRRdefType_MSR, msr); + + enable_cache(); +} + +void s3_resume(void) +{ + int status; + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + status = agesawrapper_amds3laterestore(); + if (status) + printk(BIOS_DEBUG, "error level: %x \n", (u32) status); + else + printk(BIOS_DEBUG, "passed.\n"); +} diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h new file mode 100644 index 0000000..a62f90e --- /dev/null +++ b/src/cpu/amd/agesa/s3_resume.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef S3_RESUME_H +#define S3_RESUME_H + +#define S3_DATA_NONVOLATILE_POS 0xFFFF4000 +#define S3_DATA_VOLATILE_POS 0xFFFF0000 +#define S3_DATA_MTRR_POS 0xFFFF3100 + +typedef enum { + S3DataTypeNonVolatile=0, ///< NonVolatile Data Type + S3DataTypeVolatile ///< Volatile Data Type +} S3_DATA_TYPE; + +void restore_mtrr(void); +void s3_resume(void); +inline void *backup_resume(void); +void set_resume_cache(void); +void move_stack_high_mem(void *resume_backup_memory); + +u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data); +void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data); +void OemAgesaSaveMtrr (void); + +#endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 6a48dd2..9bec621 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -32,11 +32,11 @@ extern uint64_t high_tables_base, high_tables_size; #endif #if CONFIG_HAVE_ACPI_RESUME -#define HIGH_MEMORY_SIZE ((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE) -#define HIGH_MEMORY_SAVE ( HIGH_MEMORY_SIZE - HIGH_MEMORY_DEF_SIZE ) -#else +#define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) +#define HIGH_MEMORY_SIZE (HIGH_MEMORY_SAVE + CONFIG_HIGH_SCRATCH_MEMORY_SIZE + HIGH_MEMORY_DEF_SIZE) +#else /* CONFIG_HAVE_ACPI_RESUME */ #define HIGH_MEMORY_SIZE HIGH_MEMORY_DEF_SIZE -#endif +#endif /* CONFIG_HAVE_ACPI_RESUME */ #define CBMEM_ID_FREESPACE 0x46524545 #define CBMEM_ID_GDT 0x4c474454 diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 2ee921b..ebdda38 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -27,6 +27,10 @@ config CONSOLE_VGA_MULTI bool default n +config S3_VGA_ROM_RUN + bool + default n + source src/northbridge/amd/agesa/family10/Kconfig source src/northbridge/amd/agesa/family12/Kconfig source src/northbridge/amd/agesa/family14/Kconfig diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 15efe12..2647814 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -745,20 +745,46 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(device_t dev) { +extern u8 acpi_slp_type; + +static void domain_enable_resources(device_t dev) +{ u32 val; #if CONFIG_AMD_SB_CIMX + #if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + sb_After_Pci_Init(); + sb_Mid_Post_Init(); + } else { + sb_After_Pci_Restore_Init(); + } + #else sb_After_Pci_Init(); sb_Mid_Post_Init(); + #endif #endif /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n"); - val = agesawrapper_amdinitmid(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); + +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); } +#else + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); +#endif printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); } @@ -788,24 +814,41 @@ static void cpu_bus_set_resources(device_t dev) { pci_dev_set_resources(dev); } -static void cpu_bus_init(device_t dev) { - struct device_path cpu_path; +static u32 cpu_bus_scan(device_t dev, u32 max) +{ device_t cpu; - int apic_id; + struct device_path cpu_path; + int apic_id, cores_found; - initialize_cpus(dev->link_list); + /* There is only one node for fam14, but there may be multiple cores. */ + cpu = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (!cpu) + printk(BIOS_ERR, "ERROR: %02x:%02x.0 not found", 0, 0x18); - /* Build the AP cpu device path(s) */ - for (apic_id = 1; apic_id < CONFIG_MAX_CPUS; apic_id++) { + cores_found = (pci_read_config32(dev_find_slot(0,PCI_DEVFN(0x18,0x3)), 0xe8) >> 12) & 3; + printk(BIOS_DEBUG, " AP siblings=%d\n", cores_found); + + + for (apic_id = 0; apic_id <= cores_found; apic_id++) { cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = apic_id; - cpu = alloc_dev(dev->link_list, &cpu_path); - if (!cpu) - return; - cpu->enabled = 1; - cpu->path.apic.node_id = 0; - cpu->path.apic.core_id = apic_id; + cpu = alloc_find_dev(dev->link_list, &cpu_path); + if (cpu) { + cpu->enabled = 1; + cpu->path.apic.node_id = 0; + cpu->path.apic.core_id = apic_id; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } else { + cpu->enabled = 0; + } } + return max; +} + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); } /* North Bridge Structures */ @@ -844,7 +887,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = cpu_bus_set_resources, .enable_resources = NULL, .init = cpu_bus_init, - .scan_bus = NULL, + .scan_bus = cpu_bus_scan, }; static void root_complex_enable_dev(struct device *dev) { [View Less]

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Patch set updated for coreboot: 325bdf4 S3 code in the mainboard.
by Zheng Bao 04 Apr '12

04 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/624 -gerrit commit 325bdf4d44842c49c9d767fb95fc0f97a6bf69a9 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 5 13:22:50 2012 +0800 S3 code in the mainboard. Persimmon is the demo board. Tested by Linux and Windows 7. Change-Id: I5ded942b51e63ebeb08ace0b202b4ed239b0c14c Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-… [View More]by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/persimmon/BiosCallOuts.c | 40 +++-- src/mainboard/amd/persimmon/BiosCallOuts.h | 4 +- src/mainboard/amd/persimmon/Kconfig | 1 + src/mainboard/amd/persimmon/PlatformGnbPcie.c | 2 +- .../amd/persimmon/PlatformGnbPcieComplex.h | 1 + src/mainboard/amd/persimmon/agesawrapper.c | 175 +++++++++++++++++++- src/mainboard/amd/persimmon/agesawrapper.h | 5 + src/mainboard/amd/persimmon/buildOpts.c | 6 +- src/mainboard/amd/persimmon/get_bus_conf.c | 21 ++- src/mainboard/amd/persimmon/mainboard.c | 16 ++- src/mainboard/amd/persimmon/romstage.c | 90 ++++++++-- 11 files changed, 312 insertions(+), 49 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 7323832..52eb9dd 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -119,8 +119,10 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams->BufferPointer = NULL; AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + printk(BIOS_SPEW, "%s BiosHeapBaseAddr: %x\n", __func__, (u32) BiosHeapBaseAddr); if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { /* First allocation */ @@ -229,26 +231,26 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_BUFFER_NODE *PrevNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *NextNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + /* Find target node to deallocate in list of allocated nodes. - Return AGESA_BOUNDS_CHK if the BufferHandle is not found + Return AGESA_BOUNDS_CHK if the BufferHandle is not found */ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); @@ -355,8 +357,8 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index d9e4497..071c73c 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -23,8 +23,8 @@ #include "Porting.h" #include "AGESA.h" -#define BIOS_HEAP_START_ADDRESS 0x00010000 -#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ +#define BIOS_HEAP_SIZE 0x20000 +#define BSP_STACK_BASE_ADDR 0x30000 typedef struct _BIOS_HEAP_MANAGER { //UINT32 AvailableSize; diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 9212e20..27e27a5 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES + select HAVE_ACPI_RESUME select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index 5e37f51..bdfcb66 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -23,6 +23,7 @@ #include "heapManager.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include "BiosCallOuts.h" #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -165,4 +166,3 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; } - diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index b50cb1a..a49be62 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -23,6 +23,7 @@ #include "Porting.h" #include "AGESA.h" #include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 6e9997f..be00ab4 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -33,10 +33,12 @@ #include "cpuLateInit.h" #include "Dispatcher.h" #include "cpuCacheInit.h" +#include "heapManager.h" #include "amdlib.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" #include <arch/io.h> +#include <cpu/amd/agesa/s3_resume.h> #define FILECODE UNASSIGNED_FILE_FILECODE @@ -243,6 +245,35 @@ agesawrapper_amdinitearly ( return (UINT32)status; } + +UINT32 GetHeapBase( + AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrReg; + UINT32 sys_mem, uma_base, uma_size; + + /* TOP_MEM: the top of DRAM below 4G */ + LibAmdMsrRead(TOP_MEM, &MsrReg, StdHeader); + + /* refer to UMA Size Consideration in Family14h BKDG. */ + sys_mem = (UINT32)(MsrReg & 0xFFFFFFFFUL) + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() + if ((MsrReg & 0x0000000F00000000) || (sys_mem >= 0x80000000)) { + uma_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ + } + else { + if (sys_mem >= 0x40000000) { + uma_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ + } + else { + uma_size = 0x4000000; /* <1G memory, 64M recommended UMA */ + } + } + + uma_base = (UINT32)(MsrReg & 0xFFFFFFFFUL) - uma_size ; /* TOP_MEM1 */ + return uma_base - BIOS_HEAP_SIZE; +} + UINT32 agesawrapper_amdinitpost ( VOID @@ -272,7 +303,7 @@ agesawrapper_amdinitpost ( AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ - BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader); HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { @@ -496,6 +527,148 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } +#if CONFIG_HAVE_ACPI_RESUME == 1 +UINT32 +agesawrapper_amdinitresume ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amds3laterestore ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdS3LateParams, + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + + AmdCreateStruct (&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +#ifndef __PRE_RAM__ +UINT32 +agesawrapper_amdS3Save ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdInterfaceParams, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save (AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + S3DataType = S3DataTypeNonVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage + ); + } + + OemAgesaSaveMtrr(); + AmdReleaseStruct (&AmdInterfaceParams); + + return (UINT32)Status; +} +#endif /* #ifndef __PRE_RAM__ */ +#endif /* CONFIG_HAVE_ACPI_RESUME */ + UINT32 agesawrapper_amdlaterunaptask ( UINT32 Func, diff --git a/src/mainboard/amd/persimmon/agesawrapper.h b/src/mainboard/amd/persimmon/agesawrapper.h index 7bed570..7babd58 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.h +++ b/src/mainboard/amd/persimmon/agesawrapper.h @@ -84,7 +84,12 @@ UINT32 agesawrapper_amdreadeventlog (void); UINT32 agesawrapper_amdinitcpuio (void); UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdinitresume (void); +UINT32 agesawrapper_amdS3Save (void); +UINT32 agesawrapper_amds3laterestore (void); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); void *agesawrapper_getlateinitptr (int pick); +UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); + #endif diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 3e5b14e..389e1d4 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -120,8 +120,8 @@ #define AGESA_ENTRY_INIT_LATE TRUE #define AGESA_ENTRY_INIT_S3SAVE TRUE #define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -169,7 +169,7 @@ //#define BLDCFG_USE_HT_ASSIST TRUE //#define BLDCFG_USE_ATM_MODE TRUE //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE +#define BLDCFG_S3_LATE_RESTORE TRUE //#define BLDCFG_USE_32_BYTE_REFRESH FALSE //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE //#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 0142762..4c094ae 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -51,6 +51,9 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +#endif void get_bus_conf(void) { @@ -80,11 +83,20 @@ void get_bus_conf(void) * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + status = agesawrapper_amdS3Save(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } +#else status = agesawrapper_amdinitlate(); - if(status) { + if(status) printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - +#endif sbdn_sb800 = 0; for (i = 0; i < 3; i++) { @@ -124,7 +136,8 @@ void get_bus_conf(void) for (j = bus_sb800[2]; j < bus_isa; j++) bus_type[j] = 1; - /* I/O APICs: APIC ID Version State Address */ + + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 3b181a1..9a8428e 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -23,10 +23,13 @@ #include <arch/io.h> #include <boot/tables.h> #include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -//#include <southbridge/amd/sb800/sb800.h> +#include <southbridge/amd/sb800/sb800.h> +#include <arch/acpi.h> #include "chip.h" +#include "BiosCallOuts.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/amd/mtrr.h> void set_pcie_reset(void); void set_pcie_dereset(void); @@ -56,6 +59,14 @@ static void persimmon_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); +/* + * The mainboard is the first place that we get control in ramstage. Check + * for S3 resume and call the approriate AGESA/CIMx resume functions. + */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + acpi_slp_type = acpi_get_sleep_type(); +#endif + #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; uint32_t sys_mem; @@ -110,6 +121,7 @@ int add_mainboard_resources(struct lb_memory *mem) #endif return 0; } + struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = persimmon_enable, diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index dfb1aca..f52b447 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -35,9 +35,14 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "pc80/i8254.c" #include "pc80/i8259.c" +#include <cpu/x86/cache.h> #include "sb_cimx.h" #include "SBPLATFORM.h" +#include "cbmem.h" +#include "cpu/amd/mtrr.h" +#include "cpu/amd/agesa/s3_resume.h" +void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) @@ -46,6 +51,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; +#if CONFIG_HAVE_ACPI_RESUME == 1 + void *resume_backup_memory; +#endif + /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) @@ -98,28 +107,75 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - post_code(0x40); - printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); - val = agesawrapper_amdinitpost (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); - - post_code(0x41); - printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); - val = agesawrapper_amdinitenv (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ +#endif + post_code(0x40); + printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); + val = agesawrapper_amdinitpost (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x42); + printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); + val = agesawrapper_amdinitenv (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); + val = agesawrapper_amdinitresume(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + val = agesawrapper_amds3laterestore (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x61); + printk(BIOS_DEBUG, "Find resume memory location\n"); + resume_backup_memory = backup_resume(); + + post_code(0x62); + printk(BIOS_DEBUG, "Move CAR stack.\n"); + move_stack_high_mem(resume_backup_memory + HIGH_MEMORY_SAVE); + printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); + + post_code(0x63); + disable_cache_as_ram(); + printk(BIOS_DEBUG, "CAR disabled.\n"); + set_resume_cache(); + + /* + * Copy the system memory that is in the ramstage area to the + * reserved area. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); + + printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + } +#endif /* Initialize i8259 pic */ - post_code(0x41); + post_code(0x43); setup_i8259 (); /* Initialize i8254 timers */ - post_code(0x42); + post_code(0x44); setup_i8254 (); post_code(0x50); [View Less]

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Patch set updated for coreboot: fe35e15 S3 code in vendorcode folder.
by Zheng Bao 04 Apr '12

04 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/622 -gerrit commit fe35e15686970be4488bfe86cda8559f9172bde8 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 5 13:20:50 2012 +0800 S3 code in vendorcode folder. Change the ExecuteFinalHltInstruction to assembly code. so we can make sure the code can run stackless. Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d Signed-off-by: … [View More]Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/family14/Makefile.inc | 1 + src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h | 10 +- src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c | 141 +------------- src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S | 203 ++++++++++++++++++++ .../amd/agesa/f14/Proc/Common/AmdS3Save.c | 2 +- .../amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c | 10 +- src/vendorcode/amd/agesa/f14/gcccar.inc | 192 ++++++++++--------- 7 files changed, 325 insertions(+), 234 deletions(-) diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 774d401..b08ceeb 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -113,6 +113,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtMidPost.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnPciTables.c diff --git a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h index 58438b9..5ce3ee3 100644 --- a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h @@ -305,7 +305,9 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr0, %[value]" - : [value] "=a" (value)); + : [value] "=a" (value) + : + : "memory"); return value; } @@ -379,6 +381,7 @@ static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long D "mov %%eax, %%cr0" : : "a" (Data) + : "memory" ); } @@ -508,13 +511,16 @@ static __inline__ __attribute__((always_inline)) void __debugbreak(void) __asm__ __volatile__ ("int3"); } +static __inline__ __attribute__((always_inline)) void __invd(void) +{ + __asm__ __volatile__ ("invd"); +} static __inline__ __attribute__((always_inline)) void __wbinvd(void) { __asm__ __volatile__ ("wbinvd"); } - static __inline__ __attribute__((always_inline)) void __lidt(void *Source) { __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source)); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c index ae9f3c7..938300a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c @@ -106,149 +106,16 @@ ExecuteWbinvdInstruction ( */ -//---------------------------------------------------------------------------- - -STATIC -VOID -PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) - { - UINT64 data; - UINT32 msrno; - // Configure the MTRRs on the AP so - // when it runs remote code it will execute - // out of RAM instead of ROM. - // Disable MTRRs and turn on modification enable bit - - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data &= ~(1 << 18); // MtrrFixDramEn - data &= ~(1 << 20); // MtrrVarDramEn - data |= (1 << 19); // MtrrFixDramModEn - data |= (1 << 17); // SysUcLockEn - - - __writemsr (0xC0010010, data); - - // Set 7FFFh-00000h and 9FFFFh-80000h as WB DRAM - __writemsr (0x250, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX64k_00000 - __writemsr (0x258, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX16k_80000 - - // Set BFFFFh-A0000h, DFFFFh-C0000h as Uncacheable Memory-mapped IO - __writemsr (0x259, 0); // AMD_AP_MTRR_FIX16k_A0000 - __writemsr (0x268, 0); // AMD_MTRR_FIX4k_C0000 - __writemsr (0x269, 0); // AMD_MTRR_FIX4k_C8000 - __writemsr (0x26A, 0); // AMD_MTRR_FIX4k_D0000 - __writemsr (0x26B, 0); // AMD_MTRR_FIX4k_D8000 - - // Set FFFFFh-E0000h as Uncacheable Memory - for (msrno = 0x26C; msrno <= 0x26F; msrno++) - __writemsr (msrno, 0x1818181818181818); - - // If IBV provided settings for Fixed-Sized MTRRs, - // overwrite the default settings. - if ((uintptr_t) ApMtrrSettingsList != 0 && (uintptr_t) ApMtrrSettingsList != 0xFFFFFFFF) - { - int index; - for (index = 0; ApMtrrSettingsList [index].MsrAddr != CPU_LIST_TERMINAL; index++) - __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); - } - - // restore variable MTTR6 and MTTR7 to default states - for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared - __writemsr (msrno, 0); - - // Enable fixed-range and variable-range MTRRs - // Set Fixed-Range Enable (FE) and MTRR Enable (E) bits - __writemsr (0x2FF, __readmsr (0x2FF) | 0xC00); - - // Enable Top-of-Memory setting - // Enable use of RdMem/WrMem bits attributes - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data |= (1 << 18); // MtrrFixDramEn - data |= (1 << 20); // MtrrVarDramEn - data &= ~(1 << 19); // MtrrFixDramModEn - __writemsr (0xC0010010, data); - } - -//---------------------------------------------------------------------------- - +/* see cahaltasm.S VOID ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, + IN UINT32 HaltFlags, IN AP_MTRR_SETTINGS *ApMtrrSettingsList, IN AMD_CONFIG_PARAMS *StdHeader ) { - int abcdRegs [4]; - UINT32 cr0val; - UINT64 data; - - cr0val = __readcr0 (); - if (SharedCore & 2) - { - // set CombineCr0Cd and enable cache in CR0 - __writemsr (MSR_CU_CFG3, __readmsr (MSR_CU_CFG3) | 1ULL << 49); - __writecr0 (cr0val & ~0x60000000); - } - else - __writecr0 (cr0val | 0x60000000); - - if (SharedCore & 1) PrimaryCoreFunctions (ApMtrrSettingsList); - - // Make sure not to touch any Shared MSR from this point on - - // Restore settings that were temporarily overridden for the cache as ram phase - data = __readmsr (0xC0011022); // MSR_DC_CFG - data &= ~(1 << 4); // DC_DIS_SPEC_TLB_RLD - data &= ~(1 << 8); // DIS_CLR_WBTOL2_SMC_HIT - data &= ~(1 << 13); // DIS_HW_PF - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); // MSR_IC_CFG - C001_1021 - data &= ~(1 << 9); // IC_DIS_SPEC_TLB_RLD - __writemsr (0xC0011021, data); - - // AMD_DISABLE_STACK_FAMILY_HOOK - __cpuid (abcdRegs, 1); - if ((abcdRegs [0] >> 20) == 1) //-----family 10h (Hydra) only----- - { - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1 << 8); - data &= ~(1 << 13); - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 14); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC001102A); - data &= ~(1 << 15); - data &= ~(1ull << 35); - __writemsr (0xC001102A, data); - } - else if ((abcdRegs [0] >> 20) == 6) //-----family 15h (Orochi) only----- - { - data = __readmsr (0xC0011020); - data &= ~(1 << 28); - __writemsr (0xC0011020, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1l << 13); - __writemsr (0xC0011022, data); - } - - for (;;) - { - _disable (); - __halt (); - } - } +} +*/ //---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S new file mode 100644 index 0000000..48ee5d0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +.include "src/vendorcode/amd/agesa/f14/gcccar.inc" + +.code32 +.align 4 +.globl ExecuteFinalHltInstruction + .type ExecuteFinalHltInstruction, @function +/* ExecuteFinalHltInstruction ( + IN UINT32 HaltFlags, + IN AP_MTRR_SETTINGS *ApMtrrSettingsList, + IN AMD_CONFIG_PARAMS *StdHeader + ) +*/ + +/* This function disables CAR. We don't care about the stack on this CPU */ +ExecuteFinalHltInstruction: + movl 4(%esp), %esi /* HaltFlags*/ + movl 8(%esp), %edi /* ApMtrrSettingList */ + +/* Do these special steps in case if the core is part of a compute unit + * Note: The following bits are family specific flags, that gets set during build time, + * and indicates things like "family cache control methodology", etc. + * esi bit0 = 0 -> not a Primary core + * esi bit0 = 1 -> Primary core + * esi bit1 = 0 -> Cache disable + * esi bit1 = 1 -> Cache enable + */ + + bt $1, %esi /* .if (esi & 2h) */ + jz 0f + /* Set CombineCr0Cd bit */ + movl $CU_CFG3, %ecx + rdmsr + bts $(COMBINE_CR0_CD - 32), %edx + wrmsr + /* Clear the CR0.CD bit */ + movl %cr0, %eax /* Make sure cache is enabled for all APs */ + btr $CR0_CD, %eax + btr $CR0_NW, %eax + mov %eax, %cr0 /* Write back to CR0 */ + jmp 1f /* .else */ +0: + movl %cr0, %eax /* Make sure cache is disabled for all APs */ + bts $CR0_CD, %eax /* Disable cache */ + bts $CR0_NW, %eax + movl %eax, %cr0 /* Write back to CR0 */ +1: /* .endif */ + + bt $0, %esi /* .if (esi & 1h) */ + jz 2f + /* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */ + movl %edi, %esi /* Get ApMtrrSettingList */ + + /* Configure the MTRRs on the AP so + * when it runs remote code it will execute + * out of RAM instead of ROM. + */ + + /* Disable MTRRs and turn on modification enable bit */ + movl $MTRR_SYS_CFG, %ecx + rdmsr + btr $MTRR_VAR_DRAM_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_MOD_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_EN, %eax /* Disable */ + bts $SYS_UC_LOCK_EN, %eax + wrmsr + + /* Setup default values for Fixed-Sized MTRRs */ + /* Set 7FFFh-00000h as WB */ + movl $AMD_AP_MTRR_FIX64k_00000, %ecx + movl $0x1E1E1E1E, %eax + movl %eax, %edx + wrmsr + + /* Set 9FFFFh-80000h also as WB */ + movl $AMD_AP_MTRR_FIX16k_80000, %ecx + wrmsr + + /* Set BFFFFh-A0000h as Uncacheable Memory-mapped IO */ + movl $AMD_AP_MTRR_FIX16k_A0000, %ecx + xorl %eax, %eax + xorl %edx, %edx + wrmsr + + /* Set DFFFFh-C0000h as Uncacheable Memory-mapped IO */ + xorl %eax, %eax + xorl %edx, %edx + movl $AMD_AP_MTRR_FIX4k_C0000, %ecx + +CDLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_D8000, %ecx + jbe CDLoop + + /* Set FFFFFh-E0000h as Uncacheable Memory */ + movl $0x18181818, %eax + movl %eax, %edx + + mov $AMD_AP_MTRR_FIX4k_E0000, %ecx + +EFLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_F8000, %ecx + jbe EFLoop + + /* If IBV provided settings for Fixed-Sized MTRRs, + * overwrite the default settings. */ + cmp $0, %esi /*.if ((esi != 0) && (esi != 0FFFFFFFFh)) */ + jz 4f + cmp $0xFFFFFFFF, %esi + jz 4f + 5: + mov (%esi), %ecx /* (AP_MTRR_SETTINGS ptr [esi]).MsrAddr */ + /* While we are not at the end of the list */ + cmp $CPU_LIST_TERMINAL, %ecx /* .while (ecx != CPU_LIST_TERMINAL)*/ + je 4f + /* TODO - coreboot isn't checking for valid data. + * Ensure that the MSR address is valid for Fixed-Sized MTRRs */ + /*.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \ + (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || \ + (ecx == AMD_AP_MTRR_FIX16k_A0000)) + */ + mov 4(%esi), %eax /* MsrData */ + mov 8(%esi), %edx /* MsrData */ + wrmsr + /* .endif */ + add $12, %esi /* sizeof (AP_MTRR_SETTINGS) */ + jmp 5b /* .endw */ + 4: /* .endif */ + + /* restore variable MTTR6 and MTTR7 to default states */ + movl $AMD_MTRR_VARIABLE_BASE6, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ + xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */ + xor %edx, %edx + cmp $10, %ecx /* .while (cl < 010h) */ + jge 6f + wrmsr + inc %ecx + 6: /* .endw */ + + /* Enable fixed-range and variable-range MTRRs */ + mov $AMD_MTRR_DEFTYPE, %ecx + rdmsr + bts $MTRR_DEF_TYPE_EN, %eax /* MtrrDefTypeEn */ + bts $MTRR_DEF_TYPE_FIX_EN, %eax /* MtrrDefTypeFixEn */ + wrmsr + + /* Enable Top-of-Memory setting */ + /* Enable use of RdMem/WrMem bits attributes */ + mov $MTRR_SYS_CFG, %ecx + rdmsr + bts $MTRR_VAR_DRAM_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_MOD_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_EN, %eax /* Enable */ + wrmsr + + bts $FLAG_IS_PRIMARY, %esi + jmp 3f /* .else ; end if primary core */ + 2: + xor %esi, %esi + 3: /* .endif*/ + + /* Make sure not to touch any Shared MSR from this point on */ + + AMD_DISABLE_STACK_FAMILY_HOOK + + xor %eax, %eax + +7: + cli + hlt + jmp 7b /* ExecuteHltInstruction */ + + .size ExecuteFinalHltInstruction, .-ExecuteFinalHltInstruction diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c index f994c87..448d0f9 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c @@ -245,7 +245,7 @@ AmdS3Save ( HeapStatus = AmdS3SaveParams->StdHeader.HeapStatus; AmdS3SaveParams->StdHeader.HeapStatus = HEAP_S3_RESUME; - AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT64) HeapPtr; + AmdS3SaveParams->StdHeader.HeapBasePtr = (VOID *) HeapPtr; for (i = 0; i < S3LATE_TABLE_SIZE; i++) { if (HeapPtrs[i] != NULL) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c index df2071f..eee9804 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c @@ -259,30 +259,30 @@ MemFS3GetDeviceList ( (*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize; // Copy device list on the stack to the heap. - BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr; + BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) (UINT32) AllocHeapParams.BufferPtr; for (Die = 0; Die < DieCount; Die ++) { for (i = PRESELFREF; i <= POSTSELFREF; i ++) { // Copy PCI device descriptor to the heap if it exists. if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR); } // Copy conditional PCI device descriptor to the heap if it exists. if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); } // Copy MSR device descriptor to the heap if it exists. if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR); } // Copy conditional MSR device descriptor to the heap if it exists. if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); } diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 8743919..d81b6af 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -37,99 +37,113 @@ .altmacro -BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ -BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ -CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ -CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ -CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ -CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ - -APIC_BASE_ADDRESS = 0x0000001B - APIC_BSC = 8 /* Boot Strap Core */ - -AMD_MTRR_VARIABLE_BASE0 = 0x0200 -AMD_MTRR_VARIABLE_BASE6 = 0x020C -AMD_MTRR_FIX64k_00000 = 0x0250 -AMD_MTRR_FIX16k_80000 = 0x0258 -AMD_MTRR_FIX16k_A0000 = 0x0259 -AMD_MTRR_FIX4k_C0000 = 0x0268 -AMD_MTRR_FIX4k_C8000 = 0x0269 -AMD_MTRR_FIX4k_D0000 = 0x026A -AMD_MTRR_FIX4k_D8000 = 0x026B -AMD_MTRR_FIX4k_E0000 = 0x026C -AMD_MTRR_FIX4k_E8000 = 0x026D -AMD_MTRR_FIX4k_F0000 = 0x026E -AMD_MTRR_FIX4k_F8000 = 0x026F - -AMD_MTRR_DEFTYPE = 0x02FF - WB_DRAM_TYPE = 0x1E /* MemType - memory type */ - MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ - MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ - -HWCR = 0x0C0010015 /* Hardware Configuration */ - INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ - -IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ - /* uses 16h - 19h */ -TOP_MEM = 0x0C001001A /* Top of Memory */ -TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ - -LS_CFG = 0x0C0011020 /* Load-Store Configuration */ - DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ - DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ - -IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ - IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ - DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ - DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ - -DC_CFG = 0x0C0011022 /* Data Cache Configuration */ - DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ - DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ - DIS_HW_PF = 13 /* Hardware prefetches bit */ - -DE_CFG = 0x0C0011029 /* Decode Configuration */ - CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ - -BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ -CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ - F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ - IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ - -CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ - COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ - - +BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ +BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ +CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ +CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ +CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ +CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ + +APIC_BASE_ADDRESS = 0x0000001B + APIC_BSC = 8 /* Boot Strap Core */ + +AMD_MTRR_VARIABLE_BASE0 = 0x0200 +AMD_MTRR_VARIABLE_BASE6 = 0x020C +AMD_MTRR_FIX64k_00000 = 0x0250 +AMD_MTRR_FIX16k_80000 = 0x0258 +AMD_MTRR_FIX16k_A0000 = 0x0259 +AMD_MTRR_FIX4k_C0000 = 0x0268 +AMD_MTRR_FIX4k_C8000 = 0x0269 +AMD_MTRR_FIX4k_D0000 = 0x026A +AMD_MTRR_FIX4k_D8000 = 0x026B +AMD_MTRR_FIX4k_E0000 = 0x026C +AMD_MTRR_FIX4k_E8000 = 0x026D +AMD_MTRR_FIX4k_F0000 = 0x026E +AMD_MTRR_FIX4k_F8000 = 0x026F + +/* Reproduced from AGESA.h */ +AMD_AP_MTRR_FIX64k_00000 = 0x00000250 +AMD_AP_MTRR_FIX16k_80000 = 0x00000258 +AMD_AP_MTRR_FIX16k_A0000 = 0x00000259 +AMD_AP_MTRR_FIX4k_C0000 = 0x00000268 +AMD_AP_MTRR_FIX4k_C8000 = 0x00000269 +AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A +AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B +AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C +AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D +AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E +AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F +CPU_LIST_TERMINAL = 0xFFFFFFFF + +AMD_MTRR_DEFTYPE = 0x02FF + WB_DRAM_TYPE = 0x1E /* MemType - memory type */ + MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ + MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ + +HWCR = 0x0C0010015 /* Hardware Configuration */ + INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ + +IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ + /* uses 16h - 19h */ +TOP_MEM = 0x0C001001A /* Top of Memory */ +TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ + +LS_CFG = 0x0C0011020 /* Load-Store Configuration */ + DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ + DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ + +IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ + IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ + DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ + DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ + +DC_CFG = 0x0C0011022 /* Data Cache Configuration */ + DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ + DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ + DIS_HW_PF = 13 /* Hardware prefetches bit */ + +DE_CFG = 0x0C0011029 /* Decode Configuration */ + CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ + +BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ +CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ + F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ + IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ + +CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ + COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ + + CR0_PE = 1 # Protection Enable CR0_NW = 29 # Not Write-through CR0_CD = 30 # Cache Disable CR0_PG = 31 # Paging Enable - -/* CPUID Functions */ - -CPUID_MODEL = 1 -AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ - -NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ - INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ - -MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ - CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ - SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ - MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ - MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ - MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ - MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ - -PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ - PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ - PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ - CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ - CONFIG_EVENT_H = 4 /* Increment count by number of event */ - /* occured in clock cycle */ - EVENT_ENABLE = 22 /* Enable the event */ -PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ + +/* CPUID Functions */ + +CPUID_MODEL = 1 +AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ +AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ + +NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ + INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ + +MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ + CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ + SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ + MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ + MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ + MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ + MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ + +PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ + PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ + PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ + CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ + CONFIG_EVENT_H = 4 /* Increment count by number of event */ + /* occured in clock cycle */ + EVENT_ENABLE = 22 /* Enable the event */ +PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ # Local use flags, in upper most byte if ESI FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized [View Less]

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Re: [coreboot] Dual SPI Flash
by Oliver Schinagl 04 Apr '12

04 Apr '12

Well My electrical engineering knowledge does not reach as far that I would know where to connect what :) I can read a schematic and solder based on that, but those pictures from the wiki that I linked, http://www.coreboot.org/Developer_Manual/Tools/Dual_Flash has a small PCB, with 2 flash chips on it, but I can't figure out where to connect what. I do think it's a great idea, and maybe it would be an idea to draw the PCB in kicad/geda or the like, and actually have small batches made. I … [View More]

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New patch to review for coreboot: c2e50ec Use fast memset in SMM mode, too
by Stefan Reinauer 04 Apr '12

04 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/827 -gerrit commit c2e50ece4dec0fbfdc714b171530a658b8d8d13a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 16:28:20 2012 -0700 Use fast memset in SMM mode, too ... and always include IP checksumming in romstage. It's generally useful and our upcoming port needs it. Change-Id: … [View More]

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Re: [coreboot] GSoC project ideas
by Svetoslav Trochev 04 Apr '12

04 Apr '12

Hi Paul, On Tue, Apr 3, 2012 at 11:19 PM, Paul Geraedts <p.f.j.geraedts(a)gmail.com> wrote: >> - Flash ICE device with SPI support. >> - Flash ICE device with LPC/FWH support. >> - Serial emulation for LPC buses on a configurable I/O port with USB >> output on the other side. >> - Dual serial emulation for two LPC buses either on the same device or >> with two identical devices and a fast bus in between. >> - Serial emulation for PCI buses (i.e. … [View More]

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Re: [coreboot] Asus M5A88-v evo
by Jonathan Bennett 04 Apr '12

04 Apr '12

I've done a bit of looking, and found the code in question. It looks like the code is trying to figure out what family10 proc it is. The only problem, it's running a bulldozer processor. cpuinfo lists it as a family 21. Are the fx family processors supported at all? ~Jonathan >That's pretty clear. I suggest to boot with factory BIOS, check the >exact parameters of the CPU, look at the code which is being run, and >look for relevant documentation for your CPU in the scope of that … [View More]

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Patch merged into coreboot/master: c2e50ec Use fast memset in SMM mode, too
by gerrit＠coreboot.org 04 Apr '12

04 Apr '12

the following patch was just integrated into master: commit c2e50ece4dec0fbfdc714b171530a658b8d8d13a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 16:28:20 2012 -0700 Use fast memset in SMM mode, too ... and always include IP checksumming in romstage. It's generally useful and our upcoming port needs it. Change-Id: I248402d96a23e58354744e053b9d5cca6b74ad3a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: … [View More]

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New patch to review for coreboot: a18dc1a Update documentation in smmrelocate.S to mention TSEG
by Stefan Reinauer 04 Apr '12

04 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/861 -gerrit commit a18dc1a4fba4b2ceff70ce630fbe99979cf2863f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 10:38:05 2012 -0700 Update documentation in smmrelocate.S to mention TSEG Change-Id: I392f5fc475b15b458fc015e176e45888e7de27fb Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/… [View More]cpu/x86/smm/smmrelocate.S | 19 +++++++++++-------- 1 files changed, 11 insertions(+), 8 deletions(-) diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index bc5b2da..5a2dba5 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -54,13 +54,22 @@ .code16 /** - * This trampoline code relocates SMBASE to 0xa0000 - ( lapicid * 0x400 ) + * When starting up, x86 CPUs have their SMBASE set to 0x30000. However, + * this is not a good place for the SMM handler to live, so it needs to + * be relocated. + * Traditionally SMM handlers used to live in the A segment (0xa0000). + * With growing SMM handlers, more CPU cores, etc. CPU vendors started + * allowing to relocate the handler to the end of physical memory, which + * they refer to as TSEG. + * This trampoline code relocates SMBASE to base address - ( lapicid * 0x400 ) * * Why 0x400? It is a safe value to cover the save state area per CPU. On * current AMD CPUs this area is _documented_ to be 0x200 bytes. On Intel * Core 2 CPUs the _documented_ parts of the save state area is 48 bytes * bigger, effectively sizing our data structures 0x300 bytes. * + * Example (with SMM handler living at 0xa0000): + * * LAPICID SMBASE SMM Entry SAVE STATE * 0 0xa0000 0xa8000 0xafd00 * 1 0x9fc00 0xa7c00 0xaf900 @@ -88,13 +97,7 @@ * at 0xa8000-0xa8100 (example for core 0). That is not enough. * * This means we're basically limited to 16 cpu cores before - * we need to use the TSEG/HSEG for the actual SMM handler plus stack. - * When we exceed 32 cores, we also need to put SMBASE to TSEG/HSEG. - * - * If we figure out the documented values above are safe to use, - * we could pack the structure above even more, so we could use the - * scheme to pack save state areas for 63 AMD CPUs or 58 Intel CPUs - * in the ASEG. + * we need to move the SMM handler to TSEG. * * Note: Some versions of Pentium M need their SMBASE aligned to 32k. * On those the above only works for up to 2 cores. But for now we only [View Less]

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Patch merged into coreboot/master: c276a74 Add support for Intel Panther Point PCH
by gerrit＠coreboot.org 04 Apr '12

04 Apr '12

the following patch was just integrated into master: commit c276a7462a7f1fdfb66ff7ba446c9c3138b0690f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 00:07:22 2012 +0200 Add support for Intel Panther Point PCH Change-Id: Iac3cd25b36493bb203e849674320e113cc5fce32 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Wed Apr 4 02:34:39 2012, … [View More]

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Patch merged into coreboot/master: 460069f Add support for mainboard specific suspend/resume handler
by gerrit＠coreboot.org 04 Apr '12

04 Apr '12

the following patch was just integrated into master: commit 460069fb2ffab71a7e9dfd85a8a1020e74b47f07 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Apr 3 23:28:22 2012 +0200 Add support for mainboard specific suspend/resume handler Some mainboards (most likely laptops) will need mainboard specific functions called upon a resume from suspend. Change-Id: If1518a4b016bba776643adaef0ae64ff49f57e51 Signed-off-by: Stefan Reinauer <reinauer(… [View More]

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Patch merged into coreboot/master: d93b82f Move TPM code to romstage
by gerrit＠coreboot.org 04 Apr '12

04 Apr '12

the following patch was just integrated into master: commit d93b82ff774411f77f8d2760298cb75ffe3d0529 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 00:21:37 2012 +0200 Move TPM code to romstage We want to do TPM initialization as early as possible to keep the impact on boot time low. Therefore move it to romstage. Change-Id: I5f2e021e0b11bd70a78ad1f05ec09802d015dd9e Signed-off-by: Stefan Reinauer <reinauer(a)google.com> … [View More]

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Patch merged into coreboot/master: b11cee2 Drop verified boot code from acpi.c
by gerrit＠coreboot.org 04 Apr '12

04 Apr '12

the following patch was just integrated into master: commit b11cee23d99ffe5dcbfea2758bd1ee5cff19911b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Apr 3 18:53:48 2012 +0200 Drop verified boot code from acpi.c We changed our verified boot initialization to run from romstage, as that allows faster boot times and does not add as much ChromeOS specific code to generic files. Change-Id: Id4164c26d524ea0ffce34467cf91379a19a4b2f6 Signed-… [View More]

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Patch merged into coreboot/master: c5d7b59 Drop duplicate inclusion of src/vendorcode
by gerrit＠coreboot.org 04 Apr '12

04 Apr '12

the following patch was just integrated into master: commit c5d7b59f41b0e12b5b27c6351fbf12b3126d9006 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 00:31:14 2012 +0200 Drop duplicate inclusion of src/vendorcode Change-Id: I95908bdca51c5ee959ae9f2307d4b6e0e002d04a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/857 for details. -gerrit

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Re: [coreboot] GSoC project ideas
by Paul Geraedts 04 Apr '12

04 Apr '12

On Tue Mar 13 05:21:11 CET 2012, Peter Stuge wrote: >> we could easily attach a fast (66+ MHz) SPI flash chip to it. > > The OLS as SPI master mux for having an easy way to flash a real chip > used by a mainboard when booting is fine. But the chip should be able > to reside on the mainboard, and the OLS should drive the mainboard > reset while flashing. Having the OLS connect via wires means that the > SPI flash can not be driven quite so fast. The shorter wires the … [View More]> better. The OLS is a big board with exposed contacts on the bottom. I much prefer a separate wire-connected development board. Signals of ~30MHz over ~30cm cable should not pose a real problem I think and it enables a much cleaner hardware setup. Not sure if asserting the reset signal of an embedded controller will always be sufficient to make its SPI bus tri-state. Possibly, but not strictly neccesary on such a non-shared bus. The underdefined or even nonexistent documentation in combination with dedicated ISP pins on them make me not too confident about it. Anyhow, these reset signals are often not easily accessible. During most part of the coreboot porting I do not intend to touch the internal SPI flash anyway, not even reading it. I will just deactivate it with its hold_n signal and use one of two external flash chips instead. When I eventually do want to touch the internal flash I will first write some embedded controller bootstrap code that makes it go into a tri-state, interrupt-masked, in-chip loop if it detects a specific (externally applied) SPI signal state at startup. If possible I will prefer using existing functionality here. More generally, my plan is to focus on 3 separate use cases, lets denote them as: users, hackers and developers. No physical hardware access should be necessary for users, only reliable flashrom access. Hackers may want physical hardware access. Easy access by means of something like a SOP test clip and mini-PCIe card, preferably without even soldering an SPI and LPC pin header. Developers / automatic test setups may want full physical hardware access. Nevertheless, I prefer to avoid invasive hardware access as much as possible. (I would go as far as applying a computer-controlled power socket in combination with a mechanical finger: much more elegant. : ) > The OLS is not a good fit for installation into e.g. a laptop. This > is one of the use cases for a QiProg; it's intended to be soldered > into the target system, on top of, or very near, the flash chip. Can you please post a reference to this QiProg device? I would like to read more about it and Google does not seem to know it. > I don't know that LPC is usually available, but even so it is a nice > start, and VHDL already exists. Although not part of the official standard, many non-WWAN mini-PCIe slots carry the 7 mandatory LPC signals instead of the official 7 UIM signals. I have added the typical signal mapping below. Unfortunately, the SERIRQ signal is not part of the 7 mandatory LPC signals. It may be available on a separate LPC pin header. Regards, Paul mini-PCIe pin | offical signal | LPC signal 08 | UIM_PWR | LFRAME# 10 | UIM_DATA | LAD3 12 | UIM_CLK | LAD2 14 | UIM_RESET | LAD1 16 | UIM_VPP | LAD0 17 | UIM_C8 | LRESET# 19 | UIM_C4 | LCLK [View Less]

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Re: [coreboot] GSoC project ideas
by Paul Geraedts 04 Apr '12

04 Apr '12

On Sat Mar 10 21:27:41 CET 2012, Carl-Daniel Hailfinger wrote: > given the lack of affordable and available hardware tools for coreboot > development, I propose to look for a different set of projects this > year: Tools which would help developers, and which are usable especially > with current hardware. A list of ideas follows. > > - Flash ICE device with SPI support. > - Flash ICE device with LPC/FWH support. > - Serial emulation for LPC buses on a configurable I/O … [View More]

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Re: [coreboot] Asus M5A88-v evo
by HighlyCaffeinated 03 Apr '12

03 Apr '12

>I bought an M5A88-v Motherboard ( >http://www.newegg.com/Product/Product.aspx?Item=N82E16813131733&Tpk=m5a88-v >) and an amd FX-4170 ( >http://www.newegg.com/Product/Product.aspx?Item=N82E16819106009 ) > >I use Fedora 16 on this machine. Compiled coreboot with a vga bios >from my board, flashed it, and in doing managed to brick the board. I >have another computer I was able to use to flash a vendor bios onto >the rom chip. Compiled again without video bios, and … [View More]

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Re: [coreboot] Asus M5A88-v evo
by Peter Stuge 03 Apr '12

03 Apr '12

Jonathan Bennett wrote: > cpuSetAMDMSR FIXME! CPU Version unknown or not supported! That's pretty clear. I suggest to boot with factory BIOS, check the exact parameters of the CPU, look at the code which is being run, and look for relevant documentation for your CPU in the scope of that code. If you are lucky you only need to add a few values from the documentation to tables in the code. //Peter

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Patch merged into coreboot/master: 8a57e1f Add support to run SMM handler in TSEG instead of ASEG
by gerrit＠coreboot.org 03 Apr '12

03 Apr '12

the following patch was just integrated into master: commit 8a57e1fab956b159a549e96274d550abce724d52 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 2 13:24:04 2012 -0700 Add support to run SMM handler in TSEG instead of ASEG Traditionally coreboot's SMM handler runs in ASEG (0xa0000), "behind" the graphics memory. This approach has two issues: - It limits the possible size of the SMM handler (and the number of CPUs supported in a system) -… [View More]

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Patch set updated for coreboot: 8a57e1f Add support to run SMM handler in TSEG instead of ASEG
by Stefan Reinauer 03 Apr '12

03 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/842 -gerrit commit 8a57e1fab956b159a549e96274d550abce724d52 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 2 13:24:04 2012 -0700 Add support to run SMM handler in TSEG instead of ASEG Traditionally coreboot's SMM handler runs in ASEG (0xa0000), "behind" the graphics memory. This approach has two issues: - It … [View More]limits the possible size of the SMM handler (and the number of CPUs supported in a system) - It's not considered a supported path anymore in newer CPUs. Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Acked-by: Stefan Reinauer <reinauer(a)google.com> --- Makefile.inc | 5 + src/console/vtxprintf.c | 6 + src/cpu/x86/smm/Makefile.inc | 14 ++- src/cpu/x86/smm/smihandler.c | 9 +- src/cpu/x86/smm/smm_tseg.ld | 58 +++++++ src/cpu/x86/smm/smmhandler_tseg.S | 300 +++++++++++++++++++++++++++++++++++++ src/cpu/x86/smm/smmrelocate.S | 49 ++++++ src/include/cpu/x86/smm.h | 2 + 8 files changed, 440 insertions(+), 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 81d40df..9b67496 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -62,6 +62,11 @@ endif smm-c-ccopts:=-D__SMM__ smm-S-ccopts:=-D__SMM__ +# SMM TSEG base is dynamic +ifeq ($(CONFIG_SMM_TSEG),y) +smm-c-ccopts += -fpic +endif + ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 4053023..a370e5f 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -6,6 +6,7 @@ #include <string.h> #include <div64.h> +#include <console/console.h> #include <console/vtxprintf.h> /* haha, don't need ctype.c */ @@ -115,6 +116,11 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args int count; +#if defined(__SMM__) && CONFIG_SMM_TSEG + /* Fix pointer in TSEG */ + tx_byte = console_tx_byte; +#endif + for (count=0; *fmt ; ++fmt) { if (*fmt != '%') { tx_byte(*fmt), count++; diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 85bb454..108f8f9 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -22,15 +22,25 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm_wrap endif +# Use TSEG specific entry point and linker script +ifeq ($(CONFIG_SMM_TSEG),y) +smm-y += smmhandler_tseg.S +SMM_LDFLAGS := $(LDFLAGS) -pie +SMM_LDSCRIPT := smm_tseg.ld +else smm-y += smmhandler.S +SMM_LDFLAGS := $(LDFLAGFS) +SMM_LDSCRIPT := smm.ld +endif + smm-y += smihandler.c smm-y += smiutil.c $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(CC) $(LDFLAGS) -nostdlib -r -o $@ $^ -$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld $(obj)/ldoptions - $(CC) $(LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o +$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/ldoptions + $(CC) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o $(NM) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map $(OBJCOPY) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index a6ab87f..bbed0f1 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -25,10 +25,11 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> +#if !CONFIG_SMM_TSEG /* TSEG handler locks in assembly */ typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; /* SMI multiprocessing semaphore */ -static volatile smi_semaphore smi_handler_status __attribute__ ((aligned (4))) = SMI_UNLOCKED; +static volatile smi_semaphore smi_handler_status __attribute__ ((aligned (4))) = SMI_UNLOCKED; static int smi_obtain_lock(void) { @@ -56,6 +57,7 @@ void smi_release_lock(void) : "eax" ); } +#endif #define LAPIC_ID 0xfee00020 static inline __attribute__((always_inline)) unsigned long nodeid(void) @@ -116,6 +118,7 @@ void smi_handler(u32 smm_revision) unsigned int node; smm_state_save_area_t state_save; +#if !CONFIG_SMM_TSEG /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { /* For security reasons we don't release the other CPUs @@ -128,6 +131,7 @@ void smi_handler(u32 smm_revision) } return; } +#endif smi_backup_pci_address(); @@ -145,6 +149,7 @@ void smi_handler(u32 smm_revision) (0xa8000 + 0x7e00 - (node * 0x400)); break; case 0x00030100: + case 0x00030101: /* SandyBridge */ state_save.type = EM64T; state_save.em64t_state_save = (em64t_smm_state_save_area_t *) (0xa8000 + 0x7d00 - (node * 0x400)); @@ -173,7 +178,9 @@ void smi_handler(u32 smm_revision) smi_restore_pci_address(); +#if !CONFIG_SMM_TSEG smi_release_lock(); +#endif /* De-assert SMI# signal to allow another SMI */ smi_set_eos(); diff --git a/src/cpu/x86/smm/smm_tseg.ld b/src/cpu/x86/smm/smm_tseg.ld new file mode 100644 index 0000000..016b5a0 --- /dev/null +++ b/src/cpu/x86/smm/smm_tseg.ld @@ -0,0 +1,58 @@ +/* Maximum number of CPUs/cores */ +CPUS = 16; + +SECTIONS +{ + /* This is the actual SMM handler. + * + * We just put code, rodata, data and bss all in a row. + */ + .handler (.): { + /* Assembler stub */ + *(.handler) + + /* C code of the SMM handler */ + *(.text); + *(.text.*); + + /* C read-only data of the SMM handler */ + . = ALIGN(16); + *(.rodata) + *(.rodata.*) + *(.data.rel.ro.*) + + /* C read-write data of the SMM handler */ + . = ALIGN(4); + *(.data) + + /* C uninitialized data of the SMM handler */ + . = ALIGN(4); + *(.bss) + *(.sbss) + + /* What is this? */ + *(COMMON) + . = ALIGN(4); + } + + /* We are using the TSEG interleaved to stuff the SMM handlers + * for all CPU cores in there. The jump table redirects the execution + * to the actual SMM handler + */ + . = 0x8000 - (( CPUS - 1) * 0x400); + .jumptable : { + *(.jumptable) + } + + /* Data used in early SMM TSEG handler. */ + . = 0x8400; + .earlydata : { + *(.earlydata) + } + + /DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) + } +} diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S new file mode 100644 index 0000000..8fdd75f --- /dev/null +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -0,0 +1,300 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * +--------------------------------+ 0xffff + * | Save State Map Node 0 | + * | Save State Map Node 1 | + * | Save State Map Node 2 | + * | Save State Map Node 3 | + * | ... | + * +--------------------------------+ 0xf000 + * | | + * | | + * | EARLY DATA (lock, vectors) | + * +--------------------------------+ 0x8400 + * | SMM Entry Node 0 (+ stack) | + * +--------------------------------+ 0x8000 + * | SMM Entry Node 1 (+ stack) | + * | SMM Entry Node 2 (+ stack) | + * | SMM Entry Node 3 (+ stack) | + * | ... | + * +--------------------------------+ 0x7400 + * | | + * | SMM Handler | + * | | + * +--------------------------------+ TSEG + * + */ + +#define LAPIC_ID 0xfee00020 +#define SMM_STACK_SIZE (0x400 - 0x10) + +/* Values for the xchg lock */ +#define SMI_LOCKED 0 +#define SMI_UNLOCKED 1 + +#define __PRE_RAM__ +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE +#include <northbridge/intel/sandybridge/sandybridge.h> +#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) +#else +#error "Northbridge must define TSEG_BAR." +#endif + +/* initially SMM is some sort of real mode. Let gcc know + * how to treat the SMM handler stub + */ + +.section ".handler", "a", @progbits + +.code16 + +/** + * SMM code to enable protected mode and jump to the + * C-written function void smi_handler(u32 smm_revision) + * + * All the bad magic is not all that bad after all. + */ +smm_handler_start: + movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ + addr32 movl (%eax), %edx /* Save TSEG_BAR in %edx */ + andl $~1, %edx /* Remove lock bit */ + + /* Obtain lock */ + movl %edx, %ebx + addl $(smm_lock), %ebx + movw $SMI_LOCKED, %ax + addr32 xchg %ax, (%ebx) + cmpw $SMI_UNLOCKED, %ax + + /* Proceed if we got the lock */ + je smm_check_prot_vector + + /* If we did not get the lock, wait for release */ +wait_for_unlock: + addr32 movw (%ebx), %ax + cmpw $SMI_LOCKED, %ax + je wait_for_unlock + rsm + +smm_check_prot_vector: + /* See if we need to adjust protected vector */ + movl %edx, %eax + addl $(smm_prot_vector), %eax + addr32 movl (%eax), %ebx + cmpl $(smm_prot_start), %ebx + jne smm_check_gdt_vector + + /* Adjust vector with TSEG offset */ + addl %edx, %ebx + addr32 movl %ebx, (%eax) + +smm_check_gdt_vector: + /* See if we need to adjust GDT vector */ + movl %edx, %eax + addl $(smm_gdt_vector + 2), %eax + addr32 movl (%eax), %ebx + cmpl $(smm_gdt - smm_handler_start), %ebx + jne smm_load_gdt + + /* Adjust vector with TSEG offset */ + addl %edx, %ebx + addr32 movl %ebx, (%eax) + +smm_load_gdt: + movl $(smm_gdt_vector), %ebx + addl %edx, %ebx /* TSEG base in %edx */ + data32 lgdt (%ebx) + + movl %cr0, %eax + andl $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */ + orl $0x1, %eax /* PE = 1 */ + movl %eax, %cr0 + + /* Enable protected mode */ + movl $(smm_prot_vector), %eax + addl %edx, %eax + data32 ljmp *(%eax) + +.code32 +smm_prot_start: + /* Use flat data segment */ + movw $0x10, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + + /* Get this CPU's LAPIC ID */ + movl $LAPIC_ID, %esi + movl (%esi), %ecx + shr $24, %ecx + + /* calculate stack offset by multiplying the APIC ID + * by 1024 (0x400), and save that offset in ebp. + */ + shl $10, %ecx + movl %ecx, %ebp + + /* We put the stack for each core right above + * its SMM entry point. Core 0 starts at SMM_BASE + 0x8000, + * we spare 0x10 bytes for the jump to be sure. + */ + movl $0x8010, %eax /* core 0 address */ + addl %edx, %eax /* addjust for TSEG */ + subl %ecx, %eax /* subtract offset, see above */ + movl %eax, %ebx /* Save bottom of stack in ebx */ + + /* clear stack */ + cld + movl %eax, %edi + movl $(SMM_STACK_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + + /* set new stack */ + addl $SMM_STACK_SIZE, %ebx + movl %ebx, %esp + + /* Get SMM revision */ + movl $0xfefc, %ebx /* core 0 address */ + addl %edx, %ebx /* addjust for TSEG */ + subl %ebp, %ebx /* subtract core X offset */ + movl (%ebx), %eax + pushl %eax + + /* Call 32bit C handler */ + call smi_handler + + /* Release lock */ + movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ + movl (%eax), %ebx /* Save TSEG_BAR in %ebx */ + andl $~1, %ebx /* Remove lock bit */ + addl $(smm_lock), %ebx + movw $SMI_UNLOCKED, %ax + xchg %ax, (%ebx) + + /* To return, just do rsm. It will "clean up" protected mode */ + rsm + +smm_gdt: + /* The first GDT entry can not be used. Keep it zero */ + .long 0x00000000, 0x00000000 + + /* gdt selector 0x08, flat code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */ + + /* gdt selector 0x10, flat data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 + +smm_gdt_end: + +.section ".earlydata", "a", @progbits + +.code16 + +.align 4, 0xff + +smm_lock: + .word SMI_UNLOCKED + +.align 4, 0xff + +smm_prot_vector: + .long smm_prot_start + .short 8 + +.align 4, 0xff + +smm_gdt_vector: + .word smm_gdt_end - smm_gdt - 1 + .long smm_gdt - smm_handler_start + +.section ".jumptable", "a", @progbits + +/* This is the SMM jump table. All cores use the same SMM handler + * for simplicity. But SMM Entry needs to be different due to the + * save state area. The jump table makes sure all CPUs jump into the + * real handler on SMM entry. + */ + +/* This code currently supports up to 16 CPU cores. If more than 16 CPU cores + * shall be used, below table has to be updated, as well as smm_tseg.ld + */ + +/* When using TSEG do a relative jump and fix up the CS later since we + * do not know what our TSEG base is yet. + */ + +.code16 +jumptable: + /* core 15 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 14 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 13 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 12 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 11 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 10 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 9 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 8 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 7 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 6 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 5 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 4 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 3 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 2 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 1 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 0 */ + jmp smm_handler_start +.align 1024, 0x00 diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 7b38348..bc5b2da 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -39,6 +39,12 @@ #error "Southbridge needs SMM handler support." #endif +#if CONFIG_SMM_TSEG + +#include <cpu/x86/mtrr.h> + +#endif /* CONFIG_SMM_TSEG */ + #define LAPIC_ID 0xfee00020 .global smm_relocation_start @@ -100,6 +106,7 @@ smm_relocation_start: /* Check revision to see if AMD64 style SMM_BASE * Intel Core Solo/Duo: 0x30007 * Intel Core2 Solo/Duo: 0x30100 + * Intel SandyBridge: 0x30101 * AMD64: 0x3XX64 * This check does not make much sense, unless someone ports * SMI handling to AMD64 CPUs. @@ -127,11 +134,53 @@ smm_relocate: movl %ecx, %edx shl $10, %edx +#if CONFIG_SMM_TSEG + movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */ + addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ + andl $~1, %eax /* Remove lock bit */ +#else movl $0xa0000, %eax +#endif subl %edx, %eax /* subtract offset, see above */ addr32 movl %eax, (%ebx) +#if CONFIG_SMM_TSEG + /* Check for SMRR capability in MTRRCAP[11] */ + movl $MTRRcap_MSR, %ecx + rdmsr + bt $11, %eax + jnc skip_smrr + + /* TSEG base */ + movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */ + addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ + andl $~1, %eax /* Remove lock bit */ + movl %eax, %ebx + + /* Set SMRR base address. */ + movl $SMRRphysBase_MSR, %ecx + orl $MTRR_TYPE_WRBACK, %eax + xorl %edx, %edx + wrmsr + + /* Set SMRR mask. */ + movl $SMRRphysMask_MSR, %ecx + movl $(~(CONFIG_SMM_TSEG_SIZE - 1) | MTRRphysMaskValid), %eax + xorl %edx, %edx + wrmsr + +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE + /* + * IED base is top 4M of TSEG + */ + addl $(CONFIG_SMM_TSEG_SIZE - IED_SIZE), %ebx + movl $(0x30000 + 0x8000 + 0x7eec), %eax + addr32 movl %ebx, (%eax) +#endif + +skip_smrr: +#endif /* The next section of code is potentially southbridge specific */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index c314c39..60959f5 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -280,6 +280,8 @@ void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_ void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts); int __attribute__((weak)) mainboard_apm_cnt(u8 data); +#if !CONFIG_SMM_TSEG void smi_release_lock(void); +#endif #endif [View Less]

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Patch set updated for coreboot: 9bb029d Makefile: rename coreboot_ap linking filenames
by Kyösti Mälkki 03 Apr '12

03 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/840 -gerrit commit 9bb029d5839d4621649e361c420d40e29272a30f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 3 21:01:06 2012 +0300 Makefile: rename coreboot_ap linking filenames $(obj)/coreboot_ap -> $(objcbfs)/coreboot_ap.elf It is really a ramstage for AP CPU and not a romstage, it is not enabled for any … [View More]mainboard by default, and it doesn't compile even if enabled. Change-Id: Ifb9c5cb6df65309660b000876cf6a9a3da9b6839 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 27 +++++++++------------------ 1 files changed, 9 insertions(+), 18 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8ab5fa8..b9b811f 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -47,7 +47,7 @@ ifeq ($(CONFIG_PAYLOAD_FILO),y) COREBOOT_ROM_DEPENDENCIES+=filo endif ifeq ($(CONFIG_AP_CODE_IN_CAR),y) -COREBOOT_ROM_DEPENDENCIES+=$(obj)/coreboot_ap +COREBOOT_ROM_DEPENDENCIES+=$(objcbfs)/coreboot_ap.elf endif ifeq ($(CONFIG_GEODE_VSA_FILE),y) COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_VSA_FILENAME) @@ -76,9 +76,9 @@ endif $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp - if [ -f $(obj)/coreboot_ap ]; \ + if [ -f $(objcbfs)/coreboot_ap.elf ]; \ then \ - $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ap $(CONFIG_CBFS_PREFIX)/coreboot_ap $(CBFS_COMPRESS_FLAG); \ + $(CBFSTOOL) $@.tmp add-stage $(objcbfs)/coreboot_ap.elf $(CONFIG_CBFS_PREFIX)/coreboot_ap $(CBFS_COMPRESS_FLAG); \ fi $(CBFSTOOL) $@.tmp add-stage $(objcbfs)/coreboot_ram.elf $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) @@ -173,20 +173,15 @@ $(objsec)/coreboot_ram.a: $$(ramstage-objs) $(AR) cr $@ $^ ####################################################################### -# coreboot_ap.rom +# Ramstage for AP CPU (AMD K8, obsolete?) -ifeq ($(CONFIG_AP_CODE_IN_CAR),y) - -$(obj)/coreboot_ap: $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o +$(objcbfs)/coreboot_ap.debug: $(objsec)/ap_romstage.o $(src)/arch/x86/init/ldscript_apc.lb @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(src)/arch/x86/init/ldscript_apc.lb $^ - $(OBJCOPY) --only-keep-debug $@.tmp $@.debug - $(OBJCOPY) --strip-debug $@.tmp - $(OBJCOPY) --add-gnu-debuglink=$@.debug $@.tmp - $(NM) -n $@.tmp | sort > $@.map - mv $@.tmp $@ + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/init/ldscript_apc.lb $< -endif +$(objsec)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ ####################################################################### # done @@ -223,10 +218,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/ $(ROMCC) -c -S $(ROMCCFLAGS) -D__PRE_RAM__ -I. $(INCLUDES) $< -o $@ else -$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ - $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h @printf " CC romstage.inc\n" $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ [View Less]

1 0

Patch set updated for coreboot: 3f7b6dd Makefile: rename ramstage linking filenames
by Kyösti Mälkki 03 Apr '12

03 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/839 -gerrit commit 3f7b6ddaa8238dd806d378ebb77551620b441ae9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 3 20:39:51 2012 +0300 Makefile: rename ramstage linking filenames Move final build results under $(objcbfs). Move intermediate files under $(objsec). Change-Id: I0046f68938be81b8efa525aa50b39328ca02ecb6 … [View More]Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 23 +++++++++-------------- 1 files changed, 9 insertions(+), 14 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index db3fe0c..8ab5fa8 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -73,14 +73,14 @@ $(obj)/coreboot.pre1: $(CBFSTOOL) mv $(obj)/coreboot.rom $@ endif -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(obj)/coreboot_ram $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp if [ -f $(obj)/coreboot_ap ]; \ then \ $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ap $(CONFIG_CBFS_PREFIX)/coreboot_ap $(CBFS_COMPRESS_FLAG); \ fi - $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ram $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG) + $(CBFSTOOL) $@.tmp add-stage $(objcbfs)/coreboot_ram.elf $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) @printf " PAYLOAD \e[1;31mnone (as specified by user)\e[0m\n" endif @@ -159,23 +159,18 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug ####################################################################### # Build the coreboot_ram (stage 2) -$(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld #ldoptions +$(objcbfs)/coreboot_ram.debug: $(objsec)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $(obj)/coreboot_ram.o - $(NM) -n $@.tmp | sort > $@.map - $(OBJCOPY) --only-keep-debug $@.tmp $@.debug - $(OBJCOPY) --strip-debug $@.tmp - $(OBJCOPY) --add-gnu-debuglink=$@.debug $@.tmp - mv $@.tmp $@ + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $< -$(obj)/coreboot_ram.o: $(obj)/arch/x86/lib/c_start.ramstage.o $$(driver-objs) $(obj)/coreboot.a $(LIBGCC_FILE_NAME) +$(objsec)/coreboot_ram.o: $(obj)/arch/x86/lib/c_start.ramstage.o $$(driver-objs) $(objsec)/coreboot_ram.a $(LIBGCC_FILE_NAME) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(obj)/coreboot.a $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(objsec)/coreboot_ram.a $(LIBGCC_FILE_NAME) -Wl,--end-group -$(obj)/coreboot.a: $$(ramstage-objs) +$(objsec)/coreboot_ram.a: $$(ramstage-objs) @printf " AR $(subst $(obj)/,,$(@))\n" - rm -f $(obj)/coreboot.a - $(AR) cr $(obj)/coreboot.a $^ + rm -f $@ + $(AR) cr $@ $^ ####################################################################### # coreboot_ap.rom [View Less]

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Patch set updated for coreboot: 5b6a904 Makefile: rename bootblock linking filenames
by Kyösti Mälkki 03 Apr '12

03 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/838 -gerrit commit 5b6a90434544d1acbf254c90ead7c0708ac81eeb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 3 20:21:51 2012 +0300 Makefile: rename bootblock linking filenames Move final build results under $(objcbfs). Move intermediate files under $(objsec). Replace $(obj)/mainboard/$(MAINBOARDDIR) with $(objsec).… [View More] Change-Id: I0365304e1b0ed02a5a3ec720b0cf3e303eaefa7c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 39 ++++++++++++++------------------------- 1 files changed, 14 insertions(+), 25 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c5faf5b..db3fe0c 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -63,8 +63,8 @@ prebuild-files = \ $(call extract_nth,4,$(file)) &&) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) -$(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $$(prebuilt-files) $(CBFSTOOL) - $(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock +$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) + $(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(objcbfs)/bootblock.bin $(prebuild-files) true mv $@.tmp $@ else @@ -289,10 +289,6 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) ####################################################################### # Build the bootblock -$(obj)/coreboot.bootblock: $(obj)/bootblock.elf - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - $(OBJCOPY) -O binary $< $@ - bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds @@ -309,7 +305,7 @@ bootblock_inc += $(chipset_bootblock_inc) ifeq ($(CONFIG_SSE),y) bootblock_inc += $(src)/cpu/x86/sse_enable.inc endif -bootblock_inc += $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc +bootblock_inc += $(objsec)/bootblock.inc bootblock_inc += $(src)/arch/x86/lib/walkcbfs.S bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ @@ -317,38 +313,31 @@ ifeq ($(CONFIG_SSE),y) bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ endif -$(obj)/bootblock/ldscript.ld: $$(bootblock_lds) $(obj)/ldoptions +$(objsec)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n" - mkdir -p $(obj)/bootblock printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ -$(obj)/bootblock/bootblock.S: $$(bootblock_inc) +$(objsec)/bootblock.S: $$(bootblock_inc) @printf " GEN $(subst $(obj)/,,$(@))\n" - mkdir -p $(obj)/bootblock printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s +$(objsec)/bootblock.o: $(objsec)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -Wa,-acdlns -c -o $@ $< > $(dir $(a))/crt0.disasm + $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S $(obj)/config.h $(obj)/build.h +$(objsec)/bootblock.s: $(objsec)/bootblock.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) +$(objsec)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) @printf " ROMCC $(subst $(obj)/,,$(@))\n" - $(CC) $(INCLUDES) -MM -MT$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc \ - $< > $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc.d + $(CC) $(INCLUDES) -MM -MT$(objsec)/bootblock.inc \ + $< > $(objsec)/bootblock.inc.d $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@ -$(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld +$(objcbfs)/bootblock.debug: $(objsec)/bootblock.o $(objsec)/bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(obj)/bootblock/ldscript.ld $< - $(NM) -n $@.tmp | sort > $(obj)/bootblock.map - $(OBJCOPY) --only-keep-debug $@.tmp $(obj)/bootblock.debug - $(OBJCOPY) --strip-debug $@.tmp - $(OBJCOPY) --add-gnu-debuglink=$(obj)/bootblock.debug $@.tmp - mv $@.tmp $@ + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objsec)/bootblock.ld $< ####################################################################### # Build the romstage [View Less]

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New patch to review for coreboot: 0d1f8ce Makefile: rename romstage linking filenames
by Kyösti Mälkki 03 Apr '12

03 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/859 -gerrit commit 0d1f8cec4729d5235d6fe77a903cb65b5e87ecc6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 3 23:37:31 2012 +0300 Makefile: rename romstage linking filenames Move final build results under $(objcbfs). Move intermediate files under $(objsec). Change-Id: Ie035a1544848b26514a197c340f470201065b8d5 … [View More]Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 48 ++++++++++++++++++-------------------------- 1 files changed, 20 insertions(+), 28 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index b9b811f..4f1580c 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -230,7 +230,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/ endif # Things that appear in every board -romstage-srcs += $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s +romstage-srcs += $(objsec)/crt0.s ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c ifeq ($(CONFIG_GENERATE_MP_TABLE),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mptable.c @@ -265,11 +265,11 @@ endif ####################################################################### # Build the final rom image -$(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) +$(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre1 $@.tmp - $(CBFSTOOL) $@.tmp add-stage $(obj)/romstage.elf \ - $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(obj)/romstage/base_xip.txt) + $(CBFSTOOL) $@.tmp add-stage $(objcbfs)/romstage_xip.elf \ + $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(objcbfs)/base_xip.txt) mv $@.tmp $@ ####################################################################### @@ -328,54 +328,46 @@ $(objcbfs)/bootblock.debug: $(objsec)/bootblock.o $(objsec)/bootblock.ld ####################################################################### # Build the romstage -$(obj)/romstage.bin: $$(romstage-objs) $(obj)/romstage/link_null.ld +$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objsec)/romstage_null.ld @printf " LINK $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/link_null.ld $(romstage-objs) - $(OBJCOPY) -O binary $(obj)/romstage.elf $@ + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objsec)/romstage_null.ld $(romstage-objs) -$(obj)/coreboot.romstage: $$(romstage-objs) $(obj)/romstage/link_xip.ld +$(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objsec)/romstage_xip.ld @printf " LINK $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/link_xip.ld $(romstage-objs) - $(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map - $(OBJCOPY) --only-keep-debug $(obj)/romstage.elf $(obj)/romstage.debug - $(OBJCOPY) --strip-debug $(obj)/romstage.elf - $(OBJCOPY) --add-gnu-debuglink=$(obj)/romstage.debug $(obj)/romstage.elf - $(OBJCOPY) -O binary $(obj)/romstage.elf $@ - -$(obj)/romstage/link_null.ld: $$(ldscripts) $(obj)/ldoptions + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objsec)/romstage_xip.ld $(romstage-objs) + +$(objsec)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n" - mkdir -p $(obj)/romstage rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp printf '$(foreach ldscript,ldoptions $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@.tmp mv $@.tmp $@ -$(obj)/romstage/link_xip.ld: $(obj)/romstage/link_null.ld $(obj)/romstage/base_xip.txt +$(objsec)/romstage_xip.ld: $(objsec)/romstage_null.ld $(objcbfs)/base_xip.txt @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ - sed -e 's/^/ROMSTAGE_BASE = /g' -e 's/$$/;/g' $(obj)/romstage/base_xip.txt > $@.tmp - sed -e '/ROMSTAGE_BASE/d' $(obj)/romstage/link_null.ld >> $@.tmp + sed -e 's/^/ROMSTAGE_BASE = /g' -e 's/$$/;/g' $(objcbfs)/base_xip.txt > $@.tmp + sed -e '/ROMSTAGE_BASE/d' $(objsec)/romstage_null.ld >> $@.tmp mv $@.tmp $@ -$(obj)/romstage/base_xip.txt: $(obj)/coreboot.pre1 $(obj)/romstage.bin +$(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin rm -f $@ - $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(objcbfs)/romstage_null.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } sed -i -e 's/^/0x/g' $@.tmp mv $@.tmp $@ -$(obj)/romstage/crt0.S: $$(crt0s) +$(objsec)/crt0.S: $$(crt0s) @printf " GEN $(subst $(obj)/,,$(@))\n" - mkdir -p $(obj)/romstage printf '$(foreach crt0,$(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.romstage.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s +$(objsec)/crt0.romstage.o: $(objsec)/crt0.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -Wa,-acdlns -c -o $@ $< > $(dir $(a))/crt0.disasm + $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S $(obj)/config.h $(obj)/build.h +$(objsec)/crt0.s: $(objsec)/crt0.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ seabios: $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \ [View Less]

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New patch to review for coreboot: cc36cd1 Makefile: define build result directories
by Kyösti Mälkki 03 Apr '12

03 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/858 -gerrit commit cc36cd1f5149a5cd2f79b3caa23fbf0d07956e45 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 3 17:52:22 2012 +0300 Makefile: define build result directories Final build results (.elf, .debug, .map) are to be placed under directory $(objcbfs), the default is: $(obj)/cbfs/$(CONFIG_CBFS_PREFIX)/ … [View More] Intermediate build results (.o, .s, .S, .inc, .ld) are to be placed under directory $(objsec), the default is: $(obj)/mainboard/$(MAINBOARDDIR)/ Also defines implicit rules for final build results: .debug -> .elf and .map .elf -> .bin Change-Id: I448c6b7c9a952e54170df42091d7db438025a795 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- Makefile.inc | 10 ++++++++-- src/arch/x86/Makefile.inc | 15 +++++++++++++++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 81d40df..b321270 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -27,14 +27,17 @@ ARCHDIR-$(CONFIG_ARCH_X86) := x86 MAINBOARDDIR=$(call strip_quotes,$(CONFIG_MAINBOARD_DIR)) export MAINBOARDDIR +export objcbfs := $(obj)/cbfs/$(CONFIG_CBFS_PREFIX) +export objsec := $(obj)/mainboard/$(MAINBOARDDIR) + ####################################################################### # root rule to resolve if in build mode (ie. configuration exists) real-target: $(obj)/config.h coreboot -coreboot: $(obj)/coreboot.rom +coreboot: build-dirs $(obj)/coreboot.rom ####################################################################### # our phony targets -PHONY+= clean-abuild coreboot lint lint-stable +PHONY+= clean-abuild coreboot lint lint-stable build-dirs ####################################################################### # root source directories of coreboot @@ -164,6 +167,9 @@ $(obj)/build.h: .xcompile $(obj)/ldoptions: $(obj)/config.h awk '/^#define ([^"])* ([^"])*$$/ {gsub("\\r","",$$3); print $$2 " = " $$3 ";";}' $< > $@ +build-dirs: + mkdir -p $(objcbfs) $(objsec) + ####################################################################### # Build the tools CBFSTOOL:=$(obj)/cbfstool diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8783d4b..c5faf5b 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -142,6 +142,21 @@ $(objutil)/options/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src $(HOSTCC) $(HOSTCFLAGS) $< -o $@ ####################################################################### +# Common recipes for all stages + +$(objcbfs)/%.bin: $(objcbfs)/%.elf + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + $(OBJCOPY) -O binary $< $@ + +$(objcbfs)/%.elf: $(objcbfs)/%.debug + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cp $< $@.tmp + $(NM) -n $@.tmp | sort > $(basename $(a)).map + $(OBJCOPY) --strip-debug $@.tmp + $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp + mv $@.tmp $@ + +####################################################################### # Build the coreboot_ram (stage 2) $(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld #ldoptions [View Less]

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Patch merged into coreboot/master: 5cdbc2b libpayload: avoid excessive casts in printf.c
by gerrit＠coreboot.org 03 Apr '12

03 Apr '12

the following patch was just integrated into master: commit 5cdbc2b9e1985c6943638011d0d77f02833878cb Author: Mathias Krause <minipli(a)googlemail.com> Date: Tue Apr 3 21:02:33 2012 +0200 libpayload: avoid excessive casts in printf.c struct printf_spec is a purely internal structure. Avoid excessive casts when using the write function pointer just to make the compiler happy by using the right types in the first place. Change-Id: … [View More]

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Patch merged into coreboot/master: 82eb56b libpayload: minor cleanups
by gerrit＠coreboot.org 03 Apr '12

03 Apr '12

the following patch was just integrated into master: commit 82eb56b102aa2294961bb65a244b537d521b9d12 Author: Mathias Krause <minipli(a)googlemail.com> Date: Tue Apr 3 20:42:01 2012 +0200 libpayload: minor cleanups Apply some const correctness to const/non-const strings in libc and libpci (what an ugly cast that was). Remove duplicated NULL test in printf_putstr(), already done in print_string() - reduces size of libpayload by a few bytes. Change-… [View More]

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Patch merged into coreboot/master: 89b0a39 Don't unconditionally show ChromeOS options
by gerrit＠coreboot.org 03 Apr '12

03 Apr '12

the following patch was just integrated into master: commit 89b0a39450aa1e4d7d91f2bad7d2802833789e55 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Apr 3 11:22:15 2012 -0700 Don't unconditionally show ChromeOS options Google ChromeOS specific options were shown in the main menu unconditionally, even on non-ChromeOS devices. Instead, hide these options unless CONFIG_CHROMEOS is set, and also put them in a separate menu. Change-Id: … [View More]

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New patch to review for coreboot: c5d7b59 Drop duplicate inclusion of src/vendorcode
by Stefan Reinauer 03 Apr '12

03 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/857 -gerrit commit c5d7b59f41b0e12b5b27c6351fbf12b3126d9006 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 00:31:14 2012 +0200 Drop duplicate inclusion of src/vendorcode Change-Id: I95908bdca51c5ee959ae9f2307d4b6e0e002d04a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- Makefile.inc | … [View More]

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Re: [coreboot] Asus M5A88-v evo
by Jonathan Bennett 03 Apr '12

03 Apr '12

On Tue, Mar 20, 2012 at 4:36 PM, Julian Shulika <hercares(a)gmail.com> wrote: > Could you please show log from serial,your board has com port. Finally got a couple spare flash chips and a way to capture the serial output. coreboot-4.0-2227-g4a2daf6 Tue Apr 3 15:29:40 CDT 2012 starting... BSP Family_Model: 00600f12 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: rev id not foung, Skipping microcode patch! POST: 0x33 cpuSetAMDMSR FIXME! CPU … [View More]

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New patch to review for coreboot: d93b82f Move TPM code to romstage
by Stefan Reinauer 03 Apr '12

03 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/856 -gerrit commit d93b82ff774411f77f8d2760298cb75ffe3d0529 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 00:21:37 2012 +0200 Move TPM code to romstage We want to do TPM initialization as early as possible to keep the impact on boot time low. Therefore move it to romstage. Change-Id: … [View More]

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Patch set updated for coreboot: c276a74 Add support for Intel Panther Point PCH
by Stefan Reinauer 03 Apr '12

03 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/853 -gerrit commit c276a7462a7f1fdfb66ff7ba446c9c3138b0690f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 00:07:22 2012 +0200 Add support for Intel Panther Point PCH Change-Id: Iac3cd25b36493bb203e849674320e113cc5fce32 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan … [View More]Reinauer <reinauer(a)google.com> --- src/Kconfig | 10 + src/southbridge/intel/Kconfig | 1 + src/southbridge/intel/Makefile.inc | 2 + src/southbridge/intel/bd82x6x/Kconfig | 68 ++ src/southbridge/intel/bd82x6x/Makefile.inc | 43 + src/southbridge/intel/bd82x6x/acpi/audio.asl | 36 + src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 244 ++++++ src/southbridge/intel/bd82x6x/acpi/irqlinks.asl | 493 +++++++++++ src/southbridge/intel/bd82x6x/acpi/lpc.asl | 248 ++++++ src/southbridge/intel/bd82x6x/acpi/pch.asl | 269 ++++++ src/southbridge/intel/bd82x6x/acpi/pcie.asl | 234 +++++ src/southbridge/intel/bd82x6x/acpi/sata.asl | 83 ++ src/southbridge/intel/bd82x6x/acpi/sleepstates.asl | 27 + src/southbridge/intel/bd82x6x/acpi/smbus.asl | 242 +++++ src/southbridge/intel/bd82x6x/acpi/usb.asl | 91 ++ src/southbridge/intel/bd82x6x/azalia.c | 367 ++++++++ src/southbridge/intel/bd82x6x/bootblock.c | 73 ++ src/southbridge/intel/bd82x6x/chip.h | 79 ++ src/southbridge/intel/bd82x6x/early_me.c | 201 +++++ src/southbridge/intel/bd82x6x/early_smbus.c | 63 ++ src/southbridge/intel/bd82x6x/early_usb.c | 57 ++ src/southbridge/intel/bd82x6x/finalize.c | 56 ++ src/southbridge/intel/bd82x6x/gpio.c | 65 ++ src/southbridge/intel/bd82x6x/gpio.h | 153 ++++ src/southbridge/intel/bd82x6x/lpc.c | 678 +++++++++++++++ src/southbridge/intel/bd82x6x/me.c | 750 ++++++++++++++++ src/southbridge/intel/bd82x6x/me.h | 376 ++++++++ src/southbridge/intel/bd82x6x/me_8.x.c | 919 ++++++++++++++++++++ src/southbridge/intel/bd82x6x/me_status.c | 213 +++++ src/southbridge/intel/bd82x6x/nvs.h | 139 +++ src/southbridge/intel/bd82x6x/pch.c | 234 +++++ src/southbridge/intel/bd82x6x/pch.h | 514 +++++++++++ src/southbridge/intel/bd82x6x/pci.c | 145 +++ src/southbridge/intel/bd82x6x/pcie.c | 306 +++++++ src/southbridge/intel/bd82x6x/reset.c | 41 + src/southbridge/intel/bd82x6x/sata.c | 246 ++++++ src/southbridge/intel/bd82x6x/smbus.c | 113 +++ src/southbridge/intel/bd82x6x/smbus.h | 100 +++ src/southbridge/intel/bd82x6x/smi.c | 403 +++++++++ src/southbridge/intel/bd82x6x/smihandler.c | 709 +++++++++++++++ src/southbridge/intel/bd82x6x/usb_debug.c | 51 ++ src/southbridge/intel/bd82x6x/usb_ehci.c | 124 +++ src/southbridge/intel/bd82x6x/watchdog.c | 59 ++ 43 files changed, 9325 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 0696feb..b0261d9 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -869,6 +869,16 @@ config DEBUG_TPM help This option enables additional TPM related debug messages. +if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8 +# Only visible with the right southbridge and loglevel. +config DEBUG_INTEL_ME + bool "Verbose logging for Intel Management Engine" + default n + help + Enable verbose logging for Intel Management Engine driver that + is present on Intel 6-series chipsets. +endif + config LLSHELL bool "Built-in low-level shell" default n diff --git a/src/southbridge/intel/Kconfig b/src/southbridge/intel/Kconfig index e6ffac9..cb0ac83 100644 --- a/src/southbridge/intel/Kconfig +++ b/src/southbridge/intel/Kconfig @@ -10,3 +10,4 @@ source src/southbridge/intel/i82801gx/Kconfig source src/southbridge/intel/i82870/Kconfig source src/southbridge/intel/pxhd/Kconfig source src/southbridge/intel/sch/Kconfig +source src/southbridge/intel/bd82x6x/Kconfig diff --git a/src/southbridge/intel/Makefile.inc b/src/southbridge/intel/Makefile.inc index b399955..6869e5b 100644 --- a/src/southbridge/intel/Makefile.inc +++ b/src/southbridge/intel/Makefile.inc @@ -10,3 +10,5 @@ subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82870) += i82870 subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_PXHD) += pxhd subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_SCH) += sch +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += bd82x6x +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += bd82x6x diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig new file mode 100644 index 0000000..3891be1 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -0,0 +1,68 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_INTEL_BD82X6X + bool + +config SOUTHBRIDGE_INTEL_C216 + bool + +if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 + +config SOUTH_BRIDGE_OPTIONS # dummy + def_bool y + select IOAPIC + select HAVE_HARD_RESET + select HAVE_USBDEBUG + select USE_WATCHDOG_ON_BOOT + select PCIEXP_ASPM + select PCIEXP_COMMON_CLOCK + +config EHCI_BAR + hex + default 0xfef00000 + +config EHCI_DEBUG_OFFSET + hex + default 0xa0 + +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/intel/bd82x6x/bootblock.c" + +config SERIRQ_CONTINUOUS_MODE + bool + default n + help + If you set this option to y, the serial IRQ machine will be + operated in continuous mode. + +endif + +if SOUTHBRIDGE_INTEL_BD82X6X +config PCH_CHIP_NAME + string + default "Cougar Point" +endif + +if SOUTHBRIDGE_INTEL_C216 +config PCH_CHIP_NAME + string + default "Panther Point" +endif diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc new file mode 100644 index 0000000..5732254 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -0,0 +1,43 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +me-src-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += me.c +me-src-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += me_8.x.c + +driver-y += pch.c +driver-y += azalia.c +driver-y += lpc.c +driver-y += pci.c +driver-y += pcie.c +driver-y += sata.c +driver-y += usb_ehci.c +driver-y += $(me-src-y) +driver-y += smbus.c + +ramstage-y += me_status.c +ramstage-y += reset.c +ramstage-y += watchdog.c + +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c $(me-src-y) finalize.c + +romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c +romstage-$(CONFIG_USBDEBUG) += usb_debug.c +romstage-y += reset.c + diff --git a/src/southbridge/intel/bd82x6x/acpi/audio.asl b/src/southbridge/intel/bd82x6x/acpi/audio.asl new file mode 100644 index 0000000..a455328 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/acpi/audio.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Intel PCH HDA */ + +// Intel High Definition Audio (Azalia) 0:1b.0 + +Device (HDEF) +{ + Name (_ADR, 0x001b0000) + + // Power Resources for Wake + Name (_PRW, Package(){ + 13, // Bit 13 of GPE + 4 // Can wake from S4 state. + }) +} + diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl new file mode 100644 index 0000000..df450e3 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Global Variables */ + +Name(\PICM, 0) // IOAPIC/8259 +Name(\DSEN, 1) // Display Output Switching Enable + +/* Global ACPI memory region. This region is used for passing information + * between coreboot (aka "the system bios"), ACPI, and the SMI handler. + * Since we don't know where this will end up in memory at ACPI compile time, + * we have to fix it up in coreboot's ACPI creation phase. + */ + + +OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xf00) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + Offset (0x00), + OSYS, 16, // 0x00 - Operating System + SMIF, 8, // 0x02 - SMI function + PRM0, 8, // 0x03 - SMI function parameter + PRM1, 8, // 0x04 - SMI function parameter + SCIF, 8, // 0x05 - SCI function + PRM2, 8, // 0x06 - SCI function parameter + PRM3, 8, // 0x07 - SCI function parameter + LCKF, 8, // 0x08 - Global Lock function for EC + PRM4, 8, // 0x09 - Lock function parameter + PRM5, 8, // 0x0a - Lock function parameter + P80D, 32, // 0x0b - Debug port (IO 0x80) value + LIDS, 8, // 0x0f - LID state (open = 1) + PWRS, 8, // 0x10 - Power State (AC = 1) + /* Thermal policy */ + Offset (0x11), + TLVL, 8, // 0x11 - Throttle Level Limit + FLVL, 8, // 0x12 - Current FAN Level + TCRT, 8, // 0x13 - Critical Threshold + TPSV, 8, // 0x14 - Passive Threshold + TMAX, 8, // 0x15 - CPU Tj_max + F0OF, 8, // 0x16 - FAN 0 OFF Threshold + F0ON, 8, // 0x17 - FAN 0 ON Threshold + F0PW, 8, // 0x18 - FAN 0 PWM value + F1OF, 8, // 0x19 - FAN 1 OFF Threshold + F1ON, 8, // 0x1a - FAN 1 ON Threshold + F1PW, 8, // 0x1b - FAN 1 PWM value + F2OF, 8, // 0x1c - FAN 2 OFF Threshold + F2ON, 8, // 0x1d - FAN 2 ON Threshold + F2PW, 8, // 0x1e - FAN 2 PWM value + F3OF, 8, // 0x1f - FAN 3 OFF Threshold + F3ON, 8, // 0x20 - FAN 3 ON Threshold + F3PW, 8, // 0x21 - FAN 3 PWM value + F4OF, 8, // 0x22 - FAN 4 OFF Threshold + F4ON, 8, // 0x23 - FAN 4 ON Threshold + F4PW, 8, // 0x24 - FAN 4 PWM value + /* Processor Identification */ + Offset (0x28), + APIC, 8, // 0x28 - APIC Enabled by coreboot + MPEN, 8, // 0x29 - Multi Processor Enable + PCP0, 8, // 0x2a - PDC CPU/CORE 0 + PCP1, 8, // 0x2b - PDC CPU/CORE 1 + PPCM, 8, // 0x2c - Max. PPC state + PCNT, 8, // 0x2d - Processor count + /* Super I/O & CMOS config */ + Offset (0x32), + NATP, 8, // 0x32 - + S5U0, 8, // 0x32 - Enable USB0 in S5 + S5U1, 8, // 0x33 - Enable USB1 in S5 + S3U0, 8, // 0x35 - Enable USB0 in S3 + S3U1, 8, // 0x36 - Enable USB1 in S3 + S33G, 8, // 0x37 - Enable 3G in S3 + CMEM, 32, // 0x38 - CBMEM TOC + /* Integrated Graphics Device */ + Offset (0x3c), + IGDS, 8, // 0x3c - IGD state (primary = 1) + TLST, 8, // 0x3d - Display Toggle List pointer + CADL, 8, // 0x3e - Currently Attached Devices List + PADL, 8, // 0x3f - Previously Attached Devices List + CSTE, 16, // 0x40 - Current display state + NSTE, 16, // 0x42 - Next display state + SSTE, 16, // 0x44 - Set display state + Offset (0x46), + NDID, 8, // 0x46 - Number of Device IDs + DID1, 32, // 0x47 - Device ID 1 + DID2, 32, // 0x4b - Device ID 2 + DID3, 32, // 0x4f - Device ID 3 + DID4, 32, // 0x53 - Device ID 4 + DID5, 32, // 0x57 - Device ID 5 + /* Backlight Control */ + Offset (0x64), + BLCS, 8, // 0x64 - Backlight control possible? + BRTL, 8, // 0x65 - Brightness Level + ODDS, 8, // 0x66 + /* Ambient Light Sensors */ + Offset (0x6e), + ALSE, 8, // 0x6e - ALS enable + ALAF, 8, // 0x6f - Ambient light adjustment factor + LLOW, 8, // 0x70 - LUX Low + LHIH, 8, // 0x71 - LUX High + /* EMA */ + Offset (0x78), + EMAE, 8, // 0x78 - EMA enable + EMAP, 16, // 0x79 - EMA pointer + EMAL, 16, // 0x7b - EMA length + /* MEF */ + Offset (0x82), + MEFE, 8, // 0x82 - MEF enable + /* TPM support */ + Offset (0x8c), + TPMP, 8, // 0x8c - TPM + TPME, 8, // 0x8d - TPM enable + /* SATA */ + Offset (0x96), + GTF0, 56, // 0x96 - GTF task file buffer for port 0 + GTF1, 56, // 0x9d - GTF task file buffer for port 1 + GTF2, 56, // 0xa4 - GTF task file buffer for port 2 + IDEM, 8, // 0xab - IDE mode (compatible / enhanced) + IDET, 8, // 0xac - IDE + /* IGD OpRegion */ + Offset (0xb4), + ASLB, 32, // 0xb4 - IGD OpRegion Base Address + IBTT, 8, // 0xb8 - IGD boot panel device + IPAT, 8, // 0xb9 - IGD panel type cmos option + ITVF, 8, // 0xba - IGD TV format cmos option + ITVM, 8, // 0xbb - IGD TV minor format option + IPSC, 8, // 0xbc - IGD panel scaling + IBLC, 8, // 0xbd - IGD BLC config + IBIA, 8, // 0xbe - IGD BIA config + ISSC, 8, // 0xbf - IGD SSC config + I409, 8, // 0xc0 - IGD 0409 modified settings + I509, 8, // 0xc1 - IGD 0509 modified settings + I609, 8, // 0xc2 - IGD 0609 modified settings + I709, 8, // 0xc3 - IGD 0709 modified settings + IDMM, 8, // 0xc4 - IGD DVMT Mode + IDMS, 8, // 0xc5 - IGD DVMT memory size + IF1E, 8, // 0xc6 - IGD function 1 enable + HVCO, 8, // 0xc7 - IGD HPLL VCO + NXD1, 32, // 0xc8 - IGD _DGS next DID1 + NXD2, 32, // 0xcc - IGD _DGS next DID2 + NXD3, 32, // 0xd0 - IGD _DGS next DID3 + NXD4, 32, // 0xd4 - IGD _DGS next DID4 + NXD5, 32, // 0xd8 - IGD _DGS next DID5 + NXD6, 32, // 0xdc - IGD _DGS next DID6 + NXD7, 32, // 0xe0 - IGD _DGS next DID7 + NXD8, 32, // 0xe4 - IGD _DGS next DID8 + + /* ChromeOS specific */ + Offset (0xf0), + #include <vendorcode/google/chromeos/acpi/gnvs.asl> + // 0xe8a - end +} + +/* Set flag to enable USB charging in S3 */ +Method (S3UE) +{ + Store (One, \S3U0) + Store (One, \S3U1) +} + +/* Set flag to disable USB charging in S3 */ +Method (S3UD) +{ + Store (Zero, \S3U0) + Store (Zero, \S3U1) +} + +/* Set flag to enable USB charging in S5 */ +Method (S5UE) +{ + Store (One, \S5U0) + Store (One, \S5U1) +} + +/* Set flag to disable USB charging in S5 */ +Method (S5UD) +{ + Store (Zero, \S5U0) + Store (Zero, \S5U1) +} + +/* Set flag to enable 3G module in S3 */ +Method (S3GE) +{ + Store (One, \S33G) +} + +/* Set flag to disable 3G module in S3 */ +Method (S3GD) +{ + Store (Zero, \S33G) +} + +/* Update Fan 0 thresholds */ +Method (F0UT, 2) +{ + Store (Arg0, \F0OF) + Store (Arg1, \F0ON) +} + +/* Update Fan 1 thresholds */ +Method (F1UT, 2) +{ + Store (Arg0, \F1OF) + Store (Arg1, \F1ON) +} + +/* Update Fan 2 thresholds */ +Method (F2UT, 2) +{ + Store (Arg0, \F2OF) + Store (Arg1, \F2ON) +} + +/* Update Fan 3 thresholds */ +Method (F3UT, 2) +{ + Store (Arg0, \F3OF) + Store (Arg1, \F3ON) +} + +/* Update Fan 4 thresholds */ +Method (F4UT, 2) +{ + Store (Arg0, \F4OF) + Store (Arg1, \F4ON) +} diff --git a/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl b/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl new file mode 100644 index 0000000..5fcee45 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl @@ -0,0 +1,493 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (LNKA) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 1) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTA) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLA, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTA + ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + + Return (RTLA) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTA) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTA, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKB) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 2) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTB) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLB, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLB, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTB + ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + + Return (RTLB) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTB) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTB, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKC) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 3) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTC) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLC, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLC, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTC + ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + + Return (RTLC) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTC) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTC, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKD) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 4) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTD) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLD, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLD, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTD + ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + + Return (RTLD) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTD) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTD, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKE) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 5) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTE) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLE, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLE, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTE + ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + + Return (RTLE) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTE) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTE, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKF) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 6) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTF) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLF, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLF, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTF + ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + + Return (RTLF) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTF) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTF, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKG) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 7) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTG) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLG, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLG, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTG + ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + + Return (RTLG) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTG) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTG, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKH) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 8) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTH) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLH, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLH, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTH + ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + + Return (RTLH) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTH) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTH, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl new file mode 100644 index 0000000..cc59850 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Intel LPC Bus Device - 0:1f.0 + +Device (LPCB) +{ + Name(_ADR, 0x001f0000) + + OperationRegion(LPC0, PCI_Config, 0x00, 0x100) + Field (LPC0, AnyAcc, NoLock, Preserve) + { + Offset (0x40), + PMBS, 16, // PMBASE + Offset (0x60), // Interrupt Routing Registers + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, + Offset (0x68), + PRTE, 8, + PRTF, 8, + PRTG, 8, + PRTH, 8, + + Offset (0x80), // IO Decode Ranges + IOD0, 8, + IOD1, 8, + + Offset (0xb8), // GPIO Routing Control + GR00, 2, + GR01, 2, + GR02, 2, + GR03, 2, + GR04, 2, + GR05, 2, + GR06, 2, + GR07, 2, + GR08, 2, + GR09, 2, + GR10, 2, + GR11, 2, + GR12, 2, + GR13, 2, + GR14, 2, + GR15, 2, + + Offset (0xf0), // RCBA + RCEN, 1, + , 13, + RCBA, 18, + } + + #include "irqlinks.asl" + + #include "acpi/ec.asl" + + Device (DMAC) // DMA Controller + { + Name(_HID, EISAID("PNP0200")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x00, 0x00, 0x01, 0x20) + IO (Decode16, 0x81, 0x81, 0x01, 0x11) + IO (Decode16, 0x93, 0x93, 0x01, 0x0d) + IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } + }) + } + + Device (FWH) // Firmware Hub + { + Name (_HID, EISAID("INT0800")) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + }) + } + + Device (HPET) + { + Name (_HID, EISAID("PNP0103")) + Name (_CID, 0x010CD041) + + Name(BUF0, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + }) + + Method (_STA, 0) // Device Status + { + If (HPTE) { + // Note: Ancient versions of Windows don't want + // to see the HPET in order to work right + If (LGreaterEqual(OSYS, 2001)) { + Return (0xf) // Enable and show device + } Else { + Return (0xb) // Enable and don't show device + } + } + + Return (0x0) // Not enabled, don't show. + } + + Method (_CRS, 0, Serialized) // Current resources + { + If (HPTE) { + CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) + If (Lequal(HPAS, 1)) { + Store(0xfed01000, HPT0) + } + + If (Lequal(HPAS, 2)) { + Store(0xfed02000, HPT0) + } + + If (Lequal(HPAS, 3)) { + Store(0xfed03000, HPT0) + } + } + + Return (BUF0) + } + } + + Device(PIC) // 8259 Interrupt Controller + { + Name(_HID,EISAID("PNP0000")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x20, 0x20, 0x01, 0x02) + IO (Decode16, 0x24, 0x24, 0x01, 0x02) + IO (Decode16, 0x28, 0x28, 0x01, 0x02) + IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) + IO (Decode16, 0x30, 0x30, 0x01, 0x02) + IO (Decode16, 0x34, 0x34, 0x01, 0x02) + IO (Decode16, 0x38, 0x38, 0x01, 0x02) + IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) + IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) + IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) + IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) + IO (Decode16, 0xac, 0xac, 0x01, 0x02) + IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) + IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) + IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) + IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) + IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) + IRQNoFlags () { 2 } + }) + } + + Device(MATH) // FPU + { + Name (_HID, EISAID("PNP0C04")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) + IRQNoFlags() { 13 } + }) + } + + Device(LDRC) // LPC device: Resource consumption + { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 2) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO + IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO + IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status + IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post + IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + //IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap + IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH7-M ACPI + IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH7-M GPIO + }) + } + + Device (RTC) // Real Time Clock + { + Name (_HID, EISAID("PNP0B00")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x70, 0x70, 1, 8) +// Disable as Windows doesn't like it, and systems don't seem to use it. +// IRQNoFlags() { 8 } + }) + } + + Device (TIMR) // Intel 8254 timer + { + Name(_HID, EISAID("PNP0100")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x40, 0x40, 0x01, 0x04) + IO (Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags() {0} + }) + } + + #include "acpi/superio.asl" + +#ifdef ENABLE_TPM + Device (TPM) // Trusted Platform Module + { + Name(_HID, EISAID("IFX0102")) + Name(_CID, 0x310cd041) + Name(_UID, 1) + + Method(_STA, 0) + { + If (TPMP) { + Return (0xf) + } + Return (0x0) + } + + Name(_CRS, ResourceTemplate() { + IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) + IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) + Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) + IRQ (Edge, Activehigh, Exclusive) { 6 } + }) + } +#endif +} diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl new file mode 100644 index 0000000..3e6651d --- /dev/null +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -0,0 +1,269 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Intel Cougar Point PCH support */ + +Scope(\) +{ + // IO-Trap at 0x800. This is the ACPI->SMI communication interface. + + OperationRegion(IO_T, SystemIO, 0x800, 0x10) + Field(IO_T, ByteAcc, NoLock, Preserve) + { + Offset(0x8), + TRP0, 8 // IO-Trap at 0x808 + } + + // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l) + OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) + Field(PMIO, ByteAcc, NoLock, Preserve) + { + Offset(0x20), // GPE0_STS + , 16, + GS00, 1, // GPIO00 SCI/Wake Status + GS01, 1, // GPIO01 SCI/Wake Status + GS02, 1, // GPIO02 SCI/Wake Status + GS03, 1, // GPIO03 SCI/Wake Status + GS04, 1, // GPIO04 SCI/Wake Status + GS05, 1, // GPIO05 SCI/Wake Status + GS06, 1, // GPIO06 SCI/Wake Status + GS07, 1, // GPIO07 SCI/Wake Status + GS08, 1, // GPIO08 SCI/Wake Status + GS09, 1, // GPIO09 SCI/Wake Status + GS10, 1, // GPIO10 SCI/Wake Status + GS11, 1, // GPIO11 SCI/Wake Status + GS12, 1, // GPIO12 SCI/Wake Status + GS13, 1, // GPIO13 SCI/Wake Status + GS14, 1, // GPIO14 SCI/Wake Status + GS15, 1, // GPIO15 SCI/Wake Status + Offset(0x28), // GPE0_EN + , 16, + GE00, 1, // GPIO00 SCI/Wake Enable + GE01, 1, // GPIO01 SCI/Wake Enable + GE02, 1, // GPIO02 SCI/Wake Enable + GE03, 1, // GPIO03 SCI/Wake Enable + GE04, 1, // GPIO04 SCI/Wake Enable + GE05, 1, // GPIO05 SCI/Wake Enable + GE06, 1, // GPIO06 SCI/Wake Enable + GE07, 1, // GPIO07 SCI/Wake Enable + GE08, 1, // GPIO08 SCI/Wake Enable + GE09, 1, // GPIO09 SCI/Wake Enable + GE10, 1, // GPIO10 SCI/Wake Enable + GE11, 1, // GPIO11 SCI/Wake Enable + GE12, 1, // GPIO12 SCI/Wake Enable + GE13, 1, // GPIO13 SCI/Wake Enable + GE14, 1, // GPIO14 SCI/Wake Enable + GE15, 1, // GPIO15 SCI/Wake Enable + Offset(0x42), // General Purpose Control + , 1, // skip 1 bit + GPEC, 1, // SWGPE_CTRL + } + + // GPIO IO mapped registers (0x1f.0 reg 0x48.l) + OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c) + Field(GPIO, ByteAcc, NoLock, Preserve) + { + Offset(0x00), // GPIO Use Select + GU00, 8, + GU01, 8, + GU02, 8, + GU03, 8, + Offset(0x04), // GPIO IO Select + GIO0, 8, + GIO1, 8, + GIO2, 8, + GIO3, 8, + Offset(0x0c), // GPIO Level + GL00, 1, + GP01, 1, + GP02, 1, + GP0e, 1, + GP04, 1, + GP05, 1, + GP06, 1, + GP07, 1, + GP08, 1, + GP09, 1, + GP10, 1, + GP11, 1, + GP12, 1, + GP13, 1, + GP14, 1, + GP15, 1, + GP16, 1, + GP17, 1, + GP18, 1, + GP19, 1, + GP20, 1, + GP21, 1, + GP22, 1, + GP23, 1, + GP24, 1, + GP25, 1, + GP26, 1, + GP27, 1, + GP28, 1, + GP29, 1, + GP30, 1, + GP31, 1, + Offset(0x18), // GPIO Blink + GB00, 8, + GB01, 8, + GB02, 8, + GB03, 8, + Offset(0x2c), // GPIO Invert + GIV0, 8, + GIV1, 8, + GIV2, 8, + GIV3, 8, + Offset(0x30), // GPIO Use Select 2 + GU04, 8, + GU05, 8, + GU06, 8, + GU07, 8, + Offset(0x34), // GPIO IO Select 2 + GIO4, 8, + GIO5, 8, + GIO6, 8, + GIO7, 8, + Offset(0x38), // GPIO Level 2 + GP32, 1, + GP33, 1, + GP34, 1, + GP35, 1, + GP36, 1, + GP37, 1, + GP38, 1, + GP39, 1, + GP40, 1, + GP41, 1, + GP42, 1, + GP43, 1, + GP44, 1, + GP45, 1, + GP46, 1, + GP47, 1, + GP48, 1, + GP49, 1, + GP50, 1, + GP51, 1, + GP52, 1, + GP53, 1, + GP54, 1, + GP55, 1, + GP56, 1, + GP57, 1, + GP58, 1, + GP59, 1, + GP60, 1, + GP61, 1, + GP62, 1, + GP63, 1, + Offset(0x40), // GPIO Use Select 3 + GU08, 8, + GU09, 4, + Offset(0x44), // GPIO IO Select 3 + GIO8, 8, + GIO9, 4, + Offset(0x48), // GPIO Level 3 + GP64, 1, + GP65, 1, + GP66, 1, + GP67, 1, + GP68, 1, + GP69, 1, + GP70, 1, + GP71, 1, + GP72, 1, + GP73, 1, + GP74, 1, + GP75, 1, + } + + + // ICH7 Root Complex Register Block. Memory Mapped through RCBA) + OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + Field(RCRB, DWordAcc, Lock, Preserve) + { + Offset(0x0000), // Backbone + Offset(0x1000), // Chipset + Offset(0x3000), // Legacy Configuration Registers + Offset(0x3404), // High Performance Timer Configuration + HPAS, 2, // Address Select + , 5, + HPTE, 1, // Address Enable + Offset(0x3418), // FD (Function Disable) + , 2, // Reserved + SATD, 1, // SATA disable + SMBD, 1, // SMBUS disable + HDAD, 1, // Azalia disable + , 2, // Reserved + ILND, 1, // Internal LAN disable + US1D, 1, // UHCI #1 disable + US2D, 1, // UHCI #2 disable + US3D, 1, // UHCI #3 disable + US4D, 1, // UHCI #4 disable + , 2, // Reserved + LPBD, 1, // LPC bridge disable + EHCD, 1, // EHCI disable + Offset(0x341a), // FD Root Ports + RP1D, 1, // Root Port 1 disable + RP2D, 1, // Root Port 2 disable + RP3D, 1, // Root Port 3 disable + RP4D, 1 // Root Port 4 disable + } + +} + +// High Definition Audio (Azalia) 0:1b.0 +#include "audio.asl" + +// PCI Express Ports 0:1c.x +#include "pcie.asl" + +// USB 0:1d.0 and 0:1a.0 +#include "usb.asl" + +// LPC Bridge 0:1f.0 +#include "lpc.asl" + +// SATA 0:1f.2, 0:1f.5 +#include "sata.asl" + +// SMBus 0:1f.3 +#include "smbus.asl" + +Method (_OSC, 4) +{ + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + Else + { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } +} diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie.asl b/src/southbridge/intel/bd82x6x/acpi/pcie.asl new file mode 100644 index 0000000..f6b93bf --- /dev/null +++ b/src/southbridge/intel/bd82x6x/acpi/pcie.asl @@ -0,0 +1,234 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Intel Cougar Point PCH PCIe support */ + +// PCI Express Ports + +Device (RP01) +{ + NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation? + //#include "pcie_port.asl" + Method(_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } + }) + + } + + } +} + +Device (RP02) +{ + NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation? + //#include "pcie_port.asl" + Method(_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 17 }, + Package() { 0x0000ffff, 1, 0, 18 }, + Package() { 0x0000ffff, 2, 0, 19 }, + Package() { 0x0000ffff, 3, 0, 16 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } + }) + + } + + } +} + +Device (RP03) +{ + NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation? + //#include "pcie_port.asl" + Method(_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 18 }, + Package() { 0x0000ffff, 1, 0, 19 }, + Package() { 0x0000ffff, 2, 0, 16 }, + Package() { 0x0000ffff, 3, 0, 17 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } + }) + + } + + } +} + +Device (RP04) +{ + NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation? + //#include "pcie_port.asl" + Method(_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 17 }, + Package() { 0x0000ffff, 1, 0, 18 }, + Package() { 0x0000ffff, 2, 0, 19 }, + Package() { 0x0000ffff, 3, 0, 16 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } + }) + + } + + } +} + +Device (RP05) +{ + NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation? + //#include "pcie_port.asl" + Method(_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } + }) + + } + + } +} + +Device (RP06) +{ + NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation? + //#include "pcie_port.asl" + Method(_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 17 }, + Package() { 0x0000ffff, 1, 0, 18 }, + Package() { 0x0000ffff, 2, 0, 19 }, + Package() { 0x0000ffff, 3, 0, 16 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } + }) + + } + + } +} + +Device (RP07) +{ + NAME(_ADR, 0x001c0006) // FIXME: Have a macro for PCI Devices -> ACPI notation? + //#include "pcie_port.asl" + Method(_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 18 }, + Package() { 0x0000ffff, 1, 0, 19 }, + Package() { 0x0000ffff, 2, 0, 16 }, + Package() { 0x0000ffff, 3, 0, 17 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } + }) + + } + + } +} + +Device (RP08) +{ + NAME(_ADR, 0x001c0007) // FIXME: Have a macro for PCI Devices -> ACPI notation? + //#include "pcie_port.asl" + Method(_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 19 }, + Package() { 0x0000ffff, 1, 0, 16 }, + Package() { 0x0000ffff, 2, 0, 17 }, + Package() { 0x0000ffff, 3, 0, 18 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } + }) + + } + + } +} + + diff --git a/src/southbridge/intel/bd82x6x/acpi/sata.asl b/src/southbridge/intel/bd82x6x/acpi/sata.asl new file mode 100644 index 0000000..e0c336a --- /dev/null +++ b/src/southbridge/intel/bd82x6x/acpi/sata.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Intel SATA Controller 0:1f.2 + +// Note: Some BIOSes put the S-ATA code into an SSDT to make it easily +// pluggable + +Device (SATA) +{ + Name (_ADR, 0x001f0002) + + Device (PRID) + { + Name (_ADR, 0) + + // Get Timing Mode + Method (_GTM) + { + Name(PBUF, Buffer(20) { + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00 }) + + CreateDwordField (PBUF, 0, PIO0) + CreateDwordField (PBUF, 4, DMA0) + CreateDwordField (PBUF, 8, PIO1) + CreateDwordField (PBUF, 12, DMA1) + CreateDwordField (PBUF, 16, FLAG) + + // TODO fill return structure + + Return (PBUF) + } + + // Set Timing Mode + Method (_STM, 3) + { + CreateDwordField (Arg0, 0, PIO0) + CreateDwordField (Arg0, 4, DMA0) + CreateDwordField (Arg0, 8, PIO1) + CreateDwordField (Arg0, 12, DMA1) + CreateDwordField (Arg0, 16, FLAG) + + // TODO: Do the deed + } + + Device (DSK0) + { + Name (_ADR, 0) + // TODO: _RMV ? + // TODO: _GTF ? + } + + Device (DSK1) + { + Name (_ADR, 1) + + // TODO: _RMV ? + // TODO: _GTF ? + } + + } +} + diff --git a/src/southbridge/intel/bd82x6x/acpi/sleepstates.asl b/src/southbridge/intel/bd82x6x/acpi/sleepstates.asl new file mode 100644 index 0000000..06bfcb6 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/acpi/sleepstates.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Name(\_S0, Package(){0x0,0x0,0x0,0x0}) +// Name(\_S1, Package(){0x1,0x1,0x0,0x0}) +Name(\_S3, Package(){0x5,0x5,0x0,0x0}) +Name(\_S4, Package(){0x6,0x6,0x0,0x0}) +Name(\_S5, Package(){0x7,0x7,0x0,0x0}) + diff --git a/src/southbridge/intel/bd82x6x/acpi/smbus.asl b/src/southbridge/intel/bd82x6x/acpi/smbus.asl new file mode 100644 index 0000000..4409308 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/acpi/smbus.asl @@ -0,0 +1,242 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Intel SMBus Controller 0:1f.3 + +Device (SBUS) +{ + Name (_ADR, 0x001f0003) + +#ifdef ENABLE_SMBUS_METHODS + OperationRegion (SMBP, PCI_Config, 0x00, 0x100) + Field(SMBP, DWordAcc, NoLock, Preserve) + { + Offset(0x40), + , 2, + I2CE, 1 + } + + OperationRegion (SMBI, SystemIO, SMBUS_IO_BASE, 0x20) + Field (SMBI, ByteAcc, NoLock, Preserve) + { + HSTS, 8, // Host Status + , 8, + HCNT, 8, // Host Control + HCMD, 8, // Host Command + TXSA, 8, // Transmit Slave Address + DAT0, 8, // Host Data 0 + DAT1, 8, // Host Data 1 + HBDB, 8, // Host Block Data Byte + PECK, 8, // Packet Error Check + RXSA, 8, // Receive Slave Address + RXDA, 16, // Receive Slave Data + AUXS, 8, // Auxiliary Status + AUXC, 8, // Auxiliary Control + SLPC, 8, // SMLink Pin Control + SBPC, 8, // SMBus Pin Control + SSTS, 8, // Slave Status + SCMD, 8, // Slave Command + NADR, 8, // Notify Device Address + NDLB, 8, // Notify Data Low Byte + NDLH, 8, // Notify Data High Byte + } + + // Kill all SMBus communication + Method (KILL, 0, Serialized) + { + Or (HCNT, 0x02, HCNT) // Send Kill + Or (HSTS, 0xff, HSTS) // Clean Status + } + + // Check if last operation completed + // return Failure = 0, Success = 1 + Method (CMPL, 0, Serialized) + { + Store (4000, Local0) // Timeout 200ms in 50us steps + While (Local0) { + If (And(HSTS, 0x02)) { // Completion Status? + Return (1) // Operation Completed + } Else { + Stall (50) + Decrement (Local0) + If (LEqual(Local0, 0)) { + KILL() + } + } + } + + Return (0) // Failure + } + + + // Wait for SMBus to become ready + Method (SRDY, 0, Serialized) + { + Store (200, Local0) // Timeout 200ms + While (Local0) { + If (And(HSTS, 0x40)) { // IN_USE? + Sleep(1) // Wait 1ms + Decrement(Local0) // timeout-- + If (LEqual(Local0, 0)) { + Return (1) + } + } Else { + Store (0, Local0) // We're ready + } + } + + Store (4000, Local0) // Timeout 200ms (50us * 4000) + While (Local0) { + If (And (HSTS, 0x01)) { // Host Busy? + Stall(50) // Wait 50us + Decrement(Local0) // timeout-- + If (LEqual(Local0, 0)) { + KILL() + } + } Else { + Return (0) // Success + } + } + + Return (1) // Failure + } + + // SMBus Send Byte + // Arg0: Address + // Arg1: Data + // Return: 1 = Success, 0=Failure + + Method (SSXB, 2, Serialized) + { + + // Is the SMBus Controller Ready? + If (SRDY()) { + Return (0) + } + + // Send Byte + Store (0, I2CE) // SMBus Enable + Store (0xbf, HSTS) + Store (Arg0, TXSA) // Write Address + Store (Arg1, HCMD) // Write Data + + Store (0x48, HCNT) // Start + Byte Data Protocol + + If (CMPL()) { + Or (HSTS, 0xff, HSTS) // Clean up + Return (1) // Success + } + + Return (0) + } + + + // SMBus Receive Byte + // Arg0: Address + // Return: 0xffff = Failure, Data (8bit) = Success + + Method (SRXB, 2, Serialized) + { + + // Is the SMBus Controller Ready? + If (SRDY()) { + Return (0xffff) + } + + // Receive Byte + Store (0, I2CE) // SMBus Enable + Store (0xbf, HSTS) + Store (Or (Arg0, 1), TXSA) // Write Address + + Store (0x44, HCNT) // Start + + If (CMPL()) { + Or (HSTS, 0xff, HSTS) // Clean up + Return (DAT0) // Success + } + + Return (0xffff) + } + + + // SMBus Write Byte + // Arg0: Address + // Arg1: Command + // Arg2: Data + // Return: 1 = Success, 0=Failure + + Method (SWRB, 3, Serialized) + { + + // Is the SMBus Controller Ready? + If (SRDY()) { + Return (0) + } + + // Send Byte + Store (0, I2CE) // SMBus Enable + Store (0xbf, HSTS) + Store (Arg0, TXSA) // Write Address + Store (Arg1, HCMD) // Write Command + Store (Arg2, DAT0) // Write Data + + Store (0x48, HCNT) // Start + Byte Protocol + + If (CMPL()) { + Or (HSTS, 0xff, HSTS) // Clean up + Return (1) // Success + } + + Return (0) + } + + + // SMBus Read Byte + // Arg0: Address + // Arg1: Command + // Return: 0xffff = Failure, Data (8bit) = Success + + Method (SRDB, 2, Serialized) + { + + // Is the SMBus Controller Ready? + If (SRDY()) { + Return (0xffff) + } + + // Receive Byte + Store (0, I2CE) // SMBus Enable + Store (0xbf, HSTS) + Store (Or (Arg0, 1), TXSA) // Write Address + Store (Arg1, HCMD) // Command + + Store (0x48, HCNT) // Start + + If (CMPL()) { + Or (HSTS, 0xff, HSTS) // Clean up + Return (DAT0) // Success + } + + Return (0xffff) + } +#endif +} + diff --git a/src/southbridge/intel/bd82x6x/acpi/usb.asl b/src/southbridge/intel/bd82x6x/acpi/usb.asl new file mode 100644 index 0000000..cf3e6a0 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/acpi/usb.asl @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Intel Cougar Point USB support */ + +// EHCI Controller 0:1d.0 + +Device (EHC1) +{ + Name(_ADR, 0x001d0000) + + Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + + Device (HUB7) + { + Name (_ADR, 0x00000000) + + // How many are there? + Device (PRT1) { Name (_ADR, 1) } // USB Port 0 + Device (PRT2) { Name (_ADR, 2) } // USB Port 1 + Device (PRT3) { Name (_ADR, 3) } // USB Port 2 + Device (PRT4) { Name (_ADR, 4) } // USB Port 3 + Device (PRT5) { Name (_ADR, 5) } // USB Port 4 + Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + } +} + +// EHCI #2 Controller 0:1a.0 + +Device (EHC2) +{ + Name(_ADR, 0x001a0000) + + Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + + Device (HUB7) + { + Name (_ADR, 0x00000000) + + // How many are there? + Device (PRT1) { Name (_ADR, 1) } // USB Port 0 + Device (PRT2) { Name (_ADR, 2) } // USB Port 1 + Device (PRT3) { Name (_ADR, 3) } // USB Port 2 + Device (PRT4) { Name (_ADR, 4) } // USB Port 3 + Device (PRT5) { Name (_ADR, 5) } // USB Port 4 + Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + } +} + diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c new file mode 100644 index 0000000..5a83e38 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -0,0 +1,367 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <delay.h> +#include "pch.h" + +#define HDA_ICII_REG 0x68 +#define HDA_ICII_BUSY (1 << 0) +#define HDA_ICII_VALID (1 << 1) + +typedef struct southbridge_intel_bd82x6x_config config_t; + +static int set_bits(u32 port, u32 mask, u32 val) +{ + u32 reg32; + int count; + + /* Write (val & mask) to port */ + val &= mask; + reg32 = read32(port); + reg32 &= ~mask; + reg32 |= val; + write32(port, reg32); + + /* Wait for readback of register to + * match what was just written to it + */ + count = 50; + do { + /* Wait 1ms based on BKDG wait time */ + mdelay(1); + reg32 = read32(port); + reg32 &= mask; + } while ((reg32 != val) && --count); + + /* Timeout occurred */ + if (!count) + return -1; + return 0; +} + +static int codec_detect(u32 base) +{ + u8 reg8; + + /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 1) == -1) + goto no_codec; + + /* Write back the value once reset bit is set. */ + write16(base + 0x0, read16(base + 0x0)); + + /* Read in Codec location (BAR + 0xe)[2..0]*/ + reg8 = read8(base + 0xe); + reg8 &= 0x0f; + if (!reg8) + goto no_codec; + + return reg8; + +no_codec: + /* Codec Not found */ + /* Put HDA back in reset (BAR + 0x8) [0] */ + set_bits(base + 0x08, 1, 0); + printk(BIOS_DEBUG, "Azalia: No codec!\n"); + return 0; +} + +const u32 * cim_verb_data = NULL; +u32 cim_verb_data_size = 0; + +static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) +{ + int idx=0; + + while (idx < (cim_verb_data_size / sizeof(u32))) { + u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 + if (cim_verb_data[idx] != viddid) { + idx += verb_size + 3; // skip verb + header + continue; + } + *verb = &cim_verb_data[idx+3]; + return verb_size; + } + + /* Not all codecs need to load another verb */ + return 0; +} + +/** + * Wait 50usec for the codec to indicate it is ready + * no response would imply that the codec is non-operative + */ + +static int wait_for_ready(u32 base) +{ + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 50; + + while(timeout--) { + u32 reg32 = read32(base + HDA_ICII_REG); + if (!(reg32 & HDA_ICII_BUSY)) + return 0; + udelay(1); + } + + return -1; +} + +/** + * Wait 50usec for the codec to indicate that it accepted + * the previous command. No response would imply that the code + * is non-operative + */ + +static int wait_for_valid(u32 base) +{ + u32 reg32; + + /* Send the verb to the codec */ + reg32 = read32(base + HDA_ICII_REG); + reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; + write32(base + HDA_ICII_REG, reg32); + + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 50; + while(timeout--) { + reg32 = read32(base + HDA_ICII_REG); + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == + HDA_ICII_VALID) + return 0; + udelay(1); + } + + return -1; +} + +static void codec_init(struct device *dev, u32 base, int addr) +{ + u32 reg32; + const u32 *verb; + u32 verb_size; + int i; + + printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); + + /* 1 */ + if (wait_for_ready(base) == -1) { + printk(BIOS_DEBUG, " codec not ready.\n"); + return; + } + + reg32 = (addr << 28) | 0x000f0000; + write32(base + 0x60, reg32); + + if (wait_for_valid(base) == -1) { + printk(BIOS_DEBUG, " codec not valid.\n"); + return; + } + + reg32 = read32(base + 0x64); + + /* 2 */ + printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); + verb_size = find_verb(dev, reg32, &verb); + + if (!verb_size) { + printk(BIOS_DEBUG, "Azalia: No verb!\n"); + return; + } + printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); + + /* 3 */ + for (i = 0; i < verb_size; i++) { + if (wait_for_ready(base) == -1) + return; + + write32(base + 0x60, verb[i]); + + if (wait_for_valid(base) == -1) + return; + } + printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); +} + +static void codecs_init(struct device *dev, u32 base, u32 codec_mask) +{ + int i; + for (i = 3; i >= 0; i--) { + if (codec_mask & (1 << i)) + codec_init(dev, base, i); + } +} + +static void azalia_init(struct device *dev) +{ + u32 base; + struct resource *res; + u32 codec_mask; + u8 reg8; + u16 reg16; + u32 reg32; + + /* Find base address */ + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + // NOTE this will break as soon as the Azalia get's a bar above + // 4G. Is there anything we can do about it? + base = (u32)res->base; + printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + + if (RCBA32(0x2030) & (1 << 31)) { + reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 &= 0xf8ffff01; + reg32 |= (1 << 24); // 25 for server + reg32 |= RCBA32(0x2030) & 0xfe; + pci_mmio_write_config32(dev, 0x120, reg32); + + reg16 = pci_mmio_read_config16(dev, 0x78); + reg16 &= ~(1 << 11); + pci_mmio_write_config16(dev, 0x78, reg16); + } else + printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); + + reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 &= ~0xfe; + pci_mmio_write_config32(dev, 0x114, reg32); + + // Set VCi enable bit + if (pci_mmio_read_config32(dev, 0x120) & ((1 << 24) | + (1 << 25) | (1 << 26))) { + reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 |= (1 << 31); + pci_mmio_write_config32(dev, 0x120, reg32); + } + + // Enable HDMI codec: + reg32 = pci_read_config32(dev, 0xc4); + reg32 |= (1 << 1); + pci_write_config32(dev, 0xc4, reg32); + + reg8 = pci_read_config8(dev, 0x43); + reg8 |= (1 << 6); + pci_write_config8(dev, 0x43, reg8); + + /* Additional programming steps */ + reg32 = pci_read_config32(dev, 0xc4); + reg32 |= (1 << 13) | (1 << 10); + pci_write_config32(dev, 0xc4, reg32); + + reg32 = pci_read_config32(dev, 0xd0); + reg32 &= ~(1 << 31); + pci_write_config32(dev, 0xd0, reg32); + + /* Additional programming steps */ + reg32 = pci_read_config32(dev, 0xc4); + reg32 |= (1 << 13); + pci_write_config32(dev, 0xc4, reg32); + + reg32 = pci_read_config32(dev, 0xc4); + reg32 |= (1 << 10); + pci_write_config32(dev, 0xc4, reg32); + + reg32 = pci_read_config32(dev, 0xd0); + reg32 &= ~(1 << 31); + pci_write_config32(dev, 0xd0, reg32); + + /* Set Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + + pci_write_config8(dev, 0x3c, 0x0a); // unused? + + /* Codec Initialization Programming Sequence */ + reg32 = read32(base + 0x08); + reg32 |= (1 << 0); + write32(base + 0x08, reg32); + + // + reg8 = pci_read_config8(dev, 0x40); // Audio Control + reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb + pci_write_config8(dev, 0x40, reg8); + + reg8 = pci_read_config8(dev, 0x4d); // Docking Status + reg8 &= ~(1 << 7); // Docking not supported + pci_write_config8(dev, 0x4d, reg8); + + codec_mask = codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); + codecs_init(dev, base, codec_mask); + } + + /* Enable dynamic clock gating */ + reg8 = pci_read_config8(dev, 0x43); + reg8 &= ~0x7; + reg8 |= (1 << 2) | (1 << 0); + pci_write_config8(dev, 0x43, reg8); +} + +static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations azalia_pci_ops = { + .set_subsystem = azalia_set_subsystem, +}; + +static struct device_operations azalia_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = azalia_init, + .scan_bus = 0, + .ops_pci = &azalia_pci_ops, +}; + +static const struct pci_driver azalia_0 __pci_driver = { + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c20, +}; + +static const struct pci_driver azalia_1 __pci_driver = { + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e20, +}; + diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c new file mode 100644 index 0000000..686e820 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "pch.h" + +static void store_initial_timestamp(void) +{ + /* On Cougar Point we have two 32bit scratchpad registers available: + * D0:F0 0xdc (SKPAD) + * D31:F2 0xd0 (SATA SP) + */ + tsc_t tsc = rdtsc(); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); + pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); +} + +/* + * Enable Prefetching and Caching. + */ +static void enable_spi_prefetch(void) +{ + u8 reg8; + device_t dev; + + dev = PCI_DEV(0, 0x1f, 0); + + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); +} + +static void enable_port80_on_lpc(void) +{ + device_t dev = PCI_DEV(0, 0x1f, 0); + + /* Enable port 80 POST on LPC */ + pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); +#if 0 + RCBA32(GCS) &= (~0x04); +#else + volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS); + u32 reg32 = *gcs; + reg32 = reg32 & ~0x04; + *gcs = reg32; + post_code(0x01); +#endif +} + +static void bootblock_southbridge_init(void) +{ +#if CONFIG_COLLECT_TIMESTAMPS + store_initial_timestamp(); +#endif + enable_spi_prefetch(); + enable_port80_on_lpc(); +} diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h new file mode 100644 index 0000000..2786d72 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H +#define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H + +struct southbridge_intel_bd82x6x_config { + /** + * Interrupt Routing configuration + * If bit7 is 1, the interrupt is disabled. + */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; + + /** + * GPI Routing configuration + * + * Only the lower two bits have a meaning: + * 00: No effect + * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + * 10: SCI (if corresponding GPIO_EN bit is also set) + * 11: reserved + */ + uint8_t gpi0_routing; + uint8_t gpi1_routing; + uint8_t gpi2_routing; + uint8_t gpi3_routing; + uint8_t gpi4_routing; + uint8_t gpi5_routing; + uint8_t gpi6_routing; + uint8_t gpi7_routing; + uint8_t gpi8_routing; + uint8_t gpi9_routing; + uint8_t gpi10_routing; + uint8_t gpi11_routing; + uint8_t gpi12_routing; + uint8_t gpi13_routing; + uint8_t gpi14_routing; + uint8_t gpi15_routing; + + uint32_t gpe0_en; + uint16_t alt_gp_smi_en; + + /* IDE configuration */ + uint32_t ide_legacy_combined; + uint32_t sata_ahci; + uint8_t sata_port_map; + + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; +}; + +extern struct chip_operations southbridge_intel_bd82x6x_ops; + +#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c new file mode 100644 index 0000000..5b266cc --- /dev/null +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/hlt.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <delay.h> +#include <device/pci_ids.h> +#include <string.h> +#include "me.h" +#include "pch.h" + +static const char *me_ack_values[] = { + [ME_HFS_ACK_NO_DID] = "No DID Ack received", + [ME_HFS_ACK_RESET] = "Non-power cycle reset", + [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset", + [ME_HFS_ACK_S3] = "Go to S3", + [ME_HFS_ACK_S4] = "Go to S4", + [ME_HFS_ACK_S5] = "Go to S5", + [ME_HFS_ACK_GBL_RESET] = "Global Reset", + [ME_HFS_ACK_CONTINUE] = "Continue to boot" +}; + +static inline void pci_read_dword_ptr(void *ptr, int offset) +{ + u32 dword = pci_read_config32(PCH_ME_DEV, offset); + memcpy(ptr, &dword, sizeof(dword)); +} + +static inline void pci_write_dword_ptr(void *ptr, int offset) +{ + u32 dword = 0; + memcpy(&dword, ptr, sizeof(dword)); + pci_write_config32(PCH_ME_DEV, offset, dword); +} + +void intel_early_me_status(void) +{ + struct me_hfs hfs; + struct me_gmes gmes; + + pci_read_dword_ptr(&hfs, PCI_ME_HFS); + pci_read_dword_ptr(&gmes, PCI_ME_GMES); + + intel_me_status(&hfs, &gmes); +} + +int intel_early_me_init(void) +{ + int count; + struct me_uma uma; + struct me_hfs hfs; + + printk(BIOS_INFO, "Intel ME early init\n"); + + /* Wait for ME UMA SIZE VALID bit to be set */ + for (count = ME_RETRY; count > 0; --count) { + pci_read_dword_ptr(&uma, PCI_ME_UMA); + if (uma.valid) + break; + udelay(ME_DELAY); + } + if (!count) { + printk(BIOS_ERR, "ERROR: ME is not ready!\n"); + return -1; + } + + /* Check for valid firmware */ + pci_read_dword_ptr(&hfs, PCI_ME_HFS); + if (hfs.fpt_bad) { + printk(BIOS_WARNING, "WARNING: ME has bad firmware\n"); + return -1; + } + + printk(BIOS_INFO, "Intel ME firmware is ready\n"); + return 0; +} + +int intel_early_me_uma_size(void) +{ + struct me_uma uma; + + pci_read_dword_ptr(&uma, PCI_ME_UMA); + if (uma.valid) { + printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size); + return uma.size; + } + + printk(BIOS_DEBUG, "ME: Invalid UMA size\n"); + return 0; +} + +static inline void set_global_reset(int enable) +{ + u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); + + /* Clear CF9 Without Resume Well Reset Enable */ + etr3 &= ~ETR3_CWORWRE; + + /* CF9GR indicates a Global Reset */ + if (enable) + etr3 |= ETR3_CF9GR; + else + etr3 &= ~ETR3_CF9GR; + + pci_write_config32(PCH_LPC_DEV, ETR3, etr3); +} + +int intel_early_me_init_done(u8 status) +{ + u8 reset; + int count; + u32 mebase_l, mebase_h; + struct me_hfs hfs; + struct me_did did = { + .init_done = ME_INIT_DONE, + .status = status + }; + + /* MEBASE from MESEG_BASE[35:20] */ + mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L); + mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf; + did.uma_base = (mebase_l >> 20) | (mebase_h << 12); + + /* Send message to ME */ + printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, " + "UMA base: 0x%04x\n", status, did.uma_base); + + pci_write_dword_ptr(&did, PCI_ME_H_GS); + + /* Must wait for ME acknowledgement */ + for (count = ME_RETRY; count > 0; --count) { + pci_read_dword_ptr(&hfs, PCI_ME_HFS); + if (hfs.bios_msg_ack) + break; + udelay(ME_DELAY); + } + if (!count) { + printk(BIOS_ERR, "ERROR: ME failed to respond\n"); + return -1; + } + + /* Return the requested BIOS action */ + printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n", + me_ack_values[hfs.ack_data]); + + /* Check status after acknowledgement */ + intel_early_me_status(); + + reset = 0; + switch (hfs.ack_data) { + case ME_HFS_ACK_CONTINUE: + /* Continue to boot */ + return 0; + case ME_HFS_ACK_RESET: + /* Non-power cycle reset */ + set_global_reset(0); + reset = 0x06; + break; + case ME_HFS_ACK_PWR_CYCLE: + /* Power cycle reset */ + set_global_reset(0); + reset = 0x0e; + break; + case ME_HFS_ACK_GBL_RESET: + /* Global reset */ + set_global_reset(1); + reset = 0x0e; + break; + case ME_HFS_ACK_S3: + case ME_HFS_ACK_S4: + case ME_HFS_ACK_S5: + break; + } + + /* Perform the requested reset */ + if (reset) { + outb(reset, 0xcf9); + hlt(); + } + return -1; +} diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c new file mode 100644 index 0000000..b13369a --- /dev/null +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> +#include "pch.h" +#include "smbus.h" + +void enable_smbus(void) +{ + device_t dev; + + /* Set the SMBus device statically. */ + dev = PCI_DEV(0x0, 0x1f, 0x3); + + /* Check to make sure we've got the right device. */ + if (pci_read_config16(dev, 0x0) != 0x8086) { + die("SMBus controller not found!"); + } + + /* Set SMBus I/O base. */ + pci_write_config32(dev, SMB_BASE, + SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + + /* Set SMBus enable. */ + pci_write_config8(dev, HOSTC, HST_EN); + + /* Set SMBus I/O space enable. */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + + /* Disable interrupt generation. */ + outb(0, SMBUS_IO_BASE + SMBHSTCTL); + + /* Clear any lingering errors, so transactions can run. */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + print_debug("SMBus controller enabled.\n"); +} + +int smbus_read_byte(unsigned device, unsigned address) +{ + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); +} + diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c new file mode 100644 index 0000000..95906e3 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> +#include "pch.h" + +#define PCH_EHCI1_TEMP_BAR0 0xe8000000 +#define PCH_EHCI2_TEMP_BAR0 0xe8000400 + +/* + * Setup USB controller MMIO BAR to prevent the + * reference code from resetting the controller. + * + * The BAR will be re-assigned during device + * enumeration so these are only temporary. + */ +void enable_usb_bar(void) +{ + device_t usb0 = PCH_EHCI1_DEV; + device_t usb1 = PCH_EHCI2_DEV; + u32 cmd; + + /* USB Controller 1 */ + pci_write_config32(usb0, PCI_BASE_ADDRESS_0, + PCH_EHCI1_TEMP_BAR0); + cmd = pci_read_config32(usb0, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(usb0, PCI_COMMAND, cmd); + + /* USB Controller 1 */ + pci_write_config32(usb1, PCI_BASE_ADDRESS_0, + PCH_EHCI1_TEMP_BAR0); + cmd = pci_read_config32(usb1, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(usb1, PCI_COMMAND, cmd); +} diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c new file mode 100644 index 0000000..ed1ebf7 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <northbridge/intel/sandybridge/pcie_config.c> +#include "pch.h" + +void intel_pch_finalize_smm(void) +{ + /* Set SPI opcode menu */ + RCBA16(0x3894) = SPI_OPPREFIX; + RCBA16(0x3896) = SPI_OPTYPE; + RCBA32(0x3898) = SPI_OPMENU_LOWER; + RCBA32(0x389c) = SPI_OPMENU_UPPER; + + /* Lock SPIBAR */ + RCBA32_OR(0x3804, (1 << 15)); + + /* TCLOCKDN: TC Lockdown */ + RCBA32_OR(0x0050, (1 << 31)); + + /* BIOS Interface Lockdown */ + RCBA32_OR(0x3410, (1 << 0)); + + /* Function Disable SUS Well Lockdown */ + RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); + + /* Global SMI Lock */ + pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + + /* GEN_PMCON Lock */ + pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + + /* R/WO registers */ + RCBA32(0x21a4) = RCBA32(0x21a4); + pcie_write_config32(PCI_DEV(0, 27, 0), 0x74, + pcie_read_config32(PCI_DEV(0, 27, 0), 0x74)); +} diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c new file mode 100644 index 0000000..598726a --- /dev/null +++ b/src/southbridge/intel/bd82x6x/gpio.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <arch/romcc_io.h> + +#include "pch.h" +#include "gpio.h" + +void setup_pch_gpios(const struct pch_gpio_map *gpio) +{ + u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + + /* GPIO Set 1 */ + if (gpio->set1.level) + outl(*((u32*)gpio->set1.level), gpiobase + GP_LVL); + if (gpio->set1.mode) + outl(*((u32*)gpio->set1.mode), gpiobase + GPIO_USE_SEL); + if (gpio->set1.direction) + outl(*((u32*)gpio->set1.direction), gpiobase + GP_IO_SEL); + if (gpio->set1.reset) + outl(*((u32*)gpio->set1.reset), gpiobase + GP_RST_SEL1); + if (gpio->set1.invert) + outl(*((u32*)gpio->set1.invert), gpiobase + GPI_INV); + if (gpio->set1.blink) + outl(*((u32*)gpio->set1.blink), gpiobase + GPO_BLINK); + + /* GPIO Set 2 */ + if (gpio->set2.level) + outl(*((u32*)gpio->set2.level), gpiobase + GP_LVL2); + if (gpio->set2.mode) + outl(*((u32*)gpio->set2.mode), gpiobase + GPIO_USE_SEL2); + if (gpio->set2.direction) + outl(*((u32*)gpio->set2.direction), gpiobase + GP_IO_SEL2); + if (gpio->set2.reset) + outl(*((u32*)gpio->set2.reset), gpiobase + GP_RST_SEL2); + + /* GPIO Set 3 */ + if (gpio->set3.level) + outl(*((u32*)gpio->set3.level), gpiobase + GP_LVL3); + if (gpio->set3.mode) + outl(*((u32*)gpio->set3.mode), gpiobase + GPIO_USE_SEL3); + if (gpio->set3.direction) + outl(*((u32*)gpio->set3.direction), gpiobase + GP_IO_SEL3); + if (gpio->set3.reset) + outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3); +} diff --git a/src/southbridge/intel/bd82x6x/gpio.h b/src/southbridge/intel/bd82x6x/gpio.h new file mode 100644 index 0000000..214947f --- /dev/null +++ b/src/southbridge/intel/bd82x6x/gpio.h @@ -0,0 +1,153 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef INTEL_BD82X6X_GPIO_H +#define INTEL_BD82X6X_GPIO_H + +#define GPIO_MODE_NATIVE 0 +#define GPIO_MODE_GPIO 1 +#define GPIO_MODE_NONE 1 + +#define GPIO_DIR_OUTPUT 0 +#define GPIO_DIR_INPUT 1 + +#define GPIO_NO_INVERT 0 +#define GPIO_INVERT 1 + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 + +#define GPIO_NO_BLINK 0 +#define GPIO_BLINK 1 + +#define GPIO_RESET_PWROK 0 +#define GPIO_RESET_RSMRST 1 + +struct pch_gpio_set1 { + u32 gpio0 : 1; + u32 gpio1 : 1; + u32 gpio2 : 1; + u32 gpio3 : 1; + u32 gpio4 : 1; + u32 gpio5 : 1; + u32 gpio6 : 1; + u32 gpio7 : 1; + u32 gpio8 : 1; + u32 gpio9 : 1; + u32 gpio10 : 1; + u32 gpio11 : 1; + u32 gpio12 : 1; + u32 gpio13 : 1; + u32 gpio14 : 1; + u32 gpio15 : 1; + u32 gpio16 : 1; + u32 gpio17 : 1; + u32 gpio18 : 1; + u32 gpio19 : 1; + u32 gpio20 : 1; + u32 gpio21 : 1; + u32 gpio22 : 1; + u32 gpio23 : 1; + u32 gpio24 : 1; + u32 gpio25 : 1; + u32 gpio26 : 1; + u32 gpio27 : 1; + u32 gpio28 : 1; + u32 gpio29 : 1; + u32 gpio30 : 1; + u32 gpio31 : 1; +} __attribute__ ((packed)); + +struct pch_gpio_set2 { + u32 gpio32 : 1; + u32 gpio33 : 1; + u32 gpio34 : 1; + u32 gpio35 : 1; + u32 gpio36 : 1; + u32 gpio37 : 1; + u32 gpio38 : 1; + u32 gpio39 : 1; + u32 gpio40 : 1; + u32 gpio41 : 1; + u32 gpio42 : 1; + u32 gpio43 : 1; + u32 gpio44 : 1; + u32 gpio45 : 1; + u32 gpio46 : 1; + u32 gpio47 : 1; + u32 gpio48 : 1; + u32 gpio49 : 1; + u32 gpio50 : 1; + u32 gpio51 : 1; + u32 gpio52 : 1; + u32 gpio53 : 1; + u32 gpio54 : 1; + u32 gpio55 : 1; + u32 gpio56 : 1; + u32 gpio57 : 1; + u32 gpio58 : 1; + u32 gpio59 : 1; + u32 gpio60 : 1; + u32 gpio61 : 1; + u32 gpio62 : 1; + u32 gpio63 : 1; +} __attribute__ ((packed)); + +struct pch_gpio_set3 { + u32 gpio64 : 1; + u32 gpio65 : 1; + u32 gpio66 : 1; + u32 gpio67 : 1; + u32 gpio68 : 1; + u32 gpio69 : 1; + u32 gpio70 : 1; + u32 gpio71 : 1; + u32 gpio72 : 1; + u32 gpio73 : 1; + u32 gpio74 : 1; + u32 gpio75 : 1; +} __attribute__ ((packed)); + +struct pch_gpio_map { + struct { + const struct pch_gpio_set1 *mode; + const struct pch_gpio_set1 *direction; + const struct pch_gpio_set1 *level; + const struct pch_gpio_set1 *reset; + const struct pch_gpio_set1 *invert; + const struct pch_gpio_set1 *blink; + } set1; + struct { + const struct pch_gpio_set2 *mode; + const struct pch_gpio_set2 *direction; + const struct pch_gpio_set2 *level; + const struct pch_gpio_set2 *reset; + } set2; + struct { + const struct pch_gpio_set3 *mode; + const struct pch_gpio_set3 *direction; + const struct pch_gpio_set3 *level; + const struct pch_gpio_set3 *reset; + } set3; +}; + +/* Configure GPIOs with mainboard provided settings */ +void setup_pch_gpios(const struct pch_gpio_map *gpio); + +#endif diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c new file mode 100644 index 0000000..1ecaf8f --- /dev/null +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -0,0 +1,678 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> +#include <pc80/isa-dma.h> +#include <pc80/i8259.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <arch/acpi.h> +#include <cpu/cpu.h> +#include "pch.h" + +#define NMI_OFF 0 + +#define ENABLE_ACPI_MODE_IN_COREBOOT 0 +#define TEST_SMM_FLASH_LOCKDOWN 0 + +typedef struct southbridge_intel_bd82x6x_config config_t; + +static void pch_enable_apic(struct device *dev) +{ + int i; + u32 reg32; + volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); + volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + + /* Enable ACPI I/O and power management. + * Set SCI IRQ to IRQ9 + */ + pci_write_config8(dev, ACPI_CNTL, 0x80); + + *ioapic_index = 0; + *ioapic_data = (1 << 25); + + /* affirm full set of redirection table entries ("write once") */ + *ioapic_index = 1; + reg32 = *ioapic_data; + *ioapic_index = 1; + *ioapic_data = reg32; + + *ioapic_index = 0; + reg32 = *ioapic_data; + printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); + if (reg32 != (1 << 25)) + die("APIC Error\n"); + + printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); + for (i=0; i<3; i++) { + *ioapic_index = i; + printk(BIOS_SPEW, " reg 0x%04x:", i); + reg32 = *ioapic_data; + printk(BIOS_SPEW, " 0x%08x\n", reg32); + } + + *ioapic_index = 3; /* Select Boot Configuration register. */ + *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ +} + +static void pch_enable_serial_irqs(struct device *dev) +{ + /* Set packet length and toggle silent mode bit for one frame. */ + pci_write_config8(dev, SERIRQ_CNTL, + (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); +#if !CONFIG_SERIRQ_CONTINUOUS_MODE + pci_write_config8(dev, SERIRQ_CNTL, + (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); +#endif +} + +/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control + * 0x00 - 0000 = Reserved + * 0x01 - 0001 = Reserved + * 0x02 - 0010 = Reserved + * 0x03 - 0011 = IRQ3 + * 0x04 - 0100 = IRQ4 + * 0x05 - 0101 = IRQ5 + * 0x06 - 0110 = IRQ6 + * 0x07 - 0111 = IRQ7 + * 0x08 - 1000 = Reserved + * 0x09 - 1001 = IRQ9 + * 0x0A - 1010 = IRQ10 + * 0x0B - 1011 = IRQ11 + * 0x0C - 1100 = IRQ12 + * 0x0D - 1101 = Reserved + * 0x0E - 1110 = IRQ14 + * 0x0F - 1111 = IRQ15 + * PIRQ[n]_ROUT[7] - PIRQ Routing Control + * 0x80 - The PIRQ is not routed. + */ + +static void pch_pirq_init(device_t dev) +{ + device_t irq_dev; + /* Get the chip configuration */ + config_t *config = dev->chip_info; + + pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); + pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); + pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); + pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + + pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); + pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); + pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); + pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + + /* Eric Biederman once said we should let the OS do this. + * I am not so sure anymore he was right. + */ + + for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + u8 int_pin=0, int_line=0; + + if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + continue; + + int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + + switch (int_pin) { + case 1: /* INTA# */ int_line = config->pirqa_routing; break; + case 2: /* INTB# */ int_line = config->pirqb_routing; break; + case 3: /* INTC# */ int_line = config->pirqc_routing; break; + case 4: /* INTD# */ int_line = config->pirqd_routing; break; + } + + if (!int_line) + continue; + + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + } +} + +static void pch_gpi_routing(device_t dev) +{ + /* Get the chip configuration */ + config_t *config = dev->chip_info; + u32 reg32 = 0; + + /* An array would be much nicer here, or some + * other method of doing this. + */ + reg32 |= (config->gpi0_routing & 0x03) << 0; + reg32 |= (config->gpi1_routing & 0x03) << 2; + reg32 |= (config->gpi2_routing & 0x03) << 4; + reg32 |= (config->gpi3_routing & 0x03) << 6; + reg32 |= (config->gpi4_routing & 0x03) << 8; + reg32 |= (config->gpi5_routing & 0x03) << 10; + reg32 |= (config->gpi6_routing & 0x03) << 12; + reg32 |= (config->gpi7_routing & 0x03) << 14; + reg32 |= (config->gpi8_routing & 0x03) << 16; + reg32 |= (config->gpi9_routing & 0x03) << 18; + reg32 |= (config->gpi10_routing & 0x03) << 20; + reg32 |= (config->gpi11_routing & 0x03) << 22; + reg32 |= (config->gpi12_routing & 0x03) << 24; + reg32 |= (config->gpi13_routing & 0x03) << 26; + reg32 |= (config->gpi14_routing & 0x03) << 28; + reg32 |= (config->gpi15_routing & 0x03) << 30; + + pci_write_config32(dev, 0xb8, reg32); +} + +static void pch_power_options(device_t dev) +{ + u8 reg8; + u16 reg16, pmbase; + u32 reg32; + const char *state; + /* Get the chip configuration */ + config_t *config = dev->chip_info; + + int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int nmi_option; + + /* Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + * + * If the option is not existent (Laptops), use Kconfig setting. + */ + get_option(&pwr_on, "power_on_after_fail"); + + reg16 = pci_read_config16(dev, GEN_PMCON_3); + reg16 &= 0xfffe; + switch (pwr_on) { + case MAINBOARD_POWER_OFF: + reg16 |= 1; + state = "off"; + break; + case MAINBOARD_POWER_ON: + reg16 &= ~1; + state = "on"; + break; + case MAINBOARD_POWER_KEEP: + reg16 &= ~1; + state = "state keep"; + break; + default: + state = "undefined"; + } + + reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */ + reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */ + + reg16 &= ~(1 << 10); + reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */ + + reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ + + pci_write_config16(dev, GEN_PMCON_3, reg16); + printk(BIOS_INFO, "Set power %s after power failure.\n", state); + + /* Set up NMI on errors. */ + reg8 = inb(0x61); + reg8 &= 0x0f; /* Higher Nibble must be 0 */ + reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ + // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ + reg8 |= (1 << 2); /* PCI SERR# Disable for now */ + outb(reg8, 0x61); + + reg8 = inb(0x70); + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + printk(BIOS_INFO, "NMI sources enabled.\n"); + reg8 &= ~(1 << 7); /* Set NMI. */ + } else { + printk(BIOS_INFO, "NMI sources disabled.\n"); + reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + } + outb(reg8, 0x70); + + /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ + reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 &= ~(3 << 0); // SMI# rate 1 minute + reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME +#if DEBUG_PERIODIC_SMIS + /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using + * periodic SMIs. + */ + reg16 |= (3 << 0); // Periodic SMI every 8s +#endif + pci_write_config16(dev, GEN_PMCON_1, reg16); + + // Set the board's GPI routing. + pch_gpi_routing(dev); + + pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + + outl(config->gpe0_en, pmbase + GPE0_EN); + outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN); + + /* Set up power management block and determine sleep mode */ + reg32 = inl(pmbase + 0x04); // PM1_CNT + reg32 &= ~(7 << 10); // SLP_TYP + reg32 |= (1 << 0); // SCI_EN + outl(reg32, pmbase + 0x04); + + /* Clear magic status bits to prevent unexpected wake */ + reg32 = RCBA32(0x3310); + reg32 |= (1 << 4)|(1 << 5)|(1 << 0); + RCBA32(0x3310) = reg32; + + reg32 = RCBA32(0x3f02); + reg32 &= ~0xf; + RCBA32(0x3f02) = reg32; +} + +static void pch_rtc_init(struct device *dev) +{ + u8 reg8; + int rtc_failed; + + reg8 = pci_read_config8(dev, GEN_PMCON_3); + rtc_failed = reg8 & RTC_BATTERY_DEAD; + if (rtc_failed) { + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(dev, GEN_PMCON_3, reg8); + } + printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); + + rtc_init(rtc_failed); +} + +static void pch_pm_init(struct device *dev) +{ + pci_write_config8(dev, 0xa9, 0x47); + RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0)); + RCBA32_AND_OR(0x228c, ~0UL, (1 << 0)); + RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14)); + RCBA16_AND_OR(0x0900, ~0UL, (1 << 14)); + RCBA32(0x2304) = 0xc0388400; + RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18)); + RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1)); + RCBA32_AND_OR(0x3314, ~0x1f, 0xf); + RCBA32(0x3318) = 0x050f0000; + RCBA32(0x3324) = 0x04000000; + RCBA32_AND_OR(0x3340, ~0UL, 0xfffff); + RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)); + RCBA32(0x3360) = 0x0001c000; + RCBA32(0x3368) = 0x00061100; + RCBA32(0x3378) = 0x7f8fdfff; + RCBA32(0x337c) = 0x000003fc; + RCBA32(0x3388) = 0x00001000; + RCBA32(0x3390) = 0x0001c000; + RCBA32(0x33a0) = 0x00000800; + RCBA32(0x33b0) = 0x00001000; + RCBA32(0x33c0) = 0x00093900; + RCBA32(0x33cc) = 0x24653002; + RCBA32(0x33d0) = 0x062108fe; + RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060); + RCBA32(0x3a28) = 0x01010000; + RCBA32(0x3a2c) = 0x01010404; + RCBA32(0x3a80) = 0x01041041; + RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001); + RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ + RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */ + RCBA32(0x3a6c) = 0x00000001; + RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c); + RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20); + RCBA32(0x33c8) = 0; + RCBA32_AND_OR(0x21b0, ~0UL, 0xf); +} + +static void enable_hpet(void) +{ + u32 reg32; + + /* Move HPET to default address 0xfed00000 and enable it */ + reg32 = RCBA32(HPTC); + reg32 |= (1 << 7); // HPET Address Enable + reg32 &= ~(3 << 0); + RCBA32(HPTC) = reg32; +} + +static void enable_clock_gating(device_t dev) +{ + u32 reg32; + u16 reg16; + + RCBA32_AND_OR(0x2234, ~0UL, 0xf); + + reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 |= (1 << 2) | (1 << 11); + pci_write_config16(dev, GEN_PMCON_1, reg16); + + pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); + pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); + pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); + pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + + reg32 = RCBA32(CG); + reg32 |= (1 << 31); + reg32 |= (1 << 29) | (1 << 28); + reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); + reg32 |= (1 << 16); + reg32 |= (1 << 17); + reg32 |= (1 << 18); + reg32 |= (1 << 22); + reg32 |= (1 << 23); + reg32 &= ~(1 << 20); + reg32 |= (1 << 19); + reg32 |= (1 << 0); + reg32 |= (0xf << 1); + RCBA32(CG) = reg32; + + RCBA32_OR(0x38c0, 0x7); + RCBA32_OR(0x36d4, 0x6680c004); + RCBA32_OR(0x3564, 0x3); +} + +#if CONFIG_HAVE_SMI_HANDLER +static void pch_lock_smm(struct device *dev) +{ +#if TEST_SMM_FLASH_LOCKDOWN + u8 reg8; +#endif + +#if ENABLE_ACPI_MODE_IN_COREBOOT + printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); + outb(0xe1, 0xb2); // Enable ACPI mode + printk(BIOS_DEBUG, "done.\n"); +#else + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); + outb(0x1e, 0xb2); // Disable ACPI mode + printk(BIOS_DEBUG, "done.\n"); +#endif + /* Don't allow evil boot loaders, kernels, or + * userspace applications to deceive us: + */ + smm_lock(); + +#if TEST_SMM_FLASH_LOCKDOWN + /* Now try this: */ + printk(BIOS_DEBUG, "Locking BIOS to RO... "); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", + (reg8&1)?"rw":"ro"); + reg8 &= ~(1 << 0); /* clear BIOSWE */ + pci_write_config8(dev, 0xdc, reg8); + reg8 |= (1 << 1); /* set BLE */ + pci_write_config8(dev, 0xdc, reg8); + printk(BIOS_DEBUG, "ok.\n"); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", + (reg8&1)?"rw":"ro"); + + printk(BIOS_DEBUG, "Writing:\n"); + *(volatile u8 *)0xfff00000 = 0x00; + printk(BIOS_DEBUG, "Testing:\n"); + reg8 |= (1 << 0); /* set BIOSWE */ + pci_write_config8(dev, 0xdc, reg8); + + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", + (reg8&1)?"rw":"ro"); + printk(BIOS_DEBUG, "Done.\n"); +#endif +} +#endif + +static void pch_disable_smm_only_flashing(struct device *dev) +{ + u8 reg8; + + printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 &= ~(1 << 5); + pci_write_config8(dev, 0xdc, reg8); +} + +static void pch_fixups(struct device *dev) +{ + u8 gen_pmcon_2; + + /* Indicate DRAM init done for MRC S3 to know it can resume */ + gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); + gen_pmcon_2 |= (1 << 7); + pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); + + /* + * Enable DMI ASPM in the PCH + */ + RCBA32_AND_OR(0x2304, ~(1 << 10), 0); + RCBA32_OR(0x21a4, (1 << 11)|(1 << 10)); + RCBA32_OR(0x21a8, 0x3); +} + +static void pch_decode_init(struct device *dev) +{ + config_t *config = dev->chip_info; + + printk(BIOS_DEBUG, "pch_decode_init\n"); + + pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); +} + +static void lpc_init(struct device *dev) +{ + printk(BIOS_DEBUG, "pch: lpc_init\n"); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); + + /* IO APIC initialization. */ + pch_enable_apic(dev); + + pch_enable_serial_irqs(dev); + + /* Setup the PIRQ. */ + pch_pirq_init(dev); + + /* Setup power options. */ + pch_power_options(dev); + + /* Initialize power management */ + pch_pm_init(dev); + + /* Set the state of the GPIO lines. */ + //gpio_init(dev); + + /* Initialize the real time clock. */ + pch_rtc_init(dev); + + /* Initialize ISA DMA. */ + isa_dma_init(); + + /* Initialize the High Precision Event Timers, if present. */ + enable_hpet(); + + /* Initialize Clock Gating */ + enable_clock_gating(dev); + + setup_i8259(); + + /* The OS should do this? */ + /* Interrupt 9 should be level triggered (SCI) */ + i8259_configure_irq_trigger(9, 1); + + pch_disable_smm_only_flashing(dev); + +#if CONFIG_HAVE_SMI_HANDLER + pch_lock_smm(dev); +#endif + + pch_fixups(dev); +} + +static void pch_lpc_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void pch_lpc_enable_resources(device_t dev) +{ + pch_decode_init(dev); + return pci_dev_enable_resources(dev); +} + +static void pch_lpc_enable(device_t dev) +{ + /* Enable PCH Display Port */ + RCBA16(DISPBDF) = 0x0010; + RCBA32_OR(FD2, PCH_ENABLE_DBDF); + + pch_enable(dev); +} + +static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations pci_ops = { + .set_subsystem = set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pch_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pch_lpc_enable_resources, + .init = lpc_init, + .enable = pch_lpc_enable, + .scan_bus = scan_static_bus, + .ops_pci = &pci_ops, +}; + + +/* IDs for LPC device of Intel 6 series Chipset and + * Intel C200 Series Chipset according to specification + * update from August 2011 + */ + +static const struct pci_driver q67_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c4e, +}; +static const struct pci_driver q65_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c4c, +}; +static const struct pci_driver b65_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c50, +}; +static const struct pci_driver h67_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c4a, +}; +static const struct pci_driver z68_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c46, +}; +static const struct pci_driver h61_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c5c, +}; +static const struct pci_driver c202_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c52, +}; +static const struct pci_driver c204_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c54, +}; +static const struct pci_driver c206_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c56, +}; +static const struct pci_driver qm67_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c4f, +}; +static const struct pci_driver um67_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c47, +}; +static const struct pci_driver hm67_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c4b, +}; +static const struct pci_driver hm65_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c49, +}; +static const struct pci_driver qs67_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c4d, +}; +static const struct pci_driver c216_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e55, +}; diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c new file mode 100644 index 0000000..a1ae06d --- /dev/null +++ b/src/southbridge/intel/bd82x6x/me.c @@ -0,0 +1,750 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * This is a ramstage driver for the Intel Management Engine found in the + * 6-series chipset. It handles the required boot-time messages over the + * MMIO-based Management Engine Interface to tell the ME that the BIOS is + * finished with POST. Additional messages are defined for debug but are + * not used unless the console loglevel is high enough. + */ + +#include <arch/acpi.h> +#include <arch/hlt.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> +#include <string.h> +#include <delay.h> + +#ifdef __SMM__ +# include <arch/romcc_io.h> +# include <northbridge/intel/sandybridge/pcie_config.c> +#else +# include <device/device.h> +# include <device/pci.h> +#endif + +#include "me.h" +#include "pch.h" + +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/gnvs.h> +#endif + +#ifndef __SMM__ +/* Path that the BIOS should take based on ME state */ +static const char *me_bios_path_values[] = { + [ME_NORMAL_BIOS_PATH] = "Normal", + [ME_S3WAKE_BIOS_PATH] = "S3 Wake", + [ME_ERROR_BIOS_PATH] = "Error", + [ME_RECOVERY_BIOS_PATH] = "Recovery", + [ME_DISABLE_BIOS_PATH] = "Disable", + [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", +}; +#endif + +/* MMIO base address for MEI interface */ +static u32 mei_base_address; + +#if CONFIG_DEBUG_INTEL_ME +static void mei_dump(void *ptr, int dword, int offset, const char *type) +{ + struct mei_csr *csr; + + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); + + switch (offset) { + case MEI_H_CSR: + case MEI_ME_CSR_HA: + csr = ptr; + if (!csr) { + printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); + break; + } + printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " + "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, + csr->buffer_read_ptr, csr->buffer_write_ptr, + csr->ready, csr->reset, csr->interrupt_generate, + csr->interrupt_status, csr->interrupt_enable); + break; + case MEI_ME_CB_RW: + case MEI_H_CB_WW: + printk(BIOS_SPEW, "CB: 0x%08x\n", dword); + break; + default: + printk(BIOS_SPEW, "0x%08x\n", offset); + break; + } +} +#else +# define mei_dump(ptr,dword,offset,type) do {} while (0) +#endif + +/* + * ME/MEI access helpers using memcpy to avoid aliasing. + */ + +static inline void mei_read_dword_ptr(void *ptr, int offset) +{ + u32 dword = read32(mei_base_address + offset); + memcpy(ptr, &dword, sizeof(dword)); + mei_dump(ptr, dword, offset, "READ"); +} + +static inline void mei_write_dword_ptr(void *ptr, int offset) +{ + u32 dword = 0; + memcpy(&dword, ptr, sizeof(dword)); + write32(mei_base_address + offset, dword); + mei_dump(ptr, dword, offset, "WRITE"); +} + +#ifndef __SMM__ +static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +{ + u32 dword = pci_read_config32(dev, offset); + memcpy(ptr, &dword, sizeof(dword)); + mei_dump(ptr, dword, offset, "PCI READ"); +} +#endif + +static inline void read_host_csr(struct mei_csr *csr) +{ + mei_read_dword_ptr(csr, MEI_H_CSR); +} + +static inline void write_host_csr(struct mei_csr *csr) +{ + mei_write_dword_ptr(csr, MEI_H_CSR); +} + +static inline void read_me_csr(struct mei_csr *csr) +{ + mei_read_dword_ptr(csr, MEI_ME_CSR_HA); +} + +static inline void write_cb(u32 dword) +{ + write32(mei_base_address + MEI_H_CB_WW, dword); + mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); +} + +static inline u32 read_cb(void) +{ + u32 dword = read32(mei_base_address + MEI_ME_CB_RW); + mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); + return dword; +} + +/* Wait for ME ready bit to be asserted */ +static int mei_wait_for_me_ready(void) +{ + struct mei_csr me; + unsigned try = ME_RETRY; + + while (try--) { + read_me_csr(&me); + if (me.ready) + return 0; + udelay(ME_DELAY); + } + + printk(BIOS_ERR, "ME: failed to become ready\n"); + return -1; +} + +static void mei_reset(void) +{ + struct mei_csr host; + + if (mei_wait_for_me_ready() < 0) + return; + + /* Reset host and ME circular buffers for next message */ + read_host_csr(&host); + host.reset = 1; + host.interrupt_generate = 1; + write_host_csr(&host); + + if (mei_wait_for_me_ready() < 0) + return; + + /* Re-init and indicate host is ready */ + read_host_csr(&host); + host.interrupt_generate = 1; + host.ready = 1; + host.reset = 0; + write_host_csr(&host); +} + +static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data) +{ + struct mei_csr host; + unsigned ndata, n; + u32 *data; + + /* Number of dwords to write, ignoring MKHI */ + ndata = mei->length >> 2; + + /* Pad non-dword aligned request message length */ + if (mei->length & 3) + ndata++; + if (!ndata) { + printk(BIOS_DEBUG, "ME: request does not include MKHI\n"); + return -1; + } + ndata++; /* Add MEI header */ + + /* + * Make sure there is still room left in the circular buffer. + * Reset the buffer pointers if the requested message will not fit. + */ + read_host_csr(&host); + if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { + printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); + mei_reset(); + read_host_csr(&host); + } + + /* + * This implementation does not handle splitting large messages + * across multiple transactions. Ensure the requested length + * will fit in the available circular buffer depth. + */ + if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { + printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", + ndata + 2, host.buffer_depth); + return -1; + } + + /* Write MEI header */ + mei_write_dword_ptr(mei, MEI_H_CB_WW); + ndata--; + + /* Write MKHI header */ + mei_write_dword_ptr(mkhi, MEI_H_CB_WW); + ndata--; + + /* Write message data */ + data = req_data; + for (n = 0; n < ndata; ++n) + write_cb(*data++); + + /* Generate interrupt to the ME */ + read_host_csr(&host); + host.interrupt_generate = 1; + write_host_csr(&host); + + /* Make sure ME is ready after sending request data */ + return mei_wait_for_me_ready(); +} + +static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, + void *rsp_data, int rsp_bytes) +{ + struct mei_header mei_rsp; + struct mkhi_header mkhi_rsp; + struct mei_csr me, host; + unsigned ndata, n; + unsigned expected; + u32 *data; + + /* Total number of dwords to read from circular buffer */ + expected = (rsp_bytes + sizeof(mei_rsp) + sizeof(mkhi_rsp)) >> 2; + if (rsp_bytes & 3) + expected++; + + /* + * The interrupt status bit does not appear to indicate that the + * message has actually been received. Instead we wait until the + * expected number of dwords are present in the circular buffer. + */ + for (n = ME_RETRY; n; --n) { + read_me_csr(&me); + if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) + break; + udelay(ME_DELAY); + } + if (!n) { + printk(BIOS_ERR, "ME: timeout waiting for data: expected " + "%u, available %u\n", expected, + me.buffer_write_ptr - me.buffer_read_ptr); + return -1; + } + + /* Read and verify MEI response header from the ME */ + mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); + if (!mei_rsp.is_complete) { + printk(BIOS_ERR, "ME: response is not complete\n"); + return -1; + } + + /* Handle non-dword responses and expect at least MKHI header */ + ndata = mei_rsp.length >> 2; + if (mei_rsp.length & 3) + ndata++; + if (ndata != (expected - 1)) { + printk(BIOS_ERR, "ME: response is missing data\n"); + return -1; + } + + /* Read and verify MKHI response header from the ME */ + mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW); + if (!mkhi_rsp.is_response || + mkhi->group_id != mkhi_rsp.group_id || + mkhi->command != mkhi_rsp.command) { + printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, " + "command %u ?= %u, is_response %u\n", mkhi->group_id, + mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, + mkhi_rsp.is_response); + return -1; + } + ndata--; /* MKHI header has been read */ + + /* Make sure caller passed a buffer with enough space */ + if (ndata != (rsp_bytes >> 2)) { + printk(BIOS_ERR, "ME: not enough room in response buffer: " + "%u != %u\n", ndata, rsp_bytes >> 2); + return -1; + } + + /* Read response data from the circular buffer */ + data = rsp_data; + for (n = 0; n < ndata; ++n) + *data++ = read_cb(); + + /* Tell the ME that we have consumed the response */ + read_host_csr(&host); + host.interrupt_status = 1; + host.interrupt_generate = 1; + write_host_csr(&host); + + return mei_wait_for_me_ready(); +} + +static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data, void *rsp_data, int rsp_bytes) +{ + if (mei_send_msg(mei, mkhi, req_data) < 0) + return -1; + if (mei_recv_msg(mei, mkhi, rsp_data, rsp_bytes) < 0) + return -1; + return 0; +} + +/* Send END OF POST message to the ME */ +int mkhi_end_of_post(void) +{ + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_GEN, + .command = MKHI_END_OF_POST, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi), + }; + + /* Send request and wait for response */ + if (mei_sendrecv(&mei, &mkhi, NULL, NULL, 0) < 0) { + printk(BIOS_ERR, "ME: END OF POST message failed\n"); + return -1; + } + + printk(BIOS_INFO, "ME: END OF POST message successful\n"); + return 0; +} + +#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) +/* Get ME firmware version */ +static int mkhi_get_fw_version(void) +{ + struct me_fw_version version; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_GEN, + .command = MKHI_GET_FW_VERSION, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi), + }; + + /* Send request and wait for response */ + if (mei_sendrecv(&mei, &mkhi, NULL, &version, sizeof(version)) < 0) { + printk(BIOS_ERR, "ME: GET FW VERSION message failed\n"); + return -1; + } + + printk(BIOS_INFO, "ME: Firmware Version %u.%u.%u.%u (code) " + "%u.%u.%u.%u (recovery)\n", + version.code_major, version.code_minor, + version.code_build_number, version.code_hot_fix, + version.recovery_major, version.recovery_minor, + version.recovery_build_number, version.recovery_hot_fix); + + return 0; +} + +static inline void print_cap(const char *name, int state) +{ + printk(BIOS_DEBUG, "ME Capability: %-30s : %sabled\n", + name, state ? "en" : "dis"); +} + +/* Get ME Firmware Capabilities */ +static int mkhi_get_fwcaps(void) +{ + u32 rule_id = 0; + struct me_fwcaps cap; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_FWCAPS, + .command = MKHI_FWCAPS_GET_RULE, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi) + sizeof(rule_id), + }; + + /* Send request and wait for response */ + if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap, sizeof(cap)) < 0) { + printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); + return -1; + } + + print_cap("Full Network manageability", cap.caps_sku.full_net); + print_cap("Regular Network manageability", cap.caps_sku.std_net); + print_cap("Manageability", cap.caps_sku.manageability); + print_cap("Small business technology", cap.caps_sku.small_business); + print_cap("Level III manageability", cap.caps_sku.l3manageability); + print_cap("IntelR Anti-Theft (AT)", cap.caps_sku.intel_at); + print_cap("IntelR Capability Licensing Service (CLS)", + cap.caps_sku.intel_cls); + print_cap("IntelR Power Sharing Technology (MPC)", + cap.caps_sku.intel_mpc); + print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); + print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); + print_cap("IPV6", cap.caps_sku.ipv6); + print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); + print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); + print_cap("Virtual LAN (VLAN)", cap.caps_sku.vlan); + print_cap("TLS", cap.caps_sku.tls); + print_cap("Wireless LAN (WLAN)", cap.caps_sku.wlan); + + return 0; +} +#endif + +/* Tell ME to issue a global reset */ +int mkhi_global_reset(void) +{ + struct me_global_reset reset = { + .request_origin = GLOBAL_RESET_BIOS_POST, + .reset_type = CBM_RR_GLOBAL_RESET, + }; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_CBM, + .command = MKHI_GLOBAL_RESET, + }; + struct mei_header mei = { + .is_complete = 1, + .length = sizeof(mkhi) + sizeof(reset), + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + }; + + printk(BIOS_NOTICE, "ME: Requesting global reset\n"); + + /* Send request and wait for response */ + if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { + /* No response means reset will happen shortly... */ + hlt(); + } + + /* If the ME responded it rejected the reset request */ + printk(BIOS_ERR, "ME: Global Reset failed\n"); + return -1; +} + +#ifdef __SMM__ + +void intel_me_finalize_smm(void) +{ + struct me_hfs hfs; + u32 reg32; + + mei_base_address = + pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + + /* S3 path will have hidden this device already */ + if (!mei_base_address || mei_base_address == 0xfffffff0) + return; + + /* Make sure ME is in a mode that expects EOP */ + reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); + memcpy(&hfs, &reg32, sizeof(u32)); + + /* Abort and leave device alone if not normal mode */ + if (hfs.fpt_bad || + hfs.working_state != ME_HFS_CWS_NORMAL || + hfs.operation_mode != ME_HFS_MODE_NORMAL) + return; + + /* Try to send EOP command so ME stops accepting other commands */ + mkhi_end_of_post(); + + /* Make sure IO is disabled */ + reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + + /* Hide the PCI device */ + RCBA32_OR(FD2, PCH_DISABLE_MEI1); +} + +#else /* !__SMM__ */ + +/* Determine the path that we should take based on ME status */ +static me_bios_path intel_me_path(device_t dev) +{ + me_bios_path path = ME_DISABLE_BIOS_PATH; + struct me_hfs hfs; + struct me_gmes gmes; + +#if CONFIG_HAVE_ACPI_RESUME + /* S3 wake skips all MKHI messages */ + if (acpi_slp_type == 3) { + return ME_S3WAKE_BIOS_PATH; + } +#endif + + pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); + pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES); + + /* Check and dump status */ + intel_me_status(&hfs, &gmes); + + /* Check for valid firmware */ + if (hfs.fpt_bad) + return ME_ERROR_BIOS_PATH; + + /* Check Current Working State */ + switch (hfs.working_state) { + case ME_HFS_CWS_NORMAL: + path = ME_NORMAL_BIOS_PATH; + break; + case ME_HFS_CWS_REC: + path = ME_RECOVERY_BIOS_PATH; + break; + default: + path = ME_DISABLE_BIOS_PATH; + break; + } + + /* Check Current Operation Mode */ + switch (hfs.operation_mode) { + case ME_HFS_MODE_NORMAL: + break; + case ME_HFS_MODE_DEBUG: + case ME_HFS_MODE_DIS: + case ME_HFS_MODE_OVER_JMPR: + case ME_HFS_MODE_OVER_MEI: + default: + path = ME_DISABLE_BIOS_PATH; + break; + } + + /* Check for any error code */ + if (hfs.error_code) + path = ME_ERROR_BIOS_PATH; + + return path; +} + +/* Prepare ME for MEI messages */ +static int intel_mei_setup(device_t dev) +{ + struct resource *res; + struct mei_csr host; + u32 reg32; + + /* Find the MMIO base for the ME interface */ + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res || res->base == 0 || res->size == 0) { + printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); + return -1; + } + mei_base_address = res->base; + + /* Ensure Memory and Bus Master bits are set */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Clean up status for next message */ + read_host_csr(&host); + host.interrupt_generate = 1; + host.ready = 1; + host.reset = 0; + write_host_csr(&host); + + return 0; +} + +/* Read the Extend register hash of ME firmware */ +static int intel_me_extend_valid(device_t dev) +{ + struct me_heres status; + u32 extend[] = {0}; + int i, count = 0; + + pci_read_dword_ptr(dev, &status, PCI_ME_HERES); + if (!status.extend_feature_present) { + printk(BIOS_ERR, "ME: Extend Feature not present\n"); + return -1; + } + + if (!status.extend_reg_valid) { + printk(BIOS_ERR, "ME: Extend Register not valid\n"); + return -1; + } + + switch (status.extend_reg_algorithm) { + case PCI_ME_EXT_SHA1: + count = 5; + printk(BIOS_DEBUG, "ME: Extend SHA-1: "); + break; + case PCI_ME_EXT_SHA256: + count = 8; + printk(BIOS_DEBUG, "ME: Extend SHA-256: "); + break; + default: + printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", + status.extend_reg_algorithm); + return -1; + } + + for (i = 0; i < count; ++i) { + extend[i] = pci_read_config32(dev, PCI_ME_HER(i)); + printk(BIOS_DEBUG, "%08x", extend[i]); + } + printk(BIOS_DEBUG, "\n"); + +#if CONFIG_CHROMEOS + /* Save hash in NVS for the OS to verify */ + chromeos_set_me_hash(extend, count); +#endif + + return 0; +} + +/* Hide the ME virtual PCI devices */ +static void intel_me_hide(device_t dev) +{ + dev->enabled = 0; + pch_enable(dev); +} + +/* Check whether ME is present and do basic init */ +static void intel_me_init(device_t dev) +{ + me_bios_path path = intel_me_path(dev); + + /* Do initial setup and determine the BIOS path */ + printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); + + switch (path) { + case ME_S3WAKE_BIOS_PATH: + intel_me_hide(dev); + break; + + case ME_NORMAL_BIOS_PATH: + /* Validate the extend register */ + if (intel_me_extend_valid(dev) < 0) + break; /* TODO: force recovery mode */ + + /* Prepare MEI MMIO interface */ + if (intel_mei_setup(dev) < 0) + break; + +#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) + /* Print ME firmware version */ + mkhi_get_fw_version(); + /* Print ME firmware capabilities */ + mkhi_get_fwcaps(); +#endif + + /* + * Leave the ME unlocked in this path. + * It will be locked via SMI command later. + */ + break; + + case ME_ERROR_BIOS_PATH: + case ME_RECOVERY_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: + case ME_FIRMWARE_UPDATE_BIOS_PATH: + /* + * TODO(dlaurie) Force recovery mode if ME is unhappy? + */ + break; + } +} + +static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations pci_ops = { + .set_subsystem = set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = intel_me_init, + .scan_bus = scan_static_bus, + .ops_pci = &pci_ops, +}; + +static const struct pci_driver intel_me __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c3a, +}; + +#endif /* !__SMM__ */ diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h new file mode 100644 index 0000000..53964a2 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/me.h @@ -0,0 +1,376 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _INTEL_ME_H +#define _INTEL_ME_H + +#define ME_RETRY 100000 /* 1 second */ +#define ME_DELAY 10 /* 10 us */ + +/* + * Management Engine PCI registers + */ + +#define PCI_CPU_DEVICE PCI_DEV(0,0,0) +#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ +#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ + +#define PCI_ME_HFS 0x40 +#define ME_HFS_CWS_RESET 0 +#define ME_HFS_CWS_INIT 1 +#define ME_HFS_CWS_REC 2 +#define ME_HFS_CWS_NORMAL 5 +#define ME_HFS_CWS_WAIT 6 +#define ME_HFS_CWS_TRANS 7 +#define ME_HFS_CWS_INVALID 8 +#define ME_HFS_STATE_PREBOOT 0 +#define ME_HFS_STATE_M0_UMA 1 +#define ME_HFS_STATE_M3 4 +#define ME_HFS_STATE_M0 5 +#define ME_HFS_STATE_BRINGUP 6 +#define ME_HFS_STATE_ERROR 7 +#define ME_HFS_ERROR_NONE 0 +#define ME_HFS_ERROR_UNCAT 1 +#define ME_HFS_ERROR_IMAGE 3 +#define ME_HFS_ERROR_DEBUG 4 +#define ME_HFS_MODE_NORMAL 0 +#define ME_HFS_MODE_DEBUG 2 +#define ME_HFS_MODE_DIS 3 +#define ME_HFS_MODE_OVER_JMPR 4 +#define ME_HFS_MODE_OVER_MEI 5 +#define ME_HFS_BIOS_DRAM_ACK 1 +#define ME_HFS_ACK_NO_DID 0 +#define ME_HFS_ACK_RESET 1 +#define ME_HFS_ACK_PWR_CYCLE 2 +#define ME_HFS_ACK_S3 3 +#define ME_HFS_ACK_S4 4 +#define ME_HFS_ACK_S5 5 +#define ME_HFS_ACK_GBL_RESET 6 +#define ME_HFS_ACK_CONTINUE 7 + +struct me_hfs { + u32 working_state: 4; + u32 mfg_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reserved: 4; + u32 boot_options_present: 1; + u32 ack_data: 3; + u32 bios_msg_ack: 4; +} __attribute__ ((packed)); + +#define PCI_ME_UMA 0x44 + +struct me_uma { + u32 size: 6; + u32 reserved_1: 10; + u32 valid: 1; + u32 reserved_0: 14; + u32 set_to_one: 1; +} __attribute__ ((packed)); + +#define PCI_ME_H_GS 0x4c +#define ME_INIT_DONE 1 +#define ME_INIT_STATUS_SUCCESS 0 +#define ME_INIT_STATUS_NOMEM 1 +#define ME_INIT_STATUS_ERROR 2 + +struct me_did { + u32 uma_base: 16; + u32 reserved: 8; + u32 status: 4; + u32 init_done: 4; +} __attribute__ ((packed)); + +#define PCI_ME_GMES 0x48 +#define ME_GMES_PHASE_ROM 0 +#define ME_GMES_PHASE_BUP 1 +#define ME_GMES_PHASE_UKERNEL 2 +#define ME_GMES_PHASE_POLICY 3 +#define ME_GMES_PHASE_MODULE 4 +#define ME_GMES_PHASE_UNKNOWN 5 +#define ME_GMES_PHASE_HOST 6 + +struct me_gmes { + u32 bist_in_prog : 1; + u32 icc_prog_sts : 2; + u32 invoke_mebx : 1; + u32 cpu_replaced_sts : 1; + u32 mbp_rdy : 1; + u32 mfs_failure : 1; + u32 warm_rst_req_for_df : 1; + u32 cpu_replaced_valid : 1; + u32 reserved_1 : 2; + u32 fw_upd_ipu : 1; + u32 reserved_2 : 4; + u32 current_state: 8; + u32 current_pmevent: 4; + u32 progress_code: 4; +} __attribute__ ((packed)); + +#define PCI_ME_HERES 0xbc +#define PCI_ME_EXT_SHA1 0x00 +#define PCI_ME_EXT_SHA256 0x02 +#define PCI_ME_HER(x) (0xc0+(4*(x))) + +struct me_heres { + u32 extend_reg_algorithm: 4; + u32 reserved: 26; + u32 extend_feature_present: 1; + u32 extend_reg_valid: 1; +} __attribute__ ((packed)); + +/* + * Management Engine MEI registers + */ + +#define MEI_H_CB_WW 0x00 +#define MEI_H_CSR 0x04 +#define MEI_ME_CB_RW 0x08 +#define MEI_ME_CSR_HA 0x0c + +struct mei_csr { + u32 interrupt_enable: 1; + u32 interrupt_status: 1; + u32 interrupt_generate: 1; + u32 ready: 1; + u32 reset: 1; + u32 reserved: 3; + u32 buffer_read_ptr: 8; + u32 buffer_write_ptr: 8; + u32 buffer_depth: 8; +} __attribute__ ((packed)); + +#define MEI_ADDRESS_CORE 0x01 +#define MEI_ADDRESS_AMT 0x02 +#define MEI_ADDRESS_RESERVED 0x03 +#define MEI_ADDRESS_WDT 0x04 +#define MEI_ADDRESS_MKHI 0x07 +#define MEI_ADDRESS_ICC 0x08 +#define MEI_ADDRESS_THERMAL 0x09 + +#define MEI_HOST_ADDRESS 0 + +struct mei_header { + u32 client_address: 8; + u32 host_address: 8; + u32 length: 9; + u32 reserved: 6; + u32 is_complete: 1; +} __attribute__ ((packed)); + +#define MKHI_GROUP_ID_CBM 0x00 +#define MKHI_GROUP_ID_FWCAPS 0x03 +#define MKHI_GROUP_ID_MDES 0x08 +#define MKHI_GROUP_ID_GEN 0xff + +#define MKHI_GLOBAL_RESET 0x0b + +#define MKHI_FWCAPS_GET_RULE 0x02 + +#define MKHI_MDES_ENABLE 0x09 + +#define MKHI_GET_FW_VERSION 0x02 +#define MKHI_END_OF_POST 0x0c +#define MKHI_FEATURE_OVERRIDE 0x14 + +struct mkhi_header { + u32 group_id: 8; + u32 command: 7; + u32 is_response: 1; + u32 reserved: 8; + u32 result: 8; +} __attribute__ ((packed)); + +struct me_fw_version { + u16 code_minor; + u16 code_major; + u16 code_build_number; + u16 code_hot_fix; + u16 recovery_minor; + u16 recovery_major; + u16 recovery_build_number; + u16 recovery_hot_fix; +} __attribute__ ((packed)); + + +#define HECI_EOP_STATUS_SUCCESS 0x0 +#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 + +#define CBM_RR_GLOBAL_RESET 0x01 + +#define GLOBAL_RESET_BIOS_MRC 0x01 +#define GLOBAL_RESET_BIOS_POST 0x02 +#define GLOBAL_RESET_MEBX 0x03 + +struct me_global_reset { + u8 request_origin; + u8 reset_type; +} __attribute__ ((packed)); + +typedef enum { + ME_NORMAL_BIOS_PATH, + ME_S3WAKE_BIOS_PATH, + ME_ERROR_BIOS_PATH, + ME_RECOVERY_BIOS_PATH, + ME_DISABLE_BIOS_PATH, + ME_FIRMWARE_UPDATE_BIOS_PATH, +} me_bios_path; + +/* Defined in me_status.c for both romstage and ramstage */ +void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); + +#ifdef __PRE_RAM__ +void intel_early_me_status(void); +int intel_early_me_init(void); +int intel_early_me_uma_size(void); +int intel_early_me_init_done(u8 status); +#else +/* ME Kernel Host Interface Messages */ +int mkhi_end_of_post(void); +int mkhi_global_reset(void); +#endif + +#ifdef __SMM__ +void intel_me_finalize_smm(void); +#endif +typedef struct { + u32 major_version : 16; + u32 minor_version : 16; + u32 hotfix_version : 16; + u32 build_version : 16; +} __attribute__ ((packed)) mbp_fw_version_name; + +typedef struct { + u8 num_icc_profiles; + u8 icc_profile_soft_strap; + u8 icc_profile_index; + u8 reserved; + u32 register_lock_mask[3]; +} __attribute__ ((packed)) mbp_icc_profile; + +typedef struct { + u32 full_net : 1; + u32 std_net : 1; + u32 manageability : 1; + u32 small_business : 1; + u32 l3manageability : 1; + u32 intel_at : 1; + u32 intel_cls : 1; + u32 reserved : 3; + u32 intel_mpc : 1; + u32 icc_over_clocking : 1; + u32 pavp : 1; + u32 reserved_1 : 4; + u32 ipv6 : 1; + u32 kvm : 1; + u32 och : 1; + u32 vlan : 1; + u32 tls : 1; + u32 reserved_4 : 1; + u32 wlan : 1; + u32 reserved_5 : 8; +} __attribute__ ((packed)) mefwcaps_sku; + +typedef struct { + u16 lock_state : 1; + u16 authenticate_module : 1; + u16 s3authentication : 1; + u16 flash_wear_out : 1; + u16 flash_variable_security : 1; + u16 wwan3gpresent : 1; + u16 wwan3goob : 1; + u16 reserved : 9; +} __attribute__ ((packed)) tdt_state_flag; + +typedef struct { + u8 state; + u8 last_theft_trigger; + tdt_state_flag flags; +} __attribute__ ((packed)) tdt_state_info; + +typedef struct { + u32 platform_target_usage_type : 4; + u32 platform_target_market_type : 2; + u32 super_sku : 1; + u32 reserved : 1; + u32 intel_me_fw_image_type : 4; + u32 platform_brand : 4; + u32 reserved_1 : 16; +} __attribute__ ((packed)) platform_type_rule_data; + +typedef struct { + mefwcaps_sku fw_capabilities; + u8 available; +} mbp_fw_caps; + +typedef struct { + u16 device_id; + u16 fuse_test_flags; + u32 umchid[4]; +} __attribute__ ((packed)) mbp_rom_bist_data; + +typedef struct { + u32 key[8]; +} mbp_platform_key; + +typedef struct { + platform_type_rule_data rule_data; + u8 available; +} mbp_plat_type; + +typedef struct { + mbp_fw_version_name fw_version_name; + mbp_fw_caps fw_caps_sku; + mbp_rom_bist_data rom_bist_data; + mbp_platform_key platform_key; + mbp_plat_type fw_plat_type; + mbp_icc_profile icc_profile; + tdt_state_info at_state; + u32 mfsintegrity; +} me_bios_payload; + +typedef struct { + u32 mbp_size : 8; + u32 num_entries : 8; + u32 rsvd : 16; +} __attribute__ ((packed)) mbp_header; + +typedef struct { + u32 app_id : 8; + u32 item_id : 8; + u32 length : 8; + u32 rsvd : 8; +} __attribute__ ((packed)) mbp_item_header; + +struct me_fwcaps { + u32 id; + u8 length; + mefwcaps_sku caps_sku; + u8 reserved[3]; +} __attribute__ ((packed)); + +#endif /* _INTEL_ME_H */ diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c new file mode 100644 index 0000000..1bb2ce3 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -0,0 +1,919 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * This is a ramstage driver for the Intel Management Engine found in the + * 6-series chipset. It handles the required boot-time messages over the + * MMIO-based Management Engine Interface to tell the ME that the BIOS is + * finished with POST. Additional messages are defined for debug but are + * not used unless the console loglevel is high enough. + */ + +#include <arch/acpi.h> +#include <arch/hlt.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> +#include <string.h> +#include <delay.h> + +#ifdef __SMM__ +# include <arch/romcc_io.h> +# include <northbridge/intel/sandybridge/pcie_config.c> +#else +# include <device/device.h> +# include <device/pci.h> +#endif + +#include "me.h" +#include "pch.h" + +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/chromeos.h> +#endif + +#ifndef __SMM__ +/* Path that the BIOS should take based on ME state */ +static const char *me_bios_path_values[] = { + [ME_NORMAL_BIOS_PATH] = "Normal", + [ME_S3WAKE_BIOS_PATH] = "S3 Wake", + [ME_ERROR_BIOS_PATH] = "Error", + [ME_RECOVERY_BIOS_PATH] = "Recovery", + [ME_DISABLE_BIOS_PATH] = "Disable", + [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", +}; +static int intel_me_read_mbp(me_bios_payload *mbp_data); +#endif + +/* MMIO base address for MEI interface */ +static u32 mei_base_address; + +#if CONFIG_DEBUG_INTEL_ME +static void mei_dump(void *ptr, int dword, int offset, const char *type) +{ + struct mei_csr *csr; + + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); + + switch (offset) { + case MEI_H_CSR: + case MEI_ME_CSR_HA: + csr = ptr; + if (!csr) { + printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); + break; + } + printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " + "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, + csr->buffer_read_ptr, csr->buffer_write_ptr, + csr->ready, csr->reset, csr->interrupt_generate, + csr->interrupt_status, csr->interrupt_enable); + break; + case MEI_ME_CB_RW: + case MEI_H_CB_WW: + printk(BIOS_SPEW, "CB: 0x%08x\n", dword); + break; + default: + printk(BIOS_SPEW, "0x%08x\n", offset); + break; + } +} +#else +# define mei_dump(ptr,dword,offset,type) do {} while (0) +#endif + +/* + * ME/MEI access helpers using memcpy to avoid aliasing. + */ + +static inline void mei_read_dword_ptr(void *ptr, int offset) +{ + u32 dword = read32(mei_base_address + offset); + memcpy(ptr, &dword, sizeof(dword)); + mei_dump(ptr, dword, offset, "READ"); +} + +static inline void mei_write_dword_ptr(void *ptr, int offset) +{ + u32 dword = 0; + memcpy(&dword, ptr, sizeof(dword)); + write32(mei_base_address + offset, dword); + mei_dump(ptr, dword, offset, "WRITE"); +} + +#ifndef __SMM__ +static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +{ + u32 dword = pci_read_config32(dev, offset); + memcpy(ptr, &dword, sizeof(dword)); + mei_dump(ptr, dword, offset, "PCI READ"); +} +#endif + +static inline void read_host_csr(struct mei_csr *csr) +{ + mei_read_dword_ptr(csr, MEI_H_CSR); +} + +static inline void write_host_csr(struct mei_csr *csr) +{ + mei_write_dword_ptr(csr, MEI_H_CSR); +} + +static inline void read_me_csr(struct mei_csr *csr) +{ + mei_read_dword_ptr(csr, MEI_ME_CSR_HA); +} + +static inline void write_cb(u32 dword) +{ + write32(mei_base_address + MEI_H_CB_WW, dword); + mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); +} + +static inline u32 read_cb(void) +{ + u32 dword = read32(mei_base_address + MEI_ME_CB_RW); + mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); + return dword; +} + +/* Wait for ME ready bit to be asserted */ +static int mei_wait_for_me_ready(void) +{ + struct mei_csr me; + unsigned try = ME_RETRY; + + while (try--) { + read_me_csr(&me); + if (me.ready) + return 0; + udelay(ME_DELAY); + } + + printk(BIOS_ERR, "ME: failed to become ready\n"); + return -1; +} + +static void mei_reset(void) +{ + struct mei_csr host; + + if (mei_wait_for_me_ready() < 0) + return; + + /* Reset host and ME circular buffers for next message */ + read_host_csr(&host); + host.reset = 1; + host.interrupt_generate = 1; + write_host_csr(&host); + + if (mei_wait_for_me_ready() < 0) + return; + + /* Re-init and indicate host is ready */ + read_host_csr(&host); + host.interrupt_generate = 1; + host.ready = 1; + host.reset = 0; + write_host_csr(&host); +} + +static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data) +{ + struct mei_csr host; + unsigned ndata, n; + u32 *data; + + /* Number of dwords to write, ignoring MKHI */ + ndata = mei->length >> 2; + + /* Pad non-dword aligned request message length */ + if (mei->length & 3) + ndata++; + if (!ndata) { + printk(BIOS_DEBUG, "ME: request does not include MKHI\n"); + return -1; + } + ndata++; /* Add MEI header */ + + /* + * Make sure there is still room left in the circular buffer. + * Reset the buffer pointers if the requested message will not fit. + */ + read_host_csr(&host); + if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { + printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); + mei_reset(); + read_host_csr(&host); + } + + /* + * This implementation does not handle splitting large messages + * across multiple transactions. Ensure the requested length + * will fit in the available circular buffer depth. + */ + if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { + printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", + ndata + 2, host.buffer_depth); + return -1; + } + + /* Write MEI header */ + mei_write_dword_ptr(mei, MEI_H_CB_WW); + ndata--; + + /* Write MKHI header */ + mei_write_dword_ptr(mkhi, MEI_H_CB_WW); + ndata--; + + /* Write message data */ + data = req_data; + for (n = 0; n < ndata; ++n) + write_cb(*data++); + + /* Generate interrupt to the ME */ + read_host_csr(&host); + host.interrupt_generate = 1; + write_host_csr(&host); + + /* Make sure ME is ready after sending request data */ + return mei_wait_for_me_ready(); +} + +static int mei_recv_msg(struct mkhi_header *mkhi, + void *rsp_data, int rsp_bytes) +{ + struct mei_header mei_rsp; + struct mkhi_header mkhi_rsp; + struct mei_csr me, host; + unsigned ndata, n/*, me_data_len*/; + unsigned expected; + u32 *data; + + /* Total number of dwords to read from circular buffer */ + expected = (rsp_bytes + sizeof(mei_rsp) + sizeof(mkhi_rsp)) >> 2; + if (rsp_bytes & 3) + expected++; + + /* + * The interrupt status bit does not appear to indicate that the + * message has actually been received. Instead we wait until the + * expected number of dwords are present in the circular buffer. + */ + for (n = ME_RETRY; n; --n) { + read_me_csr(&me); + if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) + break; + udelay(ME_DELAY); + } + if (!n) { + printk(BIOS_ERR, "ME: timeout waiting for data: expected " + "%u, available %u\n", expected, + me.buffer_write_ptr - me.buffer_read_ptr); + return -1; + } + + /* Read and verify MEI response header from the ME */ + mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); + if (!mei_rsp.is_complete) { + printk(BIOS_ERR, "ME: response is not complete\n"); + return -1; + } + + /* Handle non-dword responses and expect at least MKHI header */ + ndata = mei_rsp.length >> 2; + if (mei_rsp.length & 3) + ndata++; + if (ndata != (expected - 1)) { + printk(BIOS_ERR, "ME: response is missing data %d != %d\n", + ndata, (expected - 1)); + return -1; + } + + /* Read and verify MKHI response header from the ME */ + mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW); + if (!mkhi_rsp.is_response || + mkhi->group_id != mkhi_rsp.group_id || + mkhi->command != mkhi_rsp.command) { + printk(BIOS_ERR, "ME: invalid response, group %u ?= %u," + "command %u ?= %u, is_response %u\n", mkhi->group_id, + mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, + mkhi_rsp.is_response); + return -1; + } + ndata--; /* MKHI header has been read */ + + /* Make sure caller passed a buffer with enough space */ + if (ndata != (rsp_bytes >> 2)) { + printk(BIOS_ERR, "ME: not enough room in response buffer: " + "%u != %u\n", ndata, rsp_bytes >> 2); + return -1; + } + + /* Read response data from the circular buffer */ + data = rsp_data; + for (n = 0; n < ndata; ++n) + *data++ = read_cb(); + + /* Tell the ME that we have consumed the response */ + read_host_csr(&host); + host.interrupt_status = 1; + host.interrupt_generate = 1; + write_host_csr(&host); + + return mei_wait_for_me_ready(); +} + +static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data, void *rsp_data, int rsp_bytes) +{ + if (mei_send_msg(mei, mkhi, req_data) < 0) + return -1; + if (mei_recv_msg(mkhi, rsp_data, rsp_bytes) < 0) + return -1; + return 0; +} + +/* Send END OF POST message to the ME */ +int mkhi_end_of_post(void) +{ + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_GEN, + .command = MKHI_END_OF_POST, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi), + }; + + u32 eop_ack; + + /* Send request and wait for response */ + printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); + if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) { + printk(BIOS_ERR, "ME: END OF POST message failed\n"); + return -1; + } + + printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); + return 0; +} + +#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) +static inline void print_cap(const char *name, int state) +{ + printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", + name, state ? " en" : "dis"); +} + +static void me_print_fw_version(mbp_fw_version_name *vers_name) +{ + if (!vers_name->major_version) { + printk(BIOS_ERR, "ME: mbp missing version report\n"); + return; + } + + printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n", + vers_name->major_version, vers_name->minor_version, + vers_name->hotfix_version, vers_name->build_version); +} + +/* Get ME Firmware Capabilities */ +static int mkhi_get_fwcaps(mefwcaps_sku *cap) +{ + u32 rule_id = 0; + struct me_fwcaps cap_msg; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_FWCAPS, + .command = MKHI_FWCAPS_GET_RULE, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi) + sizeof(rule_id), + }; + + /* Send request and wait for response */ + if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) + < 0) { + printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); + return -1; + } + *cap = cap_msg.caps_sku; + return 0; +} + +/* Get ME Firmware Capabilities */ +static void me_print_fwcaps(mbp_fw_caps *caps_section) +{ + mefwcaps_sku *cap = &caps_section->fw_capabilities; + if (!caps_section->available) { + printk(BIOS_ERR, "ME: mbp missing fwcaps report\n"); + if (mkhi_get_fwcaps(cap)) + return; + } + + print_cap("Full Network manageability", cap->full_net); + print_cap("Regular Network manageability", cap->std_net); + print_cap("Manageability", cap->manageability); + print_cap("Small business technology", cap->small_business); + print_cap("Level III manageability", cap->l3manageability); + print_cap("IntelR Anti-Theft (AT)", cap->intel_at); + print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); + print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); + print_cap("ICC Over Clocking", cap->icc_over_clocking); + print_cap("Protected Audio Video Path (PAVP)", cap->pavp); + print_cap("IPV6", cap->ipv6); + print_cap("KVM Remote Control (KVM)", cap->kvm); + print_cap("Outbreak Containment Heuristic (OCH)", cap->och); + print_cap("Virtual LAN (VLAN)", cap->vlan); + print_cap("TLS", cap->tls); + print_cap("Wireless LAN (WLAN)", cap->wlan); +} +#endif + +/* Tell ME to issue a global reset */ +int mkhi_global_reset(void) +{ + struct me_global_reset reset = { + .request_origin = GLOBAL_RESET_BIOS_POST, + .reset_type = CBM_RR_GLOBAL_RESET, + }; + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_CBM, + .command = MKHI_GLOBAL_RESET, + }; + struct mei_header mei = { + .is_complete = 1, + .length = sizeof(mkhi) + sizeof(reset), + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + }; + + /* Send request and wait for response */ + printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); + if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { + /* No response means reset will happen shortly... */ + hlt(); + } + + /* If the ME responded it rejected the reset request */ + printk(BIOS_ERR, "ME: Global Reset failed\n"); + return -1; +} + +#ifdef __SMM__ + +void intel_me_finalize_smm(void) +{ + struct me_hfs hfs; + u32 reg32; + + mei_base_address = + pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + + /* S3 path will have hidden this device already */ + if (!mei_base_address || mei_base_address == 0xfffffff0) + return; + + /* Make sure ME is in a mode that expects EOP */ + reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); + memcpy(&hfs, &reg32, sizeof(u32)); + + /* Abort and leave device alone if not normal mode */ + if (hfs.fpt_bad || + hfs.working_state != ME_HFS_CWS_NORMAL || + hfs.operation_mode != ME_HFS_MODE_NORMAL) + return; + + /* Try to send EOP command so ME stops accepting other commands */ + mkhi_end_of_post(); + + /* Make sure IO is disabled */ + reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + + /* Hide the PCI device */ + RCBA32_OR(FD2, PCH_DISABLE_MEI1); +} + +#else /* !__SMM__ */ + +/* Determine the path that we should take based on ME status */ +static me_bios_path intel_me_path(device_t dev) +{ + me_bios_path path = ME_DISABLE_BIOS_PATH; + struct me_hfs hfs; + struct me_gmes gmes; + +#if CONFIG_HAVE_ACPI_RESUME + /* S3 wake skips all MKHI messages */ + if (acpi_slp_type == 3) { + return ME_S3WAKE_BIOS_PATH; + } +#endif + + pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); + pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES); + + /* Check and dump status */ + intel_me_status(&hfs, &gmes); + + /* Check for valid firmware */ + if (hfs.fpt_bad) + return ME_ERROR_BIOS_PATH; + + /* Check Current Working State */ + switch (hfs.working_state) { + case ME_HFS_CWS_NORMAL: + path = ME_NORMAL_BIOS_PATH; + /* check if the MBP is ready */ + if (!gmes.mbp_rdy) { + printk(BIOS_CRIT, "%s: mbp is not ready!\n", + __FUNCTION__); + return ME_ERROR_BIOS_PATH; + } + break; + case ME_HFS_CWS_REC: + path = ME_RECOVERY_BIOS_PATH; + break; + default: + path = ME_DISABLE_BIOS_PATH; + break; + } + + /* Check Current Operation Mode */ + switch (hfs.operation_mode) { + case ME_HFS_MODE_NORMAL: + break; + case ME_HFS_MODE_DEBUG: + case ME_HFS_MODE_DIS: + case ME_HFS_MODE_OVER_JMPR: + case ME_HFS_MODE_OVER_MEI: + default: + path = ME_DISABLE_BIOS_PATH; + break; + } + + /* Check for any error code */ + if (hfs.error_code) + path = ME_ERROR_BIOS_PATH; + + return path; +} + +/* Prepare ME for MEI messages */ +static int intel_mei_setup(device_t dev) +{ + struct resource *res; + struct mei_csr host; + u32 reg32; + + /* Find the MMIO base for the ME interface */ + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res || res->base == 0 || res->size == 0) { + printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); + return -1; + } + mei_base_address = res->base; + + /* Ensure Memory and Bus Master bits are set */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Clean up status for next message */ + read_host_csr(&host); + host.interrupt_generate = 1; + host.ready = 1; + host.reset = 0; + write_host_csr(&host); + + return 0; +} + +/* Read the Extend register hash of ME firmware */ +static int intel_me_extend_valid(device_t dev) +{ + struct me_heres status; + u32 extend; + int i, count = 0; + + pci_read_dword_ptr(dev, &status, PCI_ME_HERES); + if (!status.extend_feature_present) { + printk(BIOS_ERR, "ME: Extend Feature not present\n"); + return -1; + } + + if (!status.extend_reg_valid) { + printk(BIOS_ERR, "ME: Extend Register not valid\n"); + return -1; + } + + switch (status.extend_reg_algorithm) { + case PCI_ME_EXT_SHA1: + count = 5; + printk(BIOS_DEBUG, "ME: Extend SHA-1: "); + break; + case PCI_ME_EXT_SHA256: + count = 8; + printk(BIOS_DEBUG, "ME: Extend SHA-256: "); + break; + default: + printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", + status.extend_reg_algorithm); + return -1; + } + + /* + * TODO(dlaurie) Verify the hash against a saved good value. + */ + + for (i = 0; i < count; ++i) { + extend = pci_read_config32(dev, PCI_ME_HER(i)); + printk(BIOS_DEBUG, "%08x", extend); + } + printk(BIOS_DEBUG, "\n"); + + return 0; +} + +/* Hide the ME virtual PCI devices */ +static void intel_me_hide(device_t dev) +{ + dev->enabled = 0; + pch_enable(dev); +} + +/* Check whether ME is present and do basic init */ +static void intel_me_init(device_t dev) +{ + me_bios_path path = intel_me_path(dev); + me_bios_payload mbp_data; + + /* Do initial setup and determine the BIOS path */ + printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); + + switch (path) { + case ME_S3WAKE_BIOS_PATH: + intel_me_hide(dev); + break; + + case ME_NORMAL_BIOS_PATH: + /* Validate the extend register */ + if (intel_me_extend_valid(dev) < 0) + break; /* TODO: force recovery mode */ + + /* Prepare MEI MMIO interface */ + if (intel_mei_setup(dev) < 0) + break; + + if(intel_me_read_mbp(&mbp_data)) + break; + +#if CONFIG_CHROMEOS && 0 /* DISABLED */ + /* + * Unlock ME in recovery mode. + */ + if (recovery_mode_enabled()) { + /* Unlock ME flash region */ + mkhi_hmrfpo_enable(); + + /* Issue global reset */ + mkhi_global_reset(); + return; + } +#endif + +#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) + me_print_fw_version(&mbp_data.fw_version_name); + me_print_fwcaps(&mbp_data.fw_caps_sku); +#endif + /* Tell ME that BIOS is done */ + mkhi_end_of_post(); + /* Hide the virtual PCI device */ + intel_me_hide(dev); + break; + + case ME_ERROR_BIOS_PATH: + case ME_RECOVERY_BIOS_PATH: + case ME_DISABLE_BIOS_PATH: + case ME_FIRMWARE_UPDATE_BIOS_PATH: + /* + * TODO(dlaurie) Force recovery mode if ME is unhappy? + */ + break; + } +} + +static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations pci_ops = { + .set_subsystem = set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = intel_me_init, + .scan_bus = scan_static_bus, + .ops_pci = &pci_ops, +}; + +static const struct pci_driver intel_me __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e3a, +}; + +/****************************************************************************** + * */ +static u32 me_to_host_words_pending(void) +{ + struct mei_csr me; + read_me_csr(&me); + if (!me.ready) + return 0; + return (me.buffer_write_ptr - me.buffer_read_ptr) & + (me.buffer_depth - 1); +} + +#if 0 +/* This function is not yet being used, keep it in for the future. */ +static u32 host_to_me_words_room(void) +{ + struct mei_csr csr; + + read_me_csr(&csr); + if (!csr.ready) + return 0; + + read_host_csr(&csr); + return (csr.buffer_read_ptr - csr.buffer_write_ptr - 1) & + (csr.buffer_depth - 1); +} +#endif +/* + * mbp seems to be following its own flow, let's retrieve it in a dedicated + * function. + */ +static int intel_me_read_mbp(me_bios_payload *mbp_data) +{ + mbp_header mbp_hdr; + mbp_item_header mbp_item_hdr; + u32 me2host_pending; + u32 mbp_item_id; + struct mei_csr host; + + me2host_pending = me_to_host_words_pending(); + if (!me2host_pending) { + printk(BIOS_ERR, "ME: no mbp data!\n"); + return -1; + } + + /* we know for sure that at least the header is there */ + mei_read_dword_ptr(&mbp_hdr, MEI_ME_CB_RW); + + if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) || + (me2host_pending < mbp_hdr.mbp_size)) { + printk(BIOS_ERR, "ME: mbp of %d entries, total size %d words" + " buffer contains %d words\n", + mbp_hdr.num_entries, mbp_hdr.mbp_size, + me2host_pending); + return -1; + } + + me2host_pending--; + memset(mbp_data, 0, sizeof(*mbp_data)); + + while (mbp_hdr.num_entries--) { + u32* copy_addr; + u32 copy_size, buffer_room; + void *p; + + if (!me2host_pending) { + printk(BIOS_ERR, "ME: no mbp data %d entries to go!\n", + mbp_hdr.num_entries + 1); + return -1; + } + + mei_read_dword_ptr(&mbp_item_hdr, MEI_ME_CB_RW); + + if (mbp_item_hdr.length > me2host_pending) { + printk(BIOS_ERR, "ME: insufficient mbp data %d " + "entries to go!\n", + mbp_hdr.num_entries + 1); + return -1; + } + + me2host_pending -= mbp_item_hdr.length; + + mbp_item_id = (((u32)mbp_item_hdr.item_id) << 8) + + mbp_item_hdr.app_id; + + copy_size = mbp_item_hdr.length - 1; + +#define SET_UP_COPY(field) { copy_addr = (u32 *)&mbp_data->field; \ + buffer_room = sizeof(mbp_data->field) / sizeof(u32); \ + break; \ + } + + p = &mbp_item_hdr; + printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p)); + + switch(mbp_item_id) { + case 0x101: + SET_UP_COPY(fw_version_name); + + case 0x102: + SET_UP_COPY(icc_profile); + + case 0x103: + SET_UP_COPY(at_state); + + case 0x201: + mbp_data->fw_caps_sku.available = 1; + SET_UP_COPY(fw_caps_sku.fw_capabilities); + + case 0x301: + SET_UP_COPY(rom_bist_data); + + case 0x401: + SET_UP_COPY(platform_key); + + case 0x501: + mbp_data->fw_plat_type.available = 1; + SET_UP_COPY(fw_plat_type.rule_data); + + case 0x601: + SET_UP_COPY(mfsintegrity); + + default: + printk(BIOS_ERR, "ME: unknown mbp item id 0x%x!!!\n", + mbp_item_id); + return -1; + } + + if (buffer_room != copy_size) { + printk(BIOS_ERR, "ME: buffer room %d != %d copy size" + " for item 0x%x!!!\n", + buffer_room, copy_size, mbp_item_id); + return -1; + } + while(copy_size--) + *copy_addr++ = read_cb(); + } + + read_host_csr(&host); + host.interrupt_generate = 1; + write_host_csr(&host); + + { + int cntr = 0; + while(host.interrupt_generate) { + read_host_csr(&host); + cntr++; + } + printk(BIOS_SPEW, "ME: mbp read OK after %d cycles\n", cntr); + } + + return 0; +} + +#endif /* !__SMM__ */ diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c new file mode 100644 index 0000000..b2f38d6 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -0,0 +1,213 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <console/console.h> +#include "me.h" + +#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) +/* HFS1[3:0] Current Working State Values */ +static const char *me_cws_values[] = { + [ME_HFS_CWS_RESET] = "Reset", + [ME_HFS_CWS_INIT] = "Initializing", + [ME_HFS_CWS_REC] = "Recovery", + [ME_HFS_CWS_NORMAL] = "Normal", + [ME_HFS_CWS_WAIT] = "Platform Disable Wait", + [ME_HFS_CWS_TRANS] = "OP State Transition", + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" +}; + +/* HFS1[8:6] Current Operation State Values */ +static const char *me_opstate_values[] = { + [ME_HFS_STATE_PREBOOT] = "Preboot", + [ME_HFS_STATE_M0_UMA] = "M0 with UMA", + [ME_HFS_STATE_M3] = "M3 without UMA", + [ME_HFS_STATE_M0] = "M0 without UMA", + [ME_HFS_STATE_BRINGUP] = "Bring up", + [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" +}; + +/* HFS[19:16] Current Operation Mode Values */ +static const char *me_opmode_values[] = { + [ME_HFS_MODE_NORMAL] = "Normal", + [ME_HFS_MODE_DEBUG] = "Debug", + [ME_HFS_MODE_DIS] = "Soft Temporary Disable", + [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", + [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" +}; + +/* HFS[15:12] Error Code Values */ +static const char *me_error_values[] = { + [ME_HFS_ERROR_NONE] = "No Error", + [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", + [ME_HFS_ERROR_IMAGE] = "Image Failure", + [ME_HFS_ERROR_DEBUG] = "Debug Failure" +}; + +/* GMES[31:28] ME Progress Code */ +static const char *me_progress_values[] = { + [ME_GMES_PHASE_ROM] = "ROM Phase", + [ME_GMES_PHASE_BUP] = "BUP Phase", + [ME_GMES_PHASE_UKERNEL] = "uKernel Phase", + [ME_GMES_PHASE_POLICY] = "Policy Module", + [ME_GMES_PHASE_MODULE] = "Module Loading", + [ME_GMES_PHASE_UNKNOWN] = "Unknown", + [ME_GMES_PHASE_HOST] = "Host Communication" +}; + +/* GMES[27:24] Power Management Event */ +static const char *me_pmevent_values[] = { + [0x00] = "Clean Moff->Mx wake", + [0x01] = "Moff->Mx wake after an error", + [0x02] = "Clean global reset", + [0x03] = "Global reset after an error", + [0x04] = "Clean Intel ME reset", + [0x05] = "Intel ME reset due to exception", + [0x06] = "Pseudo-global reset", + [0x07] = "S0/M0->Sx/M3", + [0x08] = "Sx/M3->S0/M0", + [0x09] = "Non-power cycle reset", + [0x0a] = "Power cycle reset through M3", + [0x0b] = "Power cycle reset through Moff", + [0x0c] = "Sx/Mx->Sx/Moff" +}; + +/* Progress Code 0 states */ +static const char *me_progress_rom_values[] = { + [0x00] = "BEGIN", + [0x06] = "DISABLE" +}; + +/* Progress Code 1 states */ +static const char *me_progress_bup_values[] = { + [0x00] = "Initialization starts", + [0x01] = "Disable the host wake event", + [0x04] = "Flow determination start process", + [0x08] = "Error reading/matching the VSCC table in the descriptor", + [0x0a] = "Check to see if straps say ME DISABLED", + [0x0b] = "Timeout waiting for PWROK", + [0x0d] = "Possibly handle BUP manufacturing override strap", + [0x11] = "Bringup in M3", + [0x12] = "Bringup in M0", + [0x13] = "Flow detection error", + [0x15] = "M3 clock switching error", + [0x18] = "M3 kernel load", + [0x1c] = "T34 missing - cannot program ICC", + [0x1f] = "Waiting for DID BIOS message", + [0x20] = "Waiting for DID BIOS message failure", + [0x21] = "DID reported an error", + [0x22] = "Enabling UMA", + [0x23] = "Enabling UMA error", + [0x24] = "Sending DID Ack to BIOS", + [0x25] = "Sending DID Ack to BIOS error", + [0x26] = "Switching clocks in M0", + [0x27] = "Switching clocks in M0 error", + [0x28] = "ME in temp disable", + [0x32] = "M0 kernel load", +}; + +/* Progress Code 3 states */ +static const char *me_progress_policy_values[] = { + [0x00] = "Entery into Policy Module", + [0x03] = "Received S3 entry", + [0x04] = "Received S4 entry", + [0x05] = "Received S5 entry", + [0x06] = "Received UPD entry", + [0x07] = "Received PCR entry", + [0x08] = "Received NPCR entry", + [0x09] = "Received host wake", + [0x0a] = "Received AC<>DC switch", + [0x0b] = "Received DRAM Init Done", + [0x0c] = "VSCC Data not found for flash device", + [0x0d] = "VSCC Table is not valid", + [0x0e] = "Flash Partition Boundary is outside address space", + [0x0f] = "ME cannot access the chipset descriptor region", + [0x10] = "Required VSCC values for flash parts do not match", +}; +#endif + +void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) +{ +#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) + /* Check Current States */ + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfs->fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", + hfs->ft_bup_ld_flr ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", + hfs->fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfs->mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfs->boot_options_present ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfs->update_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %s\n", + me_cws_values[hfs->working_state]); + printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", + me_opstate_values[hfs->operation_state]); + printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", + me_opmode_values[hfs->operation_mode]); + printk(BIOS_DEBUG, "ME: Error Code : %s\n", + me_error_values[hfs->error_code]); + printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", + me_progress_values[gmes->progress_code]); + printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", + me_pmevent_values[gmes->current_pmevent]); + + printk(BIOS_DEBUG, "ME: Progress Phase State : "); + switch (gmes->progress_code) { + case ME_GMES_PHASE_ROM: /* ROM Phase */ + printk(BIOS_DEBUG, "%s", + me_progress_rom_values[gmes->current_state]); + break; + + case ME_GMES_PHASE_BUP: /* Bringup Phase */ + if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) + && me_progress_bup_values[gmes->current_state]) + printk(BIOS_DEBUG, "%s", + me_progress_bup_values[gmes->current_state]); + else + printk(BIOS_DEBUG, "0x%02x", gmes->current_state); + break; + + case ME_GMES_PHASE_POLICY: /* Policy Module Phase */ + if (gmes->current_state < ARRAY_SIZE(me_progress_policy_values) + && me_progress_policy_values[gmes->current_state]) + printk(BIOS_DEBUG, "%s", + me_progress_policy_values[gmes->current_state]); + else + printk(BIOS_DEBUG, "0x%02x", gmes->current_state); + break; + + case ME_GMES_PHASE_HOST: /* Host Communication Phase */ + if (!gmes->current_state) + printk(BIOS_DEBUG, "Host communication established"); + else + printk(BIOS_DEBUG, "0x%02x", gmes->current_state); + break; + + default: + printk(BIOS_DEBUG, "Unknown 0x%02x", gmes->current_state); + } + printk(BIOS_DEBUG, "\n"); +#endif +} diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h new file mode 100644 index 0000000..3928804 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -0,0 +1,139 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "vendorcode/google/chromeos/gnvs.h" +typedef struct { + /* Miscellaneous */ + u16 osys; /* 0x00 - Operating System */ + u8 smif; /* 0x02 - SMI function call ("TRAP") */ + u8 prm0; /* 0x03 - SMI function call parameter */ + u8 prm1; /* 0x04 - SMI function call parameter */ + u8 scif; /* 0x05 - SCI function call (via _L00) */ + u8 prm2; /* 0x06 - SCI function call parameter */ + u8 prm3; /* 0x07 - SCI function call parameter */ + u8 lckf; /* 0x08 - Global Lock function for EC */ + u8 prm4; /* 0x09 - Lock function parameter */ + u8 prm5; /* 0x0a - Lock function parameter */ + u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ + u8 lids; /* 0x0f - LID state (open = 1) */ + u8 pwrs; /* 0x10 - Power state (AC = 1) */ + /* Thermal policy */ + u8 tlvl; /* 0x11 - Throttle Level Limit */ + u8 flvl; /* 0x12 - Current FAN Level */ + u8 tcrt; /* 0x13 - Critical Threshold */ + u8 tpsv; /* 0x14 - Passive Threshold */ + u8 tmax; /* 0x15 - CPU Tj_max */ + u8 f0of; /* 0x16 - FAN 0 OFF Threshold */ + u8 f0on; /* 0x17 - FAN 0 ON Threshold */ + u8 f0pw; /* 0x18 - FAN 0 PWM value */ + u8 f1of; /* 0x19 - FAN 1 OFF Threshold */ + u8 f1on; /* 0x1a - FAN 1 ON Threshold */ + u8 f1pw; /* 0x1b - FAN 1 PWM value */ + u8 f2of; /* 0x1c - FAN 2 OFF Threshold */ + u8 f2on; /* 0x1d - FAN 2 ON Threshold */ + u8 f2pw; /* 0x1e - FAN 2 PWM value */ + u8 f3of; /* 0x1f - FAN 3 OFF Threshold */ + u8 f3on; /* 0x20 - FAN 3 ON Threshold */ + u8 f3pw; /* 0x21 - FAN 3 PWM value */ + u8 f4of; /* 0x22 - FAN 4 OFF Threshold */ + u8 f4on; /* 0x23 - FAN 4 ON Threshold */ + u8 f4pw; /* 0x24 - FAN 4 PWM value */ + u8 rsvd3[3]; + /* Processor Identification */ + u8 apic; /* 0x28 - APIC enabled */ + u8 mpen; /* 0x29 - MP capable/enabled */ + u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ + u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ + u8 ppcm; /* 0x2c - Max. PPC state */ + u8 pcnt; /* 0x2d - Processor Count */ + u8 rsvd4[4]; + /* Super I/O & CMOS config */ + u8 natp; /* 0x32 - SIO type */ + u8 s5u0; /* 0x33 - Enable USB0 in S5 */ + u8 s5u1; /* 0x34 - Enable USB1 in S5 */ + u8 s3u0; /* 0x35 - Enable USB0 in S3 */ + u8 s3u1; /* 0x36 - Enable USB1 in S3 */ + u8 s33g; /* 0x37 - Enable S3 in 3G */ + u32 cmem; /* 0x38 - CBMEM TOC */ + /* Integrated Graphics Device */ + u8 igds; /* 0x3c - IGD state */ + u8 tlst; /* 0x3d - Display Toggle List Pointer */ + u8 cadl; /* 0x3e - currently attached devices */ + u8 padl; /* 0x3f - previously attached devices */ + u16 cste; /* 0x40 - current display state */ + u16 nste; /* 0x42 - next display state */ + u16 sste; /* 0x44 - set display state */ + u8 ndid; /* 0x46 - number of device ids */ + u32 did[5]; /* 0x47 - 5b device id 1..5 */ + u8 rsvd5[0x9]; + /* Backlight Control */ + u8 blcs; /* 0x64 - Backlight Control possible */ + u8 brtl; + u8 odds; + u8 rsvd6[0x7]; + /* Ambient Light Sensors*/ + u8 alse; /* 0x6e - ALS enable */ + u8 alaf; + u8 llow; + u8 lhih; + u8 rsvd7[0x6]; + /* EMA */ + u8 emae; /* 0x78 - EMA enable */ + u16 emap; + u16 emal; + u8 rsvd8[0x5]; + /* MEF */ + u8 mefe; /* 0x82 - MEF enable */ + u8 rsvd9[0x9]; + /* TPM support */ + u8 tpmp; /* 0x8c - TPM */ + u8 tpme; + u8 rsvd10[8]; + /* SATA */ + u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */ + u8 gtf1[7]; + u8 gtf2[7]; + u8 idem; + u8 idet; + u8 rsvd11[7]; + /* IGD OpRegion (not implemented yet) */ + u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ + u8 ibtt; + u8 ipat; + u8 itvf; + u8 itvm; + u8 ipsc; + u8 iblc; + u8 ibia; + u8 issc; + u8 i409; + u8 i509; + u8 i609; + u8 i709; + u8 idmm; + u8 idms; + u8 if1e; + u8 hvco; + u32 nxd[8]; + u8 rsvd12[8]; + /* ChromeOS specific (starts at 0xf0)*/ + chromeos_acpi_t chromeos; +} __attribute__((packed)) global_nvs_t; + diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c new file mode 100644 index 0000000..e83c2e6 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -0,0 +1,234 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include "pch.h" + +static int pch_revision_id = -1; + +int pch_silicon_revision(void) +{ + if (pch_revision_id < 0) + pch_revision_id = pci_read_config8( + dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + PCI_REVISION_ID); + return pch_revision_id; +} + +/* Set bit in Function Disble register to hide this device */ +static void pch_hide_devfn(unsigned devfn) +{ + switch (devfn) { + case PCI_DEVFN(22, 0): /* MEI #1 */ + RCBA32_OR(FD2, PCH_DISABLE_MEI1); + break; + case PCI_DEVFN(22, 1): /* MEI #2 */ + RCBA32_OR(FD2, PCH_DISABLE_MEI2); + break; + case PCI_DEVFN(22, 2): /* IDE-R */ + RCBA32_OR(FD2, PCH_DISABLE_IDER); + break; + case PCI_DEVFN(22, 3): /* KT */ + RCBA32_OR(FD2, PCH_DISABLE_KT); + break; + case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ + RCBA32_OR(BUC, PCH_DISABLE_GBE); + break; + case PCI_DEVFN(26, 0): /* EHCI #2 */ + RCBA32_OR(FD, PCH_DISABLE_EHCI2); + break; + case PCI_DEVFN(27, 0): /* HD Audio Controller */ + RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); + break; + case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ + case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ + case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ + case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ + case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ + case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ + case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ + case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ + RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn))); + break; + case PCI_DEVFN(29, 0): /* EHCI #1 */ + RCBA32_OR(FD, PCH_DISABLE_EHCI1); + break; + case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */ + RCBA32_OR(FD, PCH_DISABLE_P2P); + break; + case PCI_DEVFN(31, 0): /* LPC */ + RCBA32_OR(FD, PCH_DISABLE_LPC); + break; + case PCI_DEVFN(31, 2): /* SATA #1 */ + RCBA32_OR(FD, PCH_DISABLE_SATA1); + break; + case PCI_DEVFN(31, 3): /* SMBUS */ + RCBA32_OR(FD, PCH_DISABLE_SMBUS); + break; + case PCI_DEVFN(31, 5): /* SATA #22 */ + RCBA32_OR(FD, PCH_DISABLE_SATA2); + break; + case PCI_DEVFN(31, 6): /* Thermal Subsystem */ + RCBA32_OR(FD, PCH_DISABLE_THERMAL); + break; + } +} + +#define IOBP_RETRY 1000 +static inline int iobp_poll(void) +{ + unsigned try = IOBP_RETRY; + u32 data; + + while (try--) { + data = RCBA32(IOBPS); + if ((data & 1) == 0) + return 1; + udelay(10); + } + + printk(BIOS_ERR, "IOBP timeout\n"); + return 0; +} + +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +{ + u32 data; + + /* Set the address */ + RCBA32(IOBPIRI) = address; + + /* READ OPCODE */ + if (pch_silicon_revision() >= PCH_STEP_B0) + RCBA32(IOBPS) = IOBPS_RW_BX; + else + RCBA32(IOBPS) = IOBPS_READ_AX; + if (!iobp_poll()) + return; + + /* Read IOBP data */ + data = RCBA32(IOBPD); + if (!iobp_poll()) + return; + + /* Check for successful transaction */ + if ((RCBA32(IOBPS) & 0x6) != 0) { + printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address); + return; + } + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + /* WRITE OPCODE */ + if (pch_silicon_revision() >= PCH_STEP_B0) + RCBA32(IOBPS) = IOBPS_RW_BX; + else + RCBA32(IOBPS) = IOBPS_WRITE_AX; + if (!iobp_poll()) + return; + + /* Write IOBP data */ + RCBA32(IOBPD) = data; + if (!iobp_poll()) + return; +} + +/* Check if any port in set X to X+3 is enabled */ +static int pch_pcie_check_set_enabled(device_t dev) +{ + device_t port; + int port_func; + int dev_func = PCI_FUNC(dev->path.pci.devfn); + + printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev)); + + /* Go through static device tree list of devices + * because enumeration is still in progress */ + for (port = all_devices; port; port = port->next) { + /* Only care about PCIe root ports */ + if (PCI_SLOT(port->path.pci.devfn) != + PCI_SLOT(dev->path.pci.devfn)) + continue; + + /* Check if port is in range and enabled */ + port_func = PCI_FUNC(port->path.pci.devfn); + if (port_func >= dev_func && + port_func < (dev_func + 4) && + port->enabled) + return 1; + } + + /* None of the ports in this set are enabled */ + return 0; +} + +void pch_enable(device_t dev) +{ + u32 reg32; + + if (!dev->enabled) { + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + + /* + * PCIE Power Savings for stepping B1+: + * + * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1 + * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1 + * + * This check is done here instead of pcie driver + * because the pcie driver enable() handler is not + * called unless the device is enabled. + */ + if (pch_silicon_revision() >= PCH_STEP_B1 && + PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT && + (PCI_FUNC(dev->path.pci.devfn) == 0 || + PCI_FUNC(dev->path.pci.devfn) == 4)) { + if (!pch_pcie_check_set_enabled(dev)) { + u8 reg8 = pci_read_config8(dev, 0xe2); + reg8 |= 1; + pci_write_config8(dev, 0xe2, reg8); + } + } + + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO ); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Hide this device if possible */ + pch_hide_devfn(dev->path.pci.devfn); + } else { + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); + } +} + +struct chip_operations southbridge_intel_bd82x6x_ops = { + CHIP_NAME("Intel Series 6 (" CONFIG_PCH_CHIP_NAME ") Southbridge") + .enable_dev = pch_enable, +}; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h new file mode 100644 index 0000000..80b09e2 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -0,0 +1,514 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H +#define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H + +/* PCH stepping values for LPC device */ +#define PCH_STEP_A0 0 +#define PCH_STEP_A1 1 +#define PCH_STEP_B0 2 +#define PCH_STEP_B1 3 +#define PCH_STEP_B2 4 +#define PCH_STEP_B3 5 + +/* + * It does not matter where we put the SMBus I/O base, as long as we + * keep it consistent and don't interfere with other devices. Stage2 + * will relocate this anyways. + * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE + * again. But handling static BARs is a generic problem that should be + * solved in the device allocator. + */ +#define SMBUS_IO_BASE 0x0400 +#define SMBUS_SLAVE_ADDR 0x24 +/* TODO Make sure these don't get changed by stage2 */ +#define DEFAULT_GPIOBASE 0x0480 +#define DEFAULT_PMBASE 0x0500 + +#define HPET_ADDR 0xfed00000 +#define DEFAULT_RCBA 0xfed1c000 + +#ifndef __ACPI__ +#define DEBUG_PERIODIC_SMIS 0 + +#if defined (__SMM__) && !defined(__ASSEMBLER__) +void intel_pch_finalize_smm(void); +#endif + +#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +#if !defined(__PRE_RAM__) && !defined(__SMM__) +#include "chip.h" +int pch_silicon_revision(void); +void pch_enable(device_t dev); +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +#else +void enable_smbus(void); +void enable_usb_bar(void); +int smbus_read_byte(unsigned device, unsigned address); +#endif +#endif + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + +/* PCI Configuration Space (D30:F0): PCI2PCI */ +#define PSTS 0x06 +#define SMLT 0x1b +#define SECSTS 0x1e +#define INTR 0x3c +#define BCTRL 0x3e +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0) + +#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) +#define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) +#define PCH_ME_DEV PCI_DEV(0, 0x16, 0) +#define PCH_PCIE_DEV_SLOT 28 + +/* PCI Configuration Space (D31:F0): LPC */ +#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) +#define SERIRQ_CNTL 0x64 + +#define GEN_PMCON_1 0xa0 +#define GEN_PMCON_2 0xa2 +#define GEN_PMCON_3 0xa4 +#define ETR3 0xac +#define ETR3_CWORWRE (1 << 18) +#define ETR3_CF9GR (1 << 20) + +/* GEN_PMCON_3 bits */ +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define BIOS_CNTL 0xDC +#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ +#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ +#define GPIO_ROUT 0xb8 + +#define PIRQA_ROUT 0x60 +#define PIRQB_ROUT 0x61 +#define PIRQC_ROUT 0x62 +#define PIRQD_ROUT 0x63 +#define PIRQE_ROUT 0x68 +#define PIRQF_ROUT 0x69 +#define PIRQG_ROUT 0x6A +#define PIRQH_ROUT 0x6B + +#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define LPC_EN 0x82 /* LPC IF Enables Register */ +#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ +#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ +#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ +#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ +#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ +#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ +#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ +#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ +#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ + +/* PCI Configuration Space (D31:F1): IDE */ +#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) +#define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) +#define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) +#define INTR_LN 0x3c +#define IDE_TIM_PRI 0x40 /* IDE timings, primary */ +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) +#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ + +#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ +#define IDE_SSDE1 (1 << 3) +#define IDE_SSDE0 (1 << 2) +#define IDE_PSDE1 (1 << 1) +#define IDE_PSDE0 (1 << 0) + +#define IDE_SDMA_TIM 0x4a + +#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0) + +#define SATA_SP 0xd0 /* Scratchpad */ + +/* PCI Configuration Space (D31:F3): SMBus */ +#define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3) +#define SMB_BASE 0x20 +#define HOSTC 0x40 +#define SMB_RCV_SLVA 0x09 + +/* HOSTC bits */ +#define I2C_EN (1 << 2) +#define SMB_SMI_EN (1 << 1) +#define HST_EN (1 << 0) + +/* SMBus I/O bits. */ +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +#define SMBUS_TIMEOUT (10 * 1000 * 100) + + +/* Southbridge IO BARs */ + +#define GPIOBASE 0x48 + +#define PMBASE 0x40 + +/* Root Complex Register Block */ +#define RCBA 0xf0 + +#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) +#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) +#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) + +#define RCBA_AND_OR(bits, x, and, or) \ + RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) +#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) +#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) +#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) +#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) + +#define VCH 0x0000 /* 32bit */ +#define VCAP1 0x0004 /* 32bit */ +#define VCAP2 0x0008 /* 32bit */ +#define PVC 0x000c /* 16bit */ +#define PVS 0x000e /* 16bit */ + +#define V0CAP 0x0010 /* 32bit */ +#define V0CTL 0x0014 /* 32bit */ +#define V0STS 0x001a /* 16bit */ + +#define V1CAP 0x001c /* 32bit */ +#define V1CTL 0x0020 /* 32bit */ +#define V1STS 0x0026 /* 16bit */ + +#define RCTCL 0x0100 /* 32bit */ +#define ESD 0x0104 /* 32bit */ +#define ULD 0x0110 /* 32bit */ +#define ULBA 0x0118 /* 64bit */ + +#define RP1D 0x0120 /* 32bit */ +#define RP1BA 0x0128 /* 64bit */ +#define RP2D 0x0130 /* 32bit */ +#define RP2BA 0x0138 /* 64bit */ +#define RP3D 0x0140 /* 32bit */ +#define RP3BA 0x0148 /* 64bit */ +#define RP4D 0x0150 /* 32bit */ +#define RP4BA 0x0158 /* 64bit */ +#define HDD 0x0160 /* 32bit */ +#define HDBA 0x0168 /* 64bit */ +#define RP5D 0x0170 /* 32bit */ +#define RP5BA 0x0178 /* 64bit */ +#define RP6D 0x0180 /* 32bit */ +#define RP6BA 0x0188 /* 64bit */ + +#define RPC 0x0224 /* 32bit */ +#define RPFN 0x0238 /* 32bit */ + +#define TRSR 0x1e00 /* 8bit */ +#define TRCR 0x1e10 /* 64bit */ +#define TWDR 0x1e18 /* 64bit */ + +#define IOTR0 0x1e80 /* 64bit */ +#define IOTR1 0x1e88 /* 64bit */ +#define IOTR2 0x1e90 /* 64bit */ +#define IOTR3 0x1e98 /* 64bit */ + +#define TCTL 0x3000 /* 8bit */ + +#define NOINT 0 +#define INTA 1 +#define INTB 2 +#define INTC 3 +#define INTD 4 + +#define DIR_IDR 12 /* Interrupt D Pin Offset */ +#define DIR_ICR 8 /* Interrupt C Pin Offset */ +#define DIR_IBR 4 /* Interrupt B Pin Offset */ +#define DIR_IAR 0 /* Interrupt A Pin Offset */ + +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +/* IO Buffer Programming */ +#define IOBPIRI 0x2330 +#define IOBPD 0x2334 +#define IOBPS 0x2338 +#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) +#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) +#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) + +#define D31IP 0x3100 /* 32bit */ +#define D31IP_TTIP 24 /* Thermal Throttle Pin */ +#define D31IP_SIP2 20 /* SATA Pin 2 */ +#define D31IP_SMIP 12 /* SMBUS Pin */ +#define D31IP_SIP 8 /* SATA Pin */ +#define D30IP 0x3104 /* 32bit */ +#define D30IP_PIP 0 /* PCI Bridge Pin */ +#define D29IP 0x3108 /* 32bit */ +#define D29IP_E1P 0 /* EHCI #1 Pin */ +#define D28IP 0x310c /* 32bit */ +#define D28IP_P8IP 28 /* PCI Express Port 8 */ +#define D28IP_P7IP 24 /* PCI Express Port 7 */ +#define D28IP_P6IP 20 /* PCI Express Port 6 */ +#define D28IP_P5IP 16 /* PCI Express Port 5 */ +#define D28IP_P4IP 12 /* PCI Express Port 4 */ +#define D28IP_P3IP 8 /* PCI Express Port 3 */ +#define D28IP_P2IP 4 /* PCI Express Port 2 */ +#define D28IP_P1IP 0 /* PCI Express Port 1 */ +#define D27IP 0x3110 /* 32bit */ +#define D27IP_ZIP 0 /* HD Audio Pin */ +#define D26IP 0x3114 /* 32bit */ +#define D26IP_E2P 0 /* EHCI #2 Pin */ +#define D25IP 0x3118 /* 32bit */ +#define D25IP_LIP 0 /* GbE LAN Pin */ +#define D22IP 0x3124 /* 32bit */ +#define D22IP_KTIP 12 /* KT Pin */ +#define D22IP_IDERIP 8 /* IDE-R Pin */ +#define D22IP_MEI2IP 4 /* MEI #2 Pin */ +#define D22IP_MEI1IP 0 /* MEI #1 Pin */ +#define D31IR 0x3140 /* 16bit */ +#define D30IR 0x3142 /* 16bit */ +#define D29IR 0x3144 /* 16bit */ +#define D28IR 0x3146 /* 16bit */ +#define D27IR 0x3148 /* 16bit */ +#define D26IR 0x314c /* 16bit */ +#define D25IR 0x3150 /* 16bit */ +#define D22IR 0x315c /* 16bit */ +#define OIC 0x31fe /* 16bit */ + +#define DIR_ROUTE(x,a,b,c,d) \ + RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ + ((b) << DIR_IBR) | ((a) << DIR_IAR)) + +#define RC 0x3400 /* 32bit */ +#define HPTC 0x3404 /* 32bit */ +#define GCS 0x3410 /* 32bit */ +#define BUC 0x3414 /* 32bit */ +#define PCH_DISABLE_GBE (1 << 5) +#define FD 0x3418 /* 32bit */ +#define DISPBDF 0x3424 /* 16bit */ +#define FD2 0x3428 /* 32bit */ +#define CG 0x341c /* 32bit */ + +/* Function Disable 1 RCBA 0x3418 */ +#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)|(1 << 27)) +#define PCH_DISABLE_P2P (1 << 1) +#define PCH_DISABLE_SATA1 (1 << 2) +#define PCH_DISABLE_SMBUS (1 << 3) +#define PCH_DISABLE_HD_AUDIO (1 << 4) +#define PCH_DISABLE_EHCI2 (1 << 13) +#define PCH_DISABLE_LPC (1 << 14) +#define PCH_DISABLE_EHCI1 (1 << 15) +#define PCH_DISABLE_PCIE(x) (1 << (16 + x)) +#define PCH_DISABLE_THERMAL (1 << 24) +#define PCH_DISABLE_SATA2 (1 << 25) + +/* Function Disable 2 RCBA 0x3428 */ +#define PCH_DISABLE_KT (1 << 4) +#define PCH_DISABLE_IDER (1 << 3) +#define PCH_DISABLE_MEI2 (1 << 2) +#define PCH_DISABLE_MEI1 (1 << 1) +#define PCH_ENABLE_DBDF (1 << 0) + +/* ICH7 GPIOBASE */ +#define GPIO_USE_SEL 0x00 +#define GP_IO_SEL 0x04 +#define GP_LVL 0x0c +#define GPO_BLINK 0x18 +#define GPI_INV 0x2c +#define GPIO_USE_SEL2 0x30 +#define GP_IO_SEL2 0x34 +#define GP_LVL2 0x38 +#define GPIO_USE_SEL3 0x40 +#define GP_IO_SEL3 0x44 +#define GP_LVL3 0x48 +#define GP_RST_SEL1 0x60 +#define GP_RST_SEL2 0x64 +#define GP_RST_SEL3 0x68 + +/* ICH7 PMBASE */ +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define PROC_CNT 0x10 +#define LV2 0x14 +#define LV3 0x15 +#define LV4 0x16 +#define PM2_CNT 0x50 // mobile only +#define GPE0_STS 0x20 +#define PME_B0_STS (1 << 13) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN 0x28 +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define SMI_EN 0x30 +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define SMI_STS 0x34 +#define ALT_GP_SMI_EN 0x38 +#define ALT_GP_SMI_STS 0x3a +#define GPE_CNTL 0x42 +#define DEVACT_STS 0x44 +#define SS_CNT 0x50 +#define C3_RES 0x54 + +/* + * SPI Opcode Menu setup for SPIBAR lockdown + * should support most common flash chips. + */ + +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x52 /* BE52: Block Erase 0x52 */ +#define SPI_OPTYPE_7 0x03 /* Write, address required */ + +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) + +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ + +#endif /* __ACPI__ */ +#endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */ diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c new file mode 100644 index 0000000..845a6fe --- /dev/null +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "pch.h" + +static void pci_init(struct device *dev) +{ + u16 reg16; + u8 reg8; + + printk(BIOS_DEBUG, "PCI init.\n"); + /* Enable Bus Master */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* This device has no interrupt */ + pci_write_config8(dev, INTR, 0xff); + + /* disable parity error response and SERR */ + reg16 = pci_read_config16(dev, BCTRL); + reg16 &= ~(1 << 0); + reg16 &= ~(1 << 1); + pci_write_config16(dev, BCTRL, reg16); + + /* Master Latency Count must be set to 0x04! */ + reg8 = pci_read_config8(dev, SMLT); + reg8 &= 0x07; + reg8 |= (0x04 << 3); + pci_write_config8(dev, SMLT, reg8); + + /* Will this improve throughput of bus masters? */ + pci_write_config8(dev, PCI_MIN_GNT, 0x06); + + /* Clear errors in status registers */ + reg16 = pci_read_config16(dev, PSTS); + //reg16 |= 0xf900; + pci_write_config16(dev, PSTS, reg16); + + reg16 = pci_read_config16(dev, SECSTS); + // reg16 |= 0xf900; + pci_write_config16(dev, SECSTS, reg16); +} + +#undef PCI_BRIDGE_UPDATE_COMMAND +static void ich_pci_dev_enable_resources(struct device *dev) +{ + const struct pci_operations *ops; + uint16_t command; + + /* Set the subsystem vendor and device id for mainboard devices */ + ops = ops_pci(dev); + if (dev->on_mainboard && ops && ops->set_subsystem) { + printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n", + dev_path(dev), + CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); + ops->set_subsystem(dev, + CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); + } + + command = pci_read_config16(dev, PCI_COMMAND); + command |= dev->command; +#ifdef PCI_BRIDGE_UPDATE_COMMAND + /* If we write to PCI_COMMAND, on some systems + * this will cause the ROM and APICs not being visible + * anymore. + */ + printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command); + pci_write_config16(dev, PCI_COMMAND, command); +#else + printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); +#endif +} + +static void ich_pci_bus_enable_resources(struct device *dev) +{ + uint16_t ctrl; + /* enable IO in command register if there is VGA card + * connected with (even it does not claim IO resource) + */ + if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) + dev->command |= PCI_COMMAND_IO; + ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + ctrl |= dev->link_list->bridge_ctrl; + ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */ + printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); + pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); + + /* This is the reason we need our own pci_bus_enable_resources */ + ich_pci_dev_enable_resources(dev); +} + +static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + /* NOTE: This is not the default position! */ + if (!vendor || !device) { + pci_write_config32(dev, 0x54, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, 0x54, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations pci_ops = { + .set_subsystem = set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = ich_pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, + .ops_pci = &pci_ops, +}; + +static const struct pci_driver pch_pci __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2448, +}; diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c new file mode 100644 index 0000000..599692d --- /dev/null +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -0,0 +1,306 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_ids.h> +#include "pch.h" + +static u16 pcie_port_link_width(int port) +{ + u16 link_width; + + link_width = pci_read_config16( + dev_find_slot(0, PCI_DEVFN(0x1c, port)), 0x52); + link_width >>= 4; + link_width &= 0x3f; + return link_width; +} + +static void pch_pcie_pm_early(struct device *dev) +{ + u16 link_width_p0, link_width_p4; + u8 slot_power_limit = 10; /* 10W for x1 */ + u32 reg32; + u8 reg8; + + link_width_p0 = pcie_port_link_width(0); + link_width_p4 = pcie_port_link_width(4); + + /* Enable dynamic clock gating where needed */ + reg8 = pci_read_config8(dev, 0xe1); + switch (PCI_FUNC(dev->path.pci.devfn)) { + case 0: /* Port 0 */ + if (link_width_p0 == 4) + slot_power_limit = 40; /* 40W for x4 */ + else if (link_width_p0 == 2) + slot_power_limit = 20; /* 20W for x2 */ + case 4: /* Port 4 */ + if (link_width_p4 == 4) + slot_power_limit = 40; /* 40W for x4 */ + else if (link_width_p4 == 2) + slot_power_limit = 20; /* 20W for x2 */ + reg8 |= 0x3f; + break; + case 1: /* Port 1 only if Port 0 is x1 */ + if (link_width_p0 == 1) + reg8 |= 0x3; + break; + case 2: /* Port 2 only if Port 0 is x1 or x2 */ + case 3: /* Port 3 only if Port 0 is x1 or x2 */ + if (link_width_p0 <= 2) + reg8 |= 0x3; + break; + case 5: /* Port 5 only if Port 4 is x1 */ + if (link_width_p4 == 1) + reg8 |= 0x3; + break; + case 6: /* Port 7 only if Port 4 is x1 or x2 */ + case 7: /* Port 7 only if Port 4 is x1 or x2 */ + if (link_width_p4 <= 2) + reg8 |= 0x3; + break; + } + pci_write_config8(dev, 0xe1, reg8); + + /* Set 0xE8[0] = 1 */ + reg32 = pci_read_config32(dev, 0xe8); + reg32 |= 1; + pci_write_config32(dev, 0xe8, reg32); + + /* Adjust Common Clock exit latency */ + reg32 = pci_read_config32(dev, 0xd8); + reg32 &= ~(1 << 17); + reg32 |= (1 << 16) | (1 << 15); + reg32 &= ~(1 << 31); /* Disable PME# SCI for native PME handling */ + pci_write_config32(dev, 0xd8, reg32); + + /* Adjust ASPM L1 exit latency */ + reg32 = pci_read_config32(dev, 0x4c); + reg32 &= ~((1 << 17) | (1 << 16) | (1 << 15)); + if (RCBA32(0x2320) & (1 << 16)) { + /* If RCBA+2320[15]=1 set ASPM L1 to 8-16us */ + reg32 |= (1 << 17); + } else { + /* Else set ASPM L1 to 2-4us */ + reg32 |= (1 << 16); + } + pci_write_config32(dev, 0x4c, reg32); + + /* Set slot power limit as configured above */ + reg32 = pci_read_config32(dev, 0x54); + reg32 &= ~((1 << 15) | (1 << 16)); /* 16:15 = Slot power scale */ + reg32 &= ~(0xff << 7); /* 14:7 = Slot power limit */ + reg32 |= (slot_power_limit << 7); + pci_write_config32(dev, 0x54, reg32); +} + +static void pch_pcie_pm_late(struct device *dev) +{ + enum aspm_type apmc; + u32 reg32; + + /* Set 0x314 = 0x743a361b */ + pci_mmio_write_config32(dev, 0x314, 0x743a361b); + + /* Set 0x318[31:16] = 0x1414 */ + reg32 = pci_mmio_read_config32(dev, 0x318); + reg32 &= 0x0000ffff; + reg32 |= 0x14140000; + pci_mmio_write_config32(dev, 0x318, reg32); + + /* Set 0x324[5] = 1 */ + reg32 = pci_mmio_read_config32(dev, 0x324); + reg32 |= (1 << 5); + pci_mmio_write_config32(dev, 0x324, reg32); + + /* Set 0x330[7:0] = 0x40 */ + reg32 = pci_mmio_read_config32(dev, 0x330); + reg32 &= ~(0xff); + reg32 |= 0x40; + pci_mmio_write_config32(dev, 0x330, reg32); + + /* Set 0x33C[24:0] = 0x854c74 */ + reg32 = pci_mmio_read_config32(dev, 0x33c); + reg32 &= 0xff000000; + reg32 |= 0x00854c74; + pci_mmio_write_config32(dev, 0x33c, reg32); + + /* No IO-APIC, Disable EOI forwarding */ + reg32 = pci_read_config32(dev, 0xd4); + reg32 |= (1 << 1); + pci_write_config32(dev, 0xd4, reg32); + + /* Get configured ASPM state */ + apmc = pci_read_config32(dev, 0x50) & 3; + + /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */ + if (apmc == PCIE_ASPM_BOTH) { + reg32 = pci_read_config32(dev, 0xe8); + reg32 |= (1 << 1); + pci_write_config32(dev, 0xe8, reg32); + } +} + +static void pci_init(struct device *dev) +{ + u16 reg16; + u32 reg32; + + printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); + + /* Enable Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Set Cache Line Size to 0x10 */ + // This has no effect but the OS might expect it + pci_write_config8(dev, 0x0c, 0x10); + + reg16 = pci_read_config16(dev, 0x3e); + reg16 &= ~(1 << 0); /* disable parity error response */ + // reg16 &= ~(1 << 1); /* disable SERR */ + reg16 |= (1 << 2); /* ISA enable */ + pci_write_config16(dev, 0x3e, reg16); + +#ifdef EVEN_MORE_DEBUG + reg32 = pci_read_config32(dev, 0x20); + printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); + reg32 = pci_read_config32(dev, 0x24); + printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); + reg32 = pci_read_config32(dev, 0x28); + printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); + reg32 = pci_read_config32(dev, 0x2c); + printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); +#endif + + /* Clear errors in status registers */ + reg16 = pci_read_config16(dev, 0x06); + //reg16 |= 0xf900; + pci_write_config16(dev, 0x06, reg16); + + reg16 = pci_read_config16(dev, 0x1e); + //reg16 |= 0xf900; + pci_write_config16(dev, 0x1e, reg16); + + /* Power Management init after enumeration */ + pch_pcie_pm_late(dev); +} + +static void pch_pcie_enable(device_t dev) +{ + /* Power Management init before enumeration */ + pch_pcie_pm_early(dev); +} + +static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + /* NOTE: This is not the default position! */ + if (!vendor || !device) { + pci_write_config32(dev, 0x94, + pci_read_config32(dev, 0)); + } else { + pci_write_config32(dev, 0x94, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations pci_ops = { + .set_subsystem = pcie_set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .enable = pch_pcie_enable, + .scan_bus = pciexp_scan_bridge, + .ops_pci = &pci_ops, +}; + +static const struct pci_driver pch_pcie_port1 __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c10, /* D28:F0 */ +}; + +static const struct pci_driver pch_pcie_port1_a __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e10, /* D28:F0 */ +}; + +static const struct pci_driver pch_pcie_port2 __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c12, /* D28:F1 */ +}; + +static const struct pci_driver pch_pcie_port3 __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c14, /* D28:F2 */ +}; + +static const struct pci_driver pch_pcie_port3_a __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e14, /* D28:F2 */ +}; + +static const struct pci_driver pch_pcie_port4 __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c16, /* D28:F3 */ +}; + +static const struct pci_driver pch_pcie_port4_a __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e16, /* D28:F3 */ +}; + +static const struct pci_driver pch_pcie_port5 __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c18, /* D28:F4 */ +}; + +static const struct pci_driver pch_pcie_port6 __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c1a, /* D28:F5 */ +}; + +static const struct pci_driver pch_pcie_port7 __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c1c, /* D28:F6 */ +}; + +static const struct pci_driver pch_pcie_port8 __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c1e, /* D28:F7 */ +}; diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c new file mode 100644 index 0000000..29b69ff --- /dev/null +++ b/src/southbridge/intel/bd82x6x/reset.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <reset.h> + +void soft_reset(void) +{ + outb(0x04, 0xcf9); +} + +#if 0 +void hard_reset(void) +{ + /* Try rebooting through port 0xcf9. */ + outb((1 << 2) | (1 << 1), 0xcf9); +} +#endif + +void hard_reset(void) +{ + outb(0x02, 0xcf9); + outb(0x06, 0xcf9); +} diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c new file mode 100644 index 0000000..057b882 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -0,0 +1,246 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "pch.h" + +typedef struct southbridge_intel_bd82x6x_config config_t; + +static void sata_init(struct device *dev) +{ + u32 reg32; + u16 reg16; + /* Get the chip configuration */ + config_t *config = dev->chip_info; + + printk(BIOS_DEBUG, "pch_sata: initializing...\n"); + + if (config == NULL) { + printk(BIOS_ERR, "pch_sata: error: device not in devicetree.cb!\n"); + return; + } + + /* SATA configuration */ + + /* Enable BARs */ + pci_write_config16(dev, PCI_COMMAND, 0x0007); + + if (config->ide_legacy_combined) { + printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); + /* Combine IDE - SATA configuration */ + pci_write_config16(dev, 0x90, 0x0000); + + /* No AHCI: clear AHCI base */ + pci_write_config32(dev, 0x24, 0x00000000); + /* And without AHCI BAR no memory decoding */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); + + pci_write_config8(dev, 0x09, 0x80); + + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | + IDE_PPE0 | IDE_IE0 | IDE_TIME0); + + /* Sync DMA */ + pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); + pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); + + /* Set IDE I/O Configuration */ + reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + pci_write_config32(dev, IDE_CONFIG, reg32); + + /* Port enable */ + reg16 = pci_read_config16(dev, 0x92); + reg16 &= ~0x3f; + reg16 |= config->sata_port_map; + pci_write_config16(dev, 0x92, reg16); + + /* SATA Initialization register */ + pci_write_config32(dev, 0x94, + ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + } else if(config->sata_ahci) { + u32 abar; + + printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); + /* Set Sata Controller Mode. */ + pci_write_config16(dev, 0x90, 0x0060 | + ((config->sata_port_map ^ 0x3f) << 8)); + + /* Set Interrupt Line */ + /* Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, INTR_LN, 0x0a); + + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | + IDE_PPE0 | IDE_IE0 | IDE_TIME0); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); + + /* Sync DMA */ + pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); + pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); + + /* Set IDE I/O Configuration */ + reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + pci_write_config32(dev, IDE_CONFIG, reg32); + + /* for AHCI, Port Enable is managed in memory mapped space */ + reg16 = pci_read_config16(dev, 0x92); + reg16 &= ~0x3f; /* 6 ports SKU + ORM */ + reg16 |= 0x8000 | config->sata_port_map; + pci_write_config16(dev, 0x92, reg16); + + /* SATA Initialization register */ + pci_write_config32(dev, 0x94, + ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + + /* Initialize AHCI memory-mapped space */ + abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "ABAR: %08X\n", abar); + /* CAP (HBA Capabilities) : enable power management */ + reg32 = read32(abar + 0x00); + reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS + reg32 &= ~0x00020060; // clear SXS+EMS+PMS + write32(abar + 0x00, reg32); + /* PI (Ports implemented) */ + write32(abar + 0x0c, config->sata_port_map); + (void) read32(abar + 0x0c); /* Read back 1 */ + (void) read32(abar + 0x0c); /* Read back 2 */ + /* CAP2 (HBA Capabilities Extended)*/ + reg32 = read32(abar + 0x24); + reg32 &= ~0x00000002; + write32(abar + 0x24, reg32); + /* VSP (Vendor Specific Register */ + reg32 = read32(abar + 0xa0); + reg32 &= ~0x00000005; + write32(abar + 0xa0, reg32); + } else { + printk(BIOS_DEBUG, "SATA controller in plain mode.\n"); + /* Set Sata Controller Mode. No Mapping(?) */ + pci_write_config16(dev, 0x90, 0x0000); + + /* No AHCI: clear AHCI base */ + pci_write_config32(dev, 0x24, 0x00000000); + + /* And without AHCI BAR no memory decoding */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* Native mode capable on both primary and secondary (0xa) + * or'ed with enabled (0x50) = 0xf + */ + pci_write_config8(dev, 0x09, 0x8f); + + /* Set Interrupt Line */ + /* Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, INTR_LN, 0xff); + + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | + IDE_PPE0 | IDE_IE0 | IDE_TIME0); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + IDE_SITRE | IDE_ISP_3_CLOCKS | + IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); + + /* Sync DMA */ + pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); + pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); + + /* Set IDE I/O Configuration */ + reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + pci_write_config32(dev, IDE_CONFIG, reg32); + + /* Port enable */ + reg16 = pci_read_config16(dev, 0x92); + reg16 &= ~0x3f; + reg16 |= config->sata_port_map; + pci_write_config16(dev, 0x92, reg16); + + /* SATA Initialization register */ + pci_write_config32(dev, 0x94, + ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + } +} + +static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations sata_pci_ops = { + .set_subsystem = sata_set_subsystem, +}; + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .scan_bus = 0, + .ops_pci = &sata_pci_ops, +}; + +/* Non-AHCI and Non-RAID Mode */ +static const struct pci_driver pch_sata_normal_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c00, +}; +static const struct pci_driver pch_sata_mobile_normal_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c01, +}; + +/* AHCI Mode */ +static const struct pci_driver pch_sata_ahci_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c02, +}; +static const struct pci_driver pch_sata_mobile_ahci_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c03, +}; +static const struct pci_driver pch_sata_mobile_ahci_driver_a __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e03, +}; + diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c new file mode 100644 index 0000000..baa3cfb --- /dev/null +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <device/smbus.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include "pch.h" +#include "smbus.h" + +static void pch_smbus_init(device_t dev) +{ + struct resource *res; + u16 reg16; + + /* Enable clock gating */ + reg16 = pci_read_config32(dev, 0x80); + reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); + pci_write_config32(dev, 0x80, reg16); + + /* Set Receive Slave Address */ + res = find_resource(dev, PCI_BASE_ADDRESS_4); + if (res) + outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); +} + +static int lsmbus_read_byte(device_t dev, u8 address) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x20); + + return do_smbus_read_byte(res->base, device, address); +} + +static struct smbus_bus_operations lops_smbus_bus = { + .read_byte = lsmbus_read_byte, +}; + +static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations smbus_pci_ops = { + .set_subsystem = smbus_set_subsystem, +}; + +static void smbus_read_resources(device_t dev) +{ + struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); + res->base = SMBUS_IO_BASE; + res->size = 32; + res->limit = res->base + res->size - 1; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Also add MMIO resource */ + res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); +} + +static struct device_operations smbus_ops = { + .read_resources = smbus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = scan_static_bus, + .init = pch_smbus_init, + .ops_smbus_bus = &lops_smbus_bus, + .ops_pci = &smbus_pci_ops, +}; + +static const struct pci_driver pch_smbus __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c22, +}; + +static const struct pci_driver pch_smbus_a __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e22, +}; diff --git a/src/southbridge/intel/bd82x6x/smbus.h b/src/southbridge/intel/bd82x6x/smbus.h new file mode 100644 index 0000000..f2f7f60 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/smbus.h @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Yinghai Lu <yinghailu(a)gmail.com> + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/smbus_def.h> +#include "pch.h" + +static void smbus_delay(void) +{ + inb(0x80); +} + +static int smbus_wait_until_ready(u16 smbus_base) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(smbus_base + SMBHSTSTAT); + } while (byte & 1); + return loops ? 0 : -1; +} + +static int smbus_wait_until_done(u16 smbus_base) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(smbus_base + SMBHSTSTAT); + } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); + return loops ? 0 : -1; +} + +static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; + + if (smbus_wait_until_ready(smbus_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Clear the data byte... */ + outb(0, smbus_base + SMBHSTDAT0); + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done(smbus_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inb(smbus_base + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + byte = inb(smbus_base + SMBHSTDAT0); + if (global_status_register != (1 << 1)) { + return SMBUS_ERROR; + } + return byte; +} + diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c new file mode 100644 index 0000000..da10840 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/smi.c @@ -0,0 +1,403 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <arch/io.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/smm.h> +#include <string.h> +#include "pch.h" + +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE +#include "northbridge/intel/sandybridge/sandybridge.h" +#endif + +extern unsigned char _binary_smm_start; +extern unsigned char _binary_smm_size; + +/* While we read PMBASE dynamically in case it changed, let's + * initialize it with a sane value + */ +static u16 pmbase = DEFAULT_PMBASE; + +/** + * @brief read and clear PM1_STS + * @return PM1_STS register + */ +static u16 reset_pm1_status(void) +{ + u16 reg16; + + reg16 = inw(pmbase + PM1_STS); + /* set status bits are cleared by writing 1 to them */ + outw(reg16, pmbase + PM1_STS); + + return reg16; +} + +static void dump_pm1_status(u16 pm1_sts) +{ + printk(BIOS_DEBUG, "PM1_STS: "); + if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK "); + if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK "); + if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR "); + if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC "); + if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN "); + if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL "); + if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM "); + if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF "); + printk(BIOS_DEBUG, "\n"); +} + +/** + * @brief read and clear SMI_STS + * @return SMI_STS register + */ +static u32 reset_smi_status(void) +{ + u32 reg32; + + reg32 = inl(pmbase + SMI_STS); + /* set status bits are cleared by writing 1 to them */ + outl(reg32, pmbase + SMI_STS); + + return reg32; +} + +static void dump_smi_status(u32 smi_sts) +{ + printk(BIOS_DEBUG, "SMI_STS: "); + if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); + if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); + if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); + if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); + if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); + if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); + if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); + if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); + if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); + if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); + if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); + if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); + if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); + if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); + if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); + if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); + if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); + if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); + if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); + if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); + printk(BIOS_DEBUG, "\n"); +} + + +/** + * @brief read and clear GPE0_STS + * @return GPE0_STS register + */ +static u32 reset_gpe0_status(void) +{ + u32 reg32; + + reg32 = inl(pmbase + GPE0_STS); + /* set status bits are cleared by writing 1 to them */ + outl(reg32, pmbase + GPE0_STS); + + return reg32; +} + +static void dump_gpe0_status(u32 gpe0_sts) +{ + int i; + printk(BIOS_DEBUG, "GPE0_STS: "); + for (i=31; i<= 16; i--) { + if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); + } + if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); + if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); + if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); + if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); + if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); + if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); + if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); + if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); + if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); + if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); + if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); + if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); + if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG "); + if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); + printk(BIOS_DEBUG, "\n"); +} + + +/** + * @brief read and clear ALT_GP_SMI_STS + * @return ALT_GP_SMI_STS register + */ +static u16 reset_alt_gp_smi_status(void) +{ + u16 reg16; + + reg16 = inl(pmbase + ALT_GP_SMI_STS); + /* set status bits are cleared by writing 1 to them */ + outl(reg16, pmbase + ALT_GP_SMI_STS); + + return reg16; +} + +static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) +{ + int i; + printk(BIOS_DEBUG, "ALT_GP_SMI_STS: "); + for (i=15; i<= 0; i--) { + if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", (i-16)); + } + printk(BIOS_DEBUG, "\n"); +} + + + +/** + * @brief read and clear TCOx_STS + * @return TCOx_STS registers + */ +static u32 reset_tco_status(void) +{ + u32 tcobase = pmbase + 0x60; + u32 reg32; + + reg32 = inl(tcobase + 0x04); + /* set status bits are cleared by writing 1 to them */ + outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS + if (reg32 & (1 << 18)) + outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS + + return reg32; +} + + +static void dump_tco_status(u32 tco_sts) +{ + printk(BIOS_DEBUG, "TCO_STS: "); + if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); + if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); + if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); + if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); + if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); + if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); + if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); + if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); + if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); + if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); + if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); + if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); + if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); + printk(BIOS_DEBUG, "\n"); +} + + + +/** + * @brief Set the EOS bit + */ +static void smi_set_eos(void) +{ + u8 reg8; + + reg8 = inb(pmbase + SMI_EN); + reg8 |= EOS; + outb(reg8, pmbase + SMI_EN); +} + +extern uint8_t smm_relocation_start, smm_relocation_end; + +static void smm_relocate(void) +{ + u32 smi_en; + u16 pm1_en; + u32 gpe0_en; + + printk(BIOS_DEBUG, "Initializing SMM handler..."); + + pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + PMBASE) & 0xff80; + + printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); + + smi_en = inl(pmbase + SMI_EN); + if (smi_en & APMC_EN) { + printk(BIOS_INFO, "SMI# handler already enabled?\n"); + return; + } + + /* copy the SMM relocation code */ + memcpy((void *)0x38000, &smm_relocation_start, + &smm_relocation_end - &smm_relocation_start); + + printk(BIOS_DEBUG, "\n"); + dump_smi_status(reset_smi_status()); + dump_pm1_status(reset_pm1_status()); + dump_gpe0_status(reset_gpe0_status()); + dump_alt_gp_smi_status(reset_alt_gp_smi_status()); + dump_tco_status(reset_tco_status()); + + /* Disable GPE0 PME_B0 */ + gpe0_en = inl(pmbase + GPE0_EN); + gpe0_en &= ~PME_B0_EN; + outl(gpe0_en, pmbase + GPE0_EN); + + /* Enable SMI generation: + * - on TCO events + * - on APMC writes (io 0xb2) + * - on writes to SLP_EN (sleep states) + * - on writes to GBL_RLS (bios commands) + * No SMIs: + * - on microcontroller writes (io 0x62/0x66) + */ + + smi_en = 0; /* reset SMI enables */ + +#if 0 + smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; +#endif + smi_en |= TCO_EN; + smi_en |= APMC_EN; +#if DEBUG_PERIODIC_SMIS + /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using + * periodic SMIs. + */ + smi_en |= PERIODIC_EN; +#endif + smi_en |= SLP_SMI_EN; +#if 0 + smi_en |= BIOS_EN; +#endif + + /* The following need to be on for SMIs to happen */ + smi_en |= EOS | GBL_SMI_EN; + + outl(smi_en, pmbase + SMI_EN); + + pm1_en = 0; + pm1_en |= PWRBTN_EN; + pm1_en |= GBL_EN; + outw(pm1_en, pmbase + PM1_EN); + + /** + * There are several methods of raising a controlled SMI# via + * software, among them: + * - Writes to io 0xb2 (APMC) + * - Writes to the Local Apic ICR with Delivery mode SMI. + * + * Using the local apic is a bit more tricky. According to + * AMD Family 11 Processor BKDG no destination shorthand must be + * used. + * The whole SMM initialization is quite a bit hardware specific, so + * I'm not too worried about the better of the methods at the moment + */ + + /* raise an SMI interrupt */ + printk(BIOS_SPEW, " ... raise SMI#\n"); + outb(0x00, 0xb2); +} + +static int smm_handler_copied = 0; + +static void smm_install(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + u32 smm_base = 0xa0000; + struct ied_header ied = { + .signature = "INTEL RSVD", + .size = IED_SIZE, + .reserved = {0}, + }; + + /* The first CPU running this gets to copy the SMM handler. But not all + * of them. + */ + if (smm_handler_copied) + return; + smm_handler_copied = 1; + + /* enable the SMM memory window */ + pci_write_config8(dev, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); + +#if CONFIG_SMM_TSEG + smm_base = pci_read_config32(dev, TSEG) & ~1; +#endif + + /* copy the real SMM handler */ + printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base); + memcpy((void *)smm_base, &_binary_smm_start, (size_t)&_binary_smm_size); + + /* copy the IED header into place */ + if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) { + /* Top of TSEG region */ + smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE; + printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n", + smm_base); + memcpy((void *)smm_base, &ied, sizeof(ied)); + } + wbinvd(); + + /* close the SMM memory window and enable normal SMM */ + pci_write_config8(dev, SMRAM, G_SMRAME | C_BASE_SEG); +} + +void smm_init(void) +{ + /* Put SMM code to 0xa0000 */ + smm_install(); + + /* Put relocation code to 0x38000 and relocate SMBASE */ + smm_relocate(); + + /* We're done. Make sure SMIs can happen! */ + smi_set_eos(); +} + +void smm_lock(void) +{ + /* LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + D_LCK | G_SMRAME | C_BASE_SEG); +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1) +{ + /* The GDT or coreboot table is going to live here. But a long time + * after we relocated the GNVS, so this is not troublesome. + */ + *(u32 *)0x500 = (u32)gnvs; + *(u32 *)0x504 = (u32)tcg; + *(u32 *)0x508 = (u32)smi1; + outb(0xea, 0xb2); +} diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c new file mode 100644 index 0000000..e311d95 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -0,0 +1,709 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <types.h> +#include <arch/hlt.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/smm.h> +#include <device/pci_def.h> +#include <cpu/x86/smm.h> +#include "pch.h" + +#include "nvs.h" + +/* While we read PMBASE dynamically in case it changed, let's + * initialize it with a sane value + */ +u16 pmbase = DEFAULT_PMBASE; +u8 smm_initialized = 0; + +/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located + * by coreboot. + */ +global_nvs_t *gnvs = (global_nvs_t *)0x0; +void *tcg = (void *)0x0; +void *smi1 = (void *)0x0; + +#if CONFIG_SMM_TSEG +static u32 tseg_base = 0; +static inline void tseg_fixup(void **ptr) +{ + /* Adjust pointer with TSEG base */ + if (*ptr) + *ptr = (void *)(((u8*)*ptr) + tseg_base); +} +#else +#define tseg_fixup(x) do {} while(0) +#endif + +/** + * @brief read and clear PM1_STS + * @return PM1_STS register + */ +static u16 reset_pm1_status(void) +{ + u16 reg16; + + reg16 = inw(pmbase + PM1_STS); + /* set status bits are cleared by writing 1 to them */ + outw(reg16, pmbase + PM1_STS); + + return reg16; +} + +static void dump_pm1_status(u16 pm1_sts) +{ + printk(BIOS_SPEW, "PM1_STS: "); + if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK "); + if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK "); + if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR "); + if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC "); + if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN "); + if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL "); + if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM "); + if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF "); + printk(BIOS_SPEW, "\n"); + int reg16 = inw(pmbase + PM1_EN); + printk(BIOS_SPEW, "PM1_EN: %x\n", reg16); +} + +/** + * @brief read and clear SMI_STS + * @return SMI_STS register + */ +static u32 reset_smi_status(void) +{ + u32 reg32; + + reg32 = inl(pmbase + SMI_STS); + /* set status bits are cleared by writing 1 to them */ + outl(reg32, pmbase + SMI_STS); + + return reg32; +} + +static void dump_smi_status(u32 smi_sts) +{ + printk(BIOS_DEBUG, "SMI_STS: "); + if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); + if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); + if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); + if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); + if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); + if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); + if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); + if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); + if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); + if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); + if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); + if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); + if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); + if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); + if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); + if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); + if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); + if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); + if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); + printk(BIOS_DEBUG, "\n"); +} + + +/** + * @brief read and clear GPE0_STS + * @return GPE0_STS register + */ +static u32 reset_gpe0_status(void) +{ + u32 reg32; + + reg32 = inl(pmbase + GPE0_STS); + /* set status bits are cleared by writing 1 to them */ + outl(reg32, pmbase + GPE0_STS); + + return reg32; +} + +static void dump_gpe0_status(u32 gpe0_sts) +{ + int i; + printk(BIOS_DEBUG, "GPE0_STS: "); + for (i=31; i<= 16; i--) { + if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); + } + if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); + if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); + if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); + if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); + if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "BATLOW "); + if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); + if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); + if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); + if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); + if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); + if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); + if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); + if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE "); + if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOTPLUG "); + if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); + printk(BIOS_DEBUG, "\n"); +} + + +/** + * @brief read and clear TCOx_STS + * @return TCOx_STS registers + */ +static u32 reset_tco_status(void) +{ + u32 tcobase = pmbase + 0x60; + u32 reg32; + + reg32 = inl(tcobase + 0x04); + /* set status bits are cleared by writing 1 to them */ + outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS + if (reg32 & (1 << 18)) + outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS + + return reg32; +} + + +static void dump_tco_status(u32 tco_sts) +{ + printk(BIOS_DEBUG, "TCO_STS: "); + if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); + if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); + if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); + if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); + if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); + if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); + if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); + if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); + if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); + if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); + if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); + if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); + if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); + printk(BIOS_DEBUG, "\n"); +} + +/* We are using PCIe accesses for now + * 1. the chipset can do it + * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind + */ +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/pcie_config.c> + +int southbridge_io_trap_handler(int smif) +{ + switch (smif) { + case 0x32: + printk(BIOS_DEBUG, "OS Init\n"); + /* gnvs->smif: + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + */ + gnvs->smif = 0; + return 1; /* IO trap handled */ + } + + /* Not handled */ + return 0; +} + +/** + * @brief Set the EOS bit + */ +void southbridge_smi_set_eos(void) +{ + u8 reg8; + + reg8 = inb(pmbase + SMI_EN); + reg8 |= EOS; + outb(reg8, pmbase + SMI_EN); +} + +static void busmaster_disable_on_bus(int bus) +{ + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } +} + +/* + * Drive GPIO 60 low to gate memory reset in S3. + * + * Intel reference designs all use GPIO 60 but it is + * not a requirement and boards could use a different pin. + */ +static void southbridge_gate_memory_reset(void) +{ + u32 reg32; + u16 gpiobase; + + gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; + if (!gpiobase) + return; + + /* Make sure it is set as GPIO */ + reg32 = inl(gpiobase + GPIO_USE_SEL2); + if (!(reg32 & (1 << 28))) { + reg32 |= (1 << 28); + outl(reg32, gpiobase + GPIO_USE_SEL2); + } + + /* Make sure it is set as output */ + reg32 = inl(gpiobase + GP_IO_SEL2); + if (reg32 & (1 << 28)) { + reg32 &= ~(1 << 28); + outl(reg32, gpiobase + GP_IO_SEL2); + } + + /* Drive the output low */ + reg32 = inl(gpiobase + GP_LVL2); + reg32 &= ~(1 << 28); + outl(reg32, gpiobase + GP_LVL2); +} + +static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) +{ + u8 reg8; + u32 reg32; + u8 slp_typ; + /* FIXME: the power state on boot should be read from + * CMOS or even better from GNVS. Right now it's hard + * coded at compile time. + */ + u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep; + + /* First, disable further SMIs */ + reg8 = inb(pmbase + SMI_EN); + reg8 &= ~SLP_SMI_EN; + outb(reg8, pmbase + SMI_EN); + + /* Figure out SLP_TYP */ + reg32 = inl(pmbase + PM1_CNT); + printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); + slp_typ = (reg32 >> 10) & 7; + + /* Do any mainboard sleep handling */ + tseg_fixup((void **)&mainboard_sleep); + if (mainboard_sleep) + mainboard_sleep(slp_typ); + + /* Next, do the deed. + */ + + switch (slp_typ) { + case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break; + case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break; + case 5: + printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); + + /* Gate memory reset */ + southbridge_gate_memory_reset(); + + /* Invalidate the cache before going to S3 */ + wbinvd(); + break; + case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break; + case 7: + printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + + outl(0, pmbase + GPE0_EN); + + /* Should we keep the power state after a power loss? + * In case the setting is "ON" or "OFF" we don't have + * to do anything. But if it's "KEEP" we have to switch + * to "OFF" before entering S5. + */ + if (s5pwr == MAINBOARD_POWER_KEEP) { + reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 |= 1; + pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + } + + /* also iterates over all bridges on bus 0 */ + busmaster_disable_on_bus(0); + break; + default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; + } + + /* Write back to the SLP register to cause the originally intended + * event again. We need to set BIT13 (SLP_EN) though to make the + * sleep happen. + */ + outl(reg32 | SLP_EN, pmbase + PM1_CNT); + + /* Make sure to stop executing code here for S3/S4/S5 */ + if (slp_typ > 1) + hlt(); + + /* In most sleep states, the code flow of this function ends at + * the line above. However, if we entered sleep state S1 and wake + * up again, we will continue to execute code in this function. + */ + reg32 = inl(pmbase + PM1_CNT); + if (reg32 & SCI_EN) { + /* The OS is not an ACPI OS, so we set the state to S0 */ + reg32 &= ~(SLP_EN | SLP_TYP); + outl(reg32, pmbase + PM1_CNT); + } +} + +static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save) +{ + u32 pmctrl; + u8 reg8; + void (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc; + + /* Emulate B2 register as the FADT / Linux expects it */ + + reg8 = inb(APM_CNT); + switch (reg8) { + case APM_CNT_CST_CONTROL: + /* Calling this function seems to cause + * some kind of race condition in Linux + * and causes a kernel oops + */ + printk(BIOS_DEBUG, "C-state control\n"); + break; + case APM_CNT_PST_CONTROL: + /* Calling this function seems to cause + * some kind of race condition in Linux + * and causes a kernel oops + */ + printk(BIOS_DEBUG, "P-state control\n"); + break; + case APM_CNT_ACPI_DISABLE: + pmctrl = inl(pmbase + PM1_CNT); + pmctrl &= ~SCI_EN; + outl(pmctrl, pmbase + PM1_CNT); + printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); + break; + case APM_CNT_ACPI_ENABLE: + pmctrl = inl(pmbase + PM1_CNT); + pmctrl |= SCI_EN; + outl(pmctrl, pmbase + PM1_CNT); + printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); + break; + case APM_CNT_GNVS_UPDATE: + if (smm_initialized) { + printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); + return; + } + gnvs = *(global_nvs_t **)0x500; + tcg = *(void **)0x504; + smi1 = *(void **)0x508; + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1); + break; + } + + tseg_fixup((void **)&mainboard_apmc); + if (mainboard_apmc) + mainboard_apmc(reg8); +} + +static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) +{ + u16 pm1_sts; + + pm1_sts = reset_pm1_status(); + dump_pm1_status(pm1_sts); + + /* While OSPM is not active, poweroff immediately + * on a power button event. + */ + if (pm1_sts & PWRBTN_STS) { + // power button pressed + u32 reg32; + reg32 = (7 << 10) | (1 << 13); + outl(reg32, pmbase + PM1_CNT); + } +} + +static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save) +{ + u32 gpe0_sts; + + gpe0_sts = reset_gpe0_status(); + dump_gpe0_status(gpe0_sts); +} + +static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save) +{ + void (*mainboard_gpi)(u16 gpi_sts) = mainboard_smi_gpi; + u16 reg16; + reg16 = inw(pmbase + ALT_GP_SMI_STS); + outw(reg16, pmbase + ALT_GP_SMI_STS); + + reg16 &= inw(pmbase + ALT_GP_SMI_EN); + + tseg_fixup((void **)&mainboard_gpi); + if (mainboard_gpi) { + mainboard_gpi(reg16); + } else { + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); + } + + outw(reg16, pmbase + ALT_GP_SMI_STS); +} + +static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) +{ + u32 reg32; + + reg32 = inl(pmbase + SMI_EN); + + /* Are periodic SMIs enabled? */ + if ((reg32 & MCSMI_EN) == 0) + return; + + printk(BIOS_DEBUG, "Microcontroller SMI.\n"); +} + + + +static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save) +{ + u32 tco_sts; + + tco_sts = reset_tco_status(); + + /* Any TCO event? */ + if (!tco_sts) + return; + + if (tco_sts & (1 << 8)) { // BIOSWR + u8 bios_cntl; + + bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + + if (bios_cntl & 1) { + /* BWE is RW, so the SMI was caused by a + * write to BWE, not by a write to the BIOS + */ + + /* This is the place where we notice someone + * is trying to tinker with the BIOS. We are + * trying to be nice and just ignore it. A more + * resolute answer would be to power down the + * box. + */ + printk(BIOS_DEBUG, "Switching back to RO\n"); + pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + } /* No else for now? */ + } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ + /* Handle TCO timeout */ + printk(BIOS_DEBUG, "TCO Timeout.\n"); + } else if (!tco_sts) { + dump_tco_status(tco_sts); + } +} + +static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save) +{ + u32 reg32; + + reg32 = inl(pmbase + SMI_EN); + + /* Are periodic SMIs enabled? */ + if ((reg32 & PERIODIC_EN) == 0) + return; + + printk(BIOS_DEBUG, "Periodic SMI.\n"); +} + +static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save) +{ +#define IOTRAP(x) (trap_sts & (1 << x)) + u32 trap_sts, trap_cycle; + u32 data, mask = 0; + int i; + + trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register + RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR + + trap_cycle = RCBA32(0x1e10); + for (i=16; i<20; i++) { + if (trap_cycle & (1 << i)) + mask |= (0xff << ((i - 16) << 2)); + } + + + /* IOTRAP(3) SMI function call */ + if (IOTRAP(3)) { + if (gnvs && gnvs->smif) + io_trap_handler(gnvs->smif); // call function smif + return; + } + + /* IOTRAP(2) currently unused + * IOTRAP(1) currently unused */ + + /* IOTRAP(0) SMIC */ + if (IOTRAP(0)) { + if (!(trap_cycle & (1 << 24))) { // It's a write + printk(BIOS_DEBUG, "SMI1 command\n"); + data = RCBA32(0x1e18); + data &= mask; + // if (smi1) + // southbridge_smi_command(data); + // return; + } + // Fall through to debug + } + + printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); + for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); + printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); + printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); + + if (!(trap_cycle & (1 << 24))) { + /* Write Cycle */ + data = RCBA32(0x1e18); + printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); + } +#undef IOTRAP +} + +typedef void (*smi_handler_t)(unsigned int node, + smm_state_save_area_t *state_save); + +static smi_handler_t southbridge_smi[32] = { + NULL, // [0] reserved + NULL, // [1] reserved + NULL, // [2] BIOS_STS + NULL, // [3] LEGACY_USB_STS + southbridge_smi_sleep, // [4] SLP_SMI_STS + southbridge_smi_apmc, // [5] APM_STS + NULL, // [6] SWSMI_TMR_STS + NULL, // [7] reserved + southbridge_smi_pm1, // [8] PM1_STS + southbridge_smi_gpe0, // [9] GPE0_STS + southbridge_smi_gpi, // [10] GPI_STS + southbridge_smi_mc, // [11] MCSMI_STS + NULL, // [12] DEVMON_STS + southbridge_smi_tco, // [13] TCO_STS + southbridge_smi_periodic, // [14] PERIODIC_STS + NULL, // [15] SERIRQ_SMI_STS + NULL, // [16] SMBUS_SMI_STS + NULL, // [17] LEGACY_USB2_STS + NULL, // [18] INTEL_USB2_STS + NULL, // [19] reserved + NULL, // [20] PCI_EXP_SMI_STS + southbridge_smi_monitor, // [21] MONITOR_STS + NULL, // [22] reserved + NULL, // [23] reserved + NULL, // [24] reserved + NULL, // [25] EL_SMI_STS + NULL, // [26] SPI_STS + NULL, // [27] reserved + NULL, // [28] reserved + NULL, // [29] reserved + NULL, // [30] reserved + NULL // [31] reserved +}; + +/** + * @brief Interrupt handler for SMI# + * + * @param smm_revision revision of the smm state save map + */ + +void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) +{ + int i, dump = 0; + u32 smi_sts; + + /* Update global variable pmbase */ + pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + +#if CONFIG_SMM_TSEG + /* Update global variable TSEG base */ + tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; +#endif + + /* We need to clear the SMI status registers, or we won't see what's + * happening in the following calls. + */ + smi_sts = reset_smi_status(); + + /* Call SMI sub handler for each of the status bits */ + for (i = 0; i < 31; i++) { + if (smi_sts & (1 << i)) { + if (southbridge_smi[i]) { +#if CONFIG_SMM_TSEG + smi_handler_t handler = (smi_handler_t) + ((u8*)southbridge_smi[i] + tseg_base); + if (handler) + handler(node, state_save); +#else + southbridge_smi[i](node, state_save); +#endif + } else { + printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no " + "handler available.\n", i); + dump = 1; + } + } + } + + if(dump) { + dump_smi_status(smi_sts); + } + +} diff --git a/src/southbridge/intel/bd82x6x/usb_debug.c b/src/southbridge/intel/bd82x6x/usb_debug.c new file mode 100644 index 0000000..4258a03 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/usb_debug.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <usbdebug.h> +#include <device/pci_def.h> +#include "pch.h" + +/* Required for successful build, but currently empty. */ +void set_debug_port(unsigned int port) +{ + /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ +} + +void enable_usbdebug(unsigned int port) +{ + u32 dbgctl; + device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ + + /* Set the EHCI BAR address. */ + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + + /* Enable access to the EHCI memory space registers. */ + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + + /* Force ownership of the Debug Port to the EHCI controller. */ + printk(BIOS_DEBUG, "Enabling OWNER_CNT\n"); + dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); + dbgctl |= (1 << 30); + write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); +} + diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c new file mode 100644 index 0000000..c299535 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "pch.h" +#include <usbdebug.h> +#include <arch/io.h> + +static void usb_ehci_init(struct device *dev) +{ + u32 reg32; + + /* Disable Wake on Disconnect in RMH */ + reg32 = RCBA32(0x35b0); + reg32 |= 0x22; + RCBA32(0x35b0) = reg32; + + printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER; + //reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); + + printk(BIOS_DEBUG, "done.\n"); +} + +static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + u8 access_cntl; + + access_cntl = pci_read_config8(dev, 0x80); + + /* Enable writes to protected registers. */ + pci_write_config8(dev, 0x80, access_cntl | 1); + + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } + + /* Restore protection. */ + pci_write_config8(dev, 0x80, access_cntl); +} + +static void usb_ehci_set_resources(struct device *dev) +{ +#if CONFIG_USBDEBUG + struct resource *res; + u32 base; + u32 usb_debug; + + usb_debug = get_ehci_debug(); + set_ehci_debug(0); +#endif + pci_dev_set_resources(dev); + +#if CONFIG_USBDEBUG + res = find_resource(dev, 0x10); + set_ehci_debug(usb_debug); + if (!res) return; + base = res->base; + set_ehci_base(base); + report_resource_stored(dev, res, ""); +#endif +} + + + +static struct pci_operations lops_pci = { + .set_subsystem = &usb_ehci_set_subsystem, +}; + +static struct device_operations usb_ehci_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = usb_ehci_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_ehci_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver pch_usb_ehci1 __pci_driver = { + .ops = &usb_ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c26, +}; +static const struct pci_driver pch_usb_ehci2 __pci_driver = { + .ops = &usb_ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1c2d, +}; +static const struct pci_driver pch_usb_ehci3 __pci_driver = { + .ops = &usb_ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e26, +}; +static const struct pci_driver pch_usb_ehci4 __pci_driver = { + .ops = &usb_ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1e2d, +}; diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/bd82x6x/watchdog.c new file mode 100644 index 0000000..362e896 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/watchdog.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <watchdog.h> + + // + // Disable PCH Watchdog timer at SB_RCBA+0x3410 + // + // Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20; + // +void watchdog_off(void) +{ + device_t dev; + unsigned long value, base; + + /* Turn off the ICH7 watchdog. */ + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + + /* Enable I/O space. */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + + /* Get TCO base. */ + base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + + /* Disable the watchdog timer. */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + + /* Clear TCO timeout status. */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); + + printk(BIOS_DEBUG, "PCH watchdog disabled\n"); +} [View Less]

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Patch set updated for coreboot: ff8097a Add support for Intel Sandybridge CPU (northbridge part)
by Stefan Reinauer 03 Apr '12

03 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/854 -gerrit commit ff8097ac89d47349ad72417959efcd8b47c70a69 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 00:08:51 2012 +0200 Add support for Intel Sandybridge CPU (northbridge part) Change-Id: I06228ecf9cac931ad34e32871d5a4f2a4857b2ac Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-… [View More]off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/Kconfig | 1 + src/northbridge/intel/Makefile.inc | 2 + src/northbridge/intel/sandybridge/Kconfig | 96 ++++ src/northbridge/intel/sandybridge/Makefile.inc | 41 ++ src/northbridge/intel/sandybridge/acpi.c | 75 +++ .../intel/sandybridge/acpi/hostbridge.asl | 250 ++++++++++ src/northbridge/intel/sandybridge/acpi/igd.asl | 324 +++++++++++++ .../intel/sandybridge/acpi/sandybridge.asl | 59 +++ src/northbridge/intel/sandybridge/chip.h | 40 ++ src/northbridge/intel/sandybridge/early_init.c | 165 +++++++ src/northbridge/intel/sandybridge/finalize.c | 58 +++ src/northbridge/intel/sandybridge/gma.c | 474 +++++++++++++++++++ src/northbridge/intel/sandybridge/northbridge.c | 483 ++++++++++++++++++++ src/northbridge/intel/sandybridge/pcie_config.c | 89 ++++ src/northbridge/intel/sandybridge/pei_data.h | 98 ++++ src/northbridge/intel/sandybridge/raminit.c | 383 ++++++++++++++++ src/northbridge/intel/sandybridge/raminit.h | 36 ++ src/northbridge/intel/sandybridge/sandybridge.h | 224 +++++++++ src/northbridge/intel/sandybridge/udelay.c | 58 +++ 19 files changed, 2956 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig index 31afe6a..8289a45 100644 --- a/src/northbridge/intel/Kconfig +++ b/src/northbridge/intel/Kconfig @@ -11,3 +11,4 @@ source src/northbridge/intel/i855/Kconfig source src/northbridge/intel/i945/Kconfig source src/northbridge/intel/sch/Kconfig source src/northbridge/intel/i5000/Kconfig +source src/northbridge/intel/sandybridge/Kconfig diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc index 6153052..a93a141 100644 --- a/src/northbridge/intel/Makefile.inc +++ b/src/northbridge/intel/Makefile.inc @@ -11,3 +11,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945) += i945 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000 +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += sandybridge +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += sandybridge diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig new file mode 100644 index 0000000..8cf0a49 --- /dev/null +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -0,0 +1,96 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config NORTHBRIDGE_INTEL_SANDYBRIDGE + bool + select CACHE_MRC_BIN + select CPU_INTEL_MODEL_206AX + +config NORTHBRIDGE_INTEL_IVYBRIDGE + bool + select CACHE_MRC_BIN + select CPU_INTEL_MODEL_306AX + +if NORTHBRIDGE_INTEL_SANDYBRIDGE + +config VGA_BIOS_ID + string + default "8086,0106" + +config CACHE_MRC_SIZE_KB + int + default 256 + +config DCACHE_RAM_BASE + hex + default 0xff7f0000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + +endif + +if NORTHBRIDGE_INTEL_IVYBRIDGE + +config VGA_BIOS_ID + string + default "8086,0166" + +config EXTERNAL_MRC_BLOB + bool + default n + +config CACHE_MRC_SIZE_KB + int + default 512 + +config DCACHE_RAM_BASE + hex + default 0xff7e0000 + +config DCACHE_RAM_SIZE + hex + default 0x20000 + +endif + +if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE + +config DCACHE_RAM_MRC_VAR_SIZE + hex + default 0x4000 + +config HAVE_MRC + bool "Add a System Agent binary" + help + Select this option to add a System Agent binary to + the resulting coreboot image. + + Note: Without this binary coreboot will not work + +config MRC_FILE + string "Intel System Agent path and filename" + depends on HAVE_MRC + default "mrc.bin" + help + The path and filename of the file to use as System Agent + binary. + +endif diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc new file mode 100644 index 0000000..9e7568c --- /dev/null +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -0,0 +1,41 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2010 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +driver-y += northbridge.c +driver-y += gma.c + +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c + +romstage-y += udelay.c +romstage-y += raminit.c +romstage-y += early_init.c +romstage-y += ../../../arch/x86/lib/walkcbfs.S + +smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c + +# We don't ship that, but booting without it is bound to fail +cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin +mrc.bin-file := $(CONFIG_MRC_FILE) +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE),y) +mrc.bin-position := 0xfffa0000 +endif +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE),y) +mrc.bin-position := 0xfffe0000 +endif +mrc.bin-type := 0xab diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c new file mode 100644 index 0000000..d1174d6 --- /dev/null +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "sandybridge.h" + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + u32 pciexbar = 0; + u32 pciexbar_reg; + int max_buses; + + dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_NB, 0); + if (!dev) + return current; + + pciexbar_reg=pci_read_config32(dev, PCIEXBAR); + + // MMCFG not supported or not enabled. + if (!(pciexbar_reg & (1 << 0))) + return current; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: // 256MB + pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + max_buses = 256; + break; + case 1: // 128M + pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + max_buses = 128; + break; + case 2: // 64M + pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + max_buses = 64; + break; + default: // RSVD + return current; + } + + if (!pciexbar) + return current; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, + pciexbar, 0x0, 0x0, max_buses - 1); + + return current; +} + + diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl new file mode 100644 index 0000000..592c4c6 --- /dev/null +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -0,0 +1,250 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +Name(_HID,EISAID("PNP0A08")) // PCIe +Name(_CID,EISAID("PNP0A03")) // PCI + +Name(_ADR, 0) +Name(_BBN, 0) + +Device (MCHC) +{ + Name(_ADR, 0x00000000) // 0:0.0 + + OperationRegion(MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset (0x40), // EPBAR + EPEN, 1, // Enable + , 11, // + EPBR, 24, // EPBAR + + Offset (0x48), // MCHBAR + MHEN, 1, // Enable + , 13, // + MHBR, 22, // MCHBAR + + Offset (0x60), // PCIe BAR + PXEN, 1, // Enable + PXSZ, 2, // BAR size + , 23, // + PXBR, 10, // PCIe BAR + + Offset (0x68), // DMIBAR + DMEN, 1, // Enable + , 11, // + DMBR, 24, // DMIBAR + + Offset (0x70), // ME Base Address + MEBA, 64, + + // ... + + Offset (0x80), // PAM0 + , 4, + PM0H, 2, + , 2, + Offset (0x81), // PAM1 + PM1L, 2, + , 2, + PM1H, 2, + , 2, + Offset (0x82), // PAM2 + PM2L, 2, + , 2, + PM2H, 2, + , 2, + Offset (0x83), // PAM3 + PM3L, 2, + , 2, + PM3H, 2, + , 2, + Offset (0x84), // PAM4 + PM4L, 2, + , 2, + PM4H, 2, + , 2, + Offset (0x85), // PAM5 + PM5L, 2, + , 2, + PM5H, 2, + , 2, + Offset (0x86), // PAM6 + PM6L, 2, + , 2, + PM6H, 2, + , 2, + + Offset (0xa0), // Top of Used Memory + TOM, 64, + + Offset (0xbc), // Top of Low Used Memory + TLUD, 32, + } + +} + + +// Current Resource Settings + +Method (_CRS, 0, Serialized) +{ + Name (MCRS, ResourceTemplate() + { + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-0xfebfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, + 0xfec00000,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) + }) + + // Find PCI resource area in MCRS + CreateDwordField(MCRS, PM01._MIN, PMIN) + CreateDwordField(MCRS, PM01._MAX, PMAX) + CreateDwordField(MCRS, PM01._LEN, PLEN) + + // Fix up PCI memory region + // Start with Top of Lower Usable DRAM + Store (^MCHC.TLUD, Local0) + Store (^MCHC.MEBA, Local1) + + // Check if ME base is equal + If (LEqual (Local0, Local1)) { + // Use Top Of Memory instead + Store (^MCHC.TOM, Local0) + } + + Store (Local0, PMIN) + Add(Subtract(PMAX, PMIN), 1, PLEN) + + Return (MCRS) +} + +/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ +#include "acpi/sandybridge_pci_irqs.asl" + + diff --git a/src/northbridge/intel/sandybridge/acpi/igd.asl b/src/northbridge/intel/sandybridge/acpi/igd.asl new file mode 100644 index 0000000..a6804ad --- /dev/null +++ b/src/northbridge/intel/sandybridge/acpi/igd.asl @@ -0,0 +1,324 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) + + /* Display Output Switching */ + Method (_DOS, 1) + { + /* Windows 2000 and Windows XP call _DOS to enable/disable + * Display Output Switching during init and while a switch + * is already active + */ + Store (And(Arg0, 7), DSEN) + } + + /* We try to support as many i945 systems as possible, + * so keep the number of DIDs flexible. + */ + Method (_DOD, 0) + { + If (LEqual(NDID, 1)) { + Name(DOD1, Package() { + 0xffffffff + }) + Store (Or(0x00010000, DID1), Index(DOD1, 0)) + Return(DOD1) + } + + If (LEqual(NDID, 2)) { + Name(DOD2, Package() { + 0xffffffff, + 0xffffffff + }) + Store (Or(0x00010000, DID2), Index(DOD2, 0)) + Store (Or(0x00010000, DID2), Index(DOD2, 1)) + Return(DOD2) + } + + If (LEqual(NDID, 3)) { + Name(DOD3, Package() { + 0xffffffff, + 0xffffffff, + 0xffffffff + }) + Store (Or(0x00010000, DID3), Index(DOD3, 0)) + Store (Or(0x00010000, DID3), Index(DOD3, 1)) + Store (Or(0x00010000, DID3), Index(DOD3, 2)) + Return(DOD3) + } + + If (LEqual(NDID, 4)) { + Name(DOD4, Package() { + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff + }) + Store (Or(0x00010000, DID4), Index(DOD4, 0)) + Store (Or(0x00010000, DID4), Index(DOD4, 1)) + Store (Or(0x00010000, DID4), Index(DOD4, 2)) + Store (Or(0x00010000, DID4), Index(DOD4, 3)) + Return(DOD4) + } + + If (LGreater(NDID, 4)) { + Name(DOD5, Package() { + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff + }) + Store (Or(0x00010000, DID5), Index(DOD5, 0)) + Store (Or(0x00010000, DID5), Index(DOD5, 1)) + Store (Or(0x00010000, DID5), Index(DOD5, 2)) + Store (Or(0x00010000, DID5), Index(DOD5, 3)) + Store (Or(0x00010000, DID5), Index(DOD5, 4)) + Return(DOD5) + } + + /* Some error happened, but we have to return something */ + Return (Package() {0x00000400}) + } + + Device(DD01) + { + /* Device Unique ID */ + Method(_ADR, 0, Serialized) + { + If(LEqual(DID1, 0)) { + Return (1) + } Else { + Return (And(0xffff, DID1)) + } + } + + /* Device Current Status */ + Method(_DCS, 0) + { + TRAP(1) + If (And(CSTE, 1)) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(_DGS, 0) + { + If (And(NSTE, 1)) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(_DSS, 1) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } + } + + Device(DD02) + { + /* Device Unique ID */ + Method(_ADR, 0, Serialized) + { + If(LEqual(DID2, 0)) { + Return (2) + } Else { + Return (And(0xffff, DID2)) + } + } + + /* Device Current Status */ + Method(_DCS, 0) + { + TRAP(1) + If (And(CSTE, 2)) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(_DGS, 0) + { + If (And(NSTE, 2)) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(_DSS, 1) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } + } + + + Device(DD03) + { + /* Device Unique ID */ + Method(_ADR, 0, Serialized) + { + If(LEqual(DID3, 0)) { + Return (3) + } Else { + Return (And(0xffff, DID3)) + } + } + + /* Device Current Status */ + Method(_DCS, 0) + { + TRAP(1) + If (And(CSTE, 4)) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(_DGS, 0) + { + If (And(NSTE, 4)) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(_DSS, 1) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } + } + + + Device(DD04) + { + /* Device Unique ID */ + Method(_ADR, 0, Serialized) + { + If(LEqual(DID4, 0)) { + Return (4) + } Else { + Return (And(0xffff, DID4)) + } + } + + /* Device Current Status */ + Method(_DCS, 0) + { + TRAP(1) + If (And(CSTE, 8)) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(_DGS, 0) + { + If (And(NSTE, 4)) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(_DSS, 1) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } + } + + + Device(DD05) + { + /* Device Unique ID */ + Method(_ADR, 0, Serialized) + { + If(LEqual(DID5, 0)) { + Return (5) + } Else { + Return (And(0xffff, DID5)) + } + } + + /* Device Current Status */ + Method(_DCS, 0) + { + TRAP(1) + If (And(CSTE, 16)) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(_DGS, 0) + { + If (And(NSTE, 4)) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(_DSS, 1) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } + } + +} + diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl new file mode 100644 index 0000000..64b5d8f --- /dev/null +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "hostbridge.asl" +#include "../sandybridge.h" + +/* PCI Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + + Name (PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) + Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000) + Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH + +#if CONFIG_CHROMEOS_RAMOOPS + Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) +#endif + + /* Required for SandyBridge sighting 3715511 */ + Memory32Fixed(ReadWrite, 0x20000000, 0x00200000) + Memory32Fixed(ReadWrite, 0x40000000, 0x00200000) + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) + { + Return(PDRS) + } +} + +// Integrated graphics 0:2.0 +#include "igd.asl" diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h new file mode 100644 index 0000000..b891884 --- /dev/null +++ b/src/northbridge/intel/sandybridge/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Digital Port Hotplug Enable: + * 0x04 = Enabled, 2ms short pulse + * 0x05 = Enabled, 4.5ms short pulse + * 0x06 = Enabled, 6ms short pulse + * 0x07 = Enabled, 100ms short pulse + */ +struct northbridge_intel_sandybridge_config { + u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */ + u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ + u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ + + u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ + u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay; /* T3 time sequence */ + u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ + u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ +}; + +extern struct chip_operations northbridge_intel_sandybridge_ops; diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c new file mode 100644 index 0000000..f052fbc --- /dev/null +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -0,0 +1,165 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include "sandybridge.h" +#include "pcie_config.c" + +static void sandybridge_setup_bars(void) +{ + /* Setting up Southbridge. In the northbridge code. */ + printk(BIOS_DEBUG, "Setting up static southbridge registers..."); + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); + + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ + + printk(BIOS_DEBUG, " done.\n"); + + printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + printk(BIOS_DEBUG, " done.\n"); + + printk(BIOS_DEBUG, "Setting up static northbridge registers..."); + /* Set up all hardcoded northbridge BARs */ + pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ + pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32); + + /* Set C0000-FFFFF to access RAM on both reads and writes */ + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); + + printk(BIOS_DEBUG, " done.\n"); +} + +static void sandybridge_setup_graphics(void) +{ + u32 reg32; + u16 reg16; + u8 reg8; + + reg16 = pci_read_config16(PCI_DEV(0,2,0), PCI_DEVICE_ID); + switch (reg16) { + case 0x0102: /* GT1 Desktop */ + case 0x0106: /* GT1 Mobile */ + case 0x010a: /* GT1 Server */ + case 0x0112: /* GT2 Desktop */ + case 0x0116: /* GT2 Mobile */ + case 0x0122: /* GT2 Desktop >=1.3GHz */ + case 0x0126: /* GT2 Mobile >=1.3GHz */ + case 0x0166: /* IvyBridge ??? */ + break; + default: + printk(BIOS_DEBUG, "Graphics not supported by this CPU/chipset.\n"); + return; + } + + printk(BIOS_DEBUG, "Initializing Graphics...\n"); + + /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ + reg16 = pci_read_config16(PCI_DEV(0,0,0), GGC); + reg16 &= ~0x00f8; + reg16 |= 1 << 3; + /* Program GTT memory by setting GGC[9:8] = 2MB */ + reg16 &= ~0x0300; + reg16 |= 2 << 8; + /* Enable VGA decode */ + reg16 &= ~0x0002; + pci_write_config16(PCI_DEV(0,0,0), GGC, reg16); + + /* Enable 256MB aperture */ + reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC); + reg8 &= ~0x06; + reg8 |= 0x02; + pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8); + + /* Erratum workarounds */ + MCHBAR8(0x5f10) = 0x20; + + reg32 = MCHBAR32(0x5f00); + reg32 |= (1 << 9)|(1 << 10); + MCHBAR32(0x5f00) = reg32; + + /* Enable SA Clock Gating */ + reg32 = MCHBAR32(0x5f00); + MCHBAR32(0x5f00) = reg32 | 1; + + /* GPU RC6 workaround for sighting 366252 */ + reg32 = MCHBAR32(0x5d14); + reg32 |= (1 << 31); + MCHBAR32(0x5d14) = reg32; + + /* VLW */ + reg32 = MCHBAR32(0x6120); + reg32 &= ~(1 << 0); + MCHBAR32(0x6120) = reg32; + + reg32 = MCHBAR32(0x5418); + reg32 |= (1 << 4) | (1 << 5); + MCHBAR32(0x5418) = reg32; +} + +void sandybridge_early_initialization(int chipset_type) +{ + u32 capid0_a; + u8 reg8; + + /* Device ID Override Enable should be done very early */ + capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); + if (capid0_a & (1 << 10)) { + reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3); + reg8 &= ~7; /* Clear 2:0 */ + + if (chipset_type == SANDYBRIDGE_MOBILE) + reg8 |= 1; /* Set bit 0 */ + + pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8); + } + + /* Setup all BARs required for early PCIe and raminit */ + sandybridge_setup_bars(); + + /* Device Enable */ + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, DEVEN_HOST | DEVEN_IGD); + + sandybridge_setup_graphics(); +} + +void sandybridge_late_initialization(void) +{ +} + diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c new file mode 100644 index 0000000..5bd3f1a --- /dev/null +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <stdlib.h> +#include "pcie_config.c" +#include "sandybridge.h" + +#define PCI_DEV_SNB PCI_DEV(0, 0, 0) + +void intel_sandybridge_finalize_smm(void) +{ + pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ + pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ + pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ + pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ + pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ + pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ + pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ + pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ + pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ + pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ + pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ + + MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ + MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ + MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ + MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ + MCHBAR32_OR(0x6800, 1 << 31); + MCHBAR32_OR(0x7000, 1 << 31); + MCHBAR32_OR(0x77fc, 1 << 0); + + /* Memory Controller Lockdown */ + MCHBAR8(0x50fc) = 0x8f; + + /* Read+write the following */ + MCHBAR32(0x6030) = MCHBAR32(0x6030); + MCHBAR32(0x6034) = MCHBAR32(0x6034); + MCHBAR32(0x6008) = MCHBAR32(0x6008); +} diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c new file mode 100644 index 0000000..00b5957 --- /dev/null +++ b/src/northbridge/intel/sandybridge/gma.c @@ -0,0 +1,474 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Chromium OS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +#include "chip.h" +#include "sandybridge.h" + +/* some vga option roms are used for several chipsets but they only have one + * PCI ID in their header. If we encounter such an option rom, we need to do + * the mapping ourselfes + */ + +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev=vendev; + + switch (vendev) { + case 0x01028086: /* GT1 Desktop */ + case 0x010a8086: /* GT1 Server */ + case 0x01128086: /* GT2 Desktop */ + case 0x01168086: /* GT2 Mobile */ + case 0x01228086: /* GT2 Desktop >=1.3GHz */ + case 0x01268086: /* GT2 Mobile >=1.3GHz */ + case 0x01668086: /* IVB */ + new_vendev=0x01068086; /* GT1 Mobile */ + break; + } + + return new_vendev; +} + +static struct resource *gtt_res = NULL; + +static inline u32 gtt_read(u32 reg) +{ + return read32(gtt_res->base + reg); +} + +static inline void gtt_write(u32 reg, u32 data) +{ + write32(gtt_res->base + reg, data); +} + +#define GTT_RETRY 1000 +static int gtt_poll(u32 reg, u32 mask, u32 value) +{ + unsigned try = GTT_RETRY; + u32 data; + + while (try--) { + data = gtt_read(reg); + if ((data & mask) == value) + return 1; + udelay(10); + } + + printk(BIOS_ERR, "GT init timeout\n"); + return 0; +} + +static void gma_pm_init_pre_vbios(struct device *dev) +{ + u32 reg32; + + printk(BIOS_DEBUG, "GT Power Management Init\n"); + + gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!gtt_res || !gtt_res->base) + return; + + if (bridge_silicon_revision() < IVB_STEP_C0) { + /* 1: Enable force wake */ + gtt_write(0xa18c, 0x00000001); + if (!gtt_poll(0x130090, (1 << 0), (1 << 0))) + return; + } else { + gtt_write(0xa180, 1 << 5); + gtt_write(0xa188, 0xffff0001); + if (!gtt_poll(0x130090, (1 << 0), (1 << 0))) + return; + } + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ + reg32 = gtt_read(0x42004); + reg32 |= (1 << 14) | (1 << 15); + gtt_write(0x42004, reg32); + } + + if (bridge_silicon_revision() >= IVB_STEP_A0) { + /* Display Reset Acknowledge Settings */ + gtt_write(0xa18c, 0x00000001); + reg32 = gtt_read(0x45010); + reg32 |= (1 << 1) | (1 << 0); + gtt_write(0x45010, reg32); + } + + /* 2: Get GT SKU from GTT+0x911c[13] */ + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + reg32 = gtt_read(0x911c); + if (reg32 & (1 << 13)) { + printk(BIOS_DEBUG, "GT1 Power Meter Weights\n"); + gtt_write(0xa200, 0xcc000000); + gtt_write(0xa204, 0x07000040); + gtt_write(0xa208, 0x0000fe00); + gtt_write(0xa20c, 0x00000000); + gtt_write(0xa210, 0x17000000); + gtt_write(0xa214, 0x00000021); + gtt_write(0xa218, 0x0817fe19); + gtt_write(0xa21c, 0x00000000); + gtt_write(0xa220, 0x00000000); + gtt_write(0xa224, 0xcc000000); + gtt_write(0xa228, 0x07000040); + gtt_write(0xa22c, 0x0000fe00); + gtt_write(0xa230, 0x00000000); + gtt_write(0xa234, 0x17000000); + gtt_write(0xa238, 0x00000021); + gtt_write(0xa23c, 0x0817fe19); + gtt_write(0xa240, 0x00000000); + gtt_write(0xa244, 0x00000000); + gtt_write(0xa248, 0x8000421e); + } else { + printk(BIOS_DEBUG, "GT2 Power Meter Weights\n"); + gtt_write(0xa200, 0x330000a6); + gtt_write(0xa204, 0x402d0031); + gtt_write(0xa208, 0x00165f83); + gtt_write(0xa20c, 0xf1000000); + gtt_write(0xa210, 0x00000000); + gtt_write(0xa214, 0x00160016); + gtt_write(0xa218, 0x002a002b); + gtt_write(0xa21c, 0x00000000); + gtt_write(0xa220, 0x00000000); + gtt_write(0xa224, 0x330000a6); + gtt_write(0xa228, 0x402d0031); + gtt_write(0xa22c, 0x00165f83); + gtt_write(0xa230, 0xf1000000); + gtt_write(0xa234, 0x00000000); + gtt_write(0xa238, 0x00160016); + gtt_write(0xa23c, 0x002a002b); + gtt_write(0xa240, 0x00000000); + gtt_write(0xa244, 0x00000000); + gtt_write(0xa248, 0x8000421e); + } + } else { + printk(BIOS_DEBUG, "IVB GT Power Meter Weights\n"); + gtt_write(0xa800, 0x00000000); + gtt_write(0xa804, 0x00023800); + gtt_write(0xa808, 0x00000902); + gtt_write(0xa80c, 0x0c002f00); + gtt_write(0xa810, 0x12000500); + gtt_write(0xa814, 0x00000000); + gtt_write(0xa818, 0x00b20000); + gtt_write(0xa81c, 0x00000002); + gtt_write(0xa820, 0x03004b02); + gtt_write(0xa824, 0x00000600); + gtt_write(0xa828, 0x07000773); + gtt_write(0xa82c, 0x00000000); + gtt_write(0xa830, 0x00010000); + gtt_write(0xa834, 0x0510020d); + gtt_write(0xa838, 0x00020100); + gtt_write(0xa83c, 0x00103700); + gtt_write(0xa840, 0x0000001d); + gtt_write(0xa844, 0x00000000); + gtt_write(0xa848, 0x20001b00); + gtt_write(0xa84c, 0x0a000010); + gtt_write(0xa850, 0x00000000); + gtt_write(0xa854, 0x00000008); + gtt_write(0xa858, 0x00000000); + gtt_write(0xa85c, 0x00000000); + gtt_write(0xa860, 0x00040000); + gtt_write(0xa248, 0x0000221e); + gtt_write(0xa900, 0x00000000); + gtt_write(0xa904, 0x00003500); + gtt_write(0xa908, 0x00000000); + gtt_write(0xa90c, 0x0c000000); + gtt_write(0xa910, 0x12000500); + gtt_write(0xa914, 0x00000000); + gtt_write(0xa918, 0x00b20000); + gtt_write(0xa91c, 0x00000000); + gtt_write(0xa920, 0x08004b02); + gtt_write(0xa924, 0x00000400); + gtt_write(0xa928, 0x07000820); + gtt_write(0xa92c, 0x00000000); + gtt_write(0xa930, 0x00030000); + gtt_write(0xa934, 0x050f020d); + gtt_write(0xa938, 0x00020300); + gtt_write(0xa93c, 0x00903900); + gtt_write(0xa940, 0x00000000); + gtt_write(0xa944, 0x00000000); + gtt_write(0xa948, 0x20001b00); + gtt_write(0xa94c, 0x0a000010); + gtt_write(0xa950, 0x00000000); + gtt_write(0xa954, 0x00000008); + gtt_write(0xa960, 0x00110000); + gtt_write(0xaa3c, 0x00003900); + gtt_write(0xaa54, 0x00000008); + gtt_write(0xaa60, 0x00110000); + } + + /* 3: Gear ratio map */ + gtt_write(0xa004, 0x00000010); + + /* 4: GFXPAUSE */ + gtt_write(0xa000, 0x00070020); + + /* 5: Dynamic EU trip control */ + gtt_write(0xa080, 0x00000004); + + /* 6: ECO bits */ + reg32 = gtt_read(0xa180); + reg32 |= (1 << 26) | (1 << 31); + /* (bit 20=1 for SNB step D1+ / IVB A0+) */ + if (bridge_silicon_revision() >= SNB_STEP_D1) + reg32 |= (1 << 20); + gtt_write(0xa180, reg32); + + /* 6a: for SnB step D2+ only */ + if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && + (bridge_silicon_revision() >= SNB_STEP_D2)) { + reg32 = gtt_read(0x9400); + reg32 |= (1 << 7); + gtt_write(0x9400, reg32); + + reg32 = gtt_read(0x941c); + reg32 &= 0xf; + reg32 |= (1 << 1); + gtt_write(0x941c, reg32); + if (!gtt_poll(0x941c, (1 << 1), (0 << 1))) + return; + } + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + reg32 = gtt_read(0x907c); + reg32 |= (1 << 16); + gtt_write(0x907c, reg32); + + /* 6b: Clocking reset controls */ + gtt_write(0x9424, 0x00000001); + } else { + /* 6b: Clocking reset controls */ + gtt_write(0x9424, 0x00000000); + } + + /* 7 */ + if (!gtt_poll(0x138124, (1 << 31), (0 << 31))) + return; + gtt_write(0x138128, 0x00000029); /* Mailbox Data */ + gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ + if (!gtt_poll(0x138124, (1 << 31), (0 << 31))) + return; + gtt_write(0x138124, 0x8000000a); /* Mailbox Cmd to clear RC6 count */ + if (!gtt_poll(0x138124, (1 << 31), (0 << 31))) + return; + + /* 8 */ + gtt_write(0xa090, 0x00000000); /* RC Control */ + gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ + gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ + gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ + gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */ + gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */ + + /* 9 */ + gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */ + gtt_write(0x12054,0x0000000a); /* Video Idle Max Count */ + gtt_write(0x22054,0x0000000a); /* Blitter Idle Max Count */ + + /* 10 */ + gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */ + gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */ + gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */ + gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */ + gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */ + + /* 11 */ + gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */ + gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */ + gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */ + gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */ + gtt_write(0xa068, 0x000186a0); /* RP Up EI */ + gtt_write(0xa06c, 0x000493e0); /* RP Down EI */ + gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */ + + /* 11a: Enable Render Standby (RC6) */ + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + /* on IVB: also enable DeepRenderStandby */ + gtt_write(0xa090, 0x88060000); /* HW RC Control */ + } else { + gtt_write(0xa090, 0x88040000); /* HW RC Control */ + } + + /* 12: Normal Frequency Request */ + /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */ + reg32 = MCHBAR32(0x5998); + reg32 >>= 16; + reg32 &= 0xef; + reg32 <<= 25; + gtt_write(0xa008, reg32); + + /* 13: RP Control */ + gtt_write(0xa024, 0x00000592); + + /* 14: Enable PM Interrupts */ + gtt_write(0x4402c, 0x03000076); + + /* Clear 0x6c024 [8:6] */ + reg32 = gtt_read(0x6c024); + reg32 &= ~0x000001c0; + gtt_write(0x6c024, reg32); +} + +static void gma_pm_init_post_vbios(struct device *dev) +{ + struct northbridge_intel_sandybridge_config *conf = dev->chip_info; + u32 reg32; + + printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); + + /* 15: Deassert Force Wake */ + gtt_write(0xa18c, gtt_read(0xa18c) & ~1); + if (!gtt_poll(0x130090, (1 << 0), (0 << 0))) + return; + + /* 16: SW RC Control */ + gtt_write(0xa094, 0x00060000); + + /* Setup Digital Port Hotplug */ + reg32 = gtt_read(0xc4030); + if (!reg32) { + reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; + reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; + reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; + gtt_write(0xc4030, reg32); + } + + /* Setup Panel Power On Delays */ + reg32 = gtt_read(0xc7208); + if (!reg32) { + reg32 = (conf->gpu_panel_port_select & 0x3) << 30; + reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + gtt_write(0xc7208, reg32); + } + + /* Setup Panel Power Off Delays */ + reg32 = gtt_read(0xc720c); + if (!reg32) { + reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + gtt_write(0xc720c, reg32); + } + + /* Setup Panel Power Cycle Delay */ + if (conf->gpu_panel_power_cycle_delay) { + reg32 = gtt_read(0xc7210); + reg32 &= ~0xff; + reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; + gtt_write(0xc7210, reg32); + } +} + +static void gma_func0_init(struct device *dev) +{ + u32 reg32; + + /* IGD needs to be Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Init graphics power management */ + gma_pm_init_pre_vbios(dev); + + /* PCI Init, will run VBIOS */ + pci_dev_init(dev); + + /* Post VBIOS init */ + gma_pm_init_post_vbios(dev); +} + +static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations gma_pci_ops = { + .set_subsystem = gma_set_subsystem, +}; + +static struct device_operations gma_func0_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func0_init, + .scan_bus = 0, + .enable = 0, + .ops_pci = &gma_pci_ops, +}; + +static const struct pci_driver gma_gt1_desktop __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0102, +}; + +static const struct pci_driver gma_gt1_mobile __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0106, +}; + +static const struct pci_driver gma_gt1_server __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x010a, +}; + +static const struct pci_driver gma_gt2_desktop __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0112, +}; + +static const struct pci_driver gma_gt2_mobile __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0116, +}; + +static const struct pci_driver gma_gt2_desktop_fast __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0122, +}; + +static const struct pci_driver gma_gt2_mobile_fast __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0126, +}; + +static const struct pci_driver gma_func0_driver_3 __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0166, +}; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c new file mode 100644 index 0000000..e3334c4 --- /dev/null +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -0,0 +1,483 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <stdint.h> +#include <delay.h> +#include <cpu/intel/model_206ax/model_206ax.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/hypertransport.h> +#include <stdlib.h> +#include <string.h> +#include <bitops.h> +#include <cpu/cpu.h> +#include <boot/tables.h> +#include "chip.h" +#include "sandybridge.h" + +static int bridge_revision_id = -1; + +int bridge_silicon_revision(void) +{ + if (bridge_revision_id < 0) { + uint8_t stepping = cpuid_eax(1) & 0xf; + uint8_t bridge_id = pci_read_config16( + dev_find_slot(0, PCI_DEVFN(0, 0)), + PCI_DEVICE_ID) & 0xf0; + bridge_revision_id = bridge_id | stepping; + } + return bridge_revision_id; +} + +/* Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) + * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI + */ +static const int legacy_hole_base_k = 0xa0000 / 1024; +static const int legacy_hole_size_k = 384; + +int add_northbridge_resources(struct lb_memory *mem) +{ + lb_add_memory_range(mem, LB_MEM_RESERVED, + legacy_hole_base_k * 1024, legacy_hole_size_k * 1024); + +#if CONFIG_CHROMEOS_RAMOOPS + lb_add_memory_range(mem, LB_MEM_RESERVED, + CONFIG_CHROMEOS_RAMOOPS_RAM_START, + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE); +#endif + + /* Required for SandyBridge sighting 3715511 */ + lb_add_memory_range(mem, LB_MEM_RESERVED, 0x20000000, 0x00200000); + lb_add_memory_range(mem, LB_MEM_RESERVED, 0x40000000, 0x00200000); + + return 0; +} + +static int get_pcie_bar(u32 *base, u32 *len) +{ + device_t dev; + u32 pciexbar_reg; + + *base = 0; + *len = 0; + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!dev) + return 0; + + pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + + if (!(pciexbar_reg & (1 << 0))) + return 0; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: // 256MB + *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + *len = 256 * 1024 * 1024; + return 1; + case 1: // 128M + *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + *len = 128 * 1024 * 1024; + return 1; + case 2: // 64M + *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + *len = 64 * 1024 * 1024; + return 1; + } + + return 0; +} + +/* IDG memory */ +uint64_t uma_memory_base=0, uma_memory_size=0; + +static void add_fixed_resources(struct device *dev, int index) +{ + struct resource *resource; + u32 pcie_config_base, pcie_config_size; + + printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " + "size=0x%llx\n", uma_memory_base, uma_memory_size); + resource = new_resource(dev, index); + resource->base = (resource_t) uma_memory_base; + resource->size = (resource_t) uma_memory_size; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Clear these values here so they don't get used by MTRR code */ + uma_memory_base = 0; + uma_memory_size = 0; + + if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { + printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " + "size=0x%x\n", pcie_config_base, pcie_config_size); + resource = new_resource(dev, index+1); + resource->base = (resource_t) pcie_config_base; + resource->size = (resource_t) pcie_config_size; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } +} + +#if CONFIG_WRITE_HIGH_TABLES==1 +#include <cbmem.h> +#endif + +static void pci_domain_set_resources(device_t dev) +{ + uint64_t tom, me_base, touud; + uint32_t tseg_base, uma_size, tolud; + uint16_t ggc; + unsigned long long tomk; + + /* Total Memory 2GB example: + * + * 00000000 0000MB-1992MB 1992MB RAM (writeback) + * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) + * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) + * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) + * 7f200000 2034MB TOLUD + * 7f800000 2040MB MEBASE + * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) + * 80000000 2048MB TOM + * 100000000 4096MB-4102MB 6MB RAM (writeback) + * + * Total Memory 4GB example: + * + * 00000000 0000MB-2768MB 2768MB RAM (writeback) + * ad000000 2768MB-2776MB 8MB TSEG (SMRR) + * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) + * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) + * afa00000 2810MB TOLUD + * ff800000 4088MB MEBASE + * ff800000 4088MB-4096MB 8MB ME UMA (uncached) + * 100000000 4096MB TOM + * 100000000 4096MB-5374MB 1278MB RAM (writeback) + * 14fe00000 5368MB TOUUD + */ + + /* Top of Upper Usable DRAM, including remap */ + touud = pci_read_config32(dev, TOUUD+4); + touud <<= 32; + touud |= pci_read_config32(dev, TOUUD); + + /* Top of Lower Usable DRAM */ + tolud = pci_read_config32(dev, TOLUD); + + /* Top of Memory - does not account for any UMA */ + tom = pci_read_config32(dev, 0xa4); + tom <<= 32; + tom |= pci_read_config32(dev, 0xa0); + + printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", + touud, tolud, tom); + + /* ME UMA needs excluding if total memory <4GB */ + me_base = pci_read_config32(dev, 0x74); + me_base <<= 32; + me_base |= pci_read_config32(dev, 0x70); + + printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base); + + tomk = tolud >> 10; + if (me_base == tolud) { + /* ME is from MEBASE-TOM */ + uma_size = (tom - me_base) >> 10; + /* Increment TOLUD to account for ME as RAM */ + tolud += uma_size << 10; + /* UMA starts at old TOLUD */ + uma_memory_base = tomk * 1024ULL; + uma_memory_size = uma_size * 1024ULL; + printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n", + me_base, uma_size >> 10); + } + + /* Graphics memory comes next */ + ggc = pci_read_config16(dev, GGC); + if (!(ggc & 2)) { + printk(BIOS_DEBUG, "IGD decoded, subtracting "); + + /* Graphics memory */ + uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; + printk(BIOS_DEBUG, "%uM UMA", uma_size >> 10); + tomk -= uma_size; + uma_memory_base = tomk * 1024ULL; + uma_memory_size += uma_size * 1024ULL; + + /* GTT Graphics Stolen Memory Size (GGMS) */ + uma_size = ((ggc >> 8) & 0x3) * 1024ULL; + tomk -= uma_size; + uma_memory_base = tomk * 1024ULL; + uma_memory_size += uma_size * 1024ULL; + printk(BIOS_DEBUG, " and %uM GTT\n", uma_size >> 10); + } + + /* Calculate TSEG size from its base which must be below GTT */ + tseg_base = pci_read_config32(dev, 0xb8); + uma_size = (uma_memory_base - tseg_base) >> 10; + tomk -= uma_size; + uma_memory_base = tomk * 1024ULL; + uma_memory_size += uma_size * 1024ULL; + printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", + tseg_base, uma_size >> 10); + + printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10); + + /* Report the memory regions */ + ram_resource(dev, 3, 0, legacy_hole_base_k); + ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, + (tomk - (legacy_hole_base_k + legacy_hole_size_k))); + + /* + * If >= 4GB installed then memory from TOLUD to 4GB + * is remapped above TOM, TOUUD will account for both + */ + touud >>= 10; /* Convert to KB */ + if (touud > 4096 * 1024) { + ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); + printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", + (touud >> 10) - 4096); + } + + add_fixed_resources(dev, 6); + + assign_resources(dev->link_list); + +#if CONFIG_WRITE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; +#endif +} + + /* TODO We could determine how many PCIe busses we need in + * the bar. For now that number is hardcoded to a max of 64. + * See e7525/northbridge.c for an example. + */ +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, +#if CONFIG_MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif +}; + +static void mc_read_resources(device_t dev) +{ + struct resource *resource; + + pci_dev_read_resources(dev); + + /* So, this is one of the big mysteries in the coreboot resource + * allocator. This resource should make sure that the address space + * of the PCIe memory mapped config space bar. But it does not. + */ + + /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ + resource = new_resource(dev, 0xcf); + resource->base = DEFAULT_PCIEXBAR; + resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ + resource->flags = + IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; + printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", + (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); +} + +static void mc_set_resources(device_t dev) +{ + struct resource *resource; + + /* Report the PCIe BAR */ + resource = find_resource(dev, 0xcf); + if (resource) { + report_resource_stored(dev, resource, "<mmconfig>"); + } + + /* And call the normal set_resources */ + pci_dev_set_resources(dev); +} + +static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static void northbridge_dmi_init(struct device *dev) +{ + u32 reg32; + + /* Clear error status bits */ + DMIBAR32(0x1c4) = 0xffffffff; + DMIBAR32(0x1d0) = 0xffffffff; + + /* Steps prior to DMI ASPM */ + reg32 = DMIBAR32(0x250); + reg32 &= ~((1 << 22)|(1 << 20)); + reg32 |= (1 << 21); + DMIBAR32(0x250) = reg32; + + reg32 = DMIBAR32(0x238); + reg32 |= (1 << 29); + DMIBAR32(0x238) = reg32; + + if (bridge_silicon_revision() >= SNB_STEP_D0) { + reg32 = DMIBAR32(0x1f8); + reg32 |= (1 << 16); + DMIBAR32(0x1f8) = reg32; + } else if (bridge_silicon_revision() >= SNB_STEP_D1) { + reg32 = DMIBAR32(0x1f8); + reg32 &= ~(1 << 26); + reg32 |= (1 << 16); + DMIBAR32(0x1f8) = reg32; + + reg32 = DMIBAR32(0x1fc); + reg32 |= (1 << 12) | (1 << 23); + DMIBAR32(0x1fc) = reg32; + } + + /* Enable ASPM on SNB link, should happen before PCH link */ + reg32 = DMIBAR32(0xd04); + reg32 |= (1 << 4); + DMIBAR32(0xd04) = reg32; + + reg32 = DMIBAR32(0x88); + reg32 |= (1 << 1) | (1 << 0); + DMIBAR32(0x88) = reg32; +} + +static void northbridge_init(struct device *dev) +{ + u8 bios_reset_cpl; + + northbridge_dmi_init(dev); + + /* + * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU + * that BIOS has initialized memory and power management + */ + bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); + bios_reset_cpl |= 1; + MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; + printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); + + /* Configure turbo power limits 1ms after reset complete bit */ + mdelay(1); + set_power_limits(28); + + /* Set here before graphics PM init */ + MCHBAR32(0x5500) = 0x00100001; +} + +static void northbridge_enable(device_t dev) +{ +#if CONFIG_HAVE_ACPI_RESUME + switch (pci_read_config32(dev, SKPAD)) { + case 0xcafebabe: + printk(BIOS_DEBUG, "Normal boot.\n"); + acpi_slp_type=0; + break; + case 0xcafed00d: + printk(BIOS_DEBUG, "S3 Resume.\n"); + acpi_slp_type=3; + break; + default: + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + acpi_slp_type=0; + break; + } +#endif +} + +static struct pci_operations intel_pci_ops = { + .set_subsystem = intel_set_subsystem, +}; + +static struct device_operations mc_ops = { + .read_resources = mc_read_resources, + .set_resources = mc_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .enable = northbridge_enable, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, +}; + +static const struct pci_driver mc_driver __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0104, /* Sandy bridge */ +}; + +static const struct pci_driver mc_driver_1 __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0154, /* Ivy bridge */ +}; + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_intel_sandybridge_ops = { + CHIP_NAME("Intel i7 (Sandybridge) integrated Northbridge") + .enable_dev = enable_dev, +}; diff --git a/src/northbridge/intel/sandybridge/pcie_config.c b/src/northbridge/intel/sandybridge/pcie_config.c new file mode 100644 index 0000000..21e131f --- /dev/null +++ b/src/northbridge/intel/sandybridge/pcie_config.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "sandybridge.h" + +static inline __attribute__ ((always_inline)) +u8 pcie_read_config8(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read8(addr); +} + +static inline __attribute__ ((always_inline)) +u16 pcie_read_config16(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read16(addr); +} + +static inline __attribute__ ((always_inline)) +u32 pcie_read_config32(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read32(addr); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config8(device_t dev, unsigned int where, u8 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write8(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config16(device_t dev, unsigned int where, u16 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write16(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config32(device_t dev, unsigned int where, u32 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write32(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config8(device_t dev, unsigned int where, u8 ormask) +{ + u8 value = pcie_read_config8(dev, where); + pcie_write_config8(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config16(device_t dev, unsigned int where, u16 ormask) +{ + u16 value = pcie_read_config16(dev, where); + pcie_write_config16(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) +{ + u32 value = pcie_read_config32(dev, where); + pcie_write_config32(dev, where, value | ormask); +} diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h new file mode 100644 index 0000000..cda08b2 --- /dev/null +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -0,0 +1,98 @@ +/* + * coreboot UEFI PEI wrapper + * + * Copyright (c) 2011, Google Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Google Inc. nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef PEI_DATA_H +#define PEI_DATA_H + +#define PEI_VERSION 1 +struct pei_data +{ + uint32_t pei_version; + uint32_t mchbar; + uint32_t dmibar; + uint32_t epbar; + uint32_t pciexbar; + uint16_t smbusbar; + uint32_t wdbbar; + uint32_t wdbsize; + uint32_t hpet_address; + uint32_t rcba; + uint32_t pmbase; + uint32_t gpiobase; + uint32_t thermalbase; + uint32_t system_type; // 0 Mobile, 1 Desktop/Server + uint32_t tseg_size; + uint8_t spd_addresses[4]; + uint8_t ts_addresses[4]; + int boot_mode; + int ec_present; + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + int dimm_channel0_disabled; + int dimm_channel1_disabled; + /* Seed values saved in CMOS */ + uint32_t scrambler_seed; + uint32_t scrambler_seed_s3; + /* Data read from flash and passed into MRC */ + unsigned char *mrc_input; + unsigned int mrc_input_len; + /* Data from MRC that should be saved to flash */ + unsigned char *mrc_output; + unsigned int mrc_output_len; + /* + * Max frequency DDR3 could be ran at. Could be one of four values: + * 800, 1067, 1333, 1600 + */ + uint32_t max_ddr3_freq; + /* + * USB Port Configuration: + * [0] = enable + * [1] = overcurrent pin + * [2] = length + * + * Port Length + * MOBILE: + * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) + * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) + * DESKTOP: + * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) + * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) + * < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude) + */ + uint16_t usb_port_config[16][3]; + /* SPD data array for onboard RAM. Specify address 0xf0, + * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in + * spd_address for a given "DIMM". + */ + uint8_t spd_data[4][256]; +} __attribute__((packed)); + +#endif diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c new file mode 100644 index 0000000..0da968d --- /dev/null +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -0,0 +1,383 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/hlt.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <cbmem.h> +#include <arch/cbfs.h> +#include <cbfs.h> +#include <ip_checksum.h> +#include <pc80/mc146818rtc.h> +#include "raminit.h" +#include "pei_data.h" +#include "sandybridge.h" + +/* Management Engine is in the southbridge */ +#include "southbridge/intel/bd82x6x/me.h" +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/chromeos.h> +#endif +#if 0 +#include <fdt/libfdt.h> +#endif + +/* + * MRC scrambler seed offsets should be reserved in + * mainboard cmos.layout and not covered by checksum. + */ +#if CONFIG_USE_OPTION_TABLE +#include "option_table.h" +#define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) +#define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) +#define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3) +#else +#define CMOS_OFFSET_MRC_SEED 112 +#define CMOS_OFFSET_MRC_SEED_S3 116 +#define CMOS_OFFSET_MRC_SEED_CHK 120 +#endif + +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) + +struct mrc_data_container { + u32 mrc_signature; // "MRCD" + u32 mrc_data_size; // Actual total size of this structure + u32 mrc_checksum; // IP style checksum + u32 reserved; // For header alignment + u8 mrc_data[0]; // Variable size, platform/run time dependent. +} __attribute__ ((packed)); + +static void save_mrc_data(struct pei_data *pei_data) +{ + u16 c1, c2, checksum; + +#if CONFIG_EARLY_CBMEM_INIT + struct mrc_data_container *mrcdata; + int output_len = ALIGN(pei_data->mrc_output_len, 16); + + /* Save the MRC S3 restore data to cbmem */ + cbmem_initialize(); + mrcdata = cbmem_add + (CBMEM_ID_MRCDATA, + output_len + sizeof(struct mrc_data_container)); + + printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n", + pei_data->mrc_output, mrcdata, output_len); + + mrcdata->mrc_signature = MRC_DATA_SIGNATURE; + mrcdata->mrc_data_size = output_len; + mrcdata->reserved = 0; + memcpy(mrcdata->mrc_data, pei_data->mrc_output, + pei_data->mrc_output_len); + + /* Zero the unused space in aligned buffer. */ + if (output_len > pei_data->mrc_output_len) + memset(mrcdata->mrc_data+pei_data->mrc_output_len, 0, + output_len - pei_data->mrc_output_len); + + mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, + mrcdata->mrc_data_size); +#endif + + /* Save the MRC seed values to CMOS */ + cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); + printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n", + pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); + + cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); + printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", + pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); + + /* Save a simple checksum of the seed values */ + c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, + sizeof(u32)); + c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, + sizeof(u32)); + checksum = add_ip_checksums(sizeof(u32), c1, c2); + + cmos_write(checksum & 0xff, CMOS_OFFSET_MRC_SEED_CHK); + cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1); +} + +#if CONFIG_CHROMEOS +static void prepare_mrc_cache(struct pei_data *pei_data) +{ + const struct fdt_header *fdt_header; + const struct fdt_property *fdtp; + int offset, len; + const char *compatible = "chromeos,flashmap"; + const char *subnode = "rw-mrc-cache"; + const char *property = "reg"; + u32 *data; + struct mrc_data_container *mrc_cache, *mrc_next; + u8 *mrc_region, *region_ptr; + u16 c1, c2, checksum, seed_checksum; + u32 region_size, entry_id = 0; + u64 flashrom_base = 0; + + // preset just in case there is an error + pei_data->mrc_input = NULL; + pei_data->mrc_input_len = 0; + + /* Read scrambler seeds from CMOS */ + pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED); + printk(BIOS_DEBUG, "Read scrambler seed 0x%08x from CMOS 0x%02x\n", + pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); + + pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3); + printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", + pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); + + /* Compute seed checksum and compare */ + c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, + sizeof(u32)); + c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, + sizeof(u32)); + checksum = add_ip_checksums(sizeof(u32), c1, c2); + + seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK); + seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK+1) << 8; + + if (checksum != seed_checksum) { + printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__); + pei_data->scrambler_seed = 0; + pei_data->scrambler_seed_s3 = 0; + return; + } + + fdt_header = cbfs_find_file(CONFIG_FDT_FILE_NAME, CBFS_TYPE_FDT); + + if (!fdt_header) { + printk(BIOS_ERR, "%s: no FDT found!\n", __func__); + return; + } + + offset = fdt_node_offset_by_compatible(fdt_header, 0, compatible); + if (offset < 0) { + printk(BIOS_ERR, "%s: no %s node found!\n", + __func__, compatible); + return; + } + + if (fdt_get_base_addr(fdt_header, offset, &flashrom_base) < 0) { + printk(BIOS_ERR, "%s: no base address in node name!\n", + __func__); + return; + } + + offset = fdt_subnode_offset(fdt_header, offset, subnode); + if (offset < 0) { + printk(BIOS_ERR, "%s: no %s found!\n", __func__, subnode); + return; + } + + fdtp = fdt_get_property(fdt_header, offset, property, &len); + if (!fdtp || (len != 8)) { + printk(BIOS_ERR, "%s: property %s at %p, len %d!\n", + __func__, property, fdtp, len); + return; + } + + data = (u32 *)fdtp->data; + + // Calculate actual address of the MRC cache in memory + region_size = fdt32_to_cpu(data[1]); + mrc_region = region_ptr = (u8*) + ((unsigned long)flashrom_base + fdt32_to_cpu(data[0])); + mrc_cache = mrc_next = (struct mrc_data_container *)mrc_region; + + if (!mrc_cache || mrc_cache->mrc_signature != MRC_DATA_SIGNATURE) { + printk(BIOS_ERR, "%s: invalid MRC data\n", __func__); + return; + } + + if (mrc_cache->mrc_data_size == -1UL) { + printk(BIOS_ERR, "%s: MRC cache not initialized?\n", __func__); + return; + } else { + /* MRC data blocks are aligned within the region */ + u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; + if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { + mrc_size &= ~(MRC_DATA_ALIGN - 1UL); + mrc_size += MRC_DATA_ALIGN; + } + + /* Search for the last filled entry in the region */ + while (mrc_next && + mrc_next->mrc_signature == MRC_DATA_SIGNATURE) { + entry_id++; + mrc_cache = mrc_next; + /* Stay in the mrcdata region defined in fdt */ + if ((entry_id * mrc_size) > region_size) + break; + region_ptr += mrc_size; + mrc_next = (struct mrc_data_container *)region_ptr; + } + entry_id--; + } + + /* Verify checksum */ + if (mrc_cache->mrc_checksum != + compute_ip_checksum(mrc_cache->mrc_data, + mrc_cache->mrc_data_size)) { + printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); + return; + } + + pei_data->mrc_input = mrc_cache->mrc_data; + pei_data->mrc_input_len = mrc_cache->mrc_data_size; + + printk(BIOS_DEBUG, "%s: at %p, entry %u size %x checksum %04x\n", + __func__, pei_data->mrc_input, entry_id, + pei_data->mrc_input_len, mrc_cache->mrc_checksum); +} +#endif + +static const char* ecc_decoder[] = { + "inactive", + "active on IO", + "disabled on IO", + "active" +}; + +/* + * Dump in the log memory controller configuration as read from the memory + * controller registers. + */ +static void report_memory_config(void) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + int i; + + addr_decoder_common = MCHBAR32(0x5000); + addr_decode_ch[0] = MCHBAR32(0x5004); + addr_decode_ch[1] = MCHBAR32(0x5008); + + printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", + (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", + addr_decoder_common & 3, + (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 4) & 3); + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", + i, ch_conf); + printk(BIOS_DEBUG, " ECC %s\n", + ecc_decoder[(ch_conf >> 24) & 3]); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", + ((ch_conf >> 22) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " rank interleave %s\n", + ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", + ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? 16 : 8, + ((ch_conf >> 17) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? "" : ", selected"); + printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", + ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 20) & 1) ? 16 : 8, + ((ch_conf >> 18) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? ", selected" : ""); + } +} + +/** + * Find PEI executable in coreboot filesystem and execute it. + * + * @param pei_data: configuration data for UEFI PEI reference code + */ +void sdram_initialize(struct pei_data *pei_data) +{ + struct sys_info sysinfo; + const char *target = "mrc.bin"; + unsigned long entry; + + /* Wait for ME to be ready */ + intel_early_me_init(); + intel_early_me_uma_size(); + + printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); + + memset(&sysinfo, 0, sizeof(sysinfo)); + + sysinfo.boot_path = pei_data->boot_mode; + +#if CONFIG_CHROMEOS + /* + * Do not pass MRC data in for recovery mode boot, + * Always pass it in for S3 resume. + */ + if (!recovery_mode_enabled() || pei_data->boot_mode == 2) + prepare_mrc_cache(pei_data); + + /* If MRC data is not found we cannot continue S3 resume. */ + if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { + outb(0x6, 0xcf9); + hlt(); + } +#endif + + /* Locate and call UEFI System Agent binary. */ + entry = (unsigned long)cbfs_find_file(target, 0xab); + if (entry) { + int rv; + asm volatile ( + "call *%%ecx\n\t" + :"=a" (rv) : "c" (entry), "a" (pei_data)); + if (rv) { + printk(BIOS_ERR, "MRC returned %d\n", rv); + die("Nonzero MRC return value\n"); + } + } else { + die("UEFI PEI System Agent not found.\n"); + } + + /* For reference print the System Agent version + * after executing the UEFI PEI stage. + */ + u32 version = MCHBAR32(0x5034); + printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", + version >> 24 , (version >> 16) & 0xff, + (version >> 8) & 0xff, version & 0xff); + + intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); + + report_memory_config(); + + /* S3 resume: don't save scrambler seed or MRC data */ + if (pei_data->boot_mode != 2) + save_mrc_data(pei_data); +} + +struct cbmem_entry *get_cbmem_toc(void) +{ + return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); +} + +unsigned long get_top_of_ram(void) +{ + /* Base of TSEG is top of usable DRAM */ + u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return (unsigned long) tom; +} diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h new file mode 100644 index 0000000..124f694 --- /dev/null +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef RAMINIT_H +#define RAMINIT_H + +#include "pei_data.h" + +struct sys_info { + u8 boot_path; +#define BOOT_PATH_NORMAL 0 +#define BOOT_PATH_RESET 1 +#define BOOT_PATH_RESUME 2 +} __attribute__ ((packed)); + +void sdram_initialize(struct pei_data *pei_data); +unsigned long get_top_of_ram(void); +int fixup_sandybridge_errata(void); + +#endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h new file mode 100644 index 0000000..9ff6555 --- /dev/null +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -0,0 +1,224 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ +#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ 1 + +/* Chipset types */ +#define SANDYBRIDGE_MOBILE 0 +#define SANDYBRIDGE_DESKTOP 1 +#define SANDYBRIDGE_SERVER 2 + +/* Device ID for SandyBridge and IvyBridge */ +#define BASE_REV_SNB 0x00 +#define BASE_REV_IVB 0x50 +#define BASE_REV_MASK 0x50 + +/* SandyBridge CPU stepping */ +#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ +#define SNB_STEP_D1 (BASE_REV_SNB + 6) +#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ + +/* IvyBridge CPU stepping */ +#define IVB_STEP_A0 (BASE_REV_IVB + 0) +#define IVB_STEP_B0 (BASE_REV_IVB + 2) +#define IVB_STEP_C0 (BASE_REV_IVB + 4) +#define IVB_STEP_K0 (BASE_REV_IVB + 5) +#define IVB_STEP_D0 (BASE_REV_IVB + 6) + +/* Intel Enhanced Debug region must be 4MB */ +#define IED_SIZE 0x400000 + +/* Northbridge BARs */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ +#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ + +#include "../../../southbridge/intel/bd82x6x/pch.h" + +/* Everything below this line is ignored in the DSDT */ +#ifndef __ACPI__ + +/* Device 0:0.0 PCI configuration space (Host Bridge) */ + +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define X60BAR 0x60 + +#define GGC 0x50 /* GMCH Graphics Control */ + +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_PEG60 (1 << 13) +#define DEVEN_IGD (1 << 4) +#define DEVEN_PEG10 (1 << 3) +#define DEVEN_PEG11 (1 << 2) +#define DEVEN_PEG12 (1 << 1) +#define DEVEN_HOST (1 << 0) + +#define PAM0 0x80 +#define PAM1 0x81 +#define PAM2 0x82 +#define PAM3 0x83 +#define PAM4 0x84 +#define PAM5 0x85 +#define PAM6 0x86 + +#define LAC 0x87 /* Legacy Access Control */ +#define SMRAM 0x88 /* System Management RAM Control */ +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +#define TOM 0xa0 +#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define TSEG 0xb8 /* TSEG base */ +#define TOLUD 0xbc /* Top of Low Used Memory */ + +#define SKPAD 0xdc /* Scratchpad Data */ + +/* Device 0:1.0 PCI configuration space (PCI Express) */ + +#define BCTRL1 0x3e /* 16bit */ + + +/* Device 0:2.0 PCI configuration space (Graphics Device) */ + +#define MSAC 0x62 /* Multi Size Aperture Control */ + + +/* + * MCHBAR + */ + +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or)) + +#define SSKPD 0x5d14 /* 16bit (scratchpad) */ +#define BIOS_RESET_CPL 0x5da8 /* 8bit */ + +/* + * EPBAR - Egress Port Root Complex Register Block + */ + +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) +#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) +#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) + +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCAP2 0x008 /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPVC1MTS 0x028 /* 32bit */ +#define EPVC1IST 0x038 /* 64bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#define PORTARB 0x100 /* 256bit */ + +/* + * DMIBAR + */ + +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) + +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ +#define DMIPVCCAP2 0x008 /* 32bit */ + +#define DMIPVCCCTL 0x00c /* 16bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL0 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ + +#define DMICTL1 0x0f0 /* 32bit */ +#define DMICTL2 0x0fc /* 32bit */ + +#define DMICC 0x208 /* 32bit */ + +#define DMIDRCCFG 0xeb4 /* 32bit */ + +#ifndef __ASSEMBLER__ +static inline void barrier(void) { asm("" ::: "memory"); } + +struct ied_header { + char signature[10]; + u32 size; + u8 reserved[34]; +} __attribute__ ((packed)); + +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE +#define PCI_DEVICE_ID_NB 0x0104 +#endif +#if CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE +#define PCI_DEVICE_ID_NB 0x0154 +#endif + +#ifdef __SMM__ +void intel_sandybridge_finalize_smm(void); +#else /* !__SMM__ */ +int bridge_silicon_revision(void); +void sandybridge_early_initialization(int chipset_type); +void sandybridge_late_initialization(void); + +/* debugging functions */ +void print_pci_devices(void); +void dump_pci_device(unsigned dev); +void dump_pci_devices(void); +void dump_spd_registers(void); +void dump_mem(unsigned start, unsigned end); +#endif /* !__SMM__ */ +#endif +#endif +#endif diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c new file mode 100644 index 0000000..3d8ba96 --- /dev/null +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <stdint.h> +#include <cpu/x86/tsc.h> +#include <cpu/x86/msr.h> + +/** + * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + */ + +void udelay(u32 us) +{ + u32 dword; + tsc_t tsc, tsc1, tscd; + msr_t msr; + u32 fsb = 100, divisor; + u32 d; /* ticks per us */ + u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */ + + msr = rdmsr(0xce); + divisor = (msr.lo >> 8) & 0xff; + + d = fsb * divisor; + + tscd.hi = us / dn; + tscd.lo = (us - tscd.hi * dn) * d; + + tsc1 = rdtsc(); + dword = tsc1.lo + tscd.lo; + if ((dword < tsc1.lo) || (dword < tscd.lo)) { + tsc1.hi++; + } + tsc1.lo = dword; + tsc1.hi += tscd.hi; + + do { + tsc = rdtsc(); + } while ((tsc.hi < tsc1.hi) + || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo))); +} [View Less]

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