November 2020 - coreboot - mail.coreboot.org

One too many I2C busses
by Andy Pont Nov. 25, 2020

Nov. 25, 2020

Hello all, When I boot my board (Intel Comet Lake based) using Coreboot I have one too many I2C busses compared to the stock AMI BIOS. Using i2cdetect under Ubuntu with the stock BIOS it shows: $ i2cdetect -l i2c-3 unknown i915 gmbus dpc N/A i2c-1 unknown Synopsys DesignWare I2C adapter N/A i2c-6 unknown DPDDC-A N/A i2c-4 unknown i915 gmbus misc N/A i2c-2 unknown i915 gmbus dpb N/A i2c-0 unknown SMBus I801 adapter at efa0 N/A i2c-7 unknown DPDDC-C N/A i2c-5 unknown i915 gmbus dpd N/A When I run the same command having booted using Coreboot then it gives: $ i2cdetect -l i2c-3 unknown i915 gmbus dpb N/A i2c-1 unknown SMBus I801 adapter at efa0 N/A i2c-8 unknown DPDDC-C N/A i2c-6 unknown i915 gmbus dpd N/A i2c-4 unknown i915 gmbus dpc N/A i2c-2 unknown Synopsys DesignWare I2C adapter N/A i2c-0 unknown Synopsys DesignWare I2C adapter N/A i2c-7 unknown DPDDC-A N/A i2c-5 unknown i915 gmbus misc N/A I’m guessing these are controlled by the devices that are configured in the devicetree.cb file. What I have currently that appears to be related to I2C is: register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }” device pci 15.0 on end # I2C #0 device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 device pci 19.0 off end # I2C #4 device pci 19.1 off end # I2C #5 device pci 1f.4 on end # SMBus The definitions of “on” and “off” are based on lspci only reporting PCI devices 15.0 and 1f.4 when Linux is booted using the stock BIOS. -Andy.

1 0

Idiots guide to devicetree.cb
by Andy Pont Nov. 25, 2020

Nov. 25, 2020

Hello, Is there an idiots guide to the definitions in devicetree.cb? Trying to make sense of the USB and PCIe configuration stuff. -Andy.

4 4

Assembling all the parts needed for display
by Andy Pont Nov. 24, 2020

Nov. 24, 2020

Hello, I’m trying to find and fit all of the pieces together to get the display running on my custom platform (based on Intel Comet Lake). Here are the known facts... 1. The LCD including the backlight enable and PWM signals are all connected to the eDP interface on the SoC. 2. When I booted the board using the regular AMI BIOS lspci reported: 00:02.0 VGA compatible controller [0300]: Intel Corporation Device [8086:9bca] (rev 04) (prog-if 00 [VGA controller]) DeviceName: Onboard - Video Subsystem: Device [1e50:800b] 3. I have managed to extract a VGA BIOS from the AMI BIOS file but the PCIR structure lists Vendor ID: 0x8086, Device ID: 0x0406 4. I have also managed to extract a VBT binary from the AMI BIOS file and have included it in the Coreboot image: In the debug output when booting there are some VGA related messages: POST: 0x73 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device POST: 0x75 PCI: 00:02.0 init FMAP: area COREBOOT found @ 490200 (11992576 bytes) CBFS: Locating 'vbt.bin' CBFS: 'vbt.bin' not found. FMAP: area COREBOOT found @ 490200 (11992576 bytes) CBFS: Locating 'pci8086,9b41.rom' CBFS: 'pci8086,9b41.rom' not found. PCI Option ROM loading disabled for PCI: 00:02.0 GMA: locate_vbt_vbios: c3e1 d591 6a 52 5f GMA: VBT couldn't be found Questions… 1. Why is the debug output claiming there is no vbt.bin file when it is lised in the output at the end of the built (Size 1168 LZMA, 4608 decompressed)? 2. Why is it searching for pci8086,9b41.rom? I haven’t defined this and the only reference I can see is in the system76/lemp9/Kconfig file? 3. Why doesn’t the VGA BIOS that I have extracted from the AMI BIOS file match the PCI VID/DID of the VGA controller? 4. What else am I missing in order to get the screen to light up? -Andy.

2 4

Coreboot computer doesn't boot with 2 CPU
by d.verdi Nov. 24, 2020

Nov. 24, 2020

Hi to all, I had this problem: when I start the computer with 1 cpu (opteron 6282se) everything is fine, if I add the second CPU, the computer doesn't boot, did you have any suggestions? I put only 2 rams module, following the Asus kgpe d16 manual, is that the correct order (one in the first and one in the last orange socket)? Thank you very much Dave

2 1

Hidden PCI device question (from 4.13 release notes)
by Rafael Send Nov. 23, 2020

Nov. 23, 2020

Hi, Unsure if appending to the 4.13 announcement email was cool, so here's a separate thread. I was using coreboot for a while, but then discovered that something about it was not accessing hidden PCI devices correctly (not enough expertise to figure out what). In my particular case, I'm adding a Thunderbolt controller to an unsupported system. The process for waking it up / unhiding it involves poking an extended capability register of the device while it is still hidden, via the EFI shell. This works fine on stock BIOS + shell, but never worked in coreboot / Tianocore so unfortunately I had to give up using coreboot. Given the "hidden PCI device" change from the 4.13 release notes, should I expect that my use-case may work now? The notes talk about a specific device, but I'm unsure if all hidden devices are treated the same way. Cheers, R

2 3

Memory initialisation error
by Andy Pont Nov. 23, 2020

Nov. 23, 2020

Hello, I have some life out of my Comet Lake based board but the debug output ends with FMAP: area RW_MRC_CACHE found @ 420000 (65536 bytes) MRC: no data in 'RW_MRC_CACHE' PRMRR disabled by config. WEAK: src/soc/intel/cannonlake/romstage/fsp_params.c/mainboard_memory_init_params called FspMemoryInit returned 0x80000007 FspMemoryInit returned an error! The board has all of the memory soldered directly down. The spd.bin file in the build directory is 0 bytes. Is there a way to extract the correct SPD information from either the original UEFI firmware or from a running Linux system? -Andy.

4 11

IRQ routing: how to do the mainboard_picr_data/_intr_data structures?
by Mike Banon Nov. 21, 2020

Nov. 21, 2020

Dear friends, I'm trying to properly program the IRQ tables for Lenovo G505S, because the old IRQ routing is bad and doesn't work for a simple OS like Kolibri. Full details are in the comments under this change: https://review.coreboot.org/c/coreboot/+/46587/ When I used the old picr_data/intr_data values of G505S for the new structures, I got only 1 IRQ working. However, with a copy-paste of AM1I-A - surprisingly 12 IRQs and a laptop boots, but still some problems. Please advise how to compose mainboard_picr_data/_intr_data and also a intel_irq_routing_table, your help will be very much appreciated. Best regards, Mike Banon

4 10

Announcing coreboot 4.13
by Angel Pons Nov. 20, 2020

Nov. 20, 2020

Hi everyone, I'm pleased to announce that coreboot 4.13 has just been released, with release notes as follows: Since 4.12 there were 4200 new commits by over 234 developers. Of these, about 72 contributed to coreboot for the first time. Thank you to all developers who again helped made coreboot better than ever, and a big welcome to our new contributors! New mainboards -------------- - Acer G43T-AM3 - AMD Cereme - Asus A88XM-E FM2+ - Biostar TH61-ITX - BostenTech GBYT4 - Clevo L140CU/L141CU - Dell OptiPlex 9010 - Example Min86 (fake board) - Google Ambassador - Google Asurada - Google Berknip - Google Boldar - Google Boten - Google Burnet - Google Cerise - Google Coachz - Google Dalboz - Google Dauntless - Google Delbin - Google Dirinboz - Google Dooly - Google Drawcia - Google Eldrid - Google Elemi - Google Esche - Google Ezkinil - Google Faffy - Google Fennel - Google Genesis - Google Hayato - Google Lantis - Google Lindar - Google Madoo - Google Magolor - Google Metaknight - Google Morphius - Google Noibat - Google Pompom - Google Shuboz - Google Stern - Google Terrador - Google Todor - Google Trembyle - Google Vilboz - Google Voema - Google Volteer2 - Google Voxel - Google Willow - Google Woomax - Google Wyvern - HP EliteBook 2560p - HP EliteBook Folio 9480m - HP ProBook 6360b - Intel Alderlake-P RVP - Kontron COMe-bSL6 - Lenovo ThinkPad X230s - Open Compute Project DeltaLake - Prodrive Hermes - Purism Librem Mini - Purism Librem Mini v2 - Siemens Chili - Supermicro X11SSH-F - System76 lemp9 Removed mainboards ------------------ - Google Cheza - Google DragonEgg - Google Ripto - Google Sushi - Open Compute Project SonoraPass Significant changes ------------------- ### Native refcode implementation for Bay Trail Bay Trail no longer needs a refcode binary to function properly. The refcode was reimplemented as coreboot code, which should be functionally equivalent. Thus, coreboot only needs to run the MRC.bin to successfully boot Bay Trail. ### Unusual config files to build test more code There's some new highly-unusual config files, whose only purpose is to coerce Jenkins into build-testing several disabled-by-default coreboot config options. This prevents them from silently decaying over time because of build failures. ### Initial support for Intel Trusted eXecution Technology coreboot now supports enabling Intel TXT. Though it's not feature-complete yet, the code allows successfully launching tboot, a Measured Launch Environment. It was tested on Haswell using an Asrock B85M Pro4 mainboard with TPM 2.0 on LPC. Though support for other platforms is still not ready, it is being worked on. The Haswell MRC.bin needs to be patched so as to enable DPR. Given that the MRC binary cannot be redistributed, the best long-term solution is to replace it. ### Hidden PCI devices This new functionality takes advantage of the existing 'hidden' keyword in the devicetree. Since no existing boards were using the keyword, its usage was repurposed to make dealing with some unique PCI devices easier. The particular case here is Intel's PMC (Power Management Controller). During the FSP-S run, the PMC device is made hidden, meaning that its config space looks as if there is no device there (Vendor ID reads as 0xFFFF_FFFF). However, the device does have fixed resources, both MMIO and I/O. These were previously recorded in different places (MMIO was typically an SA fixed resource, and I/O was treated as an LPC resource). With this change, when a device in the tree is marked as 'hidden', it is not probed (`pci_probe_dev()`) but rather assumed to exist so that its resources can be placed in a more natural location. This also adds the ability for the device to participate in SSDT generation. ### Tools for generating SPDs for LP4x memory on TGL and JSL A set of new tools `gen_spd.go` and `gen_part_id.go` are added to automate the process of generating SPDs for LP4x memory and assigning hardware strap IDs for memory parts used on TGL and JSL based boards. The SPD data obtained from memory part vendors has to be massaged to format it correctly as per JEDEC and Intel MRC expectations. These tools take a list of memory parts describing their physical attributes as per their datasheet and convert those attributes into SPD files for the platforms. More details about the tools are added in [README.md](https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/head…. ### New version of SMM loader A new version of the SMM loader which accommodates platforms with over 32 CPU threads. The existing version of SMM loader uses a 64K code/data segment and only a limited number of CPU threads can fit into one segment (because of save state, STM, other features, etc). This loader extends beyond the 64K segment to accommodate additional CPUs and in theory allows as many CPU threads as possible limited only by SMRAM space and not by 64K. By default this loader version is disabled. Please see cpu/x86/Kconfig for more info. ### Address Sanitizer coreboot now has an in-built Address Sanitizer, a runtime memory debugger designed to find out-of-bounds access and use-after-scope bugs. It is made available on all x86 platforms in ramstage and on QEMU i440fx, Intel Apollo Lake, and Haswell in romstage. Further, it can be enabled in romstage on other x86 platforms as well. Refer [ASan documentation](../technotes/asan.md) for more info. ### Initial support for x86_64 The x86_64 code support has been revived and enabled for QEMU. While it started as PoC and the only supported platform is an emulator, there's interest in enabling additional platforms. It would allow to access more than 4GiB of memory at runtime and possibly brings optimised code for faster execution times. It still needs changes in assembly, fixed integer to pointer conversions in C, wrappers for blobs, support for running Option ROMs, among other things. ### Preparations to minimize enabling PCI bus mastering For security reasons, bus mastering should be enabled as late as possible. In coreboot, it's usually not necessary and payloads should only enable it for devices they use. Since not all payloads enable bus mastering properly yet, some Kconfig options were added as an intermediate step to give some sort of "backwards compatibility", which allow enabling or disabling bus mastering by groups. Currently available groups are: * PCI bridges * Any devices For now, "Any devices" is enabled by default to keep the traditional behaviour, which also includes all other options. This is currently necessary, for instance, for libpayload-based payloads as the drivers don't enable bus mastering for PCI bridges. Exceptional cases, that may still need early bus master enabling in the future, should get their own per-reason Kconfig option. Ideally before the next release. ### Early runtime configurability of the console log level Traditionally, we didn't allow the log level of the `romstage` console to be changed at runtime (e.g. via `get_option()`). It turned out that the technical constraints for this (no global variables in `romstage`) vanished long ago, though. The new behaviour is to query `get_option()` now from the second stage that uses the console on. In other words, if the `bootblock` already enables the console, the `romstage` log level can be changed via `get_option()`. Keeping the log level of the first console static ensures that we can see console output even if there's a bug in the more involved code to query options. ### Resource allocator v4 A new revision of resource allocator v4 is now added to coreboot that supports mutiple ranges for allocating resources. Unlike the previous allocator (v3), it does not use the topmost available window for allocation. Instead, it uses the first window within the address space that is available and satisfies the resource request. This allows utilization of the entire available address space and also allows allocation above the 4G boundary. The old resource allocator v3 is still retained for some AMD platforms that do not conform to the requirements of the allocator. Deprecations ------------ ### PCI bus master configuration options In order to minimize the usage of PCI bus mastering, the options we introduced in this release will be dropped in a future release again. For more details, please see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering-in-coreboot). ### Resource allocator v3 Resource allocator v3 is retained in coreboot tree because the following platforms do not conform to the requirements of the resource allocation i.e. not all the fixed resources of the platform are provided during the `read_resources()` operation: * northbridge/amd/pi/00630F01 * northbridge/amd/pi/00730F01 * northbridge/amd/pi/00660F01 * northbridge/amd/agesa/family14 * northbridge/amd/agesa/family15tn * northbridge/amd/agesa/family16kb In order to have a single unified allocator in coreboot, this notice is being added to ensure that the platforms listed above are fixed before the next release. If there is interest in maintaining support for these platforms beyond the next release, please ensure that the platforms are fixed to conform to the expectations of resource allocation. Best regards, Angel Pons

2 1

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com Nov. 20, 2020

Nov. 20, 2020

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1436518: Error handling issues (CHECKED_RETURN) /src/lib/hardwaremain.c: 447 in main() ________________________________________________________________________________________________________ *** CID 1436518: Error handling issues (CHECKED_RETURN) /src/lib/hardwaremain.c: 447 in main() 441 cbmem_initialize(); 442 443 timestamp_add_now(TS_START_RAMSTAGE); 444 post_code(POST_ENTRY_RAMSTAGE); 445 446 /* Handoff sleep type from romstage. */ >>> CID 1436518: Error handling issues (CHECKED_RETURN) >>> Calling "acpi_is_wakeup_s3" without checking return value (as is done elsewhere 89 out of 93 times). 447 acpi_is_wakeup_s3(); 448 threads_initialize(); 449 450 /* Schedule the static boot state entries. */ 451 boot_state_schedule_static_entries(); 452 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

1 0

System gcc requirements
by Branden Waldner Nov. 20, 2020

Nov. 20, 2020

I recently looked in to why I couldn't build coreboot on one of my systems any longer and I think I found the cause. It looks like vboot uses features not available in gcc 6 on Debian Stretch. I actually did manage to get it to build and work by commenting out the offending gcc warning flags and a fallthrough switch attribute, but that's kind of pointless. Is there an expected minimal system gcc version and if so, is it documented? I couldn't find it noted anywhere. Branden

8 31