coreboot November 2020

coreboot@coreboot.org

43 participants
37 discussions

Is HP ProLiant DL360e Gen8 supported in Coreboot?
by jjs8＠gmx.com 09 Nov '20

09 Nov '20

Hello! I'm trying to find if my hardware supports Coreboot. I found 1 table which is retired, second that is probably not retired and then current documentation that doesn't seem to say as much. So, sorry if I missed it. Will Coreboot work with HP ProLiant DL360e Gen8? Flashrom worked ok but not great. Northbridge is Intel Sandy Bridge-E 07, Southbridge Intel X79 05. References: https://www.coreboot.org/Supported_Chipsets_and_Devices https://coreboot.org/status/board-status.html https://support.hpe.com/hpesc/public/docDisplay?docId=c03361169&docLocale=e… https://browser.geekbench.com/geekbench3/1879558 https://doc.coreboot.org/mainboard/index.html https://doc.coreboot.org/northbridge/intel/sandybridge/index.html Flashrom log: ------------------------ flashrom v1.2 on Linux 5.4.0-42-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found chipset "Intel C60x/X79". Enabling flash write... FREG0: Flash Descriptor region (0x00000000-0x0000ffff) is read-only. FREG2: Management Engine region (0x00010000-0x001fffff) is locked. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see https://flashrom.org/ME for details. At least some flash regions are read protected. You have to use a flash layout and include only accessible regions. For write operations, you'll additionally need the --noverify-all switch. See manpage for more details. OK. Found Macronix flash chip "MX25L1605" (2048 kB, SPI) mapped at physical address 0x00000000ffe00000. Found Macronix flash chip "MX25L1605A/MX25L1606E/MX25L1608E" (2048 kB, SPI) mapped at physical address 0x00000000ffe00000. Found Macronix flash chip "MX25L1605D/MX25L1608D/MX25L1673E" (2048 kB, SPI) mapped at physical address 0x00000000ffe00000. Multiple flash chip definitions match the detected chip(s): "MX25L1605", "MX25L1605A/MX25L1606E/MX25L1608E", "MX25L1605D/MX25L1608D/MX25L1673E" Please specify which chip definition to use with the -c <chipname> option. ------------------------

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AMD AGESA: Missing PCI bridge 00:15.2 on Asus F2A85-M PRO
by Paul Menzel 08 Nov '20

08 Nov '20

Dear coreboot folks, Trying to finish the Asus F2A85-M PRO coreboot port (AMD Family 15h/Hudson), the internal network device does not work with the state from [1]. With the vendor firmware 6601, it is 04:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] (rev 09) behind PCI bridge 00:15.2. > -[0000:00]-+-00.0 > +-00.2 > +-01.0 > +-01.1 > +-10.0 > +-10.1 > +-11.0 > +-12.0 > +-12.2 > +-13.0 > +-13.2 > +-14.0 > +-14.2 > +-14.3 > +-14.4-[01]-- > +-15.0-[02]-- > +-15.1-[03]----00.0 > +-15.2-[04]----00.0 > +-18.0 > +-18.1 > +-18.2 > +-18.3 > +-18.4 > \-18.5 In the current state [1], coreboot says device 00:15.2 is disabled > Show all devs... After init. > Root Device: enabled 1 > CPU_CLUSTER: 0: enabled 1 > DOMAIN: 0000: enabled 1 > APIC: 10: enabled 1 > PCI: 00:00.0: enabled 1 > PCI: 00:00.2: enabled 1 > PCI: 00:01.0: enabled 1 > PCI: 00:01.1: enabled 1 > PCI: 00:02.0: enabled 0 > PCI: 00:03.0: enabled 0 > PCI: 00:04.0: enabled 0 > PCI: 00:05.0: enabled 0 > PCI: 00:06.0: enabled 0 > PCI: 00:07.0: enabled 0 > PCI: 00:08.0: enabled 0 > PCI: 00:10.0: enabled 1 > PCI: 00:10.1: enabled 1 > PCI: 00:11.0: enabled 1 > PCI: 00:12.0: enabled 1 > PCI: 00:12.2: enabled 1 > PCI: 00:13.0: enabled 1 > PCI: 00:13.2: enabled 1 > PCI: 00:14.0: enabled 1 > PCI: 00:14.1: enabled 0 > PCI: 00:14.2: enabled 1 > PCI: 00:14.3: enabled 1 > PCI: 00:14.4: enabled 1 > PCI: 00:14.7: enabled 0 > PCI: 00:15.0: enabled 1 > PCI: 00:15.1: enabled 1 > PCI: 00:15.2: enabled 0 > PCI: 00:18.0: enabled 1 But it is enabled in the devicetree `src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb`. device pci 15.2 on end # PCI bridge Please find the spew log attached. Any help is appreciated. Kind regards, Paul [1]: https://review.coreboot.org/c/coreboot/+/46021/ "mb/asus/f2a85-m_pro: Enable super-i/o LDNs 0x0f and 0x14"

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Native RAM init
by Alif Ilhan 06 Nov '20

06 Nov '20

hello, Is there a way to extract mrc.bin from a normal(not chromehook rom) bios binary from the flash dump? There's no chromebook available with the Atom N2600 chip. There is one with Atom N570, but will it work? If not then I want to know if native ram init is supported in CedarTrail chipsets. I think it should be because Sandy bridge is supported and they were simillar(I think). CedarTail has no FSPs available on github so I must have to build the non-FPS version.....which means I cannot get mrc.bin.

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 06 Nov '20

06 Nov '20

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 2 new defect(s) introduced to coreboot found with Coverity Scan. 91 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 1436157: Memory - illegal accesses (OVERRUN) /src/lib/fw_config.c: 86 in fw_config_get_found() ________________________________________________________________________________________________________ *** CID 1436157: Memory - illegal accesses (OVERRUN) /src/lib/fw_config.c: 86 in fw_config_get_found() 80 return __ffs64(mask); 81 } 82 83 const struct fw_config *fw_config_get_found(uint64_t field_mask) 84 { 85 const struct fw_config *config; >>> CID 1436157: Memory - illegal accesses (OVERRUN) >>> Overrunning array "cached_configs" of 64 4-byte elements at element index 4294967295 (byte offset 17179869183) using index "probe_index(field_mask)" (which evaluates to 4294967295). 86 config = cached_configs[probe_index(field_mask)]; 87 if (config && config->mask == field_mask) 88 return config; 89 90 return NULL; 91 } ** CID 1436156: Memory - corruptions (OVERRUN) /src/lib/fw_config.c: 116 in fw_config_init() ________________________________________________________________________________________________________ *** CID 1436156: Memory - corruptions (OVERRUN) /src/lib/fw_config.c: 116 in fw_config_init() 110 if (!dev->probe_list) 111 continue; 112 113 for (probe = dev->probe_list; probe && probe->mask != 0; probe++) { 114 if (fw_config_probe(probe)) { 115 match = true; >>> CID 1436156: Memory - corruptions (OVERRUN) >>> Overrunning array "cached_configs" of 64 4-byte elements at element index 4294967295 (byte offset 17179869183) using index "probe_index(probe->mask)" (which evaluates to 4294967295). 116 cached_configs[probe_index(probe->mask)] = probe; 117 break; 118 } 119 } 120 121 if (!match) { ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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Universal Payload - RFC and Invitation from Universal Payload community
by Banik, Subrata 05 Nov '20

05 Nov '20

HI All, coreboot is a modular design with hardware initialization stage followed by a payload to boot OS https://doc.coreboot.org/payloads.html There is a new initiative to standardize the bootloader to payload interface. The initiative is called Universal Payload project and details can be found @ https://github.com/universalpayload/Introduction The goal for this initiative is interoperability between bootloaders and payloads so that different bootloaders can work with different payloads. An early draft of the spec can be found @ https://universalpayload.github.io/documentation/spec/spec.html. The Universal Payload community welcomes feedback and contributions. We are developing various POC codes to demonstrate the concept. One POC uses coreboot as the bootloader and EDKII UEFI as the payload https://github.com/universalpayload/coreboot/tree/universal_payload Thanks, Subrata

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Coreboot Hardware
by nirmalarasu＠hotmail.com 02 Nov '20

02 Nov '20

Hi all, I am a newbie for coreboot development . I am looking for open source hardware where i can debug and play around with coreboot features. Any recommendation for debug capable hardware which available in market? -Arun

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Convenient payload development part 1: QEMU Make targets
by Nico Huber 01 Nov '20

01 Nov '20

Hi folks, I'm currently looking into making payload builds and testing more convenient. That involves, among other things, QEMU make targets with default options that should ease coreboot development, incre- mental builds of payloads, support for local changes in payload dirs. So far I've finished the QEMU hook-up for x86 targets [1]. The idea is to have a Make target `qemu` that is automatically added if a com- patible coreboot target is selected. With some luck, adding more coreboot targets should be as easy as specifying the QEMU binary to use, e.g. QEMU-$(CONFIG_BOARD_EMULATION_...) ?= qemu-system-... What I only learned recently: QEMU supports configuration files that ease adding specific devices to emulate (compared to ever growing command lines). I wrote one for the Intel Q35 emulation target [2] with most of the (PCI) devices one would expect with that chipset. This should help to test in an environment that comes closer to real boards. Comments and review welcome! Cheers, Nico [1] https://review.coreboot.org/c/coreboot/+/46767 [2] https://review.coreboot.org/c/coreboot/+/46768

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coreboot November 2020