coreboot August 2018

coreboot@coreboot.org

43 participants
110 discussions

Fwd: Problem with boot coreboot
by Mike Banon 08 Aug '18

08 Aug '18

Forwarding this message: I used a flash MBR . with this form => 63 15730625 da0 MBR (7.5G) 63 1985 - free - (993K) 2048 15728640 1 ntfs [active] (7.5G) But It did not work and it shows previous message again. Could you guide me ؟ Thanks Zahra On Tue, Aug 7, 2018 at 11:40 PM zahra rahimkhani <zrahimkhani2014(a)gmail.com> wrote: > > Thank you very much for your help. > could you tell me how to repairhatd driver ? > > Thanks , > > On 07/08/2018 7:59 PM, "Mike Banon" <mikebdp2(a)gmail.com> wrote: >> >> Have you tried repairing the bootloader at your hard drive? >> are you using GRUB2, and your partitions are MBR or GPT? >> (SeaBIOS supports MBR only, so GRUB2 needs to be installed to MBR) >> >> On Tue, Aug 7, 2018 at 11:13 AM, zahra rahimkhani >> <zrahimkhani2014(a)gmail.com> wrote: >> > Hello friends >> > >> > I compiled coreboot and seabios based on >> > https://review.coreboot.org/cgit/board-status.git/plain/intel/minnowmax/4.5… >> > >> > but my Freebsd did not boot and show this message. >> > >> > Running option rom at c000:0003 >> > Turning on vga text mode console >> > SeaBIOS (version rel-1.11.2-0-gf9626cc) >> > EHCI init on dev 00:1d.0 (regs=0xd061e020) >> > WARNING - Timeout at i8042_flush:71! >> > AHCI controller at 00:13.0, iobase 0xd061d000, irq 10 >> > Searching bootorder for: /pci@i0cf8/*@12 >> > Found 0 lpt ports >> > Found 1 serial ports >> > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@1/*@0/*@0,0 >> > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@1 >> > USB MSC vendor='UFD 2.0' product='Silicon-Power8G' rev='1100' type=0 >> > removable=1 >> > USB MSC blksize=512 sectors=15730688 >> > Initialized USB HUB (1 ports used) >> > All threads complete. >> > Scan for option roms >> > >> > Press ESC for boot menu. >> > >> > Searching bootorder for: HALT >> > drive 0x000f62c0: PCHS=0/0/0 translation=lba LCHS=979/255/63 s=15730688 >> > Space available for UMB: cd800-ed800, f5b60-f62c0 >> > Returned 253952 bytes of ZoneHigh >> > e820 map has 18 items: >> > 0: 0000000000000000 - 000000000009fc00 = 1 RAM >> > 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED >> > 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED >> > 3: 0000000000100000 - 0000000020000000 = 1 RAM >> > 4: 0000000020000000 - 0000000020100000 = 2 RESERVED >> > 5: 0000000020100000 - 000000007ad9c000 = 1 RAM >> > 6: 000000007ad9c000 - 0000000080000000 = 2 RESERVED >> > 7: 00000000e0000000 - 00000000f0000000 = 2 RESERVED >> > 8: 00000000feb00000 - 00000000fec01000 = 2 RESERVED >> > 9: 00000000fed01000 - 00000000fed02000 = 2 RESERVED >> > 10: 00000000fed03000 - 00000000fed04000 = 2 RESERVED >> > 11: 00000000fed05000 - 00000000fed06000 = 2 RESERVED >> > 12: 00000000fed08000 - 00000000fed09000 = 2 RESERVED >> > 13: 00000000fed0c000 - 00000000fed10000 = 2 RESERVED >> > 14: 00000000fed1c000 - 00000000fed1d000 = 2 RESERVED >> > 15: 00000000fee00000 - 00000000fee01000 = 2 RESERVED >> > 16: 00000000fef00000 - 00000000ff000000 = 2 RESERVED >> > 17: 00000000ff800000 - 0000000100000000 = 2 RESERVED >> > enter handle_19: >> > NULL >> > Booting from Hard Disk... >> > Booting from 0000:7c00 >> > >> > I would be grateful if you guide me . >> > >> > Thanks, >> > >> > -- >> > coreboot mailing list: coreboot(a)coreboot.org >> > https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Problem with boot coreboot
by zahra rahimkhani 08 Aug '18

08 Aug '18

Also, I got a grub2 alone on flash . it is MBR t with his form => 63 15730625 da0 MBR (7.5G) 63 1985 - free - (993K) 2048 15728640 1 linux-data (7.5G) => 63 15730625 diskid/DISK-1501938400200044 MBR (7.5G) 63 1985 - free - (993K) 2048 15728640 1 linux-data (7.5G) But it did not work still . please guide me that solve my problem . Thank you for your time . On Tue, Aug 7, 2018 at 11:58 PM zahra rahimkhani <zrahimkhani2014(a)gmail.com> wrote: > > I used a flash MBR . > with this form > => 63 15730625 da0 MBR (7.5G) > 63 1985 - free - (993K) > 2048 15728640 1 ntfs [active] (7.5G) > > > But It did not work and it shows previous message again. > > Could you guide me ؟ > > Thanks > Zahra > > On Tue, Aug 7, 2018 at 11:40 PM zahra rahimkhani < > zrahimkhani2014(a)gmail.com> wrote: > >> Thank you very much for your help. >> could you tell me how to repairhatd driver ? >> >> Thanks , >> On 07/08/2018 7:59 PM, "Mike Banon" <mikebdp2(a)gmail.com> wrote: >> >>> Have you tried repairing the bootloader at your hard drive? >>> are you using GRUB2, and your partitions are MBR or GPT? >>> (SeaBIOS supports MBR only, so GRUB2 needs to be installed to MBR) >>> >>> On Tue, Aug 7, 2018 at 11:13 AM, zahra rahimkhani >>> <zrahimkhani2014(a)gmail.com> wrote: >>> > Hello friends >>> > >>> > I compiled coreboot and seabios based on >>> > >>> https://review.coreboot.org/cgit/board-status.git/plain/intel/minnowmax/4.5… >>> > >>> > but my Freebsd did not boot and show this message. >>> > >>> > Running option rom at c000:0003 >>> > Turning on vga text mode console >>> > SeaBIOS (version rel-1.11.2-0-gf9626cc) >>> > EHCI init on dev 00:1d.0 (regs=0xd061e020) >>> > WARNING - Timeout at i8042_flush:71! >>> > AHCI controller at 00:13.0, iobase 0xd061d000, irq 10 >>> > Searching bootorder for: /pci@i0cf8/*@12 >>> > Found 0 lpt ports >>> > Found 1 serial ports >>> > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@1/*@0/*@0,0 >>> > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@1 >>> > USB MSC vendor='UFD 2.0' product='Silicon-Power8G' rev='1100' type=0 >>> > removable=1 >>> > USB MSC blksize=512 sectors=15730688 >>> > Initialized USB HUB (1 ports used) >>> > All threads complete. >>> > Scan for option roms >>> > >>> > Press ESC for boot menu. >>> > >>> > Searching bootorder for: HALT >>> > drive 0x000f62c0: PCHS=0/0/0 translation=lba LCHS=979/255/63 s=15730688 >>> > Space available for UMB: cd800-ed800, f5b60-f62c0 >>> > Returned 253952 bytes of ZoneHigh >>> > e820 map has 18 items: >>> > 0: 0000000000000000 - 000000000009fc00 = 1 RAM >>> > 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED >>> > 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED >>> > 3: 0000000000100000 - 0000000020000000 = 1 RAM >>> > 4: 0000000020000000 - 0000000020100000 = 2 RESERVED >>> > 5: 0000000020100000 - 000000007ad9c000 = 1 RAM >>> > 6: 000000007ad9c000 - 0000000080000000 = 2 RESERVED >>> > 7: 00000000e0000000 - 00000000f0000000 = 2 RESERVED >>> > 8: 00000000feb00000 - 00000000fec01000 = 2 RESERVED >>> > 9: 00000000fed01000 - 00000000fed02000 = 2 RESERVED >>> > 10: 00000000fed03000 - 00000000fed04000 = 2 RESERVED >>> > 11: 00000000fed05000 - 00000000fed06000 = 2 RESERVED >>> > 12: 00000000fed08000 - 00000000fed09000 = 2 RESERVED >>> > 13: 00000000fed0c000 - 00000000fed10000 = 2 RESERVED >>> > 14: 00000000fed1c000 - 00000000fed1d000 = 2 RESERVED >>> > 15: 00000000fee00000 - 00000000fee01000 = 2 RESERVED >>> > 16: 00000000fef00000 - 00000000ff000000 = 2 RESERVED >>> > 17: 00000000ff800000 - 0000000100000000 = 2 RESERVED >>> > enter handle_19: >>> > NULL >>> > Booting from Hard Disk... >>> > Booting from 0000:7c00 >>> > >>> > I would be grateful if you guide me . >>> > >>> > Thanks, >>> > >>> > -- >>> > coreboot mailing list: coreboot(a)coreboot.org >>> > https://mail.coreboot.org/mailman/listinfo/coreboot >>> >>

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Re: [coreboot] Problem with boot coreboot
by zahra rahimkhani 08 Aug '18

08 Aug '18

Thank you very much for your help. could you tell me how to repairhatd driver ? Thanks , On 07/08/2018 7:59 PM, "Mike Banon" <mikebdp2(a)gmail.com> wrote: > Have you tried repairing the bootloader at your hard drive? > are you using GRUB2, and your partitions are MBR or GPT? > (SeaBIOS supports MBR only, so GRUB2 needs to be installed to MBR) > > On Tue, Aug 7, 2018 at 11:13 AM, zahra rahimkhani > <zrahimkhani2014(a)gmail.com> wrote: > > Hello friends > > > > I compiled coreboot and seabios based on > > https://review.coreboot.org/cgit/board-status.git/plain/ > intel/minnowmax/4.5-306-g00ad7ff/2016-11-17T17_00_43Z/ > > > > but my Freebsd did not boot and show this message. > > > > Running option rom at c000:0003 > > Turning on vga text mode console > > SeaBIOS (version rel-1.11.2-0-gf9626cc) > > EHCI init on dev 00:1d.0 (regs=0xd061e020) > > WARNING - Timeout at i8042_flush:71! > > AHCI controller at 00:13.0, iobase 0xd061d000, irq 10 > > Searching bootorder for: /pci@i0cf8/*@12 > > Found 0 lpt ports > > Found 1 serial ports > > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@1/*@0/*@0,0 > > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@1 > > USB MSC vendor='UFD 2.0' product='Silicon-Power8G' rev='1100' type=0 > > removable=1 > > USB MSC blksize=512 sectors=15730688 > > Initialized USB HUB (1 ports used) > > All threads complete. > > Scan for option roms > > > > Press ESC for boot menu. > > > > Searching bootorder for: HALT > > drive 0x000f62c0: PCHS=0/0/0 translation=lba LCHS=979/255/63 s=15730688 > > Space available for UMB: cd800-ed800, f5b60-f62c0 > > Returned 253952 bytes of ZoneHigh > > e820 map has 18 items: > > 0: 0000000000000000 - 000000000009fc00 = 1 RAM > > 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED > > 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED > > 3: 0000000000100000 - 0000000020000000 = 1 RAM > > 4: 0000000020000000 - 0000000020100000 = 2 RESERVED > > 5: 0000000020100000 - 000000007ad9c000 = 1 RAM > > 6: 000000007ad9c000 - 0000000080000000 = 2 RESERVED > > 7: 00000000e0000000 - 00000000f0000000 = 2 RESERVED > > 8: 00000000feb00000 - 00000000fec01000 = 2 RESERVED > > 9: 00000000fed01000 - 00000000fed02000 = 2 RESERVED > > 10: 00000000fed03000 - 00000000fed04000 = 2 RESERVED > > 11: 00000000fed05000 - 00000000fed06000 = 2 RESERVED > > 12: 00000000fed08000 - 00000000fed09000 = 2 RESERVED > > 13: 00000000fed0c000 - 00000000fed10000 = 2 RESERVED > > 14: 00000000fed1c000 - 00000000fed1d000 = 2 RESERVED > > 15: 00000000fee00000 - 00000000fee01000 = 2 RESERVED > > 16: 00000000fef00000 - 00000000ff000000 = 2 RESERVED > > 17: 00000000ff800000 - 0000000100000000 = 2 RESERVED > > enter handle_19: > > NULL > > Booting from Hard Disk... > > Booting from 0000:7c00 > > > > I would be grateful if you guide me . > > > > Thanks, > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > https://mail.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Problem with boot coreboot
by Mike Banon 07 Aug '18

07 Aug '18

Have you tried repairing the bootloader at your hard drive? are you using GRUB2, and your partitions are MBR or GPT? (SeaBIOS supports MBR only, so GRUB2 needs to be installed to MBR) On Tue, Aug 7, 2018 at 11:13 AM, zahra rahimkhani <zrahimkhani2014(a)gmail.com> wrote: > Hello friends > > I compiled coreboot and seabios based on > https://review.coreboot.org/cgit/board-status.git/plain/intel/minnowmax/4.5… > > but my Freebsd did not boot and show this message. > > Running option rom at c000:0003 > Turning on vga text mode console > SeaBIOS (version rel-1.11.2-0-gf9626cc) > EHCI init on dev 00:1d.0 (regs=0xd061e020) > WARNING - Timeout at i8042_flush:71! > AHCI controller at 00:13.0, iobase 0xd061d000, irq 10 > Searching bootorder for: /pci@i0cf8/*@12 > Found 0 lpt ports > Found 1 serial ports > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@1/*@0/*@0,0 > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@1 > USB MSC vendor='UFD 2.0' product='Silicon-Power8G' rev='1100' type=0 > removable=1 > USB MSC blksize=512 sectors=15730688 > Initialized USB HUB (1 ports used) > All threads complete. > Scan for option roms > > Press ESC for boot menu. > > Searching bootorder for: HALT > drive 0x000f62c0: PCHS=0/0/0 translation=lba LCHS=979/255/63 s=15730688 > Space available for UMB: cd800-ed800, f5b60-f62c0 > Returned 253952 bytes of ZoneHigh > e820 map has 18 items: > 0: 0000000000000000 - 000000000009fc00 = 1 RAM > 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED > 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED > 3: 0000000000100000 - 0000000020000000 = 1 RAM > 4: 0000000020000000 - 0000000020100000 = 2 RESERVED > 5: 0000000020100000 - 000000007ad9c000 = 1 RAM > 6: 000000007ad9c000 - 0000000080000000 = 2 RESERVED > 7: 00000000e0000000 - 00000000f0000000 = 2 RESERVED > 8: 00000000feb00000 - 00000000fec01000 = 2 RESERVED > 9: 00000000fed01000 - 00000000fed02000 = 2 RESERVED > 10: 00000000fed03000 - 00000000fed04000 = 2 RESERVED > 11: 00000000fed05000 - 00000000fed06000 = 2 RESERVED > 12: 00000000fed08000 - 00000000fed09000 = 2 RESERVED > 13: 00000000fed0c000 - 00000000fed10000 = 2 RESERVED > 14: 00000000fed1c000 - 00000000fed1d000 = 2 RESERVED > 15: 00000000fee00000 - 00000000fee01000 = 2 RESERVED > 16: 00000000fef00000 - 00000000ff000000 = 2 RESERVED > 17: 00000000ff800000 - 0000000100000000 = 2 RESERVED > enter handle_19: > NULL > Booting from Hard Disk... > Booting from 0000:7c00 > > I would be grateful if you guide me . > > Thanks, > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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Problem with boot coreboot
by zahra rahimkhani 07 Aug '18

07 Aug '18

Hello friends I compiled coreboot and seabios based on https://review.coreboot.org/cgit/board-status.git/plain/intel/minnowmax/4.5… but my Freebsd did not boot and show this message. Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version rel-1.11.2-0-gf9626cc) EHCI init on dev 00:1d.0 (regs=0xd061e020) WARNING - Timeout at i8042_flush:71! AHCI controller at 00:13.0, iobase 0xd061d000, irq 10 Searching bootorder for: /pci@i0cf8/*@12 Found 0 lpt ports Found 1 serial ports Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@1/*@0/*@0,0 Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@1 USB MSC vendor='UFD 2.0' product='Silicon-Power8G' rev='1100' type=0 removable=1 USB MSC blksize=512 sectors=15730688 Initialized USB HUB (1 ports used) All threads complete. Scan for option roms Press ESC for boot menu. Searching bootorder for: HALT drive 0x000f62c0: PCHS=0/0/0 translation=lba LCHS=979/255/63 s=15730688 Space available for UMB: cd800-ed800, f5b60-f62c0 Returned 253952 bytes of ZoneHigh e820 map has 18 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 0000000020000000 = 1 RAM 4: 0000000020000000 - 0000000020100000 = 2 RESERVED 5: 0000000020100000 - 000000007ad9c000 = 1 RAM 6: 000000007ad9c000 - 0000000080000000 = 2 RESERVED 7: 00000000e0000000 - 00000000f0000000 = 2 RESERVED 8: 00000000feb00000 - 00000000fec01000 = 2 RESERVED 9: 00000000fed01000 - 00000000fed02000 = 2 RESERVED 10: 00000000fed03000 - 00000000fed04000 = 2 RESERVED 11: 00000000fed05000 - 00000000fed06000 = 2 RESERVED 12: 00000000fed08000 - 00000000fed09000 = 2 RESERVED 13: 00000000fed0c000 - 00000000fed10000 = 2 RESERVED 14: 00000000fed1c000 - 00000000fed1d000 = 2 RESERVED 15: 00000000fee00000 - 00000000fee01000 = 2 RESERVED 16: 00000000fef00000 - 00000000ff000000 = 2 RESERVED 17: 00000000ff800000 - 0000000100000000 = 2 RESERVED enter handle_19: NULL Booting from Hard Disk... Booting from 0000:7c00 I would be grateful if you guide me . Thanks,

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Re: [coreboot] Denverton FSP usage
by Hilbert Tu(杜睿哲_Pegatron) 07 Aug '18

07 Aug '18

I found the related setting under “Generic Drivers” -> “Use FSP TempRamInit & TempRamExit APIs”. Ha. -Hilbert From: Hilbert Tu(杜睿哲_Pegatron) Sent: Monday, August 06, 2018 6:21 PM To: coreboot(a)coreboot.org Subject: Denverton FSP usage Hi, I have an Intel Denverton (C3538) CPU board and try to use coreboot 4.8 to boot it up. The FSP I have consisted of 3 parts as FSP-T, FSP-M, FSP-S, but I don’t see the settings for specifying FSP-T in coreboot’s menuconfig. From the debug output, I got error code 2526 and I doubt it is due to lack of including FSP-T. Is there anyone can tell how to correctly use FSP-T? Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。

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Denverton FSP usage
by Hilbert Tu(杜睿哲_Pegatron) 06 Aug '18

06 Aug '18

Hi, I have an Intel Denverton (C3538) CPU board and try to use coreboot 4.8 to boot it up. The FSP I have consisted of 3 parts as FSP-T, FSP-M, FSP-S, but I don’t see the settings for specifying FSP-T in coreboot’s menuconfig. From the debug output, I got error code 2526 and I doubt it is due to lack of including FSP-T. Is there anyone can tell how to correctly use FSP-T? Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。

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Re: [coreboot] USB to Serial Converters
by David Hendricks 05 Aug '18

05 Aug '18

Hi Zahra, Yes, I used the 6-pin serial port header. Also, make sure the microcode header(s) you include correspond to the CPUID of your processor. The E3825 and E3826 use different microcode headers, so M0130679901.h will not work for you. Please keep the coreboot mailing list CC'd. I haven't done anything with Minnowboard in several months and others may be able to help. On Thu, Aug 2, 2018 at 5:01 PM, zahra rahimkhani <zrahimkhani2014(a)gmail.com> wrote: > Hi David > > Thank you for your help. > I extract your file and got M0130679901.h as Microcode but my board does > not work it did not show anything. > I use E3825. > In previous notes, you told "My guess is that you don't have > CONFIG_ENABLE_BUILTIN_COM1 selected > (under "Chipset"), which is an option you have to set in addition to > the stuff under "Console." > but in your config, you had not enabled this option. > Could you help me with this and Did you use 6 pins that are separated on > board for console port? > I do not know what is my problem .it did not show anything log. > > > > Thank you for your time. > Zahra > > > > On Wed, Aug 1, 2018 at 2:04 AM David Hendricks <david.hendricks(a)gmail.com> > wrote: > >> Hi Zahra, >> That header may be out of date >> (https://mail.coreboot.org/pipermail/coreboot/2017-August/084800.html). >> >> I had to manually download the microcode file corresponding to my >> processor SKU from Intel. Use the link I sent you earlier to download >> Baytrail_FSP_Gold4.tgz and see if the microcode headers included in >> that tarball match your processor. The Atom on my Minnowboard Turbot >> has a CPUID of 30679, so I needed to use M0130679901.h. >> >> (note that the Minnowboard Max uses an Atom E3825, while the Turbot >> uses an E3826 dual-core SoC or E3845 quad-core SoC) >> >> On Mon, Jul 30, 2018 at 2:36 AM, zahra rahimkhani >> <zrahimkhani2014(a)gmail.com> wrote: >> > >> > Dear David >> > >> > for Microcode file I just it from coreboot source from this path >> > coreboot/3rdparty/blobs/soc/intel/baytrail/microcode_blob.h >> > >> > Is that good ? >> > >> > Thanks , >> > >> > >> > On Sun, Jul 29, 2018 at 1:18 PM zahra rahimkhani < >> zrahimkhani2014(a)gmail.com> >> > wrote: >> >> >> >> Hi David, >> >> >> >> Thank you very much for your guide. >> >> >> >> I got this comments on my config and changes it based on your config. >> >> But I can not see any thing on output. >> >> Could you tell me which Uart pins do you use on Minnowboard max >> >> >> >> I used it 6 pin that are separately on board . >> >> >> >> I would be grateful if you guide me . >> >> I got my new config here . >> >> https://paste.flashrom.org/view.php?id=3097 >> >> >> >> Also , Could you tell me what is this parameter >> >> CONFIG_UART_FOR_CONSOLE=0 >> >> and >> >> CONFIG_DRIVERS_UART_8250IO >> >> >> >> Cheers! >> >> Zahra >> >> >> >> >> >> >> >> On Fri, Jul 27, 2018 at 11:06 AM David Hendricks >> >> <david.hendricks(a)gmail.com> wrote: >> >>> >> >>> Hi Zahra, >> >>> >> >>>> I got my config file here >> >>>> https://paste.flashrom.org/view.php?id=3096 >> >>> >> >>> >> >>> Thanks, that helps a lot! >> >>> >> >>> The last config that I tested is >> >>> https://review.coreboot.org/cgit/board-status.git/plain/ >> intel/minnowmax/4.6-1358-g49d117c69f/2017-09-06T06_53_39Z/config.txt >> >>> >> >>> If you diff my config and yours, it seems you have several options >> >>> disabled which I think you should try enabling: >> >>> CONFIG_HAVE_IFD_BIN >> >>> CONFIG_HAVE_ME_BIN >> >>> CONFIG_TTYS0_LCS >> >>> CONFIG_DRIVERS_UART_8250IO >> >>> CONFIG_IFD_BIN_PATH >> >>> CONFIG_ME_BIN_PATH >> >>> CONFIG_LOCK_MANAGEMENT_ENGINE >> >>> CONFIG_DRIVERS_UART >> >>> CONFIG_CONSOLE_SERIAL >> >>> CONFIG_CONSOLE_SERIAL_115200 >> >>> >> >>> You can find these by using the search function in `make menuconfig`. >> >>> Press '/' and type a Kconfig option. >> >>> >> >>>> I would be grateful if you check my config and tell me what is >> ifdtool >> >>>> in Coreboot and how >> >>>> I use it. >> >>>> and How I find Intel ME file for my board and GBE for a network on >> my >> >>>> board. >> >>> >> >>> >> >>> ifdtool is a tool for viewing and manipulating an Intel Flash >> Descriptor >> >>> binary. The flash descriptor is a 4KB data structure at the start of >> the >> >>> ROM's address space (offset 0x000000-0x000fff). >> >>> >> >>> To build it: `make -C util/ifdtool` >> >>> To run it: `util/ifdtool/ifdtool` >> >>> >> >>> You'll probably want to use the '-x' option to extract the individual >> >>> modules from an existing Minnowboard Max firmware image (e.g. the >> UEFI image >> >>> that comes with the board). That will give you the ME and GBE files. >> >>> >> > >> >

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Re: [coreboot] POWER9 / Talos II coreboot support?
by Taiidan＠gmx.com 05 Aug '18

05 Aug '18

Tim you should post the latest power figures! Many people think it uses lots of power when it doesn't.

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Re: [coreboot] POWER9 / Talos II coreboot support?
by Timothy Pearson 05 Aug '18

05 Aug '18

As of late last week: W have the processor user guide, full register documentation, and a smattering of other resources released publicly [1]. The PHB documentation is still in process and still moving forward, along with the electrical datasheet. If you are interested in documentation that isn't already available and isn't on the to-do list, please let me know. My understanding is that the list above should be pretty much everything needed for firmware work. [1] https://wiki.raptorcs.com/wiki/Category:Documentation On 06/07/2018 08:05 PM, ron minnich wrote: > where are we on the docs at this point > > > On Thu, Jun 7, 2018 at 5:59 PM Timothy Pearson > <tpearson(a)raptorengineering.com <mailto:tpearson@raptorengineering.com>> > wrote: > > For anyone wanting a more affordable development platform for POWER9, > check out the Talos II Lite: > > https://raptorcs.com/TALOSIILITE/ > > Hopefully we're getting down to a price point where coreboot development > becomes more practical (if still a bit painful)? > > Looking forward to seeing coreboot on ppc64el systems! > > On 05/29/2018 03:45 PM, Timothy Pearson wrote: >> Sorry, can't add today....it's a little over 6,000 pages of new >> documentation. Still, hardly light reading! > >> On 05/29/2018 03:39 PM, Timothy Pearson wrote: >>> Register documentation was published today. Links to the three > volumes >>> (over 7000 pages of documentation!) > >>> > https://wiki.raptorcs.com/wiki/File:POWER9_Registers_vol1_version1.1_pub.pdf > >>> > https://wiki.raptorcs.com/wiki/File:POWER9_Registers_vol2_version1.2_pub.pdf > >>> > https://wiki.raptorcs.com/wiki/File:POWER9_Registers_vol3_version1.2_pub.pdf > >>> That leaves only the PHB documentation in process at this point. > Almost >>> there.... > >>> On 05/12/2018 02:34 AM, Timothy Pearson wrote: >>>> On 05/03/2018 06:02 PM, ron minnich wrote: > > >>>>> On Thu, May 3, 2018 at 1:20 PM Timothy Pearson >>>>> <tpearson(a)raptorengineering.com > <mailto:tpearson@raptorengineering.com> > <mailto:tpearson@raptorengineering.com > <mailto:tpearson@raptorengineering.com>>> >>>>> wrote: > >>>>> -----BEGIN PGP SIGNED MESSAGE----- >>>>> Hash: SHA256 > >>>>> I think I was being a bit pessimistic / too careful here. > We're close >>>>> to getting the docs publicly released, but that doesn't > help anyone >>>>> wanting access right now, which is why I mentioned the > other route. >>>>> IBM's committed to getting the documentation released, > they're just >>>>> making sure that what they release is actually correct for > the products >>>>> it covers. > >>>>> It might make sense to get our "working group" together > over the next >>>>> few weeks, by which time the documentation should be > available in public >>>>> form. > >>>>> Are you interested in joining? :-) > > >>>>> of course, but not until those docs are freed up. > > >>>> We're getting there. First manual to be released is the > processor user >>>> guide. More to follow, including register documentation, in > around a week. > >>>> Users guide: > >>>> > https://wiki.raptorcs.com/wiki/File:POWER9_um_OpenPOWER_v20GA_09APR2018_pub… > >>>>> Context: I've been trying for 2 years now to get OPAL released > under >>>>> dual gpl2 licensing with the current apache2 license, apache2 > and gpl2 >>>>> are not compatible, so we'd be in a bit of a mess should we use > OPAL >>>>> code in coreboot, and it would be easiest if we were able to > use some of >>>>> that code. > >>>>> The first response from IBM was "why do you think you need > coreboot?" I >>>>> worked through that, and there was agreement in the end it ought to >>>>> happen, said agreement reached about 2 years ago. Stuff Would > Happen, I >>>>> was told. After that, silence. > >>>> We've reignited this. It's underway. :-) > >>>>> This is pretty much par for the course with Power. In 1990 I > spent two >>>>> years getting an agreement that would allow me to .... get more > agreements. > >>>> We've plowed through this already and are at the action point. > For the >>>> most part, just let me know what you need and I'll see if we can > get it >>>> published. > >>>>> So close doesn't count. Once I see the kind of docs I need to > see, not >>>>> requiring a clickwrap, and covering all aspects of every chip > on your >>>>> board, I'm in: I'll order a board. Until then, I can't really > do much. > >>>> Is the NIC an issue? There are several people working on REing the >>>> hardware with some great progress [1][2], but there's really no > way to >>>> get Broadcom to ever release official documentation. Everything > else on >>>> the libre-friendly non-SAS version either has docs available or > we are >>>> close to getting them published. > >>>>> Thanks for your efforts on Power! > >>>> No problem! We still consider Power the best path forward for > powerful >>>> libre systems at this point, getting really tired of the other > vendors >>>> actively working against efforts to create open firmware (this > includes >>>> SiFive at this point). > >>>> Will keep you posted as we get more docs published online, but > thought >>>> you and the others here might at least be interested in the > users guide. > >>>>> ron > > > >>>> [1] https://wiki.raptorcs.com/wiki/BCM5719 >>>> [2] IRC discussions on #talos-workstation > > > > -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com

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coreboot August 2018