coreboot August 2018

coreboot@coreboot.org

43 participants
110 discussions

HV121WX4-120 screen for X200
by Piotr Kubaj 11 Aug '18

11 Aug '18

Hi, I just wanted to share my experience of using alternative screens for ThinkPad X200 (HV121WX4-120) with coreboot. After fitting the screen, it became apparent that something is wrong. Having turned on the X200, it ran happily for about 1 minute, then the screen just powered off. It didn't matter whether I stayed in SeaBIOS, or just booted my OS. And when the screen powered off, I could awake it after several minutes, but only for another minute. Apart from that, the laptop worked. nico_h from IRC helped me (thank you!) by providing alternative values for devicetree, which could make the screen work orderly. Well, it did work better, but still wasn't stable (it worked for 10-20 minutes, once I even got it to 2 hours). Still, that was a huge difference. I tried to experiment a little with it and set some crazy values: register "gpu_panel_power_up_delay" = "600" # T1+T2: 25ms register "gpu_panel_power_down_delay" = "3000" # T3: 25ms register "gpu_panel_power_backlight_on_delay" = "500" # T5: 250ms register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms register "gpu_panel_power_cycle_delay" = "255" # T4: 200ms After that, things seem to work fine. I hope someone finds it useful if they replace their X200's screen with alternative one. Again thanks to Nico for help! -- _________________________________________ / I'd rather have a bottle in front of me \ \ than a frontal lobotomy. / ----------------------------------------- \ ^__^ \ (oo)\_______ (__)\ )\/\ ||----w | || ||

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Re: [coreboot] Reducing the boot time
by Antony AbeePrakash X V 11 Aug '18

11 Aug '18

Hi, Thanks for your feedback. We enabled ENABLE_FSP_FAST_BOOT and MRC cache Training data in FSP using binary configuration tool. Also we reduced the console log level to 0. Now the boot time is reduced to 23 secs for initial boot and 11 secs for upcoming power cycles. Is this a normal behavior ? Also from the console logs we found the following: Coreboot FSP Performance Data ID: 950 - 951: 8118676370 - 2354813461 --> 4433ms (TS_FSP_MEMORY_INIT_START - TS_FSP_MEMORY_INIT_END) ID: 952 - 953: 10675414728 - 8905813067 --> 1361ms (TS_FSP_TEMP_RAM_EXIT_START - TS_FSP_TEMP_RAM_EXIT_END) ID: 954 - 955: 11761158519 - 10934089420 --> 636ms (TS_FSP_SILICON_INIT_START - TS_FSP_SILICON_INIT_END) ID: 956 - 957: 19265617974 - 19265559282 --> 0ms (TS_FSP_BEFORE_ENUMERATE - TS_FSP_AFTER_ENUMERATE) Can we reduce the above mentioned time taken by modifying the FSP source ? Please advice. Thanks From: Matt DeVillier [mailto:matt.devillier@gmail.com] Sent: Saturday, August 11, 2018 1:15 PM To: Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)LntTechservices.com> Cc: coreboot <coreboot(a)coreboot.org> Subject: Re: [coreboot] Reducing the boot time assuming you've built with CONFIG_COLLECT_TIMESTAMPS=y, you can build/run the cbmem utility and see how long each stage/section of coreboot is taking (up to the point of handing off control to the payload). 30s to boot sounds like either you're not caching the RAM training data (MRC cache) and therefore redoing RAM training each time, or outputting the boot console to a non-existent serial port (which can slow everything down). Whatever it is, looking at the timestamps will go a long way towards identifying the issue On Sat, Aug 11, 2018 at 2:13 AM Antony AbeePrakash X V <AntonyAbee.PrakashXV(a)lnttechservices.com<mailto:AntonyAbee.PrakashXV@lnttechservices.com>> wrote: Hi, We have developed a coreboot image for Apollo lake custom board. The time taken for boot up is around 30 seconds. We would like to reduce the boot time as much as possible. Following codes are removed: 1. Non-intel Apollolake specific codes in below folders * Arch * Soc * Mainboard * Vendorcode 1. Splash screen loading 2. SPI support – other than our custom board SPI. Also we have disabled the COMPRESS_RAMSTAGE. Still we are not able to reduce the boot time. Please suggest the methods to reduce the boot time. Thanks & Regards, Antony L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://mail.coreboot.org/mailman/listinfo/coreboot L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: [coreboot] Reducing the boot time
by Antony AbeePrakash X V 11 Aug '18

11 Aug '18

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Re: [coreboot] Reducing the boot time
by Matt DeVillier 11 Aug '18

11 Aug '18

assuming you've built with CONFIG_COLLECT_TIMESTAMPS=y, you can build/run the cbmem utility and see how long each stage/section of coreboot is taking (up to the point of handing off control to the payload). 30s to boot sounds like either you're not caching the RAM training data (MRC cache) and therefore redoing RAM training each time, or outputting the boot console to a non-existent serial port (which can slow everything down). Whatever it is, looking at the timestamps will go a long way towards identifying the issue On Sat, Aug 11, 2018 at 2:13 AM Antony AbeePrakash X V < AntonyAbee.PrakashXV(a)lnttechservices.com> wrote: > Hi, > > > > We have developed a coreboot image for Apollo lake custom board. The time > taken for boot up is around 30 seconds. > > We would like to reduce the boot time as much as possible. > > > > Following codes are removed: > > > > 1. Non-intel Apollolake specific codes in below folders > 1. Arch > 2. Soc > 3. Mainboard > 4. Vendorcode > > > > 1. Splash screen loading > 2. SPI support – other than our custom board SPI. > > > > Also we have disabled the COMPRESS_RAMSTAGE. Still we are not able to > reduce the boot time. > > > > Please suggest the methods to reduce the boot time. > > Thanks & Regards, > > Antony > > > > *L&T Technology Services Ltd* > > www.LntTechservices.com <http://www.lnttechservices.com/> > > This Email may contain confidential or privileged information for the > intended recipient (s). If you are not the intended recipient, please do > not use or disseminate the information, notify the sender and delete it > from your system. > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 10 Aug '18

10 Aug '18

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1394711: Control flow issues (NO_EFFECT) /src/mainboard/google/octopus/romstage.c: 46 in mainboard_save_dimm_info() ________________________________________________________________________________________________________ *** CID 1394711: Control flow issues (NO_EFFECT) /src/mainboard/google/octopus/romstage.c: 46 in mainboard_save_dimm_info() 40 save_dimm_info_by_sku_config(); 41 return; 42 } 43 44 if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_ALWAYS_IN_CBI)) { 45 /* Fall back on part numbers encoded in lp4cfg array. */ >>> CID 1394711: Control flow issues (NO_EFFECT) >>> This less-than-zero comparison of an unsigned value is never true. "board_id() < 0U". 46 if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) { 47 save_dimm_info_by_sku_config(); 48 return; 49 } 50 } 51 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Reducing the boot time
by Antony AbeePrakash X V 10 Aug '18

10 Aug '18

Hi, We have developed a coreboot image for Apollo lake custom board. The time taken for boot up is around 30 seconds. We would like to reduce the boot time as much as possible. Following codes are removed: 1. Non-intel Apollolake specific codes in below folders * Arch * Soc * Mainboard * Vendorcode 1. Splash screen loading 2. SPI support - other than our custom board SPI. Also we have disabled the COMPRESS_RAMSTAGE. Still we are not able to reduce the boot time. Please suggest the methods to reduce the boot time. Thanks & Regards, Antony L&T Technology Services Ltd www.LntTechservices.com<http://www.lnttechservices.com/> This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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Re: [coreboot] [AMD/fam15h] coreboots update_microcode is NOT working, and I know why
by awokd 09 Aug '18

09 Aug '18

On Wed, August 8, 2018 3:03 pm, Mike Banon wrote: > It seems that now the microcode loading for AMD fam15h CPUs, including > for A10-5750M fam15h Richland CPU found at coreboot-supported Lenovo G505S, > is supposed to be done in two steps: > > 1) First of all it is initializing with this microcode hardcoded as > the hex values - version 0600110F [2012-01-11] : > > ./src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePa > tch0600110F_Enc.c ( > https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/amd/age > sa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c ) > > > 2) Then it is being updated with a slightly newer microcode binary, > stored inside this container originally obtained from linux-firmware.git ( > https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.g > it/tree/amd-ucode ) - version 6001119 [2012-07-13] : > > > ./3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin ( > https://review.coreboot.org/cgit/blobs.git/tree/cpu/amd/family_15h/microco > de_amd_fam15h.bin ) > > > <<< although it is FAR from being the latest, the latest available is > version 600111F [2018-03-05] from platomav repository - > https://github.com/platomav/CPUMicrocodes , > cpu00610F01_ver0600111F_2018-03-05_AC55EB96.bin - which greedy AMD did not > share with Linux users at linux-firmware.git , but was happy to share with > companies such as Lenovo and ASUS for their proprietary UEFI/BIOS > updates...) > > However , all these microcode update operations are happening ONLY if > the equivalence tables are including the relevant CPU ID equivalence lines > ! For G505S's A10-5750M fam15h Richland CPU : > > > "1)" step is not done because this important part of awokd's change > has not been accepted (marked with >>>) : > > https://review.coreboot.org/#/c/coreboot/+/22843/4/src/vendorcode/amd/age > sa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c > > STATIC CONST UINT16 ROMDATA CpuF15TnMicrocodeEquivalenceTable[] = > { > >>>> 0x6131, 0x6101, >>>> > 0x6101, 0x6101, > 0x6100, 0x6100 > }; > > > // Unencrypted equivalent > STATIC CONST UINT16 ROMDATA CpuF15TnUnEncryptedMicrocodeEquivalenceTable[] > = > { > >>>> 0x6131, 0x6901, >>>> > 0x6101, 0x6901, > 0x6100, 0x6900 > }; > > > "2)" step is not done because for it to work, at > https://review.coreboot.org/cgit/coreboot.git/tree/src/cpu/amd/family_10h- > family_15h/update_microcode.c file there should be these lines at the > equivalence table, lines 48-49 : > > > /* Family 15h */ > { 0x600f12, 0x6012 }, /* OR-B2 */ > { 0x600f20, 0x6020 }, /* OR-C0 */ > >>>> { 0x610f01, 0x6101 }, /* TN-A1 */ >>>> { 0x610f31, 0x6101 }, /* RL-A1 */ >>>> > > ( there is no typo, Trinity 0x610f01 and Richland 0x610f31 are sharing > the same microcodes ) > > I am planning to submit a small patch which is addressing those > problems, but before I do that I would like to hear your thoughts Nice research, I had missed that update_microcode.c reference. No wonder I had to hack it to get it to work. Please submit!

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coreboot static analysis - coverity & scan-build
by Martin Roth 08 Aug '18

08 Aug '18

coreboot now has nightly static analysis using scan-build: https://www.coreboot.org/scan-build/ We aren't currently keeping any sort of metrics or making a global list of all errors, we're just publishing the output for the individual boards. coreboot also runs bi-weekly scans using coverity's free open-source interface. Log in or sign up here: https://scan.coverity.com/projects/coreboot?tab=overview The current coverity defect count is 317, broken down as follows: /payloads: 11 /src, excluding vendorcode: 154 /src/vendorcode: 120 /util: 32 Here are the "/src, excluding vendorcode" issues. To see more information about the issues, use the coverity link above. CoverityID Type File 1380296 Resource leak /src/arch/x86/acpi_device.c 1380295 Resource leak /src/arch/x86/acpi_device.c 1380294 Resource leak /src/arch/x86/acpi_device.c 1380293 Resource leak /src/arch/x86/acpi_device.c 1380292 Resource leak /src/arch/x86/acpi_device.c 1357457 Resource leak /src/arch/x86/acpi_device.c 1357456 Resource leak /src/arch/x86/acpi_device.c 1354849 Overflowed return value /src/arch/x86/tables.c 1384423 Untrusted pointer read /src/commonlib/fsp_relocate.c 1370582 Uninitialized scalar variable /src/cpu/x86/mtrr/mtrr.c 1379932 Explicit null dereferenced /src/drivers/amd/agesa/state_machine.c 1362592 Dereference null return value /src/drivers/generic/max98357a/max98357a.c 1363355 Wrong sizeof argument /src/drivers/intel/fsp2_0/upd_display.c 1375565 Logically dead code /src/drivers/spi/spi_flash.c 751084 Out-of-bounds access /src/drivers/xgi/common/vb_setmode.c 1271711 Logically dead code /src/include/device/hypertransport_def.h 1370576 Dereference before null check /src/lib/edid.c 1374795 Destination buffer too small /src/lib/edid.c 1229647 Missing break in switch /src/lib/edid.c 1354970 Out-of-bounds access /src/lib/selfboot.c 1373368 Logically dead code /src/mainboard/asus/f2a85-m/romstage.c 1370586 Uninitialized scalar variable /src/mainboard/asus/kfsn4-dre/romstage.c 1370578 Uninitialized scalar variable /src/mainboard/asus/kfsn4-dre/romstage.c 1241839 Various /src/mainboard/emulation/qemu-i440fx/fw_cfg.c 1365730 Destination buffer too small /src/mainboard/google/eve/romstage.c 1375985 Explicit null dereferenced /src/mainboard/google/link/i915.c 1375986 Improper use of negative value /src/mainboard/google/link/i915.c 1387028 Bad bit shift operation /src/mainboard/google/poppy/variants/nami/memory.c 1229682 Out-of-bounds read /src/northbridge/amd/amdfam10/ht_config.c 1229680 Out-of-bounds read /src/northbridge/amd/amdfam10/ht_config.c 1229681 Out-of-bounds write /src/northbridge/amd/amdfam10/ht_config.c 1229679 Out-of-bounds write /src/northbridge/amd/amdfam10/ht_config.c 1347343 Unintended sign extension /src/northbridge/amd/amdfam10/northbridge.c 1347336 Uninitialized scalar variable /src/northbridge/amd/amdmct/mct_ddr3/mct_d.c 1347323 Unused value /src/northbridge/amd/amdmct/mct_ddr3/mct_d.c 1347322 Unused value /src/northbridge/amd/amdmct/mct_ddr3/mct_d.c 1347321 Unused value /src/northbridge/amd/amdmct/mct_ddr3/mct_d.c 1347369 Logically dead code /src/northbridge/amd/amdmct/mct_ddr3/mctrci.c 1347370 Logically dead code /src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c 1347326 Unused value /src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c 1347325 Unused value /src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c 1347324 Unused value /src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c 1229659 Improper use of negative value /src/northbridge/amd/amdmct/mct/mct_d.c 1229618 Logically dead code /src/northbridge/amd/amdmct/mct/mct_d.c 1229583 Same on both sides /src/northbridge/amd/amdmct/mct/mctardk3.c 1229626 Logically dead code /src/northbridge/amd/amdmct/mct/mctardk4.c 1229636 Explicit null dereferenced /src/northbridge/amd/amdmct/mct/mctsrc.c 1229646 Missing break in switch /src/northbridge/amd/lx/northbridgeinit.c 1229629 Division or modulo by zero /src/northbridge/amd/lx/raminit.c 1229577 Logical vs. bitwise operator /src/northbridge/amd/lx/raminit.c 1241851 Dereference before null check /src/northbridge/amd/pi/00730F01/dimmSpd.c 1229634 Dereference after null check /src/northbridge/amd/pi/00730F01/northbridge.c 1229565 Bad bit shift operation /src/northbridge/intel/gm45/early_reset.c 1229611 Constant variable guards dead code /src/northbridge/intel/gm45/pcie.c 1229563 Bad bit shift operation /src/northbridge/intel/gm45/raminit.c 1229612 Logically dead code /src/northbridge/intel/i440bx/raminit.c 1229717 Structurally dead code /src/northbridge/intel/i945/raminit.c 1229562 Bad bit shift operation /src/northbridge/intel/nehalem/raminit.c 1229561 Bad bit shift operation /src/northbridge/intel/nehalem/raminit.c 1229628 Division or modulo by zero /src/northbridge/intel/nehalem/raminit.c 1229675 Out-of-bounds read /src/northbridge/intel/nehalem/raminit.c 1347372 Logically dead code /src/northbridge/intel/pineview/raminit.c 1347387 Operands don't affect result /src/northbridge/intel/pineview/raminit.c 1347386 Operands don't affect result /src/northbridge/intel/pineview/raminit.c 1347378 Operands don't affect result /src/northbridge/intel/pineview/raminit.c 1347356 Unsigned compared against 0 /src/northbridge/intel/pineview/raminit.c 1347330 Unused value /src/northbridge/intel/pineview/raminit.c 1347329 Unused value /src/northbridge/intel/pineview/raminit.c 1347328 Unused value /src/northbridge/intel/pineview/raminit.c 1347327 Unused value /src/northbridge/intel/pineview/raminit.c 1229715 Uninitialized scalar variable /src/northbridge/intel/sandybridge/raminit_common.c 1347351 Out-of-bounds read /src/northbridge/intel/x4x/ram_calc.c 1347350 Out-of-bounds read /src/northbridge/intel/x4x/ram_calc.c 1391088 Division or modulo by zero /src/northbridge/intel/x4x/raminit_ddr23.c 1393458 Logically dead code /src/northbridge/intel/x4x/raminit_ddr23.c 1391091 Operands don't affect result /src/northbridge/intel/x4x/raminit_ddr23.c 1391090 Operands don't affect result /src/northbridge/intel/x4x/raminit_ddr23.c 1391089 Operands don't affect result /src/northbridge/intel/x4x/raminit_ddr23.c 1391087 Operands don't affect result /src/northbridge/intel/x4x/raminit_ddr23.c 1391085 Wrong operator used /src/northbridge/intel/x4x/raminit_ddr23.c 1229564 Bad bit shift operation /src/northbridge/via/vx900/chrome9hd.c 1391086 Bad bit shift operation /src/northbridge/via/vx900/memmap.c 1229666 Unintentional integer overflow /src/northbridge/via/vx900/northbridge.c 1229665 Unintentional integer overflow /src/northbridge/via/vx900/northbridge.c 1295492 Stray semicolon /src/soc/broadcom/cygnus/ddr_init.c 1295493 Structurally dead code /src/soc/broadcom/cygnus/ddr_init.c 1295501 Dereference after null check /src/soc/broadcom/cygnus/gpio.c 1295498 Dereference after null check /src/soc/broadcom/cygnus/gpio.c 1295496 Dereference after null check /src/soc/broadcom/cygnus/gpio.c 1295495 Dereference after null check /src/soc/broadcom/cygnus/gpio.c 1295490 Dereference after null check /src/soc/broadcom/cygnus/gpio.c 1295488 Dereference after null check /src/soc/broadcom/cygnus/gpio.c 1295486 Dereference after null check /src/soc/broadcom/cygnus/gpio.c 1295497 Macro compares unsigned to 0 /src/soc/broadcom/cygnus/i2c.c 1295500 Logically dead code /src/soc/broadcom/cygnus/shmoo_and28.c 1393966 Logically dead code /src/soc/cavium/cn81xx/uart.c 1372243 Buffer not null terminated /src/soc/intel/apollolake/cse.c 1229677 Out-of-bounds read /src/soc/intel/baytrail/gfx.c 1229702 Unintended sign extension /src/soc/intel/baytrail/gfx.c 1229701 Unintended sign extension /src/soc/intel/baytrail/gfx.c 1229700 Unintended sign extension /src/soc/intel/baytrail/gfx.c 1229699 Unintended sign extension /src/soc/intel/baytrail/gfx.c 1384425 Logically dead code /src/soc/intel/broadwell/pmutil.c 1391422 Same on both sides /src/soc/intel/broadwell/romstage/raminit.c 1384424 Logically dead code /src/soc/intel/common/block/gpio/gpio.c 1384420 Logically dead code /src/soc/intel/common/block/gpio/gpio.c 1384419 Logically dead code /src/soc/intel/common/block/gpio/gpio.c 1384414 Logically dead code /src/soc/intel/common/block/gpio/gpio.c 1381621 Unused value /src/soc/intel/common/block/smm/smitraphandler.c 1371814 Buffer not null terminated /src/soc/intel/common/smbios.c 1229673 Out-of-bounds read /src/soc/intel/skylake/cpu.c 1362809 Dereference after null check /src/soc/marvell/mvmap2315/load_validate.c 1384418 Out-of-bounds access /src/soc/mediatek/mt8173/i2c.c 1260981 Division or modulo by zero /src/soc/nvidia/tegra124/clock.c 1293140 Logically dead code /src/soc/nvidia/tegra124/dp.c 1293138 Logically dead code /src/soc/nvidia/tegra124/dp.c 1293137 Missing break in switch /src/soc/nvidia/tegra124/sor.c 1287070 Unused value /src/soc/nvidia/tegra124/sor.c 1294805 Dereference after null check /src/soc/nvidia/tegra210/dsi.c 1294800 Unintended sign extension /src/soc/nvidia/tegra210/dsi.c 1241854 Dereference after null check /src/soc/nvidia/tegra210/spi.c 1241838 Dereference before null check /src/soc/nvidia/tegra210/spi.c 1294801 Resource leak /src/soc/qualcomm/ipq806x/lcc.c 1294795 Logically dead code /src/soc/rockchip/common/edp.c 1294799 Structurally dead code /src/soc/rockchip/common/edp.c 1294798 Unused value /src/soc/rockchip/common/edp.c 1325861 Operands don't affect result /src/soc/rockchip/rk3288/clock.c 1325857 Logically dead code /src/soc/rockchip/rk3288/hdmi.c 1291959 Missing break in switch /src/soc/rockchip/rk3288/sdram.c 1365976 Operands don't affect result /src/soc/rockchip/rk3399/clock.c 1355168 Operands don't affect result /src/soc/rockchip/rk3399/clock.c 1355166 Operands don't affect result /src/soc/rockchip/rk3399/clock.c 1375443 Unintentional integer overflow /src/soc/rockchip/rk3399/mipi.c 1354778 Uninitialized scalar variable /src/soc/samsung/exynos5250/uart.c 1375671 Various /src/soc/samsung/exynos5420/spi.c 1241880 Extra high-order bits /src/southbridge/amd/cimx/sb900/early.c 1241812 Logical vs. bitwise operator /src/southbridge/amd/cimx/sb900/early.c 1241823 Logically dead code /src/southbridge/amd/cimx/sb900/early.c 1229584 Extra high-order bits /src/southbridge/amd/rs780/ht.c 1347373 Logically dead code /src/southbridge/amd/sb700/early_setup.c 1229582 Extra high-order bits /src/southbridge/amd/sb800/usb.c 1347384 Extra high-order bits /src/southbridge/amd/sr5650/pcie.c 1229676 Out-of-bounds read /src/southbridge/amd/sr5650/pcie.c 1362811 Resource leak /src/southbridge/amd/sr5650/sr5650.c 1287065 Unused value /src/southbridge/amd/sr5650/sr5650.c 1229598 Logically dead code /src/southbridge/intel/i82801gx/smihandler.c 1229607 Logically dead code /src/southbridge/intel/lynxpoint/lpc.c 1384422 Logically dead code /src/southbridge/intel/lynxpoint/pmutil.c 1384421 Logically dead code /src/southbridge/intel/lynxpoint/pmutil.c 1384417 Logically dead code /src/southbridge/intel/lynxpoint/pmutil.c 1384416 Logically dead code /src/southbridge/intel/lynxpoint/pmutil.c 1384415 Logically dead code /src/southbridge/intel/lynxpoint/pmutil.c 1370583 Uninitialized scalar variable /src/southbridge/nvidia/ck804/early_setup_car.c 1370581 Uninitialized scalar variable /src/southbridge/nvidia/ck804/early_setup_car.c

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[AMD/fam15h] coreboots update_microcode is NOT working, and I know why
by Mike Banon 08 Aug '18

08 Aug '18

It seems that now the microcode loading for AMD fam15h CPUs, including for A10-5750M fam15h Richland CPU found at coreboot-supported Lenovo G505S, is supposed to be done in two steps: 1) First of all it is initializing with this microcode hardcoded as the hex values - version 0600110F [2012-01-11] : ./src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c ( https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/amd/agesa… ) 2) Then it is being updated with a slightly newer microcode binary, stored inside this container originally obtained from linux-firmware.git ( https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git… ) - version 6001119 [2012-07-13] : ./3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin ( https://review.coreboot.org/cgit/blobs.git/tree/cpu/amd/family_15h/microcod… ) <<< although it is FAR from being the latest, the latest available is version 600111F [2018-03-05] from platomav repository - https://github.com/platomav/CPUMicrocodes , cpu00610F01_ver0600111F_2018-03-05_AC55EB96.bin - which greedy AMD did not share with Linux users at linux-firmware.git , but was happy to share with companies such as Lenovo and ASUS for their proprietary UEFI/BIOS updates...) However , all these microcode update operations are happening ONLY if the equivalence tables are including the relevant CPU ID equivalence lines ! For G505S's A10-5750M fam15h Richland CPU : "1)" step is not done because this important part of awokd's change has not been accepted (marked with >>>) : https://review.coreboot.org/#/c/coreboot/+/22843/4/src/vendorcode/amd/agesa… STATIC CONST UINT16 ROMDATA CpuF15TnMicrocodeEquivalenceTable[] = { >>> 0x6131, 0x6101, 0x6101, 0x6101, 0x6100, 0x6100 }; // Unencrypted equivalent STATIC CONST UINT16 ROMDATA CpuF15TnUnEncryptedMicrocodeEquivalenceTable[] = { >>> 0x6131, 0x6901, 0x6101, 0x6901, 0x6100, 0x6900 }; "2)" step is not done because for it to work, at https://review.coreboot.org/cgit/coreboot.git/tree/src/cpu/amd/family_10h-f… file there should be these lines at the equivalence table, lines 48-49 : /* Family 15h */ { 0x600f12, 0x6012 }, /* OR-B2 */ { 0x600f20, 0x6020 }, /* OR-C0 */ >>> { 0x610f01, 0x6101 }, /* TN-A1 */ >>> { 0x610f31, 0x6101 }, /* RL-A1 */ ( there is no typo, Trinity 0x610f01 and Richland 0x610f31 are sharing the same microcodes ) I am planning to submit a small patch which is addressing those problems, but before I do that I would like to hear your thoughts Best regards, Mike Banon

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Re: [coreboot] Problem with boot coreboot
by Mike Banon 08 Aug '18

08 Aug '18

For the beginning, I recommend you to check if you could boot anything at all. In example, try making an Ubuntu LiveUSB from a spare USB flash drive, and using SeaBIOS try booting from it. If it is working, you could also try installing Ubuntu to a spare Hard Drive and also try booting for it. If all this is working (means the SeaBIOS booting capabilities are fully functional both for USB and SATA interfaces) - while booting FreeBSD still doesn't work - that means something is wrong either with FreeBSD installation or (more likely) its partition table or maybe GRUB2 is corrupted. Then you could try restoring GRUB2, by following these instructions for example - https://howtoubuntu.org/how-to-repair-restore-reinstall-grub-2-with-a-ubunt… Best regards, Mike Banon On Wed, Aug 8, 2018 at 10:56 AM, zahra rahimkhani <zrahimkhani2014(a)gmail.com> wrote: > Also, I got a grub2 alone on flash . > it is MBR t with his form > > => 63 15730625 da0 MBR (7.5G) > 63 1985 - free - (993K) > 2048 15728640 1 linux-data (7.5G) > > => 63 15730625 diskid/DISK-1501938400200044 MBR (7.5G) > 63 1985 - free - (993K) > 2048 15728640 1 linux-data (7.5G) > > > But it did not work still . > please guide me that solve my problem . > > Thank you for your time . > > > > > > > On Tue, Aug 7, 2018 at 11:58 PM zahra rahimkhani <zrahimkhani2014(a)gmail.com> > wrote: >> >> >> I used a flash MBR . >> with this form >> => 63 15730625 da0 MBR (7.5G) >> 63 1985 - free - (993K) >> 2048 15728640 1 ntfs [active] (7.5G) >> >> >> But It did not work and it shows previous message again. >> >> Could you guide me ؟ >> >> Thanks >> Zahra >> >> On Tue, Aug 7, 2018 at 11:40 PM zahra rahimkhani >> <zrahimkhani2014(a)gmail.com> wrote: >>> >>> Thank you very much for your help. >>> could you tell me how to repairhatd driver ? >>> >>> Thanks , >>> >>> On 07/08/2018 7:59 PM, "Mike Banon" <mikebdp2(a)gmail.com> wrote: >>>> >>>> Have you tried repairing the bootloader at your hard drive? >>>> are you using GRUB2, and your partitions are MBR or GPT? >>>> (SeaBIOS supports MBR only, so GRUB2 needs to be installed to MBR) >>>> >>>> On Tue, Aug 7, 2018 at 11:13 AM, zahra rahimkhani >>>> <zrahimkhani2014(a)gmail.com> wrote: >>>> > Hello friends >>>> > >>>> > I compiled coreboot and seabios based on >>>> > >>>> > https://review.coreboot.org/cgit/board-status.git/plain/intel/minnowmax/4.5… >>>> > >>>> > but my Freebsd did not boot and show this message. >>>> > >>>> > Running option rom at c000:0003 >>>> > Turning on vga text mode console >>>> > SeaBIOS (version rel-1.11.2-0-gf9626cc) >>>> > EHCI init on dev 00:1d.0 (regs=0xd061e020) >>>> > WARNING - Timeout at i8042_flush:71! >>>> > AHCI controller at 00:13.0, iobase 0xd061d000, irq 10 >>>> > Searching bootorder for: /pci@i0cf8/*@12 >>>> > Found 0 lpt ports >>>> > Found 1 serial ports >>>> > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@1/*@0/*@0,0 >>>> > Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@1 >>>> > USB MSC vendor='UFD 2.0' product='Silicon-Power8G' rev='1100' type=0 >>>> > removable=1 >>>> > USB MSC blksize=512 sectors=15730688 >>>> > Initialized USB HUB (1 ports used) >>>> > All threads complete. >>>> > Scan for option roms >>>> > >>>> > Press ESC for boot menu. >>>> > >>>> > Searching bootorder for: HALT >>>> > drive 0x000f62c0: PCHS=0/0/0 translation=lba LCHS=979/255/63 >>>> > s=15730688 >>>> > Space available for UMB: cd800-ed800, f5b60-f62c0 >>>> > Returned 253952 bytes of ZoneHigh >>>> > e820 map has 18 items: >>>> > 0: 0000000000000000 - 000000000009fc00 = 1 RAM >>>> > 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED >>>> > 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED >>>> > 3: 0000000000100000 - 0000000020000000 = 1 RAM >>>> > 4: 0000000020000000 - 0000000020100000 = 2 RESERVED >>>> > 5: 0000000020100000 - 000000007ad9c000 = 1 RAM >>>> > 6: 000000007ad9c000 - 0000000080000000 = 2 RESERVED >>>> > 7: 00000000e0000000 - 00000000f0000000 = 2 RESERVED >>>> > 8: 00000000feb00000 - 00000000fec01000 = 2 RESERVED >>>> > 9: 00000000fed01000 - 00000000fed02000 = 2 RESERVED >>>> > 10: 00000000fed03000 - 00000000fed04000 = 2 RESERVED >>>> > 11: 00000000fed05000 - 00000000fed06000 = 2 RESERVED >>>> > 12: 00000000fed08000 - 00000000fed09000 = 2 RESERVED >>>> > 13: 00000000fed0c000 - 00000000fed10000 = 2 RESERVED >>>> > 14: 00000000fed1c000 - 00000000fed1d000 = 2 RESERVED >>>> > 15: 00000000fee00000 - 00000000fee01000 = 2 RESERVED >>>> > 16: 00000000fef00000 - 00000000ff000000 = 2 RESERVED >>>> > 17: 00000000ff800000 - 0000000100000000 = 2 RESERVED >>>> > enter handle_19: >>>> > NULL >>>> > Booting from Hard Disk... >>>> > Booting from 0000:7c00 >>>> > >>>> > I would be grateful if you guide me . >>>> > >>>> > Thanks, >>>> > >>>> > -- >>>> > coreboot mailing list: coreboot(a)coreboot.org >>>> > https://mail.coreboot.org/mailman/listinfo/coreboot

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coreboot August 2018