coreboot August 2018

coreboot@coreboot.org

43 participants
110 discussions

L1TF
by Shawn 15 Aug '18

15 Aug '18

Hi guys, Some of you might already noticed the new side-channel attack called L1 Terminal Fault is made public late: https://software.intel.com/security-software-guidance/software-guidance/l1-… https://software.intel.com/security-software-guidance/insights/deep-dive-in… According to the vulnerability analysis, the SMM is affected by L1TF. Since SMM code base in coreboot is much smaller than OEM's firmware, IMOHO L1TF is not practical on coreboot. Any idea about is coreboot vulnerable to L1TF? -- GNU powered it... GPL protect it... God blessing it... regards Shawn

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Re: [coreboot] Intel G41 - Asrock G41M-GS: no coreboot screen output from Intel GPU on VGA
by h42＠memeware.net 15 Aug '18

15 Aug '18

Its not a slow reacting monitor. I already pressed it blind before reporting the issue here without any success. Its a modern, fast reacting LED monitor (ccfl takes longer to turn on). I get immediately after powering on a coreboot screen on the monitor when i insert a PCIe graphics card into the PCIe slot but i need the working internal Intel GPU. On 2018-08-14 15:30, Jose Trujillo via coreboot wrote: > Just press ESC key during booting for Seabios and if everything in the > video interface is properly configured by default you should see the > boot menu. > > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > On August 14, 2018 4:35 PM, <h42(a)memeware.net> wrote: > >> I wrote the way i had build coreboot. Tianocore is not the default >> payload. The default payload recently is (i checked now) SeaBIOS >> 1.11.2 >> . >> I have not touched anything at the payload. I just leave everything >> default and would like to be able to see the output of coreboot so >> that >> i can choose for example to boot from a usb-pendrive. >> >> What should i do now to get the <everything at default coreboot> to >> show >> output on the screen? >> >> On 2018-08-14 11:53, Jose Trujillo via coreboot wrote: >> >> > Hello h42 >> > If you are using Tianocore you must use VESA framebuffer >> > If Seabios use text mode >> > Jose >> > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ >> > On August 14, 2018 2:41 PM, h42(a)memeware.net wrote: >> > >> > > I dont get anything on the screen from coreboot. The later os is >> > > displaying fine. >> > > How i build the image: ran on a fresh git cloned (from today) 'make >> > > menuconfig', chose just the mainboard manufacturer and the model, >> > > press >> > > esc, confirmed saving, ran 'make'. I installed this image and dont get >> > > any coreboot output on the screen. When i wait long enough, i get the >> > > output from the Linux OS on the screen. >> > > From the coreboot logfile: >> > > coreboot-4.8-1195-gb75a08b199 >> > > [...] >> > > FMAP: Found "FLASH" version 1.1 at 0. >> > > FMAP: base = fff00000 size = 100000 #areas = 4 >> > > FMAP: area RW_MRC_CACHE found @ 10000 (65536 bytes) >> > > MRC: No data in cbmem for 'RW_MRC_CACHE'. >> > > BS: BS_DEV_ENUMERATE times (us): entry 0 run 150329 exit 16016 >> > > found VGA at PCI: 00:02.0 >> > > Setting up VGA for PCI: 00:02.0 >> > > Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 >> > > Setting PCI_BRIDGE_CTL_VGA for bridge Root Device >> > > Allocating resources... >> > > Reading resources... >> > > TOUUD 0x80000000 TOLUD 0x80000000 TOM 0x80000000 >> > > IGD decoded, subtracting 64M UMA and 4M GTT >> > > TSEG decoded, subtracting 8M >> > > Available memory below 4GB: 1972M >> > > Adding UMA memory area base=0x7b400000 size=0x04c00000 >> > > Adding PCIe config bar base=0xe0000000 size=0x10000000 >> > > Done reading resources. >> > > [...] >> > > [21.707417] CONFIG => >> > > [21.709411] (Primary => >> > > [21.711924] (Port => Analog , >> > > [21.715130] Framebuffer => >> > > [21.718076] (Width => 640, >> > > [21.721542] Height => 400, >> > > [21.725008] Start_X => 0, >> > > [21.728301] Start_Y => 0, >> > > [21.731594] Stride => 1, >> > > [21.734886] V_Stride => 1, >> > > [21.738179] Tiling => Linear , >> > > [21.741993] Rotation => No_Rotation, >> > > [21.746153] Offset => 0xffffffff, >> > > [21.749966] BPC => 8), >> > > [21.753085] Mode => >> > > [21.755424] (Dotclock => 148500000, >> > > [21.760192] H_Visible => 1920, >> > > [21.764524] H_Sync_Begin => 2008, >> > > [21.768857] H_Sync_End => 2052, >> > > [21.773190] H_Total => 2200, >> > > [21.777523] V_Visible => 1080, >> > > [21.781857] V_Sync_Begin => 1084, >> > > [21.786189] V_Sync_End => 1089, >> > > [21.790522] V_Total => 1125, >> > > [21.794855] H_Sync_Active_High => True, >> > > [21.799189] V_Sync_Active_High => True, >> > > [21.803521] BPC => 5)), >> > > [21.807767] Secondary => >> > > [21.810281] (Port => Disabled, >> > > [21.813487] Framebuffer => >> > > [21.816433] (Width => 1, >> > > [21.819727] Height => 1, >> > > [21.823020] Start_X => 0, >> > > [21.826313] Start_Y => 0, >> > > [21.829605] Stride => 1, >> > > [21.832899] V_Stride => 1, >> > > [21.836193] Tiling => Linear , >> > > [21.840006] Rotation => No_Rotation, >> > > [21.844166] Offset => 0x00000000, >> > > [21.847979] BPC => 8), >> > > [21.851098] Mode => >> > > [21.853438] (Dotclock => 24000000, >> > > [21.858118] H_Visible => 1, >> > > [21.862191] H_Sync_Begin => 1, >> > > [21.866263] H_Sync_End => 1, >> > > [21.870336] H_Total => 1, >> > > [21.874409] V_Visible => 1, >> > > [21.878482] V_Sync_Begin => 1, >> > > [21.882555] V_Sync_End => 1, >> > > [21.886629] V_Total => 1, >> > > [21.890702] H_Sync_Active_High => False, >> > > [21.895121] V_Sync_Active_High => False, >> > > [21.899541] BPC => 5)), >> > > [21.903787] Tertiary => >> > > [21.906300] (Port => Disabled, >> > > [21.909507] Framebuffer => >> > > [21.912453] (Width => 1, >> > > [21.915746] Height => 1, >> > > [21.919039] Start_X => 0, >> > > [21.922331] Start_Y => 0, >> > > [21.925624] Stride => 1, >> > > [21.928918] V_Stride => 1, >> > > [21.932211] Tiling => Linear , >> > > [21.936023] Rotation => No_Rotation, >> > > [21.940183] Offset => 0x00000000, >> > > [21.943996] BPC => 8), >> > > [21.947116] Mode => >> > > [21.949455] (Dotclock => 24000000, >> > > [21.954135] H_Visible => 1, >> > > [21.958207] H_Sync_Begin => 1, >> > > [21.962280] H_Sync_End => 1, >> > > [21.966353] H_Total => 1, >> > > [21.970427] V_Visible => 1, >> > > [21.974499] V_Sync_Begin => 1, >> > > [21.978572] V_Sync_End => 1, >> > > [21.982646] V_Total => 1, >> > > [21.986719] H_Sync_Active_High => False, >> > > [21.991138] V_Sync_Active_High => False, >> > > [21.995557] BPC => 5))); >> > > PCI: 00:02.0 init finished in 307222 usecs >> > > PCI: 00:02.1 init ... >> > > PCI: 00:02.1 init finished in 2009 usecs >> > > PCI: 00:1b.0 init ... >> > > [...] >> > > So it seems to have detected that my screen is 1920*1080. GPU + screen >> > > detection seems to be working. But i dont get any coreboot output on >> > > the >> > > screen. >> > > The output had worked fine on this screen with the OEM BIOS. >> > > >> > > coreboot mailing list: coreboot(a)coreboot.org >> > > https://mail.coreboot.org/mailman/listinfo/coreboot >> >> -- >> >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot

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USB cannot work
by Hilbert Tu(杜睿哲_Pegatron) 15 Aug '18

15 Aug '18

Hi, I have coreboot running on my Denverton C3538 platform with Grub2 payload and the boot up log is as attached file. But whatever configuration I have changed in coreboot or FITC, the USB interfaces always cannot work. I have verified my hardware by BIOS code and it is ok. So I guess maybe I have incorrect setting somewhere in coreboot or grub2. In grub prompt, I only can see following but no plugged in USB dongle: grub> ls (memdisk) (cbfsdisk) grub> By the way, the reference configuration is Harcuvar CRB. I would be grateful if someone can help. -Hilbert From: Hilbert Tu(杜睿哲_Pegatron) Sent: Tuesday, August 07, 2018 1:57 PM To: coreboot(a)coreboot.org Subject: RE: Denverton FSP usage I found the related setting under “Generic Drivers” -> “Use FSP TempRamInit & TempRamExit APIs”. Ha. -Hilbert From: Hilbert Tu(杜睿哲_Pegatron) Sent: Monday, August 06, 2018 6:21 PM To: coreboot(a)coreboot.org Subject: Denverton FSP usage Hi, I have an Intel Denverton (C3538) CPU board and try to use coreboot 4.8 to boot it up. The FSP I have consisted of 3 parts as FSP-T, FSP-M, FSP-S, but I don’t see the settings for specifying FSP-T in coreboot’s menuconfig. From the debug output, I got error code 2526 and I doubt it is due to lack of including FSP-T. Is there anyone can tell how to correctly use FSP-T? Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。

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Build failure, build log dont link in a proper way
by h42＠memeware.net 15 Aug '18

15 Aug '18

I cloned today the fresh code on a new machine. I first installed the dependencies listed here https://www.coreboot.org/Build_HOWTO and then i liked to build the whole build gcc for all platforms. I ran 'make crossgcc CPUS=6' in the fresh coreboot cloned directory. Error: Building GCC v8.1.0 for target ... failed. Check 'build-riscv64-elf-GCC/build.log'. Makefile:26: recipe for target 'build_gcc' failed make[3]: *** [build_gcc] Error 1 Makefile:63: recipe for target 'build-riscv' failed make[2]: *** [build-riscv] Error 2 Makefile:16: recipe for target 'all_without_gdb' failed make[1]: *** [all_without_gdb] Error 2 util/crossgcc/Makefile.inc:37: recipe for target 'crossgcc' failed make: *** [crossgcc] Error 2 I than ran 'cat build-riscv64-elf-GCC/build.log' but that file dont exist. Maybe its somewhere else. When i build the crossgcc in the main directory of the project and then it tells me to look into a file, the file should be linked properly so that i can run in the same directory i am building in a 'cat' command.

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Re: [coreboot] Reducing the boot time
by Nico Huber 14 Aug '18

14 Aug '18

Hello Antony, On 11.08.2018 12:55, Antony AbeePrakash X V wrote: > Coreboot FSP Performance Data > ID: 950 - 951: 8118676370 - 2354813461 --> 4433ms (TS_FSP_MEMORY_INIT_START - TS_FSP_MEMORY_INIT_END) > ID: 952 - 953: 10675414728 - 8905813067 --> 1361ms (TS_FSP_TEMP_RAM_EXIT_START - TS_FSP_TEMP_RAM_EXIT_END) > ID: 954 - 955: 11761158519 - 10934089420 --> 636ms (TS_FSP_SILICON_INIT_START - TS_FSP_SILICON_INIT_END) > ID: 956 - 957: 19265617974 - 19265559282 --> 0ms (TS_FSP_BEFORE_ENUMERATE - TS_FSP_AFTER_ENUMERATE) given that Google uses the same SoC for Chromebooks, I would expect about ten times faster numbers. What FSP binary do you use? There is one in Intel's FSP GitHub repo[1]. Maybe try that one if you haven't already. I know there are also bina- ries with additional debugging enabled; that might slow things down. > > Can we reduce the above mentioned time taken by modifying the FSP source ? Please advice. Questions about the FSP source are better directed towards Intel. They do not want this community to know the source. Nico [1] https://github.com/IntelFsp/FSP/tree/ApolloLake

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Re: [coreboot] Intel G41 - Asrock G41M-GS: no coreboot screen output from Intel GPU on VGA
by h42＠memeware.net 14 Aug '18

14 Aug '18

I wrote the way i had build coreboot. Tianocore is not the default payload. The default payload recently is (i checked now) SeaBIOS 1.11.2 . I have not touched anything at the payload. I just leave everything default and would like to be able to see the output of coreboot so that i can choose for example to boot from a usb-pendrive. What should i do now to get the <everything at default coreboot> to show output on the screen? On 2018-08-14 11:53, Jose Trujillo via coreboot wrote: > Hello h42 > > If you are using Tianocore you must use VESA framebuffer > If Seabios use text mode > > Jose > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > On August 14, 2018 2:41 PM, <h42(a)memeware.net> wrote: > >> I dont get anything on the screen from coreboot. The later os is >> displaying fine. >> >> How i build the image: ran on a fresh git cloned (from today) 'make >> menuconfig', chose just the mainboard manufacturer and the model, >> press >> esc, confirmed saving, ran 'make'. I installed this image and dont get >> any coreboot output on the screen. When i wait long enough, i get the >> output from the Linux OS on the screen. >> >> From the coreboot logfile: >> >> coreboot-4.8-1195-gb75a08b199 >> [...] >> FMAP: Found "FLASH" version 1.1 at 0. >> FMAP: base = fff00000 size = 100000 #areas = 4 >> FMAP: area RW_MRC_CACHE found @ 10000 (65536 bytes) >> MRC: No data in cbmem for 'RW_MRC_CACHE'. >> BS: BS_DEV_ENUMERATE times (us): entry 0 run 150329 exit 16016 >> found VGA at PCI: 00:02.0 >> Setting up VGA for PCI: 00:02.0 >> Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 >> Setting PCI_BRIDGE_CTL_VGA for bridge Root Device >> Allocating resources... >> Reading resources... >> TOUUD 0x80000000 TOLUD 0x80000000 TOM 0x80000000 >> IGD decoded, subtracting 64M UMA and 4M GTT >> TSEG decoded, subtracting 8M >> Available memory below 4GB: 1972M >> Adding UMA memory area base=0x7b400000 size=0x04c00000 >> Adding PCIe config bar base=0xe0000000 size=0x10000000 >> Done reading resources. >> [...] >> [21.707417] CONFIG => >> [21.709411] (Primary => >> [21.711924] (Port => Analog , >> [21.715130] Framebuffer => >> [21.718076] (Width => 640, >> [21.721542] Height => 400, >> [21.725008] Start_X => 0, >> [21.728301] Start_Y => 0, >> [21.731594] Stride => 1, >> [21.734886] V_Stride => 1, >> [21.738179] Tiling => Linear , >> [21.741993] Rotation => No_Rotation, >> [21.746153] Offset => 0xffffffff, >> [21.749966] BPC => 8), >> [21.753085] Mode => >> [21.755424] (Dotclock => 148500000, >> [21.760192] H_Visible => 1920, >> [21.764524] H_Sync_Begin => 2008, >> [21.768857] H_Sync_End => 2052, >> [21.773190] H_Total => 2200, >> [21.777523] V_Visible => 1080, >> [21.781857] V_Sync_Begin => 1084, >> [21.786189] V_Sync_End => 1089, >> [21.790522] V_Total => 1125, >> [21.794855] H_Sync_Active_High => True, >> [21.799189] V_Sync_Active_High => True, >> [21.803521] BPC => 5)), >> [21.807767] Secondary => >> [21.810281] (Port => Disabled, >> [21.813487] Framebuffer => >> [21.816433] (Width => 1, >> [21.819727] Height => 1, >> [21.823020] Start_X => 0, >> [21.826313] Start_Y => 0, >> [21.829605] Stride => 1, >> [21.832899] V_Stride => 1, >> [21.836193] Tiling => Linear , >> [21.840006] Rotation => No_Rotation, >> [21.844166] Offset => 0x00000000, >> [21.847979] BPC => 8), >> [21.851098] Mode => >> [21.853438] (Dotclock => 24000000, >> [21.858118] H_Visible => 1, >> [21.862191] H_Sync_Begin => 1, >> [21.866263] H_Sync_End => 1, >> [21.870336] H_Total => 1, >> [21.874409] V_Visible => 1, >> [21.878482] V_Sync_Begin => 1, >> [21.882555] V_Sync_End => 1, >> [21.886629] V_Total => 1, >> [21.890702] H_Sync_Active_High => False, >> [21.895121] V_Sync_Active_High => False, >> [21.899541] BPC => 5)), >> [21.903787] Tertiary => >> [21.906300] (Port => Disabled, >> [21.909507] Framebuffer => >> [21.912453] (Width => 1, >> [21.915746] Height => 1, >> [21.919039] Start_X => 0, >> [21.922331] Start_Y => 0, >> [21.925624] Stride => 1, >> [21.928918] V_Stride => 1, >> [21.932211] Tiling => Linear , >> [21.936023] Rotation => No_Rotation, >> [21.940183] Offset => 0x00000000, >> [21.943996] BPC => 8), >> [21.947116] Mode => >> [21.949455] (Dotclock => 24000000, >> [21.954135] H_Visible => 1, >> [21.958207] H_Sync_Begin => 1, >> [21.962280] H_Sync_End => 1, >> [21.966353] H_Total => 1, >> [21.970427] V_Visible => 1, >> [21.974499] V_Sync_Begin => 1, >> [21.978572] V_Sync_End => 1, >> [21.982646] V_Total => 1, >> [21.986719] H_Sync_Active_High => False, >> [21.991138] V_Sync_Active_High => False, >> [21.995557] BPC => 5))); >> >> PCI: 00:02.0 init finished in 307222 usecs >> PCI: 00:02.1 init ... >> PCI: 00:02.1 init finished in 2009 usecs >> PCI: 00:1b.0 init ... >> [...] >> >> So it seems to have detected that my screen is 1920*1080. GPU + screen >> detection seems to be working. But i dont get any coreboot output on >> the >> screen. >> The output had worked fine on this screen with the OEM BIOS. >> >> ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ >> >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 14 Aug '18

14 Aug '18

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1394774: Control flow issues (NO_EFFECT) /src/mainboard/google/octopus/variants/baseboard/memory.c: 208 in variant_lpddr4_config() ________________________________________________________________________________________________________ *** CID 1394774: Control flow issues (NO_EFFECT) /src/mainboard/google/octopus/variants/baseboard/memory.c: 208 in variant_lpddr4_config() 202 { 203 if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_IN_CBI)) 204 return &non_cbi_lp4cfg; 205 206 if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_ALWAYS_IN_CBI)) { 207 /* Fall back non cbi memory config. */ >>> CID 1394774: Control flow issues (NO_EFFECT) >>> This less-than-zero comparison of an unsigned value is never true. "board_id() < 0U". 208 if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) 209 return &non_cbi_lp4cfg; 210 } 211 212 return &cbi_lp4cfg; 213 } ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Re: [coreboot] Warnings/Errors while building coreboot toolchain
by h42＠memeware.net 14 Aug '18

14 Aug '18

You are right. It seems to differ(tried now an other g41 board). I thought it would be the same thing for all Intel G41 boards. The board i was building for was the Asrock G41M-GS. On 2018-08-14 10:25, Th3Fanbus . wrote: > Hello, > > Could you please specify what coreboot branch are you using and what > board are you building coreboot for? If your board is not in > coreboot's tree, could you please link it? > > Regards, > > Angel Pons > > On Tue, Aug 14, 2018, 12:20 <h42(a)memeware.net> wrote: > >> I liked to build an image for an Intel G41 based mainboard and got >> that >> in the build log: >> >> coreboot toolchain v1.52 June 11th, 2018 >> dsdt.aml 1525: CreateDwordField (PBUF, 0, PIO0) >> Remark 2089 - Object is not referenced ^ (Name [PIO0] is >> within a method [_GTM]) >> >> dsdt.aml 1526: CreateDwordField (PBUF, 4, DMA0) >> Remark 2089 - Object is not referenced ^ (Name [DMA0] is >> within a method [_GTM]) >> >> dsdt.aml 1527: CreateDwordField (PBUF, 8, PIO1) >> Remark 2089 - Object is not referenced ^ (Name [PIO1] is >> within a method [_GTM]) >> >> dsdt.aml 1528: CreateDwordField (PBUF, 12, DMA1) >> Remark 2089 - Object is not referenced ^ (Name [DMA1] is >> >> within a method [_GTM]) >> >> dsdt.aml 1529: CreateDwordField (PBUF, 16, FLAG) >> Remark 2089 - Object is not referenced ^ (Name [FLAG] is >> >> within a method [_GTM]) >> >> dsdt.aml 1534: CreateDwordField (Arg0, 0, PIO0) >> Remark 2089 - Object is not referenced ^ (Name [PIO0] is >> within a method [_STM]) >> >> dsdt.aml 1535: CreateDwordField (Arg0, 4, DMA0) >> Remark 2089 - Object is not referenced ^ (Name [DMA0] is >> within a method [_STM]) >> >> dsdt.aml 1536: CreateDwordField (Arg0, 8, PIO1) >> Remark 2089 - Object is not referenced ^ (Name [PIO1] is >> within a method [_STM]) >> >> dsdt.aml 1537: CreateDwordField (Arg0, 12, DMA1) >> Remark 2089 - Object is not referenced ^ (Name [DMA1] is >> >> within a method [_STM]) >> >> dsdt.aml 1538: CreateDwordField (Arg0, 16, FLAG) >> Remark 2089 - Object is not referenced ^ (Name [FLAG] is >> >> within a method [_STM]) >> >> dsdt.aml 1562: CreateDwordField (PBUF, 0, PIO0) >> Remark 2089 - Object is not referenced ^ (Name [PIO0] is >> within a method [_GTM]) >> >> dsdt.aml 1563: CreateDwordField (PBUF, 4, DMA0) >> Remark 2089 - Object is not referenced ^ (Name [DMA0] is >> within a method [_GTM]) >> >> dsdt.aml 1564: CreateDwordField (PBUF, 8, PIO1) >> Remark 2089 - Object is not referenced ^ (Name [PIO1] is >> within a method [_GTM]) >> >> dsdt.aml 1565: CreateDwordField (PBUF, 12, DMA1) >> Remark 2089 - Object is not referenced ^ (Name [DMA1] is >> >> within a method [_GTM]) >> >> dsdt.aml 1566: CreateDwordField (PBUF, 16, FLAG) >> Remark 2089 - Object is not referenced ^ (Name [FLAG] is >> >> within a method [_GTM]) >> >> dsdt.aml 1571: CreateDwordField (Arg0, 0, PIO0) >> Remark 2089 - Object is not referenced ^ (Name [PIO0] is >> within a method [_STM]) >> >> dsdt.aml 1572: CreateDwordField (Arg0, 4, DMA0) >> Remark 2089 - Object is not referenced ^ (Name [DMA0] is >> within a method [_STM]) >> >> dsdt.aml 1573: CreateDwordField (Arg0, 8, PIO1) >> Remark 2089 - Object is not referenced ^ (Name [PIO1] is >> within a method [_STM]) >> >> dsdt.aml 1574: CreateDwordField (Arg0, 12, DMA1) >> Remark 2089 - Object is not referenced ^ (Name [DMA1] is >> >> within a method [_STM]) >> >> dsdt.aml 1575: CreateDwordField (Arg0, 16, FLAG) >> Remark 2089 - Object is not referenced ^ (Name [FLAG] is >> >> within a method [_STM]) >>

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Warnings/Errors while building coreboot toolchain
by h42＠memeware.net 14 Aug '18

14 Aug '18

I liked to build an image for an Intel G41 based mainboard and got that in the build log: coreboot toolchain v1.52 June 11th, 2018 dsdt.aml 1525: CreateDwordField (PBUF, 0, PIO0) Remark 2089 - Object is not referenced ^ (Name [PIO0] is within a method [_GTM]) dsdt.aml 1526: CreateDwordField (PBUF, 4, DMA0) Remark 2089 - Object is not referenced ^ (Name [DMA0] is within a method [_GTM]) dsdt.aml 1527: CreateDwordField (PBUF, 8, PIO1) Remark 2089 - Object is not referenced ^ (Name [PIO1] is within a method [_GTM]) dsdt.aml 1528: CreateDwordField (PBUF, 12, DMA1) Remark 2089 - Object is not referenced ^ (Name [DMA1] is within a method [_GTM]) dsdt.aml 1529: CreateDwordField (PBUF, 16, FLAG) Remark 2089 - Object is not referenced ^ (Name [FLAG] is within a method [_GTM]) dsdt.aml 1534: CreateDwordField (Arg0, 0, PIO0) Remark 2089 - Object is not referenced ^ (Name [PIO0] is within a method [_STM]) dsdt.aml 1535: CreateDwordField (Arg0, 4, DMA0) Remark 2089 - Object is not referenced ^ (Name [DMA0] is within a method [_STM]) dsdt.aml 1536: CreateDwordField (Arg0, 8, PIO1) Remark 2089 - Object is not referenced ^ (Name [PIO1] is within a method [_STM]) dsdt.aml 1537: CreateDwordField (Arg0, 12, DMA1) Remark 2089 - Object is not referenced ^ (Name [DMA1] is within a method [_STM]) dsdt.aml 1538: CreateDwordField (Arg0, 16, FLAG) Remark 2089 - Object is not referenced ^ (Name [FLAG] is within a method [_STM]) dsdt.aml 1562: CreateDwordField (PBUF, 0, PIO0) Remark 2089 - Object is not referenced ^ (Name [PIO0] is within a method [_GTM]) dsdt.aml 1563: CreateDwordField (PBUF, 4, DMA0) Remark 2089 - Object is not referenced ^ (Name [DMA0] is within a method [_GTM]) dsdt.aml 1564: CreateDwordField (PBUF, 8, PIO1) Remark 2089 - Object is not referenced ^ (Name [PIO1] is within a method [_GTM]) dsdt.aml 1565: CreateDwordField (PBUF, 12, DMA1) Remark 2089 - Object is not referenced ^ (Name [DMA1] is within a method [_GTM]) dsdt.aml 1566: CreateDwordField (PBUF, 16, FLAG) Remark 2089 - Object is not referenced ^ (Name [FLAG] is within a method [_GTM]) dsdt.aml 1571: CreateDwordField (Arg0, 0, PIO0) Remark 2089 - Object is not referenced ^ (Name [PIO0] is within a method [_STM]) dsdt.aml 1572: CreateDwordField (Arg0, 4, DMA0) Remark 2089 - Object is not referenced ^ (Name [DMA0] is within a method [_STM]) dsdt.aml 1573: CreateDwordField (Arg0, 8, PIO1) Remark 2089 - Object is not referenced ^ (Name [PIO1] is within a method [_STM]) dsdt.aml 1574: CreateDwordField (Arg0, 12, DMA1) Remark 2089 - Object is not referenced ^ (Name [DMA1] is within a method [_STM]) dsdt.aml 1575: CreateDwordField (Arg0, 16, FLAG) Remark 2089 - Object is not referenced ^ (Name [FLAG] is within a method [_STM])

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Re: [coreboot] Reducing the boot time
by Taiidan＠gmx.com 11 Aug '18

11 Aug '18

On 08/11/2018 03:44 AM, Matt DeVillier wrote: > or outputting the boot console to a non-existent serial port (which can slow everything down). Yeah ditto, and it could also be a high log level or other debug features enabled that you don't need like the EHCI debug console...probably a combination of things.

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coreboot August 2018