coreboot August 2018

coreboot@coreboot.org

43 participants
110 discussions

Re: [coreboot] [AMD/fam15h] coreboots update_microcode is NOT working, and I know why
by Arthur Heymans 19 Aug '18

19 Aug '18

Mike Banon <mikebdp2(a)gmail.com> writes: > Before borrowing update_microcode.c for our family15tn, we need to > somehow figure out if its even working for that " > family_10h-family_15h ". If you go to the root directory with coreboot > sources, and issue ' find . -type f -print0 | xargs -0 grep > "cpu_microcode_bins" ' command, you'll see that cpu_microcode_bins > variable is defined ONLY for various Intel CPUs, and even one VIA CPU, > but never for the AMD CPUs ! > The amd microcode is included differently, by including it as a cbfs-file(s) directly. See cpu/amd/family_10h-family_15h/Makefile.inc. > So I have no idea if this update_microcode.c for AMD has been ever > tested, because there is no "cpu_microcode_bins" variable defined even > for "10h/15h" family, and its essential for this update mechanism to > work : if "cpu_microcode_bins" isnt defined, microcode_amd_fam15h.bin > isnt included, and update_microcode.c is either never launched or > gives an error > It is tested and the update is done quite early on to make sure the CPU operates properly before done any other initialization. -- ============== Arthur Heymans

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Re: [coreboot] [AMD/fam15h] coreboots update_microcode is NOT working, and I know why
by awokd 19 Aug '18

19 Aug '18

On Fri, August 17, 2018 11:00 pm, Mike Banon wrote: > After some research I've discovered serious problems with > "update_microcode" method: That's unfortunate, but understandable. The AGESA code is convoluted. Would it be possible for someone (myself included) to copy update_microcode.c into the family15tn structure with an appropriate call to it somewhere? I'll look too. [I have to trim your cc list to reply, sorry.]

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Using linux as payload
by Jorge Fernandez Monteagudo 18 Aug '18

18 Aug '18

Hi all! I have a coreboot from master git working ok in my AMD Bettong demoboard with SeaBIOS and now I'm trying to use a bzImage (2651888 bytes) and initrd.cpio.xz (2604544 bytes) generated by Heads in order to test the linux payload. When I compile the coreboot I see: Created CBFS (capacity = 8388056 bytes) CBFS apu/amdfw CBFS AGESA CBFS fallback/romstage CBFS fallback/ramstage CBFS cmos_layout.bin CBFS pci1002,9874.rom CBFS fallback/dsdt.aml CBFS fallback/payload W: Unknown type 'payload' ignored CBFS coreboot.rom CBFSLAYOUT coreboot.rom This image contains the following sections that can be manipulated with this tool: 'COREBOOT' (CBFS, size 8388096, offset 512) It is possible to perform either the write action or the CBFS add/remove actions on every section listed above. To see the image's read-only sections as well, rerun with the -w option. CBFSPRINT coreboot.rom Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 32220 none fallback/ramstage 0x7ec0 stage 56689 none cmos_layout.bin 0x15c80 cmos_layout 1516 none fallback/dsdt.aml 0x162c0 raw 6673 none (empty) 0x17d40 null 32856 none apu/amdfw 0x1fdc0 raw 622592 none pci1002,9874.rom 0xb7e00 optionrom 64512 none fallback/payload 0xc7a80 simple elf 5244700 none (empty) 0x5c8200 null 228248 none AGESA 0x5ffdc0 raw 690436 none (empty) 0x6a8740 null 1405592 none bootblock 0x7ffa00 bootblock 912 none Built amd/bettong (FP4) The "W: Unknown type 'payload' ignored" message is ok? Maybe the payload doesn't fit in the coreboot image? Now when I boot the board the last messages I can see on serial console are: ... Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 5ffd Writing coreboot table at 0x8fe11000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000008fdd9fff: RAM 3. 000000008fdda000-000000008fffffff: CONFIGURATION TABLES 4. 0000000090000000-00000000cfffffff: RESERVED 5. 00000000f8000000-00000000fbffffff: RESERVED 6. 00000000fed40000-00000000fed44fff: RESERVED 7. 0000000100000000-000000022effffff: RAM Board ID: 70 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) FMAP: Found "FLASH" version 1.1 at 0. FMAP: base = ff800000 size = 800000 #areas = 3 Wrote coreboot table at: 8fe11000, 0x2f4 bytes, checksum 6365 coreboot table: 780 bytes. IMD ROOT 0. 8ffff000 00001000 IMD SMALL 1. 8fffe000 00001000 ROMSTG STCK 2. 8ffe6000 00018000 RAMSTAGE 3. 8feff000 000e7000 57a9e100 4. 8fe19000 000e51f0 COREBOOT 5. 8fe11000 00008000 IRQ TABLE 6. 8fe10000 00001000 SMP TABLE 7. 8fe0f000 00001000 ACPI 8. 8fdeb000 00024000 TCPA LOG 9. 8fddb000 00010000 SMBIOS 10. 8fdda000 00000800 IMD small region: IMD ROOT 0. 8fffec00 00000400 CAR GLOBALS 1. 8fffeac0 00000140 ROMSTAGE 2. 8fffeaa0 00000004 57a9e000 3. 8fffea80 00000018 COREBOOTFWD 4. 8fffea40 00000028 BS: BS_WRITE_TABLES times (us): entry 0 run 207363 exit 0 CBFS: 'Master Header Locator' located CBFS at [100:7fffc0) CBFS: Locating 'fallback/payload' CBFS: Found @ offset c7b80 size 5006d5 Loading segment from ROM address 0xff8c7cb8 data (compression=0) New segment dstaddr 0x90000 memsize 0x1080 srcaddr 0xff8c7d60 filesize 0x1080 Loading segment from ROM address 0xff8c7cd4 code (compression=0) New segment dstaddr 0x1000000 memsize 0x2836f0 srcaddr 0xff8c8de0 filesize 0x2836f0 Loading segment from ROM address 0xff8c7cf0 code (compression=0) New segment dstaddr 0x40000 memsize 0xb1 srcaddr 0xffb4c4d0 filesize 0xb1 Loading segment from ROM address 0xff8c7d0c data (compression=0) New segment dstaddr 0x91000 memsize 0xc srcaddr 0xffb4c581 filesize 0xc Loading segment from ROM address 0xff8c7d28 data (compression=0) New segment dstaddr 0x4000000 memsize 0x27be00 srcaddr 0xffb4c58d filesize 0x27be00 Loading segment from ROM address 0xff8c7d44 Entry Point 0x00040000 Loading Segment: addr: 0x0000000000090000 memsz: 0x0000000000001080 filesz: 0x0000000000001080 lb: [0x000000008ff00000, 0x000000008ffe51f0) Post relocation: addr: 0x0000000000090000 memsz: 0x0000000000001080 filesz: 0x0000000000001080 it's not compressed! [ 0x00090000, 00091080, 0x00091080) <- ff8c7d60 dest 00090000, end 00091080, bouncebuffer ffffffff Loading Segment: addr: 0x0000000001000000 memsz: 0x00000000002836f0 filesz: 0x00000000002836f0 lb: [0x000000008ff00000, 0x000000008ffe51f0) Post relocation: addr: 0x0000000001000000 memsz: 0x00000000002836f0 filesz: 0x00000000002836f0 it's not compressed! [ 0x01000000, 012836f0, 0x012836f0) <- ff8c8de0 dest 01000000, end 012836f0, bouncebuffer ffffffff Loading Segment: addr: 0x0000000000040000 memsz: 0x00000000000000b1 filesz: 0x00000000000000b1 lb: [0x000000008ff00000, 0x000000008ffe51f0) Post relocation: addr: 0x0000000000040000 memsz: 0x00000000000000b1 filesz: 0x00000000000000b1 it's not compressed! [ 0x00040000, 000400b1, 0x000400b1) <- ffb4c4d0 dest 00040000, end 000400b1, bouncebuffer ffffffff Loading Segment: addr: 0x0000000000091000 memsz: 0x000000000000000c filesz: 0x000000000000000c lb: [0x000000008ff00000, 0x000000008ffe51f0) Post relocation: addr: 0x0000000000091000 memsz: 0x000000000000000c filesz: 0x000000000000000c it's not compressed! [ 0x00091000, 0009100c, 0x0009100c) <- ffb4c581 dest 00091000, end 0009100c, bouncebuffer ffffffff Loading Segment: addr: 0x0000000004000000 memsz: 0x000000000027be00 filesz: 0x000000000027be00 lb: [0x000000008ff00000, 0x000000008ffe51f0) Post relocation: addr: 0x0000000004000000 memsz: 0x000000000027be00 filesz: 0x000000000027be00 it's not compressed! [ 0x04000000, 0427be00, 0x0427be00) <- ffb4c58d dest 04000000, end 0427be00, bouncebuffer ffffffff Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 317530 exit 0 Jumping to boot code at 00040000(8fe11000) CPU0: stack: 8ff20000 - 8ff21000, lowest used address 8ff205e0, stack used: 2592 bytes But no more messages are displayed and the board do nothing. Anyone with a linux payload working already? I'm reporting in the heads github too with no luck... Any hint is welcome! Regards!

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 17 Aug '18

17 Aug '18

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1395066: Null pointer dereferences (NULL_RETURNS) ________________________________________________________________________________________________________ *** CID 1395066: Null pointer dereferences (NULL_RETURNS) /util/ifdtool/ifdtool.c: 241 in get_ifd_version_from_fcba() 235 int read_freq; 236 const fcba_t *fcba = find_fcba(image, size); 237 const fdbar_t *fdb = find_fd(image, size); 238 if (!fcba) /* a valid fcba indicates a valid fdb */ 239 exit(EXIT_FAILURE); 240 >>> CID 1395066: Null pointer dereferences (NULL_RETURNS) >>> Dereferencing a pointer that might be null "fdb" when calling "guess_ich_chipset". 241 chipset = guess_ich_chipset(fdb); 242 /* TODO: port ifd_version and max_regions 243 * against guess_ich_chipset() 244 */ 245 read_freq = (fcba->flcomp >> 17) & 7; 246 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Building an image a second/third/... time fails
by h42＠memeware.net 16 Aug '18

16 Aug '18

I had build once a coreboot image for a Intel G41 board. Then i liked to build for an other Intel G41 board. I first removed the config: rm .config* then i ran again 'make menuconfig' chose the other Intel G41 board and ran 'make'. I got this error: ..... Compile checking out/src/fw/smm.o Compile checking out/src/fw/smp.o Compile checking out/src/fw/mtrr.o Compile checking out/src/fw/xen.o Compiling IASL src/fw/ssdt-misc.hex out/src/fw/ssdt-misc.dsl.i 4: DefinitionBlock ("ssdt-misc.aml", "SSDT", 0x01, "BXPC", "BXSSDTSUSP", 0x1) Error 6155 - Invalid OEM Table ID ^ (Length cannot exceed 8 characters) ASL Input: out/src/fw/ssdt-misc.dsl.i - 102 lines, 2567 bytes, 35 keywords Listing File: out/src/fw/ssdt-misc.lst - 8393 bytes Hex Dump: out/src/fw/ssdt-misc.hex - 4096 bytes Compilation complete. 1 Errors, 0 Warnings, 0 Remarks, 2 Optimizations Makefile:254: recipe for target 'src/fw/ssdt-misc.hex' failed make[2]: *** [src/fw/ssdt-misc.hex] Error 255 Makefile:80: recipe for target 'build' failed make[1]: *** [build] Error 2 payloads/external/Makefile.inc:85: recipe for target 'seabios' failed make: *** [seabios] Error 2 I then removed the config with rm .config* ran again 'make menuconfig' and chose again the board that i was able to build an image before some minutes with a warning ( https://mail.coreboot.org/pipermail/coreboot/2018-August/087162.html ). Then i ran 'make'. Now i also get for that board the issue i have copied above. This Compiling IASL src/fw/ssdt-misc.hex failed again. But it was probably working before because i had got an image.

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Updated invitation with note: community meeting @ Every 4 weeks from 10:00 to 11:00 on Thursday from Thu Aug 17, 2017 to Wed Aug 15 (PDT) (coreboot@coreboot.org)
by gaumless＠gmail.com 16 Aug '18

16 Aug '18

This event has been changed with this note: "Nobody seems to be doing this anymore, so I'm deleting it." Title: community meeting Phone bridge call in numbers: https://www.bluejeans.com/numbers Meeting ID: 616384323 Current agenda & history: https://coreboot-meeting.pads.ccc.de/CommunityMeetingTopics? Full meeting Details on the wiki: https://www.coreboot.org/Coreboot_community_meeting Info about native bluejeans apps: https://www.bluejeans.com/downloads When: Every 4 weeks from 10:00 to 11:00 on Thursday from Thu Aug 17, 2017 to Wed Aug 15 Pacific Time - Los Angeles (changed) Where: https://bluejeans.com/616384323 Calendar: coreboot(a)coreboot.org Who: * coreboot.org(a)gmail.com - creator * coreboot(a)coreboot.org Event details: https://www.google.com/calendar/event?action=VIEW&eid=dG1hZ2RkaDJmdm82NmQ2a… Invitation from Google Calendar: https://www.google.com/calendar/ You are receiving this courtesy email at the account coreboot(a)coreboot.org because you are an attendee of this event. To stop receiving future updates for this event, decline this event. Alternatively you can sign up for a Google account at https://www.google.com/calendar/ and control your notification settings for your entire calendar. Forwarding this invitation could allow any recipient to modify your RSVP response. Learn more at https://support.google.com/calendar/answer/37135#forwarding

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Re: [coreboot] Build fails on Thinkpad W520
by Andrew A. I. 16 Aug '18

16 Aug '18

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Re: [coreboot] Build fails on Thinkpad W520
by Nico Huber 16 Aug '18

16 Aug '18

Hi Andreas, On 16.08.2018 08:25, Andreas Restle wrote: > Building coreboot for Thinkpad W520 currently fails with the following > error: > > CC romstage/northbridge/intel/sandybridge/raminit_common.o > In file included from src/northbridge/intel/sandybridge/raminit_common.c:18: > src/northbridge/intel/sandybridge/raminit_common.c: In function > 'dram_odt_stretch': > src/northbridge/intel/sandybridge/raminit_common.c:211:49: error: 'reg' > undeclared (first use in this function); did you mean 'prog'? > printram("OTHP Workaround [%x] = %x\n", addr, reg); it seems you have CONFIG_DEBUG_RAM_SETUP enabled. This is really only for debugging and nothing for end users / production builds. Debugging code is often broken (even when it does compile). Nico

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Re: [coreboot] L1TF
by Rudolf Marek 16 Aug '18

16 Aug '18

Hi, On 15.8.2018 15:58, Shawn wrote: > According to the vulnerability analysis, the SMM is affected by L1TF. Since > SMM code base in coreboot is much smaller than OEM's firmware, IMOHO L1TF is > not practical on coreboot. Any idea about is coreboot vulnerable to L1TF? You need an updated microcode, so the RSM will flush L1 cache (if L1D flush is advertised) else perhaps you will need as a workaround read at least 64KB of memory (L1 is 32KB but replacement policy is "not exactly LRU") also, you need to make sure that that all SMM cores will enter SMM same time. I don't remember how coreboot does that on Intel chips. Perhaps it is so. Remember that with L1TF you can only read any secrets which could be stored in L1. If coreboot has no secrets there, you don't need to do anything. Modification of data is not possible with this attack. Thanks Rudolf

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Build fails on Thinkpad W520
by Andreas Restle 16 Aug '18

16 Aug '18

Building coreboot for Thinkpad W520 currently fails with the following error: CC romstage/northbridge/intel/sandybridge/raminit_common.o In file included from src/northbridge/intel/sandybridge/raminit_common.c:18: src/northbridge/intel/sandybridge/raminit_common.c: In function 'dram_odt_stretch': src/northbridge/intel/sandybridge/raminit_common.c:211:49: error: 'reg' undeclared (first use in this function); did you mean 'prog'? printram("OTHP Workaround [%x] = %x\n", addr, reg); ^~~ src/include/console/console.h:65:31: note: in definition of macro 'printk' do { do_printk(LEVEL, fmt, ##args); } while (0) ^~~~ src/northbridge/intel/sandybridge/raminit_common.c:211:3: note: in expansion of macro 'printram' printram("OTHP Workaround [%x] = %x\n", addr, reg); ^~~~~~~~ src/northbridge/intel/sandybridge/raminit_common.c:211:49: note: each undeclared identifier is reported only once for each function it appears in printram("OTHP Workaround [%x] = %x\n", addr, reg); ^~~ src/include/console/console.h:65:31: note: in definition of macro 'printk' do { do_printk(LEVEL, fmt, ##args); } while (0) ^~~~ src/northbridge/intel/sandybridge/raminit_common.c:211:3: note: in expansion of macro 'printram' printram("OTHP Workaround [%x] = %x\n", addr, reg); ^~~~~~~~ make: *** [Makefile:339: build/romstage/northbridge/intel/sandybridge/raminit_common.o] Fehler 1 I've been using coreboot on the W520 for some time now, thanks to Charlotteplusplus and Nico Rikken (thank you both!). This is the first time I encountered this error. Branch master, freshly pulled of git. Thinkpad W520, 32GB Ram, i7-3940XM (Ivybridge). Any help is much appreciated. -- <°)))>< Andreas Restle andreas.restle(a)gmail.com

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coreboot August 2018