May 2017 - coreboot - mail.coreboot.org

Re: [coreboot] Blobless coreboot on Sandy Bridge and Ivy Bridge?
by Arthur Heymans May 26, 2017

May 26, 2017

Thomasheidler via coreboot <coreboot(a)coreboot.org> writes: > If one excludes any microcode and the VGA BIOS, is it possible to build a functioning, > blobless coreboot for any Sandy Bridge or Ivy Bridge device supported? I'm referring here > only to the BIOS region on the flash, not the ME region, IFD and GbE. If the FSP blob is > needed, would that be the only blob required? Coreboot has native x86 code to fully initialize sandy bridge without blobs. Even the VGA bios can be replaced with existing native graphic init (C code for LVDS or libgfxinit for every display output). There is an FSP path for sandy bridge but it is not used much due to native code being easier to work with. > > Thanks <#secure method=pgpmime mode=sign> -- Arthur Heymans

1 0

Blobless coreboot on Sandy Bridge and Ivy Bridge?
by Thomasheidler May 26, 2017

May 26, 2017

If one excludes any microcode and the VGA BIOS, is it possible to build a functioning, blobless coreboot for any Sandy Bridge or Ivy Bridge device supported? I'm referring here only to the BIOS region on the flash, not the ME region, IFD and GbE. If the FSP blob is needed, would that be the only blob required? Thanks

1 0

Re: [coreboot] ASUS KGPE-D16 Automated Test Failure [master]
by Timothy Pearson May 26, 2017

May 26, 2017

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 05/26/2017 10:40 AM, Martin Roth wrote: > On Thu, May 25, 2017 at 11:58 AM, Timothy Pearson > <tpearson(a)raptorengineering.com> wrote: > ... >>> It's this a false positive? i.e. it's a problem with the test or >>> actually coreboot doesn't boot? > ... >> I've been wondering if I should lower the debug level on the test stand >> for this particular board to mask the problem, or if these occasional >> reminders might prod someone to take a look at the problem? > > My opinion is that you should lower the debug level if that solves the > problem. Having REACTS fail occasionally for a known bug on that > platform probably won't spur anyone to look at that problem, it will > just make people ignore real failures. > > Martin Point well taken. In addition to the hang issue the hardware on the test stand seems to be experiencing another fault (not coreboot related); I've disabled the KGPE-D16 tests for now pending diagnostics. - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJZKHUCAAoJEK+E3vEXDOFbnncIAIhQGJgjeCVoZMrihdmfVaop 53pOEHmLerPKuduqFdooHHkMuE9/fZMraVJVF4m1oOQPI3Dne6UwmcuUrkcZvCoA Oq/pgeU2CeHT8YKVAFSQzc9+Fy4rUxQb05qEy1WboD3Sp49jLAkDDHTQ2S7dTxQs 06eirVIprJ9NpANoo8Ekip8Mggae+GcZjtYZONNZAkGQ//7aT4o+jwsOmcFcy5+7 HCSb0EPIMv7Qq0W9mTWaijDlGqWUCTGRz3qXcaEmqD5TrSJWha6uzq0vK4134CYi lMeFXfJOt3nV+QDlTY/gLqX001aFlbKeGxHiputnIVj2Oz5FWW6I/pq4C6i9h+Q= =GhAR -----END PGP SIGNATURE-----

1 0

ASUS KGPE-D16 Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand May 26, 2017

May 26, 2017

The ASUS KGPE-D16 fails verification for branch master as of commit 6b697ef207674c58b47058b37e11fc97634d5cb4 The following tests failed: BOOT_FAILURE Commits since last successful test: 6b697ef util/hugo: no need to enable an interactive terminal dc5eea1 util/hugo: mark source mounts read-only 73108de mainboard/google/poppy: Add PowerResource for touchscreen device See attached log for details This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

1 0

Documentation on the website
by Patrick Georgi May 26, 2017

May 26, 2017

Hi everybody, to elaborate a bit on what Martin reported from the community meeting: In the last few days I set up our server[0] to regularly render our repositories Documentation/ directory to https://www.coreboot.org/Documentation/, using hugo for formatting and conversion. The old "Documentation" page on the wiki was renamed to Documentation/old. The consequence is that contributions to documentation can be made with the same credentials and using the same review process on gerrit as code contributions. This should alleviate some of the concerns that were recently voiced on this list over the process to obtain wiki accounts. This transition is far from done: Documentation/ itself is a collection of docs of the last 15 years in at least four different formats (TeX, unstructured ASCII text, markdown, PDF), some of it outdated, most of it without declaring a license for distribution (I suppose GPLv2, just like the entire tree, might be applicable, but we should definitely see that we get on top of things here). Documentation/ now explicitly declares CC-BY 4.0 as license for all new contributions as of 2 days ago (there weren't any, so no unexpected surprises here), providing a much clearer situation going forward. The configuration of the site is rather rudimentary: Several documents aren't linked anywhere and the sidebar is somewhat nonsensical, merely mirroring what the old index.html exposed. The design might need improvements. All in all I believe it's a foundation to build upon, though. I'll clean up things over time, but that's not my primary project right now. Feel free to beat me to it :-) Contributions welcome! Thanks, Patrick [0] https://review.coreboot.org/#/c/19881/ plus some server-side work -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle

1 0

coreboot community meeting minutes for May 25, 2017
by Martin Roth May 26, 2017

May 26, 2017

These are the minutes from yesterday's coreboot community meeting. Information about the next meeting is at the bottom. The meeting yesterday was very short, with only 5 people attending. ####################################################################### Thursday May 25, 2017 General coreboot news & discussion * coreboot is now a member of the SFC - An announcement will be sent out on Tuesday. - This means that we can finally accept donations. - We will hold a fund-raiser shortly - Any volunteers to help plan this? - Question on the mailing list about stickers. It seems like making swag available would be good. Development * AMD SoC development for Stoney Ridge - https://mail.coreboot.org/pipermail/coreboot/2017-May/084291.html * Intel x4x northbridge has a native DDR3 raminit that currently works only on 400MHz Infrastructure news * Gerrit: We plan to update gerrit to version 2.40 on Sunday or Monday. * Jenkins: grumpybuilder is back online. boringbuilder is online but is in testing. * Fossology: https://www.coreboot.org/fossology is now online to analyze coreboot license data. Contact PatrickG or MartinR for a login if you're interested. * Documentation: We've started to get the coreboot/Documentation directory online: https://www.coreboot.org/Documentation/ - Note that this in its infancy, and not all documents are linked from the sidebar yet. Improvements will be coming. Conferences * Denver conference - Starts in just over a week - Working on billing with SFC - we will send out emails in the next couple of days. * European conference - Need to figure out billing details now that coreboot has joined the SFC. - Bochum has flyers - contact Philipp if you want some to distribute. https://twitter.com/_zaolin_/status/867356006552137728 ################################################################## Next meeting is Thursday, June 8, 2017 Check the coreboot calendar for the time in your timezone https://www.coreboot.org/calendar.html Join using the bluejeans web app or the phone bridge: https://bluejeans.com/616384323 Phone bridge call in numbers: https://www.bluejeans.com/numbers Meeting ID: 616384323 Current agenda & history: https://coreboot-meeting.pads.ccc.de/CommunityMeetingTopics

1 0

Re: [coreboot] ASUS KGPE-D16 Automated Test Failure [master]
by Timothy Pearson May 26, 2017

May 26, 2017

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 05/25/2017 12:35 PM, BogDan Vatra wrote: > Hi, > > It's this a false positive? i.e. it's a problem with the test or > actually coreboot doesn't boot? > > BogDan. There remains an undiagnosed race condition in coreboot's Opteron startup code that leads to an occasional (empirically this seems to be a 1 in 3 chance) hang in ramstage when the debug level is cranked up and the AP console output is enabled. I've been wondering if I should lower the debug level on the test stand for this particular board to mask the problem, or if these occasional reminders might prod someone to take a look at the problem? - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJZJxs6AAoJEK+E3vEXDOFbKIsH/iS3yOPdg27VSd1qrcF+ArWf DvqbyRw6/n0uVH74GL+H2hzZljCg8zhgzpBCcF66EqNMdmLri1VSQo3BI6fe7j7K 0ozJ9BbK1UU4yuY40BFOF7zVRE0aPE8HdNoY7tUzFBAA5tslSgfuk158FeejEmXB /qdhBiIjaGoIF8bbOMgg8lI9XUwHxpi2Dvqo7pOH58/bYmavGaKQEgai8ntDtwR7 xFt+kFNqhXvX21990sxOvK44Z0h+P7rPDMjNqniyCQbxR8hGpkflyHjNCBAQ8+i9 7QuMvnPmcaLIjW4FqEmXOFGfI0GAdqzXYARz9/ptmQoOys5u6JAJfz+oDv/4uJw= =00Vf -----END PGP SIGNATURE-----

2 1

Re: [coreboot] 2017 North American coreboot Conference
by Martin Roth May 26, 2017

May 26, 2017

Hi Juliana, (and anyone else who has opinions) I'm curious how we should have communicated this better so that we can improve communication for next year, and for the October conference in Germany: https://ecc2017.coreboot.org/ Here's what we've done: 1) We've had a banner across the top of the coreboot homepage for the past month: https://coreboot.org 2) We've had the information set as the topic of the #coreboot IRC channel for most of the past 2 months. 3) We've sent out periodic emails to the coreboot mailing list talking about it. 4) We've announced it on twitter several times. 5) It's mentioned every 2 weeks in the coreboot community meeting, and sent to the mailing list as a part of the minutes. What do you think we should have done to get more attention. Obviously from Naveed's question, other people feel that we haven't been communicating enough either. Martin On Thu, May 25, 2017 at 9:20 PM, Juliana Rodrigues <juliana.orod(a)gmail.com> wrote: > Hey, > > It is a shame that I've learned about the conference just now. > Plane tickets to Denver are too expensive atm. > > Juliana > > 2017-05-25 23:43 GMT-03:00 Martin Roth <gaumless(a)gmail.com>: >> >> Hi Naveed, >> Yes, the conference is definitely happening. For anyone who doesn't >> know where to find the information about the Denver conference, here's >> the link: https://coreboot.org/Denver2017 >> >> We've got 30 people signed up to attend currently, and expect that a >> few more will sign up in the next week. >> >> We're working with the SFC on billing. We'll be sending out emails to >> all registered attendees next week with billing information. This is >> obviously much closer that we wanted it to be, but the paperwork for >> the SFC didn't get finished until last week. An announcement about >> coreboot joining the SFC will be going out shortly. >> >> We'll also be sending another email next week with additional >> information about the conference along with arrival information and >> our contact information in case there are any issues for anyone >> arriving in town. >> >> Martin >> >> >> On Thu, May 25, 2017 at 7:31 PM, Naveed Ghori <naveed.ghori(a)dti.com.au> >> wrote: >> > Hi, >> > >> > Any update on registration payment and number of people attending. >> > >> > I guess I just want verification that it is still on there has been no >> > communications recently. >> > >> > >> > >> > Cheer, >> > >> > Naveed >> > >> > >> > >> > From: coreboot [mailto:coreboot-bounces@coreboot.org] On Behalf Of >> > Martin >> > Roth >> > Sent: Friday, 3 February 2017 1:32 AM >> > To: coreboot >> > Subject: [coreboot] 2017 North American coreboot Conference >> > >> > >> > >> > We are happy to announce that the 2017 North American coreboot >> > Conference >> > will be held in Denver, Colorado on June 5th & 6th, with an optional >> > hacking >> > day on June 7th. >> > >> > >> > Register here: https://goo.gl/o2j4gX >> > >> > >> > >> > The cost will be $250 for corporate attendees, $100 for individuals, and >> > $25 >> > for students. >> > >> > All fees go up by $50 for registrations received after May 5. >> > >> > Payment is NOT required at the time of registration. We will contact >> > you >> > later with payment information. >> > >> > >> > >> > >> > Hotel, travel, and other additional information is available on the >> > coreboot >> > wiki: https://www.coreboot.org/Denver2017 >> > >> > >> > >> > >> > >> > If you have any questions, please email us at convention(a)coreboot.org >> > >> > >> > >> > >> > >> > Martin >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot > >

1 0

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com May 26, 2017

May 26, 2017

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1375671: (NO_EFFECT) /src/soc/samsung/exynos5420/spi.c: 213 in spi_ctrlr_setup() /src/soc/qualcomm/ipq806x/spi.c: 767 in spi_ctrlr_setup() /src/soc/qualcomm/ipq40xx/spi.c: 657 in spi_ctrlr_setup() ________________________________________________________________________________________________________ *** CID 1375671: (NO_EFFECT) /src/soc/samsung/exynos5420/spi.c: 213 in spi_ctrlr_setup() 207 struct exynos_spi *regs = to_exynos_spi(slave)->regs; 208 setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); 209 } 210 211 static int spi_ctrlr_setup(const struct spi_slave *slave) 212 { >>> CID 1375671: (NO_EFFECT) >>> This greater-than-or-equal-to-zero comparison of an unsigned value is always true. "slave->bus >= 0U". 213 ASSERT(slave->bus >= 0 && slave->bus < 3); 214 struct exynos_spi_slave *eslave; 215 216 eslave = to_exynos_spi(slave); 217 if (!eslave->initialized) { 218 exynos_spi_init(eslave->regs); /src/soc/qualcomm/ipq806x/spi.c: 767 in spi_ctrlr_setup() 761 762 /* 763 * IPQ GSBI (Generic Serial Bus Interface) supports SPI Flash 764 * on different GSBI5, GSBI6 and GSBI7 765 * with different number of chip selects (CS, channels): 766 */ >>> CID 1375671: (NO_EFFECT) >>> This less-than-zero comparison of an unsigned value is never true. "bus < 0U". 767 if ((bus < GSBI5_SPI) || (bus > GSBI7_SPI) 768 || ((bus == GSBI5_SPI) && (cs > 3)) 769 || ((bus == GSBI6_SPI) && (cs > 0)) 770 || ((bus == GSBI7_SPI) && (cs > 0))) { 771 printk(BIOS_ERR, "SPI error: unsupported bus %d " 772 "(Supported busses 0,1 and 2) or chipselect\n", bus); /src/soc/qualcomm/ipq40xx/spi.c: 657 in spi_ctrlr_setup() 651 { 652 struct ipq_spi_slave *ds = NULL; 653 int i; 654 unsigned int bus = slave->bus; 655 unsigned int cs = slave->cs; 656 >>> CID 1375671: (NO_EFFECT) >>> This less-than-zero comparison of an unsigned value is never true. "bus < 0U". 657 if ((bus < BLSP0_SPI) || (bus > BLSP1_SPI) 658 || ((bus == BLSP0_SPI) && (cs > 2)) 659 || ((bus == BLSP1_SPI) && (cs > 0))) { 660 printk(BIOS_ERR, 661 "SPI error: unsupported bus %d (Supported busses 0, 1 and 2) " 662 "or chipselect\n", bus); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0… To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

1 0

Re: [coreboot] ATOM processor E3845
by Zoran Stojsavljevic May 26, 2017

May 26, 2017

Hmmmm... I went to the standard page: www.intel.com/fsp, and, indeed, it is completely redesigned. INTEL PED, amazingly, use now GitHub: https://github.com/IntelFsp/FSP . Woooow! ;-) Zoran On Fri, May 26, 2017 at 12:26 AM, Martin Roth <gaumless(a)gmail.com> wrote: > Hi Benjamin, > Yes, coreboot does support the E3845 via the Intel FSP. Among other > boards, it's used in the Minnowboard turbot, which is supported in > src/mainboards/intel/minnowmax > > Information about the Baytrail FSP can be found here: https://github.com/ > IntelFsp/FSP/blob/BayTrail/BayTrailFspBinPkg/Docs/ > BayTrailFspIntegrationGuide.pdf > > The Embedded Firmware Solutions book https://www.apress.com/us/ > book/9781484200711 might also be helpful to you. > > Finally, if you're just getting into coreboot, you might be interested in > hiring someone to help guide you or to do the port for you: > https://www.coreboot.org/consulting.html > > Martin > > On Thu, May 25, 2017 at 1:47 AM, <bnakache(a)nolam.com> wrote: > >> Hello All , >> >> >> >> We are wondering if coreboot supports the ATOM processor E3845 >> >> >> >> If it does please send us the information required for us to work on it >> for one of our motherboard. >> >> >> >> >> >> >> >> >> >> >> >> Best Regards, >> >> Benjamin Nakache >> >> Vice President Sales >> >> [image: nolam logo small] >> >> *www.nolam.com <http://www.nolam.com/>* >> >> >> >> >> >> >> >> Note: This message and any attachment hereto is intended solely for the >> use of the designated recipient(s) and their appointed delegates and may >> contain confidential information. Any unauthorized use, disclosure,copying, >> or distribution of its contents is strictly prohibited. If you have >> received this message in error, please destroy it and advise Nolam Embedded >> Systems immediately by phone, email, or fax.Thank you for your cooperation. >> >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot >> > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

1 0