coreboot May 2017

coreboot@coreboot.org

70 participants
202 discussions

Re: [coreboot] CONFIG_CBFS_SIZE vs CONFIG_ROM_SIZE
by Patrick Georgi 23 May '17

23 May '17

We always add an FMAP now (think of it of a vendor neutral flash partition table), which resides outside CBFS. 2017-05-23 9:49 GMT-07:00 Gailu Singh <gailu96(a)gmail.com>: > Hi Experts, > > If we use CBFS_SIZE to be same as ROM_SIZE on our apollolake board grub > fails to load grub.cfg located in CBFS. Based on experiments we found that > grub.cfg is loaded correctly if we keep minimum difference of 64KB between > CBFS_SIZE and ROM_SIZE if we reduce it to less that 64KB problem happens. > > Can someone please explain the behavior and if it is expected behavior or > a bug? > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot > -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle

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CONFIG_CBFS_SIZE vs CONFIG_ROM_SIZE
by Gailu Singh 23 May '17

23 May '17

Hi Experts, If we use CBFS_SIZE to be same as ROM_SIZE on our apollolake board grub fails to load grub.cfg located in CBFS. Based on experiments we found that grub.cfg is loaded correctly if we keep minimum difference of 64KB between CBFS_SIZE and ROM_SIZE if we reduce it to less that 64KB problem happens. Can someone please explain the behavior and if it is expected behavior or a bug?

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Re: [coreboot] REG : coreboot with UEFI payload
by Martin A 23 May '17

23 May '17

Hi, I am not an expert at all, so I am for sure asking dummy question: PB1: from this how-to (https://github.com/pgeorgi/edk2) wich solution did you try: with or without CSM support ? PB2: with CSM support you use a payload (Tiano) in payload (Seabios) loading method. (It's why you fall back to Seabios, right ?) PB2: why not use QEMU as mentioned here https://www.coreboot.org/Lesson1 ? Martin. ________________________________ De : nagaraj a <nagarajnn(a)gmail.com> Envoyé : mardi 23 mai 2017 14:04 À : Martin A Objet : Re: [coreboot] REG : coreboot with UEFI payload Hi Martin, Thanks a lot for the response. Below are the details. Problem 1: Yes I am using Tianocore . I have compiled Tianocore UEFI payload successfully - However while INTEGRATING UEFI payload with coreboot I was facing the issue with error "The stage file is not in ELF format" .PFA screen shot FYR. However after converting UEFI Payload image to ELF format I am able to INTEGRATE successfully. Problem 2: After successful INTEGRATION I am trying to run coreboot in Virtual Manager, however I am not able to run coreboot with UEFI payload in Virtual Machine Manager and not able to launch UEFI BIOS and it falls back to SeaBIOS – looks like the VM don’t support firmware UEFI and the option is gray-out here. PFA screen for your reference. I am not sure if Virtual Manager support coreboot with UEFI payload. Pls suggest. Thanks, Nagaraj A On Tue, May 23, 2017 at 2:15 PM, Martin A <tintinsansmilou(a)hotmail.com<mailto:tintinsansmilou@hotmail.com>> wrote: Hi, Are you trying Tianocore ? I don't see the error you're talking about ? Martin. ________________________________ De : coreboot <coreboot-bounces(a)coreboot.org<mailto:coreboot-bounces@coreboot.org>> de la part de nagaraj a <nagarajnn(a)gmail.com<mailto:nagarajnn@gmail.com>> Envoyé : mardi 23 mai 2017 08:23 À : coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> Objet : [coreboot] REG : coreboot with UEFI payload Hi All, I'm trying to compiling coreboot with UEFI payload, however I couldn't able to get proper out file and below is the error. Pls let us know, If I am missing any configuration or compilation procedure? To instrumentation I’m trying to run coreboot UEFI payload in QEMU and will then proceed for actual H/W Thanks, Nagaraj A -- Thanks &Regards Nagaraj A Bangalore

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 23 May '17

23 May '17

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1375565: Control flow issues (DEADCODE) /src/drivers/spi/spi_flash.c: 303 in spi_flash_generic_probe() ________________________________________________________________________________________________________ *** CID 1375565: Control flow issues (DEADCODE) /src/drivers/spi/spi_flash.c: 303 in spi_flash_generic_probe() 297 for (i = 0; i < sizeof(idcode); i++) 298 printk(BIOS_SPEW, "%02x ", idcode[i]); 299 printk(BIOS_SPEW, "\n"); 300 } 301 302 /* count the number of continuation bytes */ >>> CID 1375565: Control flow issues (DEADCODE) >>> Execution cannot reach the expression "*idp == 127" inside this statement: "for ((shift = 0) , (idp = i...". 303 for (shift = 0, idp = idcode; shift < IDCODE_CONT_LEN && *idp == 0x7f; 304 ++shift, ++idp) 305 continue; 306 307 printk(BIOS_INFO, "Manufacturer: %02x\n", *idp); 308 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0… To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Intel Rangeley: System is hanging after post code 0x92.
by Dhanasekar Jaganathan 23 May '17

23 May '17

Hi All, I am trying to boot Intel Atom Rangeley Sever CPU (Mohon Peak) with coreboot BIOS. After Postcode 0x92, system is not booting. I have pasted the debug message below, *coreboot-4.5-1596-gb86ccbb Thu Apr 20 14:55:30 UTC 2017 romstage starting...* *POST: 0x41* *POST: 0x42* *Setting up static southbridge registers... done.* *Disabling Watchdog timer... done.* *RTC Failure detected. Resetting Date to 04/20/2017* *RTC Init* *RTC: Clear requested zeroing cmos* *POST: 0x46* *POST: 0x47* *Starting the Intel FSP (early_init)* *Configure Default UPD Data* *PcdEnableIQAT 1* *PcdEnableLan 1* *PcdEnableLan 1* *PcdEnableLan 1* *PcdEnableLan 1* *PcdEnableUsb20 1* *PcdEnableSata2 1* *PcdEnableSata3 1* *PcdPcieRootPort1DeEmphasis: 0x00 (default)* *PcdPcieRootPort2DeEmphasis: 0x00 (default)* *PcdPcieRootPort3DeEmphasis: 0x00 (default)* *PcdPcieRootPort4DeEmphasis: 0x00 (default)* *CBFS: 'Master Header Locator' located CBFS at [100:7fffc0)* *CBFS: Locating 'mrc.cache'* *CBFS: Checking offset 0* *CBFS: File @ offset 0 size 20* *CBFS: Unmatched 'cbfs master header' at 0* *CBFS: Checking offset 80* *CBFS: File @ offset 80 size 5e84* *CBFS: Unmatched 'fallback/romstage' at 80* *CBFS: Checking offset 5f80* *CBFS: File @ offset 5f80 size 227* *CBFS: Unmatched 'config' at 5f80* *CBFS: Checking offset 6200* *CBFS: File @ offset 6200 size 23a* *CBFS: Unmatched 'revision' at 6200* *CBFS: Checking offset 6480* *CBFS: File @ offset 6480 size 528* *CBFS: Unmatched 'cmos_layout.bin' at 6480* *CBFS: Checking offset 6a00* *CBFS: File @ offset 6a00 size 1f96* *CBFS: Unmatched 'fallback/dsdt.aml' at 6a00* *CBFS: Checking offset 8a00* *CBFS: File @ offset 8a00 size 7498* *CBFS: Unmatched '' at 8a00* *CBFS: Checking offset fec0* *CBFS: File @ offset fec0 size 10000* *CBFS: Found @ offset fec0 size 10000* *find_current_mrc_cache_local: No valid fast boot cache found.* *FSP MRC cache not present.* *POST: 0x92* Is there any setting I need to do in "make menuconfig"?. Actually, It should go to RAM Stage, but it is not. Please provide suggestion. Thanks, Dhanasekar

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Re: [coreboot] Asus M2N-E: Waiting for 1 CPUS to stop
by Timothy Pearson 23 May '17

23 May '17

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 05/21/2017 09:46 AM, Martin A wrote: > > > Thank you very much Timothy ! > > debug level @ WARNING and it boots well -> a nice bootlog in a 1 or 2 > seconds, so fast !! > > > But Seabios do not boot well: > > Ubuntu 16.04 internal SATA Drive -> PnPBIOS dev_node_info funstions not > avilable an this system > > Windows 7 x64 USB drive -> Non ACPI Bios > > > Any tips/advice I'm not directly familiar with this system; without a full boot log I'd just be guessing. :-) Perhaps someone else on this list has experience with this mainboard and recognizes these issues? - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJZIw1dAAoJEK+E3vEXDOFbP3UH/iq/A0ReMOo8vA9xc2Yxw26l foGQ01st8f/rpqlR/hY3lG4yo2F0lhF4To8JMNCjystC9BQshRPI4E/GJERjXjiH EufAY0NOV4DShp3Bo43ICpDx9XgEAkTcGBG0OklxMmvpC85nBRvdXe+8yDpLE7Gv 2GKoQH1Y1RbkwQ/8ynae0V63SEYVNbDCqI+5Z0PnZ4vs8auRLlp5GKyfsHGSjKlV CA5cJxOiEPkkjO4nWUqmUq0E8bg5F+Ax14ynsyVQxJLEOA39l4HzjClhwqHcepZt 8vGuFuaoNAW38VDhPauzM0yPrb8muN5np5bfJIDZuvbwCkgpI4MAEhaZKO2Ila4= =KfyS -----END PGP SIGNATURE-----

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REG : coreboot with UEFI payload
by nagaraj a 23 May '17

23 May '17

Hi All, I'm trying to compiling coreboot with UEFI payload, however I couldn't able to get proper out file and below is the error. Pls let us know, If I am missing any configuration or compilation procedure? To instrumentation I’m trying to run coreboot UEFI payload in QEMU and will then proceed for actual H/W Thanks, Nagaraj A

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Re: [coreboot] Intel me problems
by Alejandro Flores 23 May '17

23 May '17

Ok, so the image John uploaded of a known good me is exactly the same as the one I have been using that fails. The shasums match exactly. So I thought maybe somehow it is getting corrupted when coreboot creates the rom. I used the unhuffme tool to examine both the raw me image and the coreboot.rom file I am currently using. Both are identical except the full rom has 4 extra lines regarding the location of flash regions at the top. The output of unhuffme is here: https://pastebin.com/zRsh6TqA I downloaded the latest version of intelmetool to check out the live running me but it says my hardware is not compatible. I'm stumped at this point. If the me image is good why does the checksum fail on boot?

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Re: [coreboot] Easier accessibility for coreboot/flashrom wikipedias? What do you think?
by Peter Stuge 22 May '17

22 May '17

First, I agree with the goal of lowering the administrative overhead for write access to the wiki. qma ster wrote: > My proposal is to give the edit rights to all the subscribers of the > coreboot/flashrom mailing lists .. > I strongly believe that all the members of coreboot/flashrom > mailing lists are responsible smart individuals I don't believe that at all. There is no evidence whatsoever to support that all subscribed email addresses actually correspond to individuals. I expect that many list recipients are programs. > Alternatively, the registration could be made completely open, but > with a strong registration/login captcha or maybe even per-edit > captcha to prevent the automatic bots/spammers from ruining the > wiki pages CAPTCHA is not a good tool. It is easy to acquire human solving capacity if you can offer something desirable in exchange. It only stops very low end bots, and unless the challenge is self-hosted it is likely actually training some other bots. I think a more workable and sustainable solution is to enable more people to grant write access. Another project uses an IRC bot for this task, so that a group of trusted users on the IRC channel(s) can grant write access immediately. It works really well. However, it requires some programming to implement. Please volunteer to work on creating this solution if you can. I guess that it's about a week of R&D. //Peter

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coreboot at FrOSCon Germany? CFP ends tomorrow
by Carl-Daniel Hailfinger 22 May '17

22 May '17

Hi, the Call for Projects for the FrOSCon conference deadline is tomorrow. https://www.froscon.de/1/cfp/cfprojects/ Conference date: 19th and 20th August 2017 Location: University of Applied Sciences Bonn-Rhein-Sieg, Sankt Augustin, Germany Did anybody already submit a proposal? If not, I'll try to make an attempt at it. I can be there, and I know the location. Last year coreboot was present at the booth of the BSI (Bundesamt für Sicherheit in der Informationstechnik, Federal Office for Information Security Germany), but I'm not yet sure if there will be a BSI presence again. If there is a BSI presence, I will be in charge of that as well, so unless anybody else volunteers, I'll try to handle this as a joint appearance again. Regards, Carl-Daniel

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coreboot May 2017