coreboot October 2017

coreboot@coreboot.org

66 participants
140 discussions

Re: [coreboot] Add socket support for amd/socket-ft1?
by Alexandre Desnoyers 17 Oct '17

17 Oct '17

Hi, You probably should look into the "persimmon" AMD motherboard, which is the AMD reference design for the FT1. Check in the directory : ./src/mainboard/amd/persimmon/ I can tell you that this persimmon motherboard is booting on my own FT1 custom SoC design with very few changes. Regards, Alexandre Desnoyers Electronic Design Engineer Qtechnology A/S coreboot-request(a)coreboot.org wrote: > Date: Sun, 15 Oct 2017 01:31:45 +0200 > From: Christoph Pomaska<christoph.pomaska(a)posteo.de> > To:coreboot@coreboot.org > Subject: [coreboot] Add socket support for amd/socket-ft1? > Message-ID:<b6e3a1c0-b7f5-a9be-5f3d-3a41a0f02e14(a)posteo.de> > Content-Type: text/plain; charset=utf-8; format=flowed > > Hi, > > > I am currently attempting to port a not-yet supported Foxconn SoC > mainboard, but I am currently stuck at the variable "CPU_SOCKET_TYPE" > while trying to add a config for the socket the board is using (FT1/BGA413). > > I took a look into the socket_AM3 Kconfig and it said "0x11", the same > as in socket_AM2r2 and socket_AM2, but these are different chipsets. How > is this variable to define? > > > Best regards > > Sellerie

2 1

Re: [coreboot] [KGPE-D16] No video output with Ati x600se GPU
by Daniel Kulesz 15 Oct '17

15 Oct '17

Hi, > I'm having issues to use an Ati x600se 128mb GPU (OEM DELL) with my KGPE-D16. > With ASUS BIOS, the card works fine (either in first or second pcie-x16 slot) > With coreboot, no video output. The board still boots but the card isn't detected at all. (either in first or second pcie-x16 slot) > I don't know what is the issue since I was using a GTX660 before without issue. It seems like you are not using SeaBIOS. Normally, Seabios initializes PCI devices. Are you sure you are using the same coreboot configuration that worked fine for your GTX660 with this ATI card or did you rebuild/reflash coreboot inbetween? > Do I need to embed the VGA rom in cbfs for this card ? No, afaik the VGA rom is only needed for native gfx init on (some) devices with embedded graphics but not for add-on pci(e) cards. Cheers, Daniel

3 2

Add socket support for amd/socket-ft1?
by Christoph Pomaska 14 Oct '17

14 Oct '17

Hi, I am currently attempting to port a not-yet supported Foxconn SoC mainboard, but I am currently stuck at the variable "CPU_SOCKET_TYPE" while trying to add a config for the socket the board is using (FT1/BGA413). I took a look into the socket_AM3 Kconfig and it said "0x11", the same as in socket_AM2r2 and socket_AM2, but these are different chipsets. How is this variable to define? Best regards Sellerie

1 0

[KGPE-D16] No video output with Ati x600se GPU
by aether 14 Oct '17

14 Oct '17

Hello, I'm having issues to use an Ati x600se 128mb GPU (OEM DELL) with my KGPE-D16. With ASUS BIOS, the card works fine (either in first or second pcie-x16 slot) With coreboot, no video output. The board still boots but the card isn't detected at all. (either in first or second pcie-x16 slot) I don't know what is the issue since I was using a GTX660 before without issue. Do I need to embed the VGA rom in cbfs for this card ? Here are some logs (coreboot 4.6-1092-ge0b5795b81) with Ati card plugged in. config # This image was built using coreboot 4.6-1092-ge0b5795b81 CONFIG_USE_OPTION_TABLE=y CONFIG_VENDOR_ASUS=y # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_BOARD_ASUS_KGPE_D16=y # CONFIG_DRIVERS_UART_8250IO is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y CONFIG_CPU_MICROCODE_CBFS_NONE=y CONFIG_SEABIOS_PS2_TIMEOUT=100 ---- payload_config # # Automatically generated file; DO NOT EDIT. # SeaBIOS Configuration # # # General Features # CONFIG_COREBOOT=y # CONFIG_QEMU is not set # CONFIG_CSM is not set # CONFIG_QEMU_HARDWARE is not set CONFIG_THREADS=y CONFIG_RELOCATE_INIT=y CONFIG_BOOTMENU=y CONFIG_BOOTSPLASH=y CONFIG_BOOTORDER=y CONFIG_COREBOOT_FLASH=y CONFIG_LZMA=y CONFIG_CBFS_LOCATION=0 CONFIG_MULTIBOOT=y CONFIG_ENTRY_EXTRASTACK=y CONFIG_MALLOC_UPPERMEMORY=y CONFIG_ROM_SIZE=0 # # Hardware support # CONFIG_ATA=y # CONFIG_ATA_DMA is not set # CONFIG_ATA_PIO32 is not set CONFIG_AHCI=y CONFIG_SDCARD=y CONFIG_MEGASAS=y CONFIG_FLOPPY=y CONFIG_FLASH_FLOPPY=y CONFIG_PS2PORT=y CONFIG_USB=y CONFIG_USB_UHCI=y CONFIG_USB_OHCI=y CONFIG_USB_EHCI=y CONFIG_USB_XHCI=y CONFIG_USB_MSC=y CONFIG_USB_UAS=y CONFIG_USB_HUB=y CONFIG_USB_KEYBOARD=y CONFIG_USB_MOUSE=y CONFIG_SERIAL=y CONFIG_LPT=y CONFIG_RTC_TIMER=y CONFIG_HARDWARE_IRQ=y CONFIG_PMTIMER=y CONFIG_TSC_TIMER=y # # BIOS interfaces # CONFIG_DRIVES=y CONFIG_CDROM_BOOT=y CONFIG_CDROM_EMU=y CONFIG_PCIBIOS=y CONFIG_APMBIOS=y CONFIG_PNPBIOS=y CONFIG_OPTIONROMS=y CONFIG_PMM=y CONFIG_BOOT=y CONFIG_KEYBOARD=y CONFIG_KBD_CALL_INT15_4F=y CONFIG_MOUSE=y CONFIG_S3_RESUME=y CONFIG_VGAHOOKS=y # CONFIG_DISABLE_A20 is not set CONFIG_TCGBIOS=y # # VGA ROM # CONFIG_NO_VGABIOS=y # CONFIG_VGA_GEODEGX2 is not set # CONFIG_VGA_GEODELX is not set # CONFIG_VGA_COREBOOT is not set # CONFIG_BUILD_VGABIOS is not set CONFIG_VGA_EXTRA_STACK_SIZE=512 # # Debugging # CONFIG_DEBUG_LEVEL=1 # CONFIG_DEBUG_SERIAL is not set CONFIG_DEBUG_COREBOOT=y ---- lspci -nn 00:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD/ATI] RD890 Northbridge only dual slot (2x16) PCI-e GFX Hydra part [1002:5a10] (rev 02) 00:00.2 IOMMU [0806]: Advanced Micro Devices, Inc. [AMD/ATI] RD990 I/O Memory Management Unit (IOMMU) [1002:5a23] 00:02.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (PCI express gpp port B) [1002:5a16] 00:04.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (PCI express gpp port D) [1002:5a18] 00:09.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (PCI express gpp port H) [1002:5a1c] 00:0a.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (external gfx1 port A) [1002:5a1d] 00:0b.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (NB-SB link) [1002:5a1f] 00:0c.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD/ATI] RD890S PCI Express bridge for GPP2 port 1 [1002:5a20] 00:0d.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD/ATI] RD890 PCI to PCI bridge (external gfx1 port B) [1002:5a1e] 00:11.0 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4394] 00:12.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] 00:12.1 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0 USB OHCI1 Controller [1002:4398] 00:12.2 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] 00:13.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] 00:13.1 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0 USB OHCI1 Controller [1002:4398] 00:13.2 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] 00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 SMBus Controller [1002:4385] (rev 3d) 00:14.1 IDE interface [0101]: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 IDE Controller [1002:439c] 00:14.2 Audio device [0403]: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 Azalia (Intel HDA) [1002:4383] 00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 LPC host controller [1002:439d] 00:14.4 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 PCI to PCI Bridge [1002:4384] 00:14.5 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 USB OHCI2 Controller [1002:4399] 00:18.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 0 [1022:1600] 00:18.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 1 [1022:1601] 00:18.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 2 [1022:1602] 00:18.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 3 [1022:1603] 00:18.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 4 [1022:1604] 00:18.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 5 [1022:1605] 00:19.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 0 [1022:1600] 00:19.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 1 [1022:1601] 00:19.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 2 [1022:1602] 00:19.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 3 [1022:1603] 00:19.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 4 [1022:1604] 00:19.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 5 [1022:1605] 00:1a.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 0 [1022:1600] 00:1a.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 1 [1022:1601] 00:1a.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 2 [1022:1602] 00:1a.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 3 [1022:1603] 00:1a.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 4 [1022:1604] 00:1a.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 5 [1022:1605] 00:1b.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 0 [1022:1600] 00:1b.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 1 [1022:1601] 00:1b.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 2 [1022:1602] 00:1b.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 3 [1022:1603] 00:1b.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 4 [1022:1604] 00:1b.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h Processor Function 5 [1022:1605] 02:00.0 Serial Attached SCSI controller [0107]: LSI Logic / Symbios Logic SAS2008 PCI-Express Fusion-MPT SAS-2 [Falcon] [1000:0072] (rev 03) 03:00.0 Ethernet controller [0200]: Intel Corporation 82574L Gigabit Network Connection [8086:10d3] 04:00.0 Ethernet controller [0200]: Intel Corporation 82574L Gigabit Network Connection [8086:10d3] 08:01.0 VGA compatible controller [0300]: ASPEED Technology, Inc. ASPEED Graphics Family [1a03:2000] (rev 10) 08:02.0 FireWire (IEEE 1394) [0c00]: LSI Corporation FW322/323 [TrueFire] 1394a Controller [11c1:5811] (rev 70) ---- nvramtool boot_option = Fallback reboot_counter = 0x0 baud_rate = 115200 interleave_chip_selects = Enable interleave_nodes = Disable interleave_memory_channels = Enable max_mem_clock = DDR3-1600 multi_core = Enable debug_level = Spew ecc_scrub_rate = 1.28us slow_cpu = off nmi = Disable gart = Enable power_on_after_fail = On ECC_memory = Enable ECC_redirection = Enable hypertransport_speed_limit = Auto minimum_memory_voltage = 1.5V compute_unit_siblings = Enable cpu_c_states = Enable cpu_cc6_state = Enable sata_ahci_mode = Enable sata_alpm = Disable dimm_spd_checksum = Enforce probe_filter = Auto l3_cache_partitioning = Disable ieee1394_controller = Enable iommu = Enable cpu_core_boost = Enable ehci_async_data_cache = Enable experimental_memory_speed_boost = Disable maximum_p_state_limit = 0xf ---- cbmem (very long) state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2a000102 sr5650_gpp_sb_init: port=0xc hw_port=0xc result=0 PciePowerOffGppPorts() port 12 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:0c.0 subordinate bus PCI Express PCI: 00:0c.0 [1002/5a20] enabled sr5650_enable: dev=0012e440, VID_DID=0xffffffff sr5650_gpp_sb_init: nb_dev=0x0012ed00, dev=0x0012e440, port=0xd PcieLinkTraining port=d:lc current state=2030400 sr5650_gpp_sb_init: port=0xd hw_port=0xd result=0 PciePowerOffGppPorts() port 13 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:0d.0 subordinate bus PCI Express PCI: 00:0d.0 [1002/5a1e] enabled sb7xx_51xx_enable() PCI: 00:11.0 [1002/4394] ops PCI: 00:11.0 [1002/4394] enabled sb7xx_51xx_enable() PCI: 00:12.0 [1002/4397] ops PCI: 00:12.0 [1002/4397] enabled sb7xx_51xx_enable() PCI: 00:12.1 [1002/4398] ops PCI: 00:12.1 [1002/4398] enabled sb7xx_51xx_enable() PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled sb7xx_51xx_enable() PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb7xx_51xx_enable() PCI: 00:13.1 [1002/4398] ops PCI: 00:13.1 [1002/4398] enabled sb7xx_51xx_enable() PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled sb7xx_51xx_enable() PCI: 00:14.0 [1002/4385] bus ops PCI: 00:14.0 [1002/4385] enabled sb7xx_51xx_enable() PCI: 00:14.1 [1002/439c] ops PCI: 00:14.1 [1002/439c] enabled sb7xx_51xx_enable() PCI: 00:14.2 [1002/4383] ops PCI: 00:14.2 [1002/4383] enabled sb7xx_51xx_enable() PCI: 00:14.3 [1002/439d] bus ops PCI: 00:14.3 [1002/439d] enabled sb7xx_51xx_enable() PCI: 00:14.4 [1002/4384] bus ops PCI: 00:14.4 [1002/4384] enabled sb7xx_51xx_enable() PCI: 00:14.5 [1002/4399] ops PCI: 00:14.5 [1002/4399] enabled PCI: 00:02.0 scanning... do_pci_scan_bridge for PCI: 00:02.0 PCI: pci_scan_bus for bus 01 scan_bus: scanning of bus PCI: 00:02.0 took 29 usecs PCI: 00:04.0 scanning... do_pci_scan_bridge for PCI: 00:04.0 PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [1000/0072] enabled Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x68 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled None scan_bus: scanning of bus PCI: 00:04.0 took 242 usecs PCI: 00:09.0 scanning... do_pci_scan_bridge for PCI: 00:09.0 PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [8086/10d3] enabled Capability: type 0x01 @ 0xc8 Capability: type 0x05 @ 0xd0 Capability: type 0x10 @ 0xe0 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled None scan_bus: scanning of bus PCI: 00:09.0 took 196 usecs PCI: 00:0a.0 scanning... do_pci_scan_bridge for PCI: 00:0a.0 PCI: pci_scan_bus for bus 04 PCI: 04:00.0 [8086/10d3] enabled Capability: type 0x01 @ 0xc8 Capability: type 0x05 @ 0xd0 Capability: type 0x10 @ 0xe0 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled None scan_bus: scanning of bus PCI: 00:0a.0 took 140 usecs PCI: 00:0b.0 scanning... do_pci_scan_bridge for PCI: 00:0b.0 PCI: pci_scan_bus for bus 05 scan_bus: scanning of bus PCI: 00:0b.0 took 29 usecs PCI: 00:0c.0 scanning... do_pci_scan_bridge for PCI: 00:0c.0 PCI: pci_scan_bus for bus 06 scan_bus: scanning of bus PCI: 00:0c.0 took 29 usecs PCI: 00:0d.0 scanning... do_pci_scan_bridge for PCI: 00:0d.0 PCI: pci_scan_bus for bus 07 scan_bus: scanning of bus PCI: 00:0d.0 took 29 usecs PCI: 00:14.0 scanning... scan_generic_bus for PCI: 00:14.0 bus: PCI: 00:14.0[0]->I2C: 01:50 enabled bus: PCI: 00:14.0[0]->I2C: 01:51 enabled bus: PCI: 00:14.0[0]->I2C: 01:52 enabled bus: PCI: 00:14.0[0]->I2C: 01:53 enabled bus: PCI: 00:14.0[0]->I2C: 01:54 enabled bus: PCI: 00:14.0[0]->I2C: 01:55 enabled bus: PCI: 00:14.0[0]->I2C: 01:56 enabled bus: PCI: 00:14.0[0]->I2C: 01:57 enabled bus: PCI: 00:14.0[0]->I2C: 01:2f enabled scan_generic_bus for PCI: 00:14.0 done scan_bus: scanning of bus PCI: 00:14.0 took 12 usecs PCI: 00:14.3 scanning... scan_lpc_bus for PCI: 00:14.3 PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.5 enabled PNP: 002e.106 disabled PNP: 002e.107 disabled PNP: 002e.207 disabled PNP: 002e.307 disabled PNP: 002e.407 disabled PNP: 002e.8 disabled PNP: 002e.108 disabled PNP: 002e.9 disabled PNP: 002e.109 disabled PNP: 002e.209 disabled PNP: 002e.309 disabled PNP: 002e.a enabled PNP: 002e.b enabled PNP: 002e.c disabled PNP: 002e.d disabled PNP: 002e.f disabled PNP: 004e.0 enabled scan_lpc_bus for PCI: 00:14.3 done scan_bus: scanning of bus PCI: 00:14.3 took 464 usecs PCI: 00:14.4 scanning... do_pci_scan_bridge for PCI: 00:14.4 PCI: pci_scan_bus for bus 08 sb7xx_51xx_enable() PCI: 08:01.0 [1a03/2000] ops PCI: 08:01.0 [1a03/2000] enabled sb7xx_51xx_enable() PCI: 08:02.0 [11c1/5811] enabled sb7xx_51xx_enable() PCI: Static device PCI: 08:03.0 not found, disabling it. scan_bus: scanning of bus PCI: 00:14.4 took 90 usecs scan_bus: scanning of bus PCI: 00:18.0 took 21809073 usecs PCI: 00:19.0 scanning... scan_bus: scanning of bus PCI: 00:19.0 took 1 usecs PCI: 00:1a.0 scanning... scan_bus: scanning of bus PCI: 00:1a.0 took 1 usecs PCI: 00:1b.0 scanning... scan_bus: scanning of bus PCI: 00:1b.0 took 1 usecs DOMAIN: 0000 passpw: enabled DOMAIN: 0000 passpw: enabled DOMAIN: 0000 passpw: enabled DOMAIN: 0000 passpw: enabled scan_bus: scanning of bus DOMAIN: 0000 took 21809182 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 21810373 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 21810842 exit 0 found VGA at PCI: 08:01.0 Setting up VGA for PCI: 08:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:14.4 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done Adding PCIe enhanced config space BAR 0xc0000000-0xd0000000. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 Reserving CC6 save segment base: 838000000 size: 08000000 DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:18.0 read_resources bus 0 link: 2 done PCI: 00:18.0 read_resources bus 0 link: 3 PCI: 00:18.0 read_resources bus 0 link: 3 done PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 sr5690_read_resource: PCI: 00:00.0 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 PCI: 00:02.0 read_resources bus 1 link: 0 PCI: 00:02.0 read_resources bus 1 link: 0 done PCI: 00:04.0 read_resources bus 2 link: 0 PCI: 00:04.0 read_resources bus 2 link: 0 done PCI: 00:09.0 read_resources bus 3 link: 0 PCI: 00:09.0 read_resources bus 3 link: 0 done PCI: 00:0a.0 read_resources bus 4 link: 0 PCI: 00:0a.0 read_resources bus 4 link: 0 done PCI: 00:0b.0 read_resources bus 5 link: 0 PCI: 00:0b.0 read_resources bus 5 link: 0 done PCI: 00:0c.0 read_resources bus 6 link: 0 PCI: 00:0c.0 read_resources bus 6 link: 0 done PCI: 00:0d.0 read_resources bus 7 link: 0 PCI: 00:0d.0 read_resources bus 7 link: 0 done PCI: 00:14.0 read_resources bus 1 link: 0 I2C: 01:50 missing read_resources I2C: 01:51 missing read_resources I2C: 01:52 missing read_resources I2C: 01:53 missing read_resources I2C: 01:54 missing read_resources I2C: 01:55 missing read_resources I2C: 01:56 missing read_resources I2C: 01:57 missing read_resources PCI: 00:14.0 read_resources bus 1 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PNP: 004e.0 missing read_resources PCI: 00:14.3 read_resources bus 0 link: 0 done PCI: 00:14.4 read_resources bus 8 link: 0 PCI: 00:14.4 read_resources bus 8 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 done CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 PCI: 00:18.4 read_resources bus 0 link: 0 PCI: 00:18.4 read_resources bus 0 link: 0 done PCI: 00:18.4 read_resources bus 0 link: 1 PCI: 00:18.4 read_resources bus 0 link: 1 done PCI: 00:18.4 read_resources bus 0 link: 2 PCI: 00:18.4 read_resources bus 0 link: 2 done PCI: 00:18.4 read_resources bus 0 link: 3 PCI: 00:18.4 read_resources bus 0 link: 3 done PCI: 00:19.0 read_resources bus 0 link: 3 PCI: 00:19.0 read_resources bus 0 link: 3 done PCI: 00:19.0 read_resources bus 0 link: 2 PCI: 00:19.0 read_resources bus 0 link: 2 done PCI: 00:19.0 read_resources bus 0 link: 0 PCI: 00:19.0 read_resources bus 0 link: 0 done PCI: 00:19.0 read_resources bus 0 link: 1 PCI: 00:19.0 read_resources bus 0 link: 1 done PCI: 00:19.4 read_resources bus 0 link: 0 PCI: 00:19.4 read_resources bus 0 link: 0 done PCI: 00:19.4 read_resources bus 0 link: 1 PCI: 00:19.4 read_resources bus 0 link: 1 done PCI: 00:19.4 read_resources bus 0 link: 2 PCI: 00:19.4 read_resources bus 0 link: 2 done PCI: 00:19.4 read_resources bus 0 link: 3 PCI: 00:19.4 read_resources bus 0 link: 3 done PCI: 00:1a.0 read_resources bus 0 link: 3 PCI: 00:1a.0 read_resources bus 0 link: 3 done PCI: 00:1a.0 read_resources bus 0 link: 2 PCI: 00:1a.0 read_resources bus 0 link: 2 done PCI: 00:1a.0 read_resources bus 0 link: 0 PCI: 00:1a.0 read_resources bus 0 link: 0 done PCI: 00:1a.0 read_resources bus 0 link: 1 PCI: 00:1a.0 read_resources bus 0 link: 1 done PCI: 00:1a.4 read_resources bus 0 link: 0 PCI: 00:1a.4 read_resources bus 0 link: 0 done PCI: 00:1a.4 read_resources bus 0 link: 1 PCI: 00:1a.4 read_resources bus 0 link: 1 done PCI: 00:1a.4 read_resources bus 0 link: 2 PCI: 00:1a.4 read_resources bus 0 link: 2 done PCI: 00:1a.4 read_resources bus 0 link: 3 PCI: 00:1a.4 read_resources bus 0 link: 3 done PCI: 00:1b.0 read_resources bus 0 link: 3 PCI: 00:1b.0 read_resources bus 0 link: 3 done PCI: 00:1b.0 read_resources bus 0 link: 2 PCI: 00:1b.0 read_resources bus 0 link: 2 done PCI: 00:1b.0 read_resources bus 0 link: 0 PCI: 00:1b.0 read_resources bus 0 link: 0 done PCI: 00:1b.0 read_resources bus 0 link: 1 PCI: 00:1b.0 read_resources bus 0 link: 1 done PCI: 00:1b.4 read_resources bus 0 link: 0 PCI: 00:1b.4 read_resources bus 0 link: 0 done PCI: 00:1b.4 read_resources bus 0 link: 1 PCI: 00:1b.4 read_resources bus 0 link: 1 done PCI: 00:1b.4 read_resources bus 0 link: 2 PCI: 00:1b.4 read_resources bus 0 link: 2 done PCI: 00:1b.4 read_resources bus 0 link: 3 PCI: 00:1b.4 read_resources bus 0 link: 3 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 APIC: 06 APIC: 07 APIC: 08 APIC: 09 APIC: 0a APIC: 0b APIC: 20 APIC: 21 APIC: 22 APIC: 23 APIC: 24 APIC: 25 APIC: 26 APIC: 27 APIC: 28 APIC: 29 APIC: 2a APIC: 2b DOMAIN: 0000 child on link 0 PCI: 00:18.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7 DOMAIN: 0000 resource base 838000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 8 PCI: 00:18.0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110b0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110b8 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d8 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 1200 index fc PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 10000200 index 44 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:03.0 PCI: 00:04.0 child on link 0 PCI: 02:00.0 PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 02:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 14 PCI: 02:00.0 resource base 0 size 40000 align 18 gran 18 limit ffffffffffffffff flags 201 index 1c PCI: 02:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 child on link 0 PCI: 03:00.0 PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 03:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c PCI: 00:0a.0 child on link 0 PCI: 04:00.0 PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 04:00.0 PCI: 04:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 04:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 PCI: 04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c PCI: 00:0b.0 PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0c.0 PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0d.0 PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:11.0 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:11.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.1 PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 PCI: 00:14.0 child on link 0 I2C: 01:50 PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74 PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4 PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90 PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 I2C: 01:54 I2C: 01:55 I2C: 01:56 I2C: 01:57 I2C: 01:2f PCI: 00:14.1 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.3 child on link 0 PNP: 002e.0 PCI: 00:14.3 resource base 0 size 1 align 12 gran 0 limit ffffffff flags 200 index a0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.106 PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62 PNP: 002e.107 PNP: 002e.207 PNP: 002e.307 PNP: 002e.407 PNP: 002e.8 PNP: 002e.108 PNP: 002e.9 PNP: 002e.109 PNP: 002e.209 PNP: 002e.309 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags c0000100 index 60 PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.c PNP: 002e.d PNP: 002e.f PNP: 004e.0 PCI: 00:14.4 child on link 0 PCI: 08:01.0 PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 08:01.0 PCI: 08:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffff flags 200 index 10 PCI: 08:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 14 PCI: 08:01.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 18 PCI: 08:02.0 PCI: 08:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 08:03.0 PCI: 00:14.5 PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 PCI: 00:18.5 PCI: 00:19.0 PCI: 00:19.1 PCI: 00:19.2 PCI: 00:19.3 PCI: 00:19.4 PCI: 00:19.5 PCI: 00:1a.0 PCI: 00:1a.1 PCI: 00:1a.2 PCI: 00:1a.3 PCI: 00:1a.4 PCI: 00:1a.5 PCI: 00:1b.0 PCI: 00:1b.1 PCI: 00:1b.2 PCI: 00:1b.3 PCI: 00:1b.4 PCI: 00:1b.5 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0xff] io PCI: 00:04.0 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:09.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 03:00.0 18 * [0x0 - 0x1f] io PCI: 00:09.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 04:00.0 18 * [0x0 - 0x1f] io PCI: 00:0a.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 08:01.0 18 * [0x0 - 0x7f] io PCI: 00:14.4 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:04.0 1c * [0x0 - 0xfff] io PCI: 00:09.0 1c * [0x1000 - 0x1fff] io PCI: 00:0a.0 1c * [0x2000 - 0x2fff] io PCI: 00:14.4 1c * [0x3000 - 0x3fff] io PCI: 00:11.0 20 * [0x4000 - 0x400f] io PCI: 00:14.1 20 * [0x4010 - 0x401f] io PCI: 00:11.0 10 * [0x4020 - 0x4027] io PCI: 00:11.0 18 * [0x4028 - 0x402f] io PCI: 00:14.1 10 * [0x4030 - 0x4037] io PCI: 00:14.1 18 * [0x4038 - 0x403f] io PCI: 00:11.0 14 * [0x4040 - 0x4043] io PCI: 00:11.0 1c * [0x4044 - 0x4047] io PCI: 00:14.1 14 * [0x4048 - 0x404b] io PCI: 00:14.1 1c * [0x404c - 0x404f] io PCI: 00:18.0 io: base: 4050 size: 5000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 110d8 * [0x0 - 0x4fff] io DOMAIN: 0000 io: base: 5000 size: 5000 align: 12 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.0 fc * [0x0 - 0xff] prefmem PCI: 00:18.0 prefmem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 30 * [0x0 - 0x7ffff] mem PCI: 02:00.0 1c * [0x80000 - 0xbffff] mem PCI: 02:00.0 14 * [0xc0000 - 0xc3fff] mem PCI: 00:04.0 mem: base: c4000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:00.0 10 * [0x0 - 0x1ffff] mem PCI: 03:00.0 1c * [0x20000 - 0x23fff] mem PCI: 00:09.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 04:00.0 10 * [0x0 - 0x1ffff] mem PCI: 04:00.0 1c * [0x20000 - 0x23fff] mem PCI: 00:0a.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 08:01.0 10 * [0x0 - 0x7fffff] mem PCI: 08:01.0 14 * [0x800000 - 0x81ffff] mem PCI: 08:02.0 10 * [0x820000 - 0x820fff] mem PCI: 00:14.4 mem: base: 821000 size: 900000 align: 23 gran: 20 limit: ffffffff done PCI: 00:14.4 20 * [0x0 - 0x8fffff] mem PCI: 00:04.0 20 * [0x900000 - 0x9fffff] mem PCI: 00:09.0 20 * [0xa00000 - 0xafffff] mem PCI: 00:0a.0 20 * [0xb00000 - 0xbfffff] mem PCI: 00:00.2 44 * [0xc00000 - 0xc03fff] mem PCI: 00:14.2 10 * [0xc04000 - 0xc07fff] mem PCI: 00:12.0 10 * [0xc08000 - 0xc08fff] mem PCI: 00:12.1 10 * [0xc09000 - 0xc09fff] mem PCI: 00:13.0 10 * [0xc0a000 - 0xc0afff] mem PCI: 00:13.1 10 * [0xc0b000 - 0xc0bfff] mem PCI: 00:14.5 10 * [0xc0c000 - 0xc0cfff] mem PCI: 00:11.0 24 * [0xc0d000 - 0xc0d3ff] mem PCI: 00:12.2 10 * [0xc0e000 - 0xc0e0ff] mem PCI: 00:13.2 10 * [0xc0f000 - 0xc0f0ff] mem PCI: 00:14.3 a0 * [0xc10000 - 0xc10000] mem PCI: 00:18.0 mem: base: c10001 size: d00000 align: 23 gran: 20 limit: ffffffff done PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem PCI: 00:18.0 110b8 * [0x4000000 - 0x4cfffff] mem PCI: 00:18.0 110b0 * [0x4d00000 - 0x4dfffff] prefmem DOMAIN: 0000 mem: base: 4e00000 size: 4e00000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed) constrain_resources: DOMAIN: 0000 07 base 00000000 limit bfffffff mem (fixed) constrain_resources: DOMAIN: 0000 08 base 838000000 limit 83fffffff mem (fixed) constrain_resources: PCI: 00:14.0 74 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:14.0 b4 base fed00000 limit fed003ff mem (fixed) constrain_resources: PCI: 00:14.0 90 base 00000b00 limit 00000b0f io (fixed) constrain_resources: PCI: 00:14.0 58 base 00000b20 limit 00000b2f io (fixed) constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:14.3 10000100 base ff800000 limit ffffffff mem (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base f8000000 limit ffffffff Setting resources... DOMAIN: 0000 io: base:1000 size:5000 align:12 gran:0 limit:ffff PCI: 00:18.0 110d8 * [0x1000 - 0x5fff] io DOMAIN: 0000 io: next_base: 6000 size: 5000 align: 12 gran: 0 done PCI: 00:18.0 io: base:1000 size:5000 align:12 gran:12 limit:5fff PCI: 00:04.0 1c * [0x1000 - 0x1fff] io PCI: 00:09.0 1c * [0x2000 - 0x2fff] io PCI: 00:0a.0 1c * [0x3000 - 0x3fff] io PCI: 00:14.4 1c * [0x4000 - 0x4fff] io PCI: 00:11.0 20 * [0x5000 - 0x500f] io PCI: 00:14.1 20 * [0x5010 - 0x501f] io PCI: 00:11.0 10 * [0x5020 - 0x5027] io PCI: 00:11.0 18 * [0x5028 - 0x502f] io PCI: 00:14.1 10 * [0x5030 - 0x5037] io PCI: 00:14.1 18 * [0x5038 - 0x503f] io PCI: 00:11.0 14 * [0x5040 - 0x5043] io PCI: 00:11.0 1c * [0x5044 - 0x5047] io PCI: 00:14.1 14 * [0x5048 - 0x504b] io PCI: 00:14.1 1c * [0x504c - 0x504f] io PCI: 00:18.0 io: next_base: 5050 size: 5000 align: 12 gran: 12 done PCI: 00:02.0 io: base:5fff size:0 align:12 gran:12 limit:5fff PCI: 00:02.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done PCI: 00:04.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff PCI: 02:00.0 10 * [0x1000 - 0x10ff] io PCI: 00:04.0 io: next_base: 1100 size: 1000 align: 12 gran: 12 done PCI: 00:09.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff PCI: 03:00.0 18 * [0x2000 - 0x201f] io PCI: 00:09.0 io: next_base: 2020 size: 1000 align: 12 gran: 12 done PCI: 00:0a.0 io: base:3000 size:1000 align:12 gran:12 limit:3fff PCI: 04:00.0 18 * [0x3000 - 0x301f] io PCI: 00:0a.0 io: next_base: 3020 size: 1000 align: 12 gran: 12 done PCI: 00:0b.0 io: base:5fff size:0 align:12 gran:12 limit:5fff PCI: 00:0b.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done PCI: 00:0c.0 io: base:5fff size:0 align:12 gran:12 limit:5fff PCI: 00:0c.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done PCI: 00:0d.0 io: base:5fff size:0 align:12 gran:12 limit:5fff PCI: 00:0d.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done PCI: 00:14.4 io: base:4000 size:1000 align:12 gran:12 limit:4fff PCI: 08:01.0 18 * [0x4000 - 0x407f] io PCI: 00:14.4 io: next_base: 4080 size: 1000 align: 12 gran: 12 done DOMAIN: 0000 mem: base:f8000000 size:4e00000 align:26 gran:0 limit:ffffffff PCI: 00:18.3 94 * [0xf8000000 - 0xfbffffff] mem PCI: 00:18.0 110b8 * [0xfc000000 - 0xfccfffff] mem PCI: 00:18.0 110b0 * [0xfcd00000 - 0xfcdfffff] prefmem DOMAIN: 0000 mem: next_base: fce00000 size: 4e00000 align: 26 gran: 0 done PCI: 00:18.0 prefmem: base:fcd00000 size:100000 align:20 gran:20 limit:fcdfffff PCI: 00:00.0 fc * [0xfcd00000 - 0xfcd000ff] prefmem PCI: 00:18.0 prefmem: next_base: fcd00100 size: 100000 align: 20 gran: 20 done PCI: 00:02.0 prefmem: base:fcdfffff size:0 align:20 gran:20 limit:fcdfffff PCI: 00:02.0 prefmem: next_base: fcdfffff size: 0 align: 20 gran: 20 done PCI: 00:04.0 prefmem: base:fcdfffff size:0 align:20 gran:20 limit:fcdfffff PCI: 00:04.0 prefmem: next_base: fcdfffff size: 0 align: 20 gran: 20 done PCI: 00:09.0 prefmem: base:fcdfffff size:0 align:20 gran:20 limit:fcdfffff PCI: 00:09.0 prefmem: next_base: fcdfffff size: 0 align: 20 gran: 20 done PCI: 00:0a.0 prefmem: base:fcdfffff size:0 align:20 gran:20 limit:fcdfffff PCI: 00:0a.0 prefmem: next_base: fcdfffff size: 0 align: 20 gran: 20 done PCI: 00:0b.0 prefmem: base:fcdfffff size:0 align:20 gran:20 limit:fcdfffff PCI: 00:0b.0 prefmem: next_base: fcdfffff size: 0 align: 20 gran: 20 done PCI: 00:0c.0 prefmem: base:fcdfffff size:0 align:20 gran:20 limit:fcdfffff PCI: 00:0c.0 prefmem: next_base: fcdfffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 prefmem: base:fcdfffff size:0 align:20 gran:20 limit:fcdfffff PCI: 00:0d.0 prefmem: next_base: fcdfffff size: 0 align: 20 gran: 20 done PCI: 00:14.4 prefmem: base:fcdfffff size:0 align:20 gran:20 limit:fcdfffff PCI: 00:14.4 prefmem: next_base: fcdfffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 mem: base:fc000000 size:d00000 align:23 gran:20 limit:fccfffff PCI: 00:14.4 20 * [0xfc000000 - 0xfc8fffff] mem PCI: 00:04.0 20 * [0xfc900000 - 0xfc9fffff] mem PCI: 00:09.0 20 * [0xfca00000 - 0xfcafffff] mem PCI: 00:0a.0 20 * [0xfcb00000 - 0xfcbfffff] mem PCI: 00:00.2 44 * [0xfcc00000 - 0xfcc03fff] mem PCI: 00:14.2 10 * [0xfcc04000 - 0xfcc07fff] mem PCI: 00:12.0 10 * [0xfcc08000 - 0xfcc08fff] mem PCI: 00:12.1 10 * [0xfcc09000 - 0xfcc09fff] mem PCI: 00:13.0 10 * [0xfcc0a000 - 0xfcc0afff] mem PCI: 00:13.1 10 * [0xfcc0b000 - 0xfcc0bfff] mem PCI: 00:14.5 10 * [0xfcc0c000 - 0xfcc0cfff] mem PCI: 00:11.0 24 * [0xfcc0d000 - 0xfcc0d3ff] mem PCI: 00:12.2 10 * [0xfcc0e000 - 0xfcc0e0ff] mem PCI: 00:13.2 10 * [0xfcc0f000 - 0xfcc0f0ff] mem PCI: 00:14.3 a0 * [0xfcc10000 - 0xfcc10000] mem PCI: 00:18.0 mem: next_base: fcc10001 size: d00000 align: 23 gran: 20 done PCI: 00:02.0 mem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff PCI: 00:02.0 mem: next_base: fccfffff size: 0 align: 20 gran: 20 done PCI: 00:04.0 mem: base:fc900000 size:100000 align:20 gran:20 limit:fc9fffff PCI: 02:00.0 30 * [0xfc900000 - 0xfc97ffff] mem PCI: 02:00.0 1c * [0xfc980000 - 0xfc9bffff] mem PCI: 02:00.0 14 * [0xfc9c0000 - 0xfc9c3fff] mem PCI: 00:04.0 mem: next_base: fc9c4000 size: 100000 align: 20 gran: 20 done PCI: 00:09.0 mem: base:fca00000 size:100000 align:20 gran:20 limit:fcafffff PCI: 03:00.0 10 * [0xfca00000 - 0xfca1ffff] mem PCI: 03:00.0 1c * [0xfca20000 - 0xfca23fff] mem PCI: 00:09.0 mem: next_base: fca24000 size: 100000 align: 20 gran: 20 done PCI: 00:0a.0 mem: base:fcb00000 size:100000 align:20 gran:20 limit:fcbfffff PCI: 04:00.0 10 * [0xfcb00000 - 0xfcb1ffff] mem PCI: 04:00.0 1c * [0xfcb20000 - 0xfcb23fff] mem PCI: 00:0a.0 mem: next_base: fcb24000 size: 100000 align: 20 gran: 20 done PCI: 00:0b.0 mem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff PCI: 00:0b.0 mem: next_base: fccfffff size: 0 align: 20 gran: 20 done PCI: 00:0c.0 mem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff PCI: 00:0c.0 mem: next_base: fccfffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 mem: base:fccfffff size:0 align:20 gran:20 limit:fccfffff PCI: 00:0d.0 mem: next_base: fccfffff size: 0 align: 20 gran: 20 done PCI: 00:14.4 mem: base:fc000000 size:900000 align:23 gran:20 limit:fc8fffff PCI: 08:01.0 10 * [0xfc000000 - 0xfc7fffff] mem PCI: 08:01.0 14 * [0xfc800000 - 0xfc81ffff] mem PCI: 08:02.0 10 * [0xfc820000 - 0xfc820fff] mem PCI: 00:14.4 mem: next_base: fc821000 size: 900000 align: 23 gran: 20 done Root Device assign_resources, bus 0 link: 0 0: mmio_basek=00300000, basek=00400000, limitk=00900000 1: mmio_basek=00300000, basek=00900000, limitk=01100000 2: mmio_basek=00300000, basek=01100000, limitk=01900000 3: mmio_basek=00300000, basek=01900000, limitk=02100000 DOMAIN: 0000 assign_resources, bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device PCI: 00:18.0 111b8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 1> PCI: 00:18.0 110b0 <- [0x00fcd00000 - 0x00fcdfffff] size 0x00100000 gran 0x14 prefmem <node 0 link 1> PCI: 00:18.0 110b8 <- [0x00fc000000 - 0x00fccfffff] size 0x00d00000 gran 0x14 mem <node 0 link 1> PCI: 00:18.0 110d8 <- [0x0000001000 - 0x0000005fff] size 0x00005000 gran 0x0c io <node 0 link 1> PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:00.0 sr5690_set_resources sr5690_set_resources: PCI: 00:00.0[0x1c] base = c0000000 limit = cfffffff PCI: 00:00.0 c0010058 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x00 mem <mmconfig> sr5690_set_resources: PCI: 00:18.1 <- index a8 base c00003 limit cfff90 PCI: 00:00.0 fc <- [0x00fcd00000 - 0x00fcd000ff] size 0x00000100 gran 0x08 prefmem CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 PCI: 00:00.2 44 <- [0x00fcc00000 - 0x00fcc03fff] size 0x00004000 gran 0x0e mem PCI: 00:02.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:02.0 24 <- [0x00fcdfffff - 0x00fcdffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:02.0 20 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:04.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 02 io PCI: 00:04.0 24 <- [0x00fcdfffff - 0x00fcdffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:04.0 20 <- [0x00fc900000 - 0x00fc9fffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:04.0 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 02:00.0 14 <- [0x00fc9c0000 - 0x00fc9c3fff] size 0x00004000 gran 0x0e mem64 PCI: 02:00.0 1c <- [0x00fc980000 - 0x00fc9bffff] size 0x00040000 gran 0x12 mem64 PCI: 02:00.0 30 <- [0x00fc900000 - 0x00fc97ffff] size 0x00080000 gran 0x13 romem PCI: 00:04.0 assign_resources, bus 2 link: 0 PCI: 00:09.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io PCI: 00:09.0 24 <- [0x00fcdfffff - 0x00fcdffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:09.0 20 <- [0x00fca00000 - 0x00fcafffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 00:09.0 assign_resources, bus 3 link: 0 PCI: 03:00.0 10 <- [0x00fca00000 - 0x00fca1ffff] size 0x00020000 gran 0x11 mem PCI: 03:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io PCI: 03:00.0 1c <- [0x00fca20000 - 0x00fca23fff] size 0x00004000 gran 0x0e mem PCI: 00:09.0 assign_resources, bus 3 link: 0 PCI: 00:0a.0 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 04 io PCI: 00:0a.0 24 <- [0x00fcdfffff - 0x00fcdffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:0a.0 20 <- [0x00fcb00000 - 0x00fcbfffff] size 0x00100000 gran 0x14 bus 04 mem PCI: 00:0a.0 assign_resources, bus 4 link: 0 PCI: 04:00.0 10 <- [0x00fcb00000 - 0x00fcb1ffff] size 0x00020000 gran 0x11 mem PCI: 04:00.0 18 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io PCI: 04:00.0 1c <- [0x00fcb20000 - 0x00fcb23fff] size 0x00004000 gran 0x0e mem PCI: 00:0a.0 assign_resources, bus 4 link: 0 PCI: 00:0b.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 05 io PCI: 00:0b.0 24 <- [0x00fcdfffff - 0x00fcdffffe] size 0x00000000 gran 0x14 bus 05 prefmem PCI: 00:0b.0 20 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 05 mem PCI: 00:0c.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 06 io PCI: 00:0c.0 24 <- [0x00fcdfffff - 0x00fcdffffe] size 0x00000000 gran 0x14 bus 06 prefmem PCI: 00:0c.0 20 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 06 mem PCI: 00:0d.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 07 io PCI: 00:0d.0 24 <- [0x00fcdfffff - 0x00fcdffffe] size 0x00000000 gran 0x14 bus 07 prefmem PCI: 00:0d.0 20 <- [0x00fccfffff - 0x00fccffffe] size 0x00000000 gran 0x14 bus 07 mem PCI: 00:11.0 10 <- [0x0000005020 - 0x0000005027] size 0x00000008 gran 0x03 io PCI: 00:11.0 14 <- [0x0000005040 - 0x0000005043] size 0x00000004 gran 0x02 io PCI: 00:11.0 18 <- [0x0000005028 - 0x000000502f] size 0x00000008 gran 0x03 io PCI: 00:11.0 1c <- [0x0000005044 - 0x0000005047] size 0x00000004 gran 0x02 io PCI: 00:11.0 20 <- [0x0000005000 - 0x000000500f] size 0x00000010 gran 0x04 io PCI: 00:11.0 24 <- [0x00fcc0d000 - 0x00fcc0d3ff] size 0x00000400 gran 0x0a mem PCI: 00:12.0 10 <- [0x00fcc08000 - 0x00fcc08fff] size 0x00001000 gran 0x0c mem PCI: 00:12.1 10 <- [0x00fcc09000 - 0x00fcc09fff] size 0x00001000 gran 0x0c mem PCI: 00:12.2 10 <- [0x00fcc0e000 - 0x00fcc0e0ff] size 0x00000100 gran 0x08 mem PCI: 00:13.0 10 <- [0x00fcc0a000 - 0x00fcc0afff] size 0x00001000 gran 0x0c mem PCI: 00:13.1 10 <- [0x00fcc0b000 - 0x00fcc0bfff] size 0x00001000 gran 0x0c mem PCI: 00:13.2 10 <- [0x00fcc0f000 - 0x00fcc0f0ff] size 0x00000100 gran 0x08 mem PCI: 00:14.0 assign_resources, bus 1 link: 0 PCI: 00:14.0 assign_resources, bus 1 link: 0 PCI: 00:14.1 10 <- [0x0000005030 - 0x0000005037] size 0x00000008 gran 0x03 io PCI: 00:14.1 14 <- [0x0000005048 - 0x000000504b] size 0x00000004 gran 0x02 io PCI: 00:14.1 18 <- [0x0000005038 - 0x000000503f] size 0x00000008 gran 0x03 io PCI: 00:14.1 1c <- [0x000000504c - 0x000000504f] size 0x00000004 gran 0x02 io PCI: 00:14.1 20 <- [0x0000005010 - 0x000000501f] size 0x00000010 gran 0x04 io PCI: 00:14.2 10 <- [0x00fcc04000 - 0x00fcc07fff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.3 a0 <- [0x00fcc10000 - 0x00fcc10000] size 0x00000001 gran 0x00 mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.4 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 08 io PCI: 00:14.4 24 <- [0x00fcdfffff - 0x00fcdffffe] size 0x00000000 gran 0x14 bus 08 prefmem PCI: 00:14.4 20 <- [0x00fc000000 - 0x00fc8fffff] size 0x00900000 gran 0x14 bus 08 mem PCI: 00:14.4 assign_resources, bus 8 link: 0 PCI: 08:01.0 10 <- [0x00fc000000 - 0x00fc7fffff] size 0x00800000 gran 0x17 mem PCI: 08:01.0 14 <- [0x00fc800000 - 0x00fc81ffff] size 0x00020000 gran 0x11 mem PCI: 08:01.0 18 <- [0x0000004000 - 0x000000407f] size 0x00000080 gran 0x07 io PCI: 08:02.0 10 <- [0x00fc820000 - 0x00fc820fff] size 0x00001000 gran 0x0c mem PCI: 00:14.4 assign_resources, bus 8 link: 0 PCI: 00:14.5 10 <- [0x00fcc0c000 - 0x00fcc0cfff] size 0x00001000 gran 0x0c mem PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart> PCI: 00:19.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart> PCI: 00:1a.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart> PCI: 00:1b.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart> DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 APIC: 06 APIC: 07 APIC: 08 APIC: 09 APIC: 0a APIC: 0b APIC: 20 APIC: 21 APIC: 22 APIC: 23 APIC: 24 APIC: 25 APIC: 26 APIC: 27 APIC: 28 APIC: 29 APIC: 2a APIC: 2b DOMAIN: 0000 child on link 0 PCI: 00:18.0 DOMAIN: 0000 resource base 1000 size 5000 align 12 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f8000000 size 4e00000 align 26 gran 0 limit ffffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7 DOMAIN: 0000 resource base 838000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 8 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20 DOMAIN: 0000 resource base 100000000 size 140000000 align 0 gran 0 limit 0 flags e0004200 index 30 DOMAIN: 0000 resource base 240000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 41 DOMAIN: 0000 resource base 440000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 52 DOMAIN: 0000 resource base 640000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 63 PCI: 00:18.0 PCI: 00:18.0 resource base fcd00000 size 100000 align 20 gran 20 limit fcdfffff flags 60081200 index 110b0 PCI: 00:18.0 resource base fc000000 size d00000 align 23 gran 20 limit fccfffff flags 60080200 index 110b8 PCI: 00:18.0 resource base 1000 size 5000 align 12 gran 12 limit 5fff flags 60080100 index 110d8 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags e0000200 index 111b8 PCI: 00:00.0 PCI: 00:00.0 resource base fcd00000 size 100 align 12 gran 8 limit fcd000ff flags 60001200 index fc PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.2 resource base fcc00000 size 4000 align 14 gran 14 limit fcc03fff flags 70000200 index 44 PCI: 00:02.0 PCI: 00:02.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c PCI: 00:02.0 resource base fcdfffff size 0 align 20 gran 20 limit fcdfffff flags 60081202 index 24 PCI: 00:02.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60080202 index 20 PCI: 00:03.0 PCI: 00:04.0 child on link 0 PCI: 02:00.0 PCI: 00:04.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c PCI: 00:04.0 resource base fcdfffff size 0 align 20 gran 20 limit fcdfffff flags 60081202 index 24 PCI: 00:04.0 resource base fc900000 size 100000 align 20 gran 20 limit fc9fffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 10 PCI: 02:00.0 resource base fc9c0000 size 4000 align 14 gran 14 limit fc9c3fff flags 60000201 index 14 PCI: 02:00.0 resource base fc980000 size 40000 align 18 gran 18 limit fc9bffff flags 60000201 index 1c PCI: 02:00.0 resource base fc900000 size 80000 align 19 gran 19 limit fc97ffff flags 60002200 index 30 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 child on link 0 PCI: 03:00.0 PCI: 00:09.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c PCI: 00:09.0 resource base fcdfffff size 0 align 20 gran 20 limit fcdfffff flags 60081202 index 24 PCI: 00:09.0 resource base fca00000 size 100000 align 20 gran 20 limit fcafffff flags 60080202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base fca00000 size 20000 align 17 gran 17 limit fca1ffff flags 60000200 index 10 PCI: 03:00.0 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 18 PCI: 03:00.0 resource base fca20000 size 4000 align 14 gran 14 limit fca23fff flags 60000200 index 1c PCI: 00:0a.0 child on link 0 PCI: 04:00.0 PCI: 00:0a.0 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c PCI: 00:0a.0 resource base fcdfffff size 0 align 20 gran 20 limit fcdfffff flags 60081202 index 24 PCI: 00:0a.0 resource base fcb00000 size 100000 align 20 gran 20 limit fcbfffff flags 60080202 index 20 PCI: 04:00.0 PCI: 04:00.0 resource base fcb00000 size 20000 align 17 gran 17 limit fcb1ffff flags 60000200 index 10 PCI: 04:00.0 resource base 3000 size 20 align 5 gran 5 limit 301f flags 60000100 index 18 PCI: 04:00.0 resource base fcb20000 size 4000 align 14 gran 14 limit fcb23fff flags 60000200 index 1c PCI: 00:0b.0 PCI: 00:0b.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c PCI: 00:0b.0 resource base fcdfffff size 0 align 20 gran 20 limit fcdfffff flags 60081202 index 24 PCI: 00:0b.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60080202 index 20 PCI: 00:0c.0 PCI: 00:0c.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c PCI: 00:0c.0 resource base fcdfffff size 0 align 20 gran 20 limit fcdfffff flags 60081202 index 24 PCI: 00:0c.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60080202 index 20 PCI: 00:0d.0 PCI: 00:0d.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c PCI: 00:0d.0 resource base fcdfffff size 0 align 20 gran 20 limit fcdfffff flags 60081202 index 24 PCI: 00:0d.0 resource base fccfffff size 0 align 20 gran 20 limit fccfffff flags 60080202 index 20 PCI: 00:11.0 PCI: 00:11.0 resource base 5020 size 8 align 3 gran 3 limit 5027 flags 60000100 index 10 PCI: 00:11.0 resource base 5040 size 4 align 2 gran 2 limit 5043 flags 60000100 index 14 PCI: 00:11.0 resource base 5028 size 8 align 3 gran 3 limit 502f flags 60000100 index 18 PCI: 00:11.0 resource base 5044 size 4 align 2 gran 2 limit 5047 flags 60000100 index 1c PCI: 00:11.0 resource base 5000 size 10 align 4 gran 4 limit 500f flags 60000100 index 20 PCI: 00:11.0 resource base fcc0d000 size 400 align 12 gran 10 limit fcc0d3ff flags 60000200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base fcc08000 size 1000 align 12 gran 12 limit fcc08fff flags 60000200 index 10 PCI: 00:12.1 PCI: 00:12.1 resource base fcc09000 size 1000 align 12 gran 12 limit fcc09fff flags 60000200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base fcc0e000 size 100 align 12 gran 8 limit fcc0e0ff flags 60000200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base fcc0a000 size 1000 align 12 gran 12 limit fcc0afff flags 60000200 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base fcc0b000 size 1000 align 12 gran 12 limit fcc0bfff flags 60000200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base fcc0f000 size 100 align 12 gran 8 limit fcc0f0ff flags 60000200 index 10 PCI: 00:14.0 child on link 0 I2C: 01:50 PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74 PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4 PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90 PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 I2C: 01:54 I2C: 01:55 I2C: 01:56 I2C: 01:57 I2C: 01:2f PCI: 00:14.1 PCI: 00:14.1 resource base 5030 size 8 align 3 gran 3 limit 5037 flags 60000100 index 10 PCI: 00:14.1 resource base 5048 size 4 align 2 gran 2 limit 504b flags 60000100 index 14 PCI: 00:14.1 resource base 5038 size 8 align 3 gran 3 limit 503f flags 60000100 index 18 PCI: 00:14.1 resource base 504c size 4 align 2 gran 2 limit 504f flags 60000100 index 1c PCI: 00:14.1 resource base 5010 size 10 align 4 gran 4 limit 501f flags 60000100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base fcc04000 size 4000 align 14 gran 14 limit fcc07fff flags 60000201 index 10 PCI: 00:14.3 child on link 0 PNP: 002e.0 PCI: 00:14.3 resource base fcc10000 size 1 align 12 gran 0 limit fcc10000 flags 60000200 index a0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 PNP: 002e.106 PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62 PNP: 002e.107 PNP: 002e.207 PNP: 002e.307 PNP: 002e.407 PNP: 002e.8 PNP: 002e.108 PNP: 002e.9 PNP: 002e.109 PNP: 002e.209 PNP: 002e.309 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags e0000100 index 60 PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.c PNP: 002e.d PNP: 002e.f PNP: 004e.0 PCI: 00:14.4 child on link 0 PCI: 08:01.0 PCI: 00:14.4 resource base 4000 size 1000 align 12 gran 12 limit 4fff flags 60080102 index 1c PCI: 00:14.4 resource base fcdfffff size 0 align 20 gran 20 limit fcdfffff flags 60081202 index 24 PCI: 00:14.4 resource base fc000000 size 900000 align 23 gran 20 limit fc8fffff flags 60080202 index 20 PCI: 08:01.0 PCI: 08:01.0 resource base fc000000 size 800000 align 23 gran 23 limit fc7fffff flags 60000200 index 10 PCI: 08:01.0 resource base fc800000 size 20000 align 17 gran 17 limit fc81ffff flags 60000200 index 14 PCI: 08:01.0 resource base 4000 size 80 align 7 gran 7 limit 407f flags 60000100 index 18 PCI: 08:01.0 resource base a0000 size 1fc00 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 08:02.0 PCI: 08:02.0 resource base fc820000 size 1000 align 12 gran 12 limit fc820fff flags 60000200 index 10 PCI: 08:03.0 PCI: 00:14.5 PCI: 00:14.5 resource base fcc0c000 size 1000 align 12 gran 12 limit fcc0cfff flags 60000200 index 10 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60000200 index 94 PCI: 00:18.4 PCI: 00:18.5 PCI: 00:19.0 PCI: 00:19.1 PCI: 00:19.2 PCI: 00:19.3 PCI: 00:19.4 PCI: 00:19.5 PCI: 00:1a.0 PCI: 00:1a.1 PCI: 00:1a.2 PCI: 00:1a.3 PCI: 00:1a.4 PCI: 00:1a.5 PCI: 00:1b.0 PCI: 00:1b.1 PCI: 00:1b.2 PCI: 00:1b.3 PCI: 00:1b.4 PCI: 00:1b.5 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 5277 exit 0 Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/8163 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/8163 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 cmd <- 00 PCI: 00:19.0 cmd <- 00 PCI: 00:19.1 subsystem <- 1043/8163 PCI: 00:19.1 cmd <- 00 PCI: 00:19.2 subsystem <- 1043/8163 PCI: 00:19.2 cmd <- 00 PCI: 00:19.3 cmd <- 00 PCI: 00:19.4 cmd <- 00 PCI: 00:19.5 cmd <- 00 PCI: 00:1a.0 cmd <- 00 PCI: 00:1a.1 subsystem <- 1043/8163 PCI: 00:1a.1 cmd <- 00 PCI: 00:1a.2 subsystem <- 1043/8163 PCI: 00:1a.2 cmd <- 00 PCI: 00:1a.3 cmd <- 00 PCI: 00:1a.4 cmd <- 00 PCI: 00:1a.5 cmd <- 00 PCI: 00:1b.0 cmd <- 00 PCI: 00:1b.1 subsystem <- 1043/8163 PCI: 00:1b.1 cmd <- 00 PCI: 00:1b.2 subsystem <- 1043/8163 PCI: 00:1b.2 cmd <- 00 PCI: 00:1b.3 cmd <- 00 PCI: 00:1b.4 cmd <- 00 PCI: 00:1b.5 cmd <- 00 PCI: 00:00.0 subsystem <- 1043/8163 PCI: 00:00.0 cmd <- 02 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 Initializing IOMMU PCI: 00:02.0 bridge ctrl <- 0003 PCI: 00:02.0 cmd <- 00 PCI: 00:04.0 bridge ctrl <- 0003 PCI: 00:04.0 cmd <- 07 PCI: 00:09.0 bridge ctrl <- 0003 PCI: 00:09.0 cmd <- 07 PCI: 00:0a.0 bridge ctrl <- 0003 PCI: 00:0a.0 cmd <- 07 PCI: 00:0b.0 bridge ctrl <- 0003 PCI: 00:0b.0 cmd <- 00 PCI: 00:0c.0 bridge ctrl <- 0003 PCI: 00:0c.0 cmd <- 00 PCI: 00:0d.0 bridge ctrl <- 0003 PCI: 00:0d.0 cmd <- 00 PCI: 00:11.0 subsystem <- 1043/8163 PCI: 00:11.0 cmd <- 03 PCI: 00:12.0 subsystem <- 1043/8163 PCI: 00:12.0 cmd <- 02 PCI: 00:12.1 subsystem <- 1043/8163 PCI: 00:12.1 cmd <- 02 PCI: 00:12.2 subsystem <- 1043/8163 PCI: 00:12.2 cmd <- 02 PCI: 00:13.0 subsystem <- 1043/8163 PCI: 00:13.0 cmd <- 02 PCI: 00:13.1 subsystem <- 1043/8163 PCI: 00:13.1 cmd <- 02 PCI: 00:13.2 subsystem <- 1043/8163 PCI: 00:13.2 cmd <- 02 PCI: 00:14.0 subsystem <- 1043/8163 PCI: 00:14.0 cmd <- 403 PCI: 00:14.1 subsystem <- 1043/8163 PCI: 00:14.1 cmd <- 01 PCI: 00:14.2 subsystem <- 1043/8163 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 subsystem <- 1043/8163 PCI: 00:14.3 cmd <- 0f sb700 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff sb700 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060 sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064 sb700 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000291 PCI: 00:14.4 bridge ctrl <- 000b PCI: 00:14.4 cmd <- 07 PCI: 00:14.5 subsystem <- 1043/8163 PCI: 00:14.5 cmd <- 02 PCI: 02:00.0 cmd <- 03 PCI: 03:00.0 cmd <- 03 PCI: 04:00.0 cmd <- 03 PCI: 08:01.0 cmd <- 03 PCI: 08:02.0 subsystem <- 1043/8163 PCI: 08:02.0 cmd <- 02 done. BS: BS_DEV_ENABLE times (us): entry 0 run 1147 exit 0 Initializing devices... Root Device init ... Root Device init finished in 0 usecs CPU_CLUSTER: 0 init ... CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 Enabling probe filter Enabling ATM mode CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 start_eip=0x00001000, code_size=0x00000031 CPU1: stack_base 0014f000, stack_end 0014fff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 1. After apic_write. Initializing CPU #1 CPU: vendor AMD device 600f12 CPU: family 15, model 01, stepping 02 Startup point 1. Waiting for send to finish... +nodeid = 00, coreid = 01 Enabling cache After Startup. CPU2: stack_base 0014e000, stack_end 0014eff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 2. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU3: stack_base 0014d000, stack_end 0014dff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 3. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU4: stack_base 0014c000, stack_end 0014cff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 4. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU5: stack_base 0014b000, stack_end 0014bff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 5. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU6: stack_base 0014a000, stack_end 0014aff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 6. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU7: stack_base 00149000, stack_end 00149ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 7. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU8: stack_base 00148000, stack_end 00148ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 8. After apic_write. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Startup point 1. Waiting for send to finish... +After Startup. MTRR check CPU9: stack_base 00147000, stack_end 00147ff8 Fixed MTRRs : Enabled Variable MTRRs: Enabled Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 9. After apic_write. Startup point 1. Waiting for send to finish... +Setting up local APIC...After Startup. Setting up local APIC...CPU10: stack_base 00146000, stack_end 00146ff8 apic_id: 0x02 apic_id: 0x04 done. done. Asserting INIT. Waiting for send to finish... +Deasserting INIT. CPU model: Waiting for send to finish... +CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, siblings = 11, #startup loops: 1. Disabling SMM ASeg memory Sending STARTUP #1 to 10. After apic_write. Disabling SMM ASeg memory MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU #4 initialized Setting up local APIC...Setting up local APIC...CPU #2 initialized Startup point 1. Waiting for send to finish... + apic_id: 0x05 done. apic_id: 0x03 After Startup. CPU model: AMD Opteron(TM) Processor 6238 CPU11: stack_base 00145000, stack_end 00145ff8 done. siblings = 11, Disabling SMM ASeg memory CPU #5 initialized Asserting INIT. Waiting for send to finish... +CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory CPU #3 initialized Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 11. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU12: stack_base 00144000, stack_end 00144ff8 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 32. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU13: stack_base 00143000, stack_end 00143ff8 Asserting INIT. Setting up local APIC...Waiting for send to finish... + apic_id: 0x06 done. CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory CPU #6 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 33. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU14: stack_base 00142000, stack_end 00142ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Setting up local APIC...Waiting for send to finish... + apic_id: 0x07 done. CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory CPU #7 initialized #startup loops: 1. Sending STARTUP #1 to 34. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU15: stack_base 00141000, stack_end 00141ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 35. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU16: stack_base 00140000, stack_end 00140ff8 MTRR check Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +Enabling cache Fixed MTRRs : Enabled Variable MTRRs: Enabled #startup loops: 1. Sending STARTUP #1 to 36. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU17: stack_base 0013f000, stack_end 0013fff8 Asserting INIT. Waiting for send to finish... +Setting up local APIC... apic_id: 0x08 done. Deasserting INIT. Waiting for send to finish... +#startup loops: 1. CPU model: AMD Opteron(TM) Processor 6238 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled siblings = 11, Sending STARTUP #1 to 37. After apic_write. Disabling SMM ASeg memory MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU #8 initialized Setting up local APIC...Setting up local APIC... apic_id: 0x09 done. apic_id: 0x0a done. Startup point 1. CPU model: AMD Opteron(TM) Processor 6238 Waiting for send to finish... +siblings = 11, Disabling SMM ASeg memory CPU #9 initialized CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory CPU #10 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled After Startup. CPU18: stack_base 0013e000, stack_end 0013eff8 Setting up local APIC... MTRR check apic_id: 0x0b done. Asserting INIT. nodeid = 02, coreid = 01 Waiting for send to finish... CPU model: AMD Opteron(TM) Processor 6238 Fixed MTRRs : Enabled Variable MTRRs: Enabled siblings = 11, +Disabling SMM ASeg memory CPU #11 initialized Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 38. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU19: stack_base 0013d000, stack_end 0013dff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 39. After apic_write. Startup point 1. Waiting for send to finish... +Enabling cache Setting up local APIC...After Startup. CPU20: stack_base 0013c000, stack_end 0013cff8 apic_id: 0x20 done. Asserting INIT. Waiting for send to finish... +CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU #12 initialized Setting up local APIC...Deasserting INIT. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled apic_id: 0x21 done. Waiting for send to finish... +CPU model: AMD Opteron(TM) Processor 6238 #startup loops: 1. Sending STARTUP #1 to 40. siblings = 11, After apic_write. Disabling SMM ASeg memory CPU #13 initialized Startup point 1. Waiting for send to finish... +After Startup. CPU: vendor AMD device 600f12 CPU21: stack_base 0013b000, stack_end 0013bff8 MTRR check CPU: family 15, model 01, stepping 02 Asserting INIT. Fixed MTRRs : Enabled Variable MTRRs: Enabled Waiting for send to finish... +Deasserting INIT. Setting up local APIC...Waiting for send to finish... + apic_id: 0x22 done. CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory CPU #14 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled #startup loops: 1. Sending STARTUP #1 to 41. After apic_write. Startup point 1. Waiting for send to finish... +Setting up local APIC... apic_id: 0x23 done. After Startup. CPU model: AMD Opteron(TM) Processor 6238 Setting up local APIC...siblings = 11, CPU22: stack_base 0013a000, stack_end 0013aff8 Asserting INIT. nodeid = 02, coreid = 05 Waiting for send to finish... Disabling SMM ASeg memory apic_id: 0x24 Enabling cache +Deasserting INIT. done. CPU model: AMD Opteron(TM) Processor 6238 CPU #15 initialized siblings = 11, Waiting for send to finish... +Disabling SMM ASeg memory MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU #16 initialized Setting up local APIC...#startup loops: 1. Sending STARTUP #1 to 42. After apic_write. apic_id: 0x25 done. Startup point 1. Waiting for send to finish... +CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory CPU #17 initialized After Startup. CPU23: stack_base 00139000, stack_end 00139ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 43. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #0 CPU: vendor AMD device 600f12 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU: family 15, model 01, stepping 02 nodeid = 00, coreid = 00 Enabling cache odeid = 03, coreid = 03 CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB Setting up local APIC...Enabling cache MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixnabled Variable MTRRs: Enabled CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory CPU #18 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local APIC... apic_id: 0x28 done. CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory CPU #20 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled odeid = 03, coreid = 05 Setting up local APIC...Setting up local APIC... apic_id: 0x27 done. apic_id: 0x29 done. Enabling cache MTRR check MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model: AMD Opteron(TM) ProcessoAMD AMD Opteron(TM) Pro Fixed MTRRs : CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, siblings = 11, Enabled Variable MTRRs: Enabled Disabling SMM ASeg memory Disabling SMM ASeg memory CPU #19 initialized CPU #21 initialized Setting up local APIC... apic_id: 0x2a done. CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory Setting up local APIC...CPU #22 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled apic_id: 0x00 done. CPU model: AMD Opteron(TM) Processor 6238 siblings = 11, Disabling SMM ASeg memory CPU #0 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Waiting for 2 CPUS to stop Setting up local APIC...Setting up local APIC... apic_id: 0x2b done. apic_id: 0x01 done. CPU model: AMD Opteron(AMD ProcessoAMD 38 TM) CPU model: AMD ron(TM) siblings = 11, siblings = 11, Disabling SMM ASeg memory Disabling SMM ASeg memory CPU #1 initialized CPU #23 initialized All AP CPUs stopped (3 loops) CPU0: stack: 00150000 - 00151000, lowest used address 001509d0, stack used: 1584 bytes CPU1: stack: 0014f000 - 00150000, lowest used address 0014fde0, stack used: 544 bytes CPU2: stack: 0014e000 - 0014f000, lowest used address 0014ece0, stack used: 800 bytes CPU3: stack: 0014d000 - 0014e000, lowest used address 0014dde0, stack used: 544 bytes CPU4: stack: 0014c000 - 0014d000, lowest used address 0014cd00, stack used: 768 bytes CPU5: stack: 0014b000 - 0014c000, lowest used address 0014bde0, stack used: 544 bytes CPU6: stack: 0014a000 - 0014b000, lowest used address 0014ad00, stack used: 768 bytes CPU7: stack: 00149000 - 0014a000, lowest used address 00149de0, stack used: 544 bytes CPU8: stack: 00148000 - 00149000, lowest used address 00148d00, stack used: 768 bytes CPU9: stack: 00147000 - 00148000, lowest used address 00147de0, stack used: 544 bytes CPU10: stack: 00146000 - 00147000, lowest used address 00146d00, stack used: 768 bytes CPU11: stack: 00145000 - 00146000, lowest used address 00145de0, stack used: 544 bytes CPU12: stack: 00144000 - 00145000, lowest used address 00144d00, stack used: 768 bytes CPU13: stack: 00143000 - 00144000, lowest used address 00143de0, stack used: 544 bytes CPU14: stack: 00142000 - 00143000, lowest used address 00142d00, stack used: 768 bytes CPU15: stack: 00141000 - 00142000, lowest used address 00141de0, stack used: 544 bytes CPU16: stack: 00140000 - 00141000, lowest used address 00140d00, stack used: 768 bytes CPU17: stack: 0013f000 - 00140000, lowest used address 0013fde0, stack used: 544 bytes CPU18: stack: 0013e000 - 0013f000, lowest used address 0013ed00, stack used: 768 bytes CPU19: stack: 0013d000 - 0013e000, lowest used address 0013dde0, stack used: 544 bytes CPU20: stack: 0013c000 - 0013d000, lowest used address 0013cd00, stack used: 768 bytes CPU21: stack: 0013b000 - 0013c000, lowest used address 0013bde0, stack used: 544 bytes CPU22: stack: 0013a000 - 0013b000, lowest used address 0013ad00, stack used: 768 bytes CPU23: stack: 00139000 - 0013a000, lowest used address 00139de0, stack used: 544 bytes CPU_CLUSTER: 0 init finished in 85450 usecs PCI: 00:18.0 init ... PCI: 00:18.0 init finished in 0 usecs PCI: 00:18.1 init ... PCI: 00:18.1 init finished in 0 usecs PCI: 00:18.2 init ... PCI: 00:18.2 init finished in 0 usecs PCI: 00:18.3 init ... NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 done. PCI: 00:18.3 init finished in 940 usecs PCI: 00:18.4 init ... NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 done. PCI: 00:18.4 init finished in 1474 usecs PCI: 00:18.5 init ... NB: Function 5 Northbridge Control.. done. PCI: 00:18.5 init finished in 1 usecs PCI: 00:19.0 init ... PCI: 00:19.0 init finished in 0 usecs PCI: 00:19.1 init ... PCI: 00:19.1 init finished in 0 usecs PCI: 00:19.2 init ... PCI: 00:19.2 init finished in 0 usecs PCI: 00:19.3 init ... NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 done. PCI: 00:19.3 init finished in 942 usecs PCI: 00:19.4 init ... NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 done. PCI: 00:19.4 init finished in 1492 usecs PCI: 00:19.5 init ... NB: Function 5 Northbridge Control.. done. PCI: 00:19.5 init finished in 1 usecs PCI: 00:1a.0 init ... PCI: 00:1a.0 init finished in 0 usecs PCI: 00:1a.1 init ... PCI: 00:1a.1 init finished in 0 usecs PCI: 00:1a.2 init ... PCI: 00:1a.2 init finished in 0 usecs PCI: 00:1a.3 init ... NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 done. PCI: 00:1a.3 init finished in 943 usecs PCI: 00:1a.4 init ... NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 done. PCI: 00:1a.4 init finished in 1474 usecs PCI: 00:1a.5 init ... NB: Function 5 Northbridge Control.. done. PCI: 00:1a.5 init finished in 1 usecs PCI: 00:1b.0 init ... PCI: 00:1b.0 init finished in 0 usecs PCI: 00:1b.1 init ... PCI: 00:1b.1 init finished in 0 usecs PCI: 00:1b.2 init ... PCI: 00:1b.2 init finished in 0 usecs PCI: 00:1b.3 init ... NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 done. PCI: 00:1b.3 init finished in 942 usecs PCI: 00:1b.4 init ... NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 done. PCI: 00:1b.4 init finished in 1473 usecs PCI: 00:1b.5 init ... NB: Function 5 Northbridge Control.. done. PCI: 00:1b.5 init finished in 1 usecs PCI: 00:00.0 init ... pcie_init in sr5650_ht.c IOAPIC: Initializing IOAPIC at 0xfcd00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x01 IOAPIC: Dumping registers reg 0x0000: 0x01000000 reg 0x0001: 0x001f8021 reg 0x0002: 0x00000000 IOAPIC: 32 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: reg 0x00000018 value 0x00000000 0x00010000 IOAPIC: reg 0x00000019 value 0x00000000 0x00010000 IOAPIC: reg 0x0000001a value 0x00000000 0x00010000 IOAPIC: reg 0x0000001b value 0x00000000 0x00010000 IOAPIC: reg 0x0000001c value 0x00000000 0x00010000 IOAPIC: reg 0x0000001d value 0x00000000 0x00010000 IOAPIC: reg 0x0000001e value 0x00000000 0x00010000 IOAPIC: reg 0x0000001f value 0x00000000 0x00010000 PCI: 00:00.0 init finished in 33 usecs PCI: 00:11.0 init ... CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 rev_id=15 sata_bar0=5020 sata_bar1=5040 sata_bar2=5028 sata_bar3=5044 sata_bar4=5000 sata_bar5=fcc0d000 ide_bar0=5030 ide_bar1=5048 ide_bar2=5038 ide_bar3=504c Maximum SATA port count supported by silicon: 6 SATA port 0 status = 23 drive detection done after 0 ms AHCI device 0 is ready after 1 tries SATA port 1 status = 0 No AHCI SATA drive on Slot1 SATA port 2 status = 0 No AHCI SATA drive on Slot2 SATA port 3 status = 13 drive detection done after 0 ms AHCI device 3 is ready after 1 tries SATA port 4 status = 0 No AHCI SATA drive on Slot4 SATA port 5 status = 0 No AHCI SATA drive on Slot5 PCI: 00:11.0 init finished in 11272 usecs PCI: 00:12.0 init ... PCI: 00:12.0 init finished in 25 usecs PCI: 00:12.1 init ... PCI: 00:12.1 init finished in 25 usecs PCI: 00:12.2 init ... CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 usb2_bar0=0xfcc0e000 rpr 6.23, final dword=849e03c8 PCI: 00:12.2 init finished in 946 usecs PCI: 00:13.0 init ... PCI: 00:13.0 init finished in 25 usecs PCI: 00:13.1 init ... PCI: 00:13.1 init finished in 24 usecs PCI: 00:13.2 init ... CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 usb2_bar0=0xfcc0f000 rpr 6.23, final dword=849e03c8 PCI: 00:13.2 init finished in 947 usecs PCI: 00:14.0 init ... sm_init(). IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: Dumping registers reg 0x0000: 0x00000000 reg 0x0001: 0x00178021 reg 0x0002: 0x00000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 WARNING: No CMOS option 'enable_legacy_usb'. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 set power "on" after power fail CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 ++++++++++no set NMI+++++ RTC Init sm_init() end PCI: 00:14.0 init finished in 2480 usecs PCI: 00:14.1 init ... CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 PCI: 00:14.1 init finished in 713 usecs PCI: 00:14.2 init ... base = 0xfcc04000 codec_mask = 01 0(th) codec viddid: 10ec0892 PCI: 00:14.2 init finished in 2489 usecs PCI: 00:14.3 init ... lpc_init PCI: 00:14.3 init finished in 26 usecs PCI: 00:14.4 init ... PCI: 00:14.4 init finished in 19 usecs PCI: 00:14.5 init ... PCI: 00:14.5 init finished in 25 usecs PCI: 02:00.0 init ... PCI: 02:00.0 init finished in 0 usecs PCI: 03:00.0 init ... PCI: 03:00.0 init finished in 0 usecs PCI: 04:00.0 init ... PCI: 04:00.0 init finished in 0 usecs smbus: PCI: 00:14.0[0]->I2C: 01:2f init ... Set SMBUS controller to channel 1 Found 64 pin W83795G Nuvoton H/W Monitor W83795G/ADG work in Thermal Cruise Mode Fan CTFS(celsius) TTTI(celsius) 1 80 80 2 80 80 3 80 80 4 80 80 5 80 80 6 80 80 DTS1 current value: 14 DTS2 current value: 10 DTS3 current value: 0 DTS4 current value: 0 DTS5 current value: 0 DTS6 current value: 0 DTS7 current value: 0 DTS8 current value: 0 Set SMBUS controller to channel 0 I2C: 01:2f init finished in 283275 usecs PNP: 002e.2 init ... PNP: 002e.2 init finished in 0 usecs PNP: 002e.3 init ... PNP: 002e.3 init finished in 0 usecs PNP: 002e.5 init ... PNP: 002e.5 init finished in 18 usecs PNP: 002e.a init ... CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 set power on after power fail PNP: 002e.a init finished in 611 usecs PNP: 002e.b init ... PNP: 002e.b init finished in 0 usecs PCI: 08:01.0 init ... ASpeed AST2050: initializing video device ast_detect_chip: AST 1100 detected ast_detect_chip: VGA not enabled on entry, requesting chip POST ast_detect_chip: Analog VGA only ast_driver_load: dram 18000000 0 32 00800000 ASpeed VGA text mode initialized PCI: 08:01.0 init finished in 17427 usecs PCI: 08:02.0 init ... PCI: 08:02.0 init finished in 0 usecs Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:00.2: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.1: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 01:50: enabled 1 I2C: 01:51: enabled 1 I2C: 01:52: enabled 1 I2C: 01:53: enabled 1 I2C: 01:54: enabled 1 I2C: 01:55: enabled 1 I2C: 01:56: enabled 1 I2C: 01:57: enabled 1 I2C: 01:2f: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.106: enabled 0 PNP: 002e.107: enabled 0 PNP: 002e.207: enabled 0 PNP: 002e.307: enabled 0 PNP: 002e.407: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.108: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.109: enabled 0 PNP: 002e.209: enabled 0 PNP: 002e.309: enabled 0 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PNP: 002e.c: enabled 0 PNP: 002e.d: enabled 0 PNP: 002e.f: enabled 0 PNP: 004e.0: enabled 1 PCI: 00:14.4: enabled 1 PCI: 08:01.0: enabled 1 PCI: 08:02.0: enabled 1 PCI: 08:03.0: enabled 0 PCI: 00:14.5: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:19.1: enabled 1 PCI: 00:19.2: enabled 1 PCI: 00:19.3: enabled 1 PCI: 00:19.4: enabled 1 PCI: 00:19.5: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1a.1: enabled 1 PCI: 00:1a.2: enabled 1 PCI: 00:1a.3: enabled 1 PCI: 00:1a.4: enabled 1 PCI: 00:1a.5: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1b.1: enabled 1 PCI: 00:1b.2: enabled 1 PCI: 00:1b.3: enabled 1 PCI: 00:1b.4: enabled 1 PCI: 00:1b.5: enabled 1 APIC: 01: enabled 1 APIC: 02: enabled 1 APIC: 03: enabled 1 APIC: 04: enabled 1 APIC: 05: enabled 1 APIC: 06: enabled 1 APIC: 07: enabled 1 APIC: 08: enabled 1 APIC: 09: enabled 1 APIC: 0a: enabled 1 APIC: 0b: enabled 1 APIC: 20: enabled 1 APIC: 21: enabled 1 APIC: 22: enabled 1 APIC: 23: enabled 1 APIC: 24: enabled 1 APIC: 25: enabled 1 APIC: 26: enabled 1 APIC: 27: enabled 1 APIC: 28: enabled 1 APIC: 29: enabled 1 APIC: 2a: enabled 1 APIC: 2b: enabled 1 PCI: 02:00.0: enabled 1 PCI: 03:00.0: enabled 1 PCI: 04:00.0: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 415750 exit 0 Finalize devices... Devices finalized BS: BS_POST_DEVICE times (us): entry 0 run 3 exit 0 BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 Writing IRQ routing tables to 0xf0000...done. Writing IRQ routing tables to 0xb7cbf000...done. PIRQ table: 48 bytes. Wrote the mp table end at: 000f0410 - 000f080c Wrote the mp table end at: b7cbe010 - b7cbe40c MP table: 1036 bytes. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'fallback/dsdt.aml' CBFS: Found @ offset 2b900 size 266b CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'fallback/slic' CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at b7c9a000. ACPI: * FACS ACPI: * DSDT ACPI: * FADT pm_base: 0x0800 ACPI: added table 1/32, length now 40 ACPI: * SSDT CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 processor_brand=AMD Opteron(AMD ProcessoAMD 38 TM) Pstates algorithm ... Pstate_freq[0] = 2600MHz Pstate_power[0] = 7492mw Pstate_latency[0] = 5us Pstate_freq[1] = 2300MHz Pstate_power[1] = 6800mw Pstate_latency[1] = 5us Pstate_freq[2] = 1900MHz Pstate_power[2] = 5871mw Pstate_latency[2] = 5us Pstate_freq[3] = 1600MHz Pstate_power[3] = 4653mw Pstate_latency[3] = 5us Pstate_freq[4] = 1400MHz Pstate_power[4] = 3905mw Pstate_latency[4] = 5us PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 PSS: 2600MHz power 7492 control 0x0 status 0x0 PSS: 2300MHz power 6800 control 0x1 status 0x1 PSS: 1900MHz power 5871 control 0x2 status 0x2 PSS: 1600MHz power 4653 control 0x3 status 0x3 PSS: 1400MHz power 3905 control 0x4 status 0x4 ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TCPA TCPA log created at b7c8a000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = b7c9f7b0 ACPI: * SRAT at b7c9f7b0 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 SRAT: lapic cpu_index=06, node_id=01, apic_id=06 SRAT: lapic cpu_index=07, node_id=01, apic_id=07 SRAT: lapic cpu_index=08, node_id=01, apic_id=08 SRAT: lapic cpu_index=09, node_id=01, apic_id=09 SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b SRAT: lapic cpu_index=0c, node_id=02, apic_id=20 SRAT: lapic cpu_index=0d, node_id=02, apic_id=21 SRAT: lapic cpu_index=0e, node_id=02, apic_id=22 SRAT: lapic cpu_index=0f, node_id=02, apic_id=23 SRAT: lapic cpu_index=10, node_id=02, apic_id=24 SRAT: lapic cpu_index=11, node_id=02, apic_id=25 SRAT: lapic cpu_index=12, node_id=03, apic_id=26 SRAT: lapic cpu_index=13, node_id=03, apic_id=27 SRAT: lapic cpu_index=14, node_id=03, apic_id=28 SRAT: lapic cpu_index=15, node_id=03, apic_id=29 SRAT: lapic cpu_index=16, node_id=03, apic_id=2a SRAT: lapic cpu_index=17, node_id=03, apic_id=2b set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=020e0000, sizek=00020000 set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00500000 set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=00900000, sizek=00800000 set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=01100000, sizek=00800000 set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=01900000, sizek=00800000 ACPI: added table 6/32, length now 60 ACPI: * SLIT at b7c9fa50 ACPI: added table 7/32, length now 64 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 ACPI: * IVRS at b7c9fa90 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x68 Capability: type 0x01 @ 0xc8 Capability: type 0x05 @ 0xd0 Capability: type 0x10 @ 0xe0 Capability: type 0x01 @ 0xc8 Capability: type 0x05 @ 0xd0 Capability: type 0x10 @ 0xe0 Capability: type 0x01 @ 0x40 Capability: type 0x01 @ 0x44 ACPI: added table 8/32, length now 68 ACPI: * HPET ACPI: added table 9/32, length now 72 ACPI: * SRAT at b7c9fb80 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 SRAT: lapic cpu_index=06, node_id=01, apic_id=06 SRAT: lapic cpu_index=07, node_id=01, apic_id=07 SRAT: lapic cpu_index=08, node_id=01, apic_id=08 SRAT: lapic cpu_index=09, node_id=01, apic_id=09 SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b SRAT: lapic cpu_index=0c, node_id=02, apic_id=20 SRAT: lapic cpu_index=0d, node_id=02, apic_id=21 SRAT: lapic cpu_index=0e, node_id=02, apic_id=22 SRAT: lapic cpu_index=0f, node_id=02, apic_id=23 SRAT: lapic cpu_index=10, node_id=02, apic_id=24 SRAT: lapic cpu_index=11, node_id=02, apic_id=25 SRAT: lapic cpu_index=12, node_id=03, apic_id=26 SRAT: lapic cpu_index=13, node_id=03, apic_id=27 SRAT: lapic cpu_index=14, node_id=03, apic_id=28 SRAT: lapic cpu_index=15, node_id=03, apic_id=29 SRAT: lapic cpu_index=16, node_id=03, apic_id=2a SRAT: lapic cpu_index=17, node_id=03, apic_id=2b set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=020e0000, sizek=00020000 set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00500000 set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=00900000, sizek=00800000 set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=01100000, sizek=00800000 set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=01900000, sizek=00800000 ACPI: added table 10/32, length now 76 ACPI: * SLIT at b7c9fe20 ACPI: added table 11/32, length now 80 ACPI: * SRAT at b7c9fe60 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 SRAT: lapic cpu_index=06, node_id=01, apic_id=06 SRAT: lapic cpu_index=07, node_id=01, apic_id=07 SRAT: lapic cpu_index=08, node_id=01, apic_id=08 SRAT: lapic cpu_index=09, node_id=01, apic_id=09 SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b SRAT: lapic cpu_index=0c, node_id=02, apic_id=20 SRAT: lapic cpu_index=0d, node_id=02, apic_id=21 SRAT: lapic cpu_index=0e, node_id=02, apic_id=22 SRAT: lapic cpu_index=0f, node_id=02, apic_id=23 SRAT: lapic cpu_index=10, node_id=02, apic_id=24 SRAT: lapic cpu_index=11, node_id=02, apic_id=25 SRAT: lapic cpu_index=12, node_id=03, apic_id=26 SRAT: lapic cpu_index=13, node_id=03, apic_id=27 SRAT: lapic cpu_index=14, node_id=03, apic_id=28 SRAT: lapic cpu_index=15, node_id=03, apic_id=29 SRAT: lapic cpu_index=16, node_id=03, apic_id=2a SRAT: lapic cpu_index=17, node_id=03, apic_id=2b set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=020e0000, sizek=00020000 set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00500000 set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=00900000, sizek=00800000 set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=01100000, sizek=00800000 set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=01900000, sizek=00800000 ACPI: added table 12/32, length now 84 ACPI: * SLIT at b7ca0100 ACPI: added table 13/32, length now 88 ACPI: * SRAT at b7ca0140 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 SRAT: lapic cpu_index=06, node_id=01, apic_id=06 SRAT: lapic cpu_index=07, node_id=01, apic_id=07 SRAT: lapic cpu_index=08, node_id=01, apic_id=08 SRAT: lapic cpu_index=09, node_id=01, apic_id=09 SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b SRAT: lapic cpu_index=0c, node_id=02, apic_id=20 SRAT: lapic cpu_index=0d, node_id=02, apic_id=21 SRAT: lapic cpu_index=0e, node_id=02, apic_id=22 SRAT: lapic cpu_index=0f, node_id=02, apic_id=23 SRAT: lapic cpu_index=10, node_id=02, apic_id=24 SRAT: lapic cpu_index=11, node_id=02, apic_id=25 SRAT: lapic cpu_index=12, node_id=03, apic_id=26 SRAT: lapic cpu_index=13, node_id=03, apic_id=27 SRAT: lapic cpu_index=14, node_id=03, apic_id=28 SRAT: lapic cpu_index=15, node_id=03, apic_id=29 SRAT: lapic cpu_index=16, node_id=03, apic_id=2a SRAT: lapic cpu_index=17, node_id=03, apic_id=2b set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=020e0000, sizek=00020000 set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00500000 set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=00900000, sizek=00800000 set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=01100000, sizek=00800000 set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=01900000, sizek=00800000 ACPI: added table 14/32, length now 92 ACPI: * SLIT at b7ca03e0 ACPI: added table 15/32, length now 96 ACPI: done. ACPI tables: 25632 bytes. smbios_write_tables: b7c89000 Root Device (ASUS KGPE-D16) CPU_CLUSTER: 0 (AMD Family 10h/15h Root Complex) APIC: 00 (unknown) DOMAIN: 0000 (AMD Family 10h/15h Root Complex) PCI: 00:18.0 (AMD Family 10h/15h Northbridge) PCI: 00:00.0 (ATI SR5650) PCI: 00:00.1 (ATI SR5650) PCI: 00:00.2 (ATI SR5650) PCI: 00:02.0 (ATI SR5650) PCI: 00:03.0 (ATI SR5650) PCI: 00:04.0 (ATI SR5650) PCI: 00:05.0 (ATI SR5650) PCI: 00:06.0 (ATI SR5650) PCI: 00:07.0 (ATI SR5650) PCI: 00:08.0 (ATI SR5650) PCI: 00:09.0 (ATI SR5650) PCI: 00:0a.0 (ATI SR5650) PCI: 00:0b.0 (ATI SR5650) PCI: 00:0c.0 (ATI SR5650) PCI: 00:0d.0 (ATI SR5650) PCI: 00:11.0 (ATI SP5100) PCI: 00:12.0 (ATI SP5100) PCI: 00:12.1 (ATI SP5100) PCI: 00:12.2 (ATI SP5100) PCI: 00:13.0 (ATI SP5100) PCI: 00:13.1 (ATI SP5100) PCI: 00:13.2 (ATI SP5100) PCI: 00:14.0 (ATI SP5100) I2C: 01:50 (unknown) I2C: 01:51 (unknown) I2C: 01:52 (unknown) I2C: 01:53 (unknown) I2C: 01:54 (unknown) I2C: 01:55 (unknown) I2C: 01:56 (unknown) I2C: 01:57 (unknown) I2C: 01:2f (Nuvoton W83795G/ADG Hardware Monitor) PCI: 00:14.1 (ATI SP5100) PCI: 00:14.2 (ATI SP5100) PCI: 00:14.3 (ATI SP5100) PNP: 002e.0 (WINBOND W83667HG-A Super I/O) PNP: 002e.1 (WINBOND W83667HG-A Super I/O) PNP: 002e.2 (WINBOND W83667HG-A Super I/O) PNP: 002e.3 (WINBOND W83667HG-A Super I/O) PNP: 002e.5 (WINBOND W83667HG-A Super I/O) PNP: 002e.106 (WINBOND W83667HG-A Super I/O) PNP: 002e.107 (WINBOND W83667HG-A Super I/O) PNP: 002e.207 (WINBOND W83667HG-A Super I/O) PNP: 002e.307 (WINBOND W83667HG-A Super I/O) PNP: 002e.407 (WINBOND W83667HG-A Super I/O) PNP: 002e.8 (WINBOND W83667HG-A Super I/O) PNP: 002e.108 (WINBOND W83667HG-A Super I/O) PNP: 002e.9 (WINBOND W83667HG-A Super I/O) PNP: 002e.109 (WINBOND W83667HG-A Super I/O) PNP: 002e.209 (WINBOND W83667HG-A Super I/O) PNP: 002e.309 (WINBOND W83667HG-A Super I/O) PNP: 002e.a (WINBOND W83667HG-A Super I/O) PNP: 002e.b (WINBOND W83667HG-A Super I/O) PNP: 002e.c (WINBOND W83667HG-A Super I/O) PNP: 002e.d (WINBOND W83667HG-A Super I/O) PNP: 002e.f (WINBOND W83667HG-A Super I/O) PNP: 004e.0 (unknown) PCI: 00:14.4 (ATI SP5100) PCI: 08:01.0 (ATI SP5100) PCI: 08:02.0 (ATI SP5100) PCI: 08:03.0 (ATI SP5100) PCI: 00:14.5 (ATI SP5100) PCI: 00:18.1 (AMD Family 10h/15h Northbridge) PCI: 00:18.2 (AMD Family 10h/15h Northbridge) PCI: 00:18.3 (AMD Family 10h/15h Northbridge) PCI: 00:18.4 (AMD Family 10h/15h Northbridge) PCI: 00:18.5 (AMD Family 10h/15h Northbridge) PCI: 00:19.0 (AMD Family 10h/15h Northbridge) PCI: 00:19.1 (AMD Family 10h/15h Northbridge) PCI: 00:19.2 (AMD Family 10h/15h Northbridge) PCI: 00:19.3 (AMD Family 10h/15h Northbridge) PCI: 00:19.4 (AMD Family 10h/15h Northbridge) PCI: 00:19.5 (AMD Family 10h/15h Northbridge) PCI: 00:1a.0 (AMD Family 10h/15h Northbridge) PCI: 00:1a.1 (AMD Family 10h/15h Northbridge) PCI: 00:1a.2 (AMD Family 10h/15h Northbridge) PCI: 00:1a.3 (AMD Family 10h/15h Northbridge) PCI: 00:1a.4 (AMD Family 10h/15h Northbridge) PCI: 00:1a.5 (AMD Family 10h/15h Northbridge) PCI: 00:1b.0 (AMD Family 10h/15h Northbridge) PCI: 00:1b.1 (AMD Family 10h/15h Northbridge) PCI: 00:1b.2 (AMD Family 10h/15h Northbridge) PCI: 00:1b.3 (AMD Family 10h/15h Northbridge) PCI: 00:1b.4 (AMD Family 10h/15h Northbridge) PCI: 00:1b.5 (AMD Family 10h/15h Northbridge) APIC: 01 (unknown) APIC: 02 (unknown) APIC: 03 (unknown) APIC: 04 (unknown) APIC: 05 (unknown) APIC: 06 (unknown) APIC: 07 (unknown) APIC: 08 (unknown) APIC: 09 (unknown) APIC: 0a (unknown) APIC: 0b (unknown) APIC: 20 (unknown) APIC: 21 (unknown) APIC: 22 (unknown) APIC: 23 (unknown) APIC: 24 (unknown) APIC: 25 (unknown) APIC: 26 (unknown) APIC: 27 (unknown) APIC: 28 (unknown) APIC: 29 (unknown) APIC: 2a (unknown) APIC: 2b (unknown) PCI: 02:00.0 (unknown) PCI: 03:00.0 (unknown) PCI: 04:00.0 (unknown) SMBIOS tables: 727 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4812 Writing coreboot table at 0xb7cc0000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000bffff: RESERVED 3. 00000000000c0000-00000000b7c88fff: RAM 4. 00000000b7c89000-00000000b7ffffff: CONFIGURATION TABLES 5. 00000000b8000000-00000000bfffffff: RAM 6. 00000000c0000000-00000000cfffffff: RESERVED 7. 00000000fcc00000-00000000fcc03fff: RESERVED 8. 00000000feb00000-00000000feb00fff: RESERVED 9. 00000000fec00000-00000000fec00fff: RESERVED 10. 00000000fed00000-00000000fed00fff: RESERVED 11. 0000000100000000-0000000837ffffff: RAM 12. 0000000838000000-000000083fffffff: RESERVED Manufacturer: ef SF: Detected W25Q128 with sector size 0x1000, total 0x1000000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) FMAP: Found "FLASH" version 1.1 at 0. FMAP: base = ff000000 size = 1000000 #areas = 3 Wrote coreboot table at: b7cc0000, 0x11b4 bytes, checksum cd8 coreboot table: 4556 bytes. IMD ROOT 0. b7fff000 00001000 IMD SMALL 1. b7ffe000 00001000 CAR GLOBALS 2. b7ff3000 0000a6c0 CONSOLE 3. b7fd3000 00020000 AMDMEM INFO 4. b7fc9000 000093fc ACPI RESUME 5. b7cc8000 00301000 COREBOOT 6. b7cc0000 00008000 IRQ TABLE 7. b7cbf000 00001000 SMP TABLE 8. b7cbe000 00001000 ACPI 9. b7c9a000 00024000 TCPA LOG 10. b7c8a000 00010000 SMBIOS 11. b7c89000 00000800 IMD small region: IMD ROOT 0. b7ffec00 00000400 ROMSTAGE 1. b7ffebe0 00000004 GDT 2. b7ffe9e0 00000200 Writing AMD DCT configuration to Flash CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 Manufacturer: ef SF: Detected W25Q128 with sector size 0x1000, total 0x1000000 SF: Successfully erased 32768 bytes @ 0x38000 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2aa40 size e88 BS: BS_WRITE_TABLES times (us): entry 1 run 491064 exit 0 CBFS: 'Master Header Locator' located CBFS at [100:ffffc0) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 550c0 size f66b Loading segment from ROM address 0xff0551f8 code (compression=1) New segment dstaddr 0xe31c0 memsize 0x1ce40 srcaddr 0xff055230 filesize 0xf633 Loading segment from ROM address 0xff055214 Entry Point 0x000ff06e Bounce Buffer at bfdd3000, 2278240 bytes Loading Segment: addr: 0x00000000000e31c0 memsz: 0x000000000001ce40 filesz: 0x000000000000f633 lb: [0x0000000000100000, 0x00000000002161b0) Post relocation: addr: 0x00000000000e31c0 memsz: 0x000000000001ce40 filesz: 0x000000000000f633 using LZMA [ 0x000e31c0, 00100000, 0x00100000) <- ff055230 dest 000e31c0, end 00100000, bouncebuffer bfdd3000 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 29539 exit 0 Jumping to boot code at 000ff06e(b7cc0000) CPU0: stack: 00150000 - 00151000, lowest used address 001509d0, stack used: 1584 bytes entry = 0x000ff06e lb_start = 0x00100000 lb_size = 0x001161b0 buffer = 0xbfdd3000 port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current state=2030506 link_width=2, lane_mask=ffPcieLinkTraining port=c:lc current ---- Thanks for your help

1 0

Where is the serial number stored on the thinkpad ivy/sandy bridge laptops
by Taiidan＠gmx.com 13 Oct '17

13 Oct '17

see "# dmidecode" Under system information and base board information I am curious as to how it survives the coreboot flash re-write, maybe the EC?

3 3

Does coreboot table still exist in F000 segment?
by WANG FEI 13 Oct '17

13 Oct '17

Hi, all Beside placing coreboot table (lb_header) in low RAM (0x0-0x1000), I remember a copy of coreboot table should be placed at F000 segment and it can be controlled with a Kconfig flag, does this feature still exist? I just can't find it right now. -Fei

1 0

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 13 Oct '17

13 Oct '17

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 2 new defect(s) introduced to coreboot found with Coverity Scan. 3 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 1381709: Null pointer dereferences (FORWARD_NULL) /src/soc/intel/skylake/pmutil.c: 220 in soc_get_gpi_gpe_configs() ________________________________________________________________________________________________________ *** CID 1381709: Null pointer dereferences (FORWARD_NULL) /src/soc/intel/skylake/pmutil.c: 220 in soc_get_gpi_gpe_configs() 214 215 /* Look up the device in devicetree */ 216 DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); 217 if (!dev || !dev->chip_info) { 218 printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); 219 } >>> CID 1381709: Null pointer dereferences (FORWARD_NULL) >>> Dereferencing null pointer "dev". 220 config = dev->chip_info; 221 222 /* Assign to out variable */ 223 *dw0 = config->gpe0_dw0; 224 *dw1 = config->gpe0_dw1; 225 *dw2 = config->gpe0_dw2; ** CID 1381708: Null pointer dereferences (FORWARD_NULL) /src/soc/intel/skylake/pmutil.c: 223 in soc_get_gpi_gpe_configs() ________________________________________________________________________________________________________ *** CID 1381708: Null pointer dereferences (FORWARD_NULL) /src/soc/intel/skylake/pmutil.c: 223 in soc_get_gpi_gpe_configs() 217 if (!dev || !dev->chip_info) { 218 printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); 219 } 220 config = dev->chip_info; 221 222 /* Assign to out variable */ >>> CID 1381708: Null pointer dereferences (FORWARD_NULL) >>> Dereferencing null pointer "config". 223 *dw0 = config->gpe0_dw0; 224 *dw1 = config->gpe0_dw1; 225 *dw2 = config->gpe0_dw2; 226 } 227 228 int rtc_failure(void) ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0… To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

1 0

Possibility to tear electrically out the Bios chip
by ingegneriaforense＠alice.it 13 Oct '17

13 Oct '17

Hello everybody, please, has some of you ripped out the BIOS chip from the motherboard when the pc is power on ? Has someone of you done this experiment ? Could be damages to the motherboard ? Or maybe Coreboot should be programmed to switch electrically off the chip before tear out it from its case ? I pose this question because, if really the Bios chip is only necessary for the boot process of a machine, has not sense that it is on board during the usual activity of the O.S. So, is it possible tear out it from its case after the boot process, when the pc is working and the O.S. has taken into account the whole control of the pc ? Tips are welcome. Thanks very much in advance ! I hope to hear you soon. Best Regards. Vincenzo. Forensic Consultant Tribunale di Lecce Studio: Strada di Garibaldi - Contrada Paradisi 73010 Lequile (LE) cell: 339.7968555 skype: vincenzo.di_salvo

3 2

Add mutable variable support to CBFS (was: Re: how to implement variable read/write variable in coreboot)
by Nico Huber 12 Oct '17

12 Oct '17

Hi Peter, On 01.10.2017 00:48, Peter Stuge wrote:> Nico Huber wrote: >> wear leveling >> ring buffer >> sanitation phase >> optimizing every update >> Defragmentation > .. >> Might work? > > Please don't invent a new format Can you give an example of an existing format that might do? I have to admit, I didn't took the time yet to look at related work. > don't reinvent JFFS2 and/or UBI.. These implement wear leveling for NAND flashes, AIUI. We are talking about NOR flashes. I'm pretty sure you know the difference better than I do. > > Let's make CBFS work for this, please. Reusing the existing data > structure is incredibly valuable, even if it means some overhead. There are a few obstacles to overcome and decisions to make if we want to use CBFS. First, what level of compatibility should we target? Some ideas, only some are mutually exclusive: 1. Just reuse the CBFS data structures for a new kind of entry (without implied compatibility to other entry types). 2. Handle any kind of CBFS entry in the variable storage implemen- tation that fits an erase block and can easily be moved around. 3. Handle any kind of CBFS entry in the variable storage implemen- tation. (even "complex" entries, e.g. bigger than erase block size, entries with fixed alignment or positions). 4. Always keep the variable storage in a state such that current CBFS readers succeed to read it. 5. Bloat current CBFS readers until they can handle the variable storage in any state (including fail states due to interrupted updates). 6. Always keep the variable storage in a state such that current `cbfstool` can alter a dump safely. 7. Bloat `cbfstool` until it can alter a dump safely. I hope we can agree that 1. alone would only result in confusion and is to be avoided. 2. seems to be easily accomplished, but I don't see any benefit. 3. together with 4. or 5. would allow us to put mutable variables into the same CBFS space that we use for the coreboot stages. It implies that we could never have a per erase block header but I've tried to avoid that in my drafts anyway, so far. I don't see how 4. and 6. could be accomplished without always keeping things in order and, thus, not having a backup in case an update fails. Maybe I miss something, could it be done? I don't like 5. and 7. (that's why I used the word bloat). But so far the only combination where I see a win by reusing CBFS structures with- out a loss in reliability is 3. + 5. (+ optionally 7.). Peter, please choose your preferred combination of compatibility targets (add new ones that you miss). Nico

1 0

Re: [coreboot] greetings and laptop questions
by Zoran Stojsavljevic 11 Oct '17

11 Oct '17

> Sorry for my part of starting this heated debate. Nothing to be sorry for... You are very welcome (and other guys who might join this discussion, from INTEL, GOOGLE, you name it! But they risk to loose at least $200K USD/per annum, and they are mortally afraid for outcome). :-) Zoran Stojsavljevic On Wed, Oct 11, 2017 at 8:22 PM, Jim Hendrick <james.r.hendrick(a)gmail.com> wrote: > Sorry if I triggered the emotional part of this thread! > > My 2 cents is this - the hardware industry has sacrificed privacy for the > sake of enterprise customers (can hardly blame them I suppose) and that has > left many of us with very few options. > > We can compromise on privacy for the latest performance, and take some > steps to guard against backdoors (which - at some level - we need to accept > that hardware is not actively compromised or we should all go back to > slide-rules...) > > We can insist on the best privacy and accept using (rapidly aging) > hardware. > > I have no hard data on coreboot, Purism, or any of the other tools / > products / companies out there. (and hope that that part of this thread has > run its course) > > It does seem to me that in order to even play in the market - that any > company would need to take the (reasonably current) hardware that is > available and do what it can to minimize the likelihood that the (assumed > or proven) backdoors can be exploited. > > I would like to see any company (Purism, system76 or anyone else) be able > to work with the major vendors to acquire hardware AND be able to replace > or wrap the compromised firmware to give us the best of both. > > To the degree that they fully disclose what they are able OR not able to > do to mitigate these risks is really between their marketing department and > their customers. > > For myself - I will probably end up with accepting the problems with more > recent hardware for functionality and performance and try to use other > security / privacy layers to minimize the risk. > > Sorry for my part of starting this heated debate. > > And thanks again to all for the insight! > > Jim > > > > > > On Wed, Oct 11, 2017 at 5:52 PM, Zoran Stojsavljevic < > zoran.stojsavljevic(a)gmail.com> wrote: > >> > let's pause this discussion until the new mailing list is up, and then >> move it there, ok? This is not technical >> > It's decreasing the signal to noise ratio on this list. >> >> It is NOT a NOISE, Ron... It is true ESSENCE. Do you, Ron, after all, >> think, I am a noise??? INTEL does think I am (fatal mistake). Don't you >> agree?? I am, after all, Open Source stray dog... And.. You would like to >> understand it?! Don't you?! You are GOOGLE (protected) dog, and INTEL dogs >> are trying out there to intercept me... Other stray dogs... .. . :-))) I >> laugh... why, Ron??? >> >> Do you think they are successful?! Really??? >> >> I am sorry to disappoint you. NO NOISE here... And if you do serve to >> INTEL main purposes... DO not distract with tricks, and proxys' to make it >> much easier for flock sheep... >> >> I am not fighting Purism, Ron, mu targets are much higher... Imagine! ;-) >> >> Don't You agree? >> >> TRUE essence. For TRUE purposes (I could NOT be blackmailed, never ever)! >> >> Sorry to be Honest Straight! >> Zoran Stojsavljevic >> >> On Wed, Oct 11, 2017 at 5:43 PM, ron minnich <rminnich(a)gmail.com> wrote: >> >>> let's pause this discussion until the new mailing list is up, and then >>> move it there, ok? This is not technical. It's decreasing the signal to >>> noise ratio on this list. >>> >>> Thanks >>> >>> On Tue, Oct 10, 2017 at 8:55 PM Zoran Stojsavljevic < >>> zoran.stojsavljevic(a)gmail.com> wrote: >>> >>>> > Sorry for that. My last sentence probably doesn't even express what >>>> > I was trying to say. Could be my bad English. >>>> >>>> Your English is quite good. >>>> >>>> > I just meant that there are people who are easily offended by >>>> dishonesty. >>>> >>>> Tell me about dishonesty, Nico. What Purism does is just a pebble of >>>> sand in the desert of big IT companies' dishonesty! >>>> >>>> Zoran Stojsavljevic >>>> >>>> >>>> On Wed, Oct 11, 2017 at 12:57 AM, Nico Huber <nico.h(a)gmx.de> wrote: >>>> >>>>> On 10.10.2017 20:02, Youness Alaoui wrote: >>>>> >> So my conclusion, Purism draws customers from other Linux supporting >>>>> >> vendors with dishonest marketing. If that doesn't bother you, fine. >>>>> >> But please don't get angry if it bothers honest people. >>>>> > >>>>> > ... >>>>> > 3 - By stating that it "bothers honest people", right after saying >>>>> > that it doesn't bother me, you're implying that I'm not an honest >>>>> > person (at least that's how I read it) and that kind of statement >>>>> > doesn't lead to cool headed discussions, so I'll simply withdraw from >>>>> > this one. >>>>> >>>>> Sorry for that. My last sentence probably doesn't even express what >>>>> I was trying to say. Could be my bad English. I just meant that there >>>>> are people who are easily offended by dishonesty. Well, yeah, it does >>>>> imply that I don't count you among them. >>>>> >>>>> Nico >>>>> >>>>> -- >>>>> coreboot mailing list: coreboot(a)coreboot.org >>>>> https://mail.coreboot.org/mailman/listinfo/coreboot >>>>> >>>> >>>> -- >>>> coreboot mailing list: coreboot(a)coreboot.org >>>> https://mail.coreboot.org/mailman/listinfo/coreboot >>> >>> >> >

1 0

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coreboot October 2017