coreboot March 2015

coreboot@coreboot.org

62 participants
166 discussions

Tianocore boot fails, [GSoc] CBFS support in tiano - discussion (C Ganesh Sundar)
by 107112017＠nitt.edu 15 Mar '15

15 Mar '15

Hi! I tried booting ELILO (disk.img - in gpt), ubuntu & windows 8(iso) on QEMU but wasn't successful. I am able to boot into serial uefi shell only(a blank fully black screen). I tried std vga ROM in QEMU too but no result. Any comments/help would be grateful. Below is the serial output: Booting EFI DVD/CDROM BlockSize : 2048 LastBlock : 1E9AF3 BlockSize : 2048 LastBlock : 7 BlockSize : 2048 LastBlock : 1E9539 PlatformBdsBootFail Boot Failed. EFI DVD/CDROM Memory Previous Current Next Type Pages Pages Pages ====== ======== ======== ======== 0A 00000004 00000002 00000004 09 00000008 00000002 00000008 00 00000004 00000000 00000004 06 00000065 00000051 00000065 05 00000030 0000002D 00000030 03 00000180 00000170 00000180 04 00000F00 000007C2 00000F00 Booting EFI Internal Shell InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 78064A8 Loading driver at 0x00006B0E000 EntryPoint=0x00006B0E240 Shell.efi -------------------------------------------------------------- I want to try creating CBFS support in tianocore by writing a UEFI DXE Driver. Since the ROM's address will be known, raw access of memory corresponding to the ROM could be done and parsing functions provided. For CBFS located elsewhere a base address could be provided as an argument. Existing cbfstool's code could be used. I would like to know if this is a correct approach. Thanking You! Ganesh

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Re: [coreboot] coreboot lenovo x230
by Peter Stuge 15 Mar '15

15 Mar '15

Mario Goljak wrote: > I've been following coreboots official guide > http://www.coreboot.org/Board:lenovo/x230 but I'm unable to read bios chip > content with the buspirate and flashrom. I've connected it according to > this datasheet > http://www.macronix.com/Lists/DataSheet/Attachments/1740/MX25L3206E,%203V,%… > but I'm not exactly sure how to connect 3.3V power lines from another > computer. Not at all, ideally. Never apply a voltage to a voltage rail without knowing that you are actually following the required power sequence for the system. Sometimes this is documented in the schematic, other times not, then you can't know. See if you can let the board power the voltage rail. Look for flash chip accesses if you only connect the power but do not power on the system. Macronix flash is very sensitive to signal integrity. Keep your wires as short as possible, max 2-3 cm. //Peter

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Hello coreboot
by Łukasz Dmitrowski 14 Mar '15

14 Mar '15

Hello coreboot, My name is Lukasz and I am a Computer Science student at West Pomeranian University of Technology in Szczecin. Main area of my interests are embedded systems and for me coreboot is the most interesting organization in GSoC 2015. Thats why I am here. I have experience with low level programming and good knowledge of C and C++. Often I use Arduino, Raspberry Pi and BeagleBone Black for fast prototyping my ideas. I have also teamwork experience gained while working on the embedded systems commercial project for automotive industry. I am interested in participating in GSoC 2015 through realization of one of the coreboot projects as I find it as a good start for diving into computer firmware. For now I am getting familiar with coreboot and trying to build it and run it in QEMU. More detailed information I will give you through my proposal, but if you want to ask me some questions now please feel free to do that. I will be also often available on #coreboot IRC channel. I have one question: Are project ideas on coreboot wiki prioritized or acceptance depends only on student attitude, arrangements(build coreboot + send patch) and quality of proposal? Thank you in advance. Regards, Lukasz Dmitrowski

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coreboot lenovo x230
by Mario Goljak 14 Mar '15

14 Mar '15

I've been following coreboots official guide http://www.coreboot.org/Board:lenovo/x230 but I'm unable to read bios chip content with the buspirate and flashrom. I've connected it according to this datasheet http://www.macronix.com/Lists/DataSheet/Attachments/1740/MX25L3206E,%203V,%… but I'm not exactly sure how to connect 3.3V power lines from another computer. can somebody please give me some guidelines. thanks in advance.

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Re: [coreboot] questions about google/samus
by Alexandru Gagniuc 14 Mar '15

14 Mar '15

On Friday, March 13, 2015 12:42:38 AM ron minnich wrote: > On Thu, Mar 12, 2015 at 3:48 PM Paul Menzel < > > paulepanter(a)users.sourceforge.net> wrote: > > As this is an Intel device [1] and I am waiting for an AMD based laptop, > > I’d say no. ;-) > > I'm not sure AMD improves the situation much any more, and in some ways a > non-chromeos laptop has lots of other problems. On your AMD laptop, the EC > will be a binary blob. If you're not worried about that, you should be. > Sadly, I don't think AMD understands what a Chromebook is. > ron

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Re: [coreboot] Re : Re: Re : Re: Re : Re: questions about google/samus
by Peter Stuge 14 Mar '15

14 Mar '15

echelon(a)free.fr wrote: > So we don't have the right to even ask or wonder why is this so secret?.. Everyone has the right to ask and wonder anything in the free world. We are all curious to learn, but there are always better ways to learn, and worse ways. I think the engineering that Google puts into coreboot deserves respect. > Call me a moron but I don't find it justified to keep the memory > initialisation code a "very close secret". That seems to be a matter between you and Intel, unrelated to this thread. //Peter

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Re: [coreboot] questions about google/samus
by Patrick Georgi 14 Mar '15

14 Mar '15

Hi all, I put the mailing list under emergency moderation for a while because things heated up quickly. This wasn't coordinated with anyone, so please direct complaints about that at me. All incoming emails (to this thread = all of them) in that period were rejected with an explanation (I hope these ended up with the authors, we don't use that mechanism very often), and their authors can resend them if they feel that the mails add value while keeping the flames low. There are tons of fun (and some not so fun) stories about interactions with silicon vendors, some of them involving various degrees of binary only modules. But I think they're better told in person over some beverage of choice (eg. at the meet-ups we want to do in summer?) rather than on an impersonal medium like a mailing list - especially because it's such a frustrating issue. Patrick (speaking only for myself)

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Re : Re: Re : Re: Re : Re: questions about google/samus
by echelon＠free.fr 13 Mar '15

13 Mar '15

So we don't have the right to even ask or wonder why is this so secret?.. Call me a moron but I don't find it justified to keep the memory initialisation code a "very close secret". And I will not change my mind until I am presented with real arguments. (And this will never happen because this implies signing an NDA - and I will NEVER sign an NDA with Intel) Florentin ----- Mail d'origine ----- De: Vadim Bendebury <vbendeb(a)chromium.org> À: Florentin Demetrescu <echelon(a)free.fr> Cc: Coreboot <coreboot(a)coreboot.org> Envoyé: Fri, 13 Mar 2015 16:25:38 +0100 (CET) Objet: Re: [coreboot] Re : Re: Re : Re: questions about google/samus Guys, I don't speak for Ron but I don't find his comment (apparently sent in a emailed to a few folks but then made public (sic!)) elitist, it was a matter of fact question. I have been with Chromebook program pretty much from the very beginning, and I can tell you that the public availability of FSP and Coreboot support at Intel could not have been dreamed of even three years ago. Also, it is quite common among the SOC vendors to keep the early initialization and memory initialization code a very close secret. My $.02 (which might become as valuable as EU.02 any time now :) --vb On Fri, Mar 13, 2015 at 5:26 AM, <echelon(a)free.fr> wrote: > Ok Ron, > We all recognise your efforts and don't deny that the question of the binary blobs" is a very complex and "politicaly hot" one.. > But (and I speak here from a STRICTLY personal point of view) it is the fashion you chose to lecture Paul than I found not very nice.. > I sense a trace of elitism in your atitude (like you "GODs" have the exclusive right to acces some secrets and we "mere mortals" have even no right to think about these "things"..) I for one cannot swallow that!.. > Just my 2 (euro-cents) > Florentin > > ----- Mail d'origine ----- > De: ron minnich <rminnich(a)gmail.com> > À: echelon(a)free.fr, Coreboot <coreboot(a)coreboot.org> > Envoyé: Fri, 13 Mar 2015 13:04:36 +0100 (CET) > Objet: Re: [coreboot] Re : Re: questions about google/samus > > On Fri, Mar 13, 2015 at 4:41 AM <echelon(a)free.fr> wrote: > >> Sorry Ron, >> What is his crime? >> Thought crime?.. >> Florentin >> >> > The problem with people making comments like this: > > >> > Sadly, I don’t think Google has understood how much power they have over >> > Intel with their Chromebook and Chromebox success. RAM initialization is >> > for example still a BLOB > > > is that people who don't know what's going on might take Paul's comments > seriously, and the next thing we know we're seeing mistakes like the Purism > laptop. > > It's also not very nice, given the amount of effort that we have made over > the years to get the blobs opened up, for Paul to claim that we "don't > understand how much power we have." Unless you've been involved in these > discussions, you can't possibly understand how difficult they are. > > ron > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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x60 and macbook21 builds fail
by Mono 13 Mar '15

13 Mar '15

is it just me? trying to build coreboot for a X60 motherboard or a macbook21 fails with tons of the following error: src/northbridge/intel/i945/gma.c: In function 'gtt_setup': src/northbridge/intel/i945/gma.c:72:10: error: passing argument 1 of 'write32' makes pointer from integer without a cast [-Werror] write32(mmiobase + GFX_FLSH_CNTL, 0); ^ In file included from src/include/device/pci.h:23:0, from src/northbridge/intel/i945/gma.c:24: src/arch/x86/include/arch/io.h:170:51: note: expected 'volatile void *' but argument is of type 'unsigned int' static inline __attribute__((always_inline)) void write32(volatile void *addr, uint32_t value) ^ src/northbridge/intel/i945/gma.c:74:10: error: passing argument 1 of 'write32' makes pointer from integer without a cast [-Werror] write32(mmiobase + PGETBL_CTL, PGETBL_save); I figured this error occurs since commit bde6d309 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer). I don't know how to fix it though or did I configured any wrong? Any help is much appreciated. greets Mono

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Re: [coreboot] questions about google/samus
by Vadim Bendebury 13 Mar '15

13 Mar '15

Guys, I don't speak for Ron but I don't find his comment (apparently sent in a emailed to a few folks but then made public (sic!)) elitist, it was a matter of fact question. I have been with Chromebook program pretty much from the very beginning, and I can tell you that the public availability of FSP and Coreboot support at Intel could not have been dreamed of even three years ago. Also, it is quite common among the SOC vendors to keep the early initialization and memory initialization code a very close secret. My $.02 (which might become as valuable as EU.02 any time now :) --vb On Fri, Mar 13, 2015 at 5:26 AM, <echelon(a)free.fr> wrote: > Ok Ron, > We all recognise your efforts and don't deny that the question of the binary blobs" is a very complex and "politicaly hot" one.. > But (and I speak here from a STRICTLY personal point of view) it is the fashion you chose to lecture Paul than I found not very nice.. > I sense a trace of elitism in your atitude (like you "GODs" have the exclusive right to acces some secrets and we "mere mortals" have even no right to think about these "things"..) I for one cannot swallow that!.. > Just my 2 (euro-cents) > Florentin > > ----- Mail d'origine ----- > De: ron minnich <rminnich(a)gmail.com> > À: echelon(a)free.fr, Coreboot <coreboot(a)coreboot.org> > Envoyé: Fri, 13 Mar 2015 13:04:36 +0100 (CET) > Objet: Re: [coreboot] Re : Re: questions about google/samus > > On Fri, Mar 13, 2015 at 4:41 AM <echelon(a)free.fr> wrote: > >> Sorry Ron, >> What is his crime? >> Thought crime?.. >> Florentin >> >> > The problem with people making comments like this: > > >> > Sadly, I don’t think Google has understood how much power they have over >> > Intel with their Chromebook and Chromebox success. RAM initialization is >> > for example still a BLOB > > > is that people who don't know what's going on might take Paul's comments > seriously, and the next thing we know we're seeing mistakes like the Purism > laptop. > > It's also not very nice, given the amount of effort that we have made over > the years to get the blobs opened up, for Paul to claim that we "don't > understand how much power we have." Unless you've been involved in these > discussions, you can't possibly understand how difficult they are. > > ron > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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coreboot March 2015