February 2015 - coreboot - mail.coreboot.org

by A. Veek

1 year, 3 months

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Re: [coreboot] No VGA output on e350m1 after flashing. what to do?

by Reiner Luett

Hi! On 30.06.2013 19:28, Christian Weinz wrote: > Maybe I didn't include the VGA option in the make menuconfig process. > How can I solve this problem? You need to add the VGA Option ROM (VGA BIOS -> Add VGA BIOS image). I've extracted it from the UEFI, but you also could use these: http://www.coreboot.org/index.php?title=ASRock_E350M1&oldid=11114 at the end of the page or you also may be able to use the default AMD fam14 (Persimmon) vbios. You will need to agree to the click through: http://wwwd.amd.com/support/vbioslic.nsf/userverify?openform http://www.coreboot.org/AMD_DB-FT1_PERSIMMON It's a pity, that bios_extract didn't work for now. You could use the AMI Aptio EFI MMTool with wine: http://win-lite.de/benutzer/fernando/BIOS-Tools/AMI_Aptio_EFI_MMTool_v4.50.… You need to extract OntarioEFIVbios with PCI ID 1002,9802 as Option ROM. Regards, Reiner --

2 years, 6 months

5
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memtest86 reading 0k memory

by Timothy Pearson

All, I have a board here that loads memtest86 but won't actually test memory. This is the output: Memtest86+ v2.11 AMD K10 CPU @ 2312 MHz L1 Cache: 64K 35028 MB/s L2 Cache: 512K 6963 MB/s L3 Cache: 2048K 6052 MB/s Memory : 0K |------------------------------------------------- Chipset : 0K LinuxBIOS I'm guessing memtest86 doesn't understand coreboot's memory tables/structure, but I have no idea why that would be. The e820 map is valid: e820: BIOS-provided physical RAM map: BIOS-e820: [mem 0x0000000000000000-0x000000000009fbff] usable BIOS-e820: [mem 0x000000000009fc00-0x000000000009ffff] reserved BIOS-e820: [mem 0x00000000000f0000-0x00000000000fffff] reserved BIOS-e820: [mem 0x0000000000100000-0x000000003ffacfff] usable BIOS-e820: [mem 0x000000003ffad000-0x000000003fffffff] reserved BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved Any ideas? Other than this one irritating glitch coreboot is working perfectly on this board. Thanks! -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com

4 years, 11 months

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New flashrom logo

by Stefan Tauner

Hello, we have used two logos in the past for flashrom. The one most are familiar with is actually a generic icon stemming from coreboot's "Related Tools" section, i.e.: http://www.coreboot.org/images/a/ae/Chip_tools.png This is not only set up as the "Mediawiki" icon on flashrom.org but is also used on our Twitter account and other sites like openhub (https://www.openhub.net/p/flashrom) The second logo was specifically designed for this purpose and was used at various occasions in presentation slides and on marketing materials (e.g. posters). Namely http://3.bp.blogspot.com/_PTt3TWYKjnQ/TI_oZ3cqvaI/AAAAAAAAALY/eLvM6K16Glw/s… (the one described as "Different style of bolt" on http://kmacphail.blogspot.de/2010/09/flashrom-logos.html) I think that one is way lesser known since even I was not really aware about the fact that it kind of the "official" logo at the moment. I am not too happy with either. The hammer logo has grown dear to me... the hammer perfectly symbolizes the force we have to exert to get some systems to work and the logo as such is very recognizable. But... I only have it in very low quality... is there a better source for it? It also does not represent our generally gentle and cautious approach when dealing with hardware and our focus on stability. The DIP logo on the other hand is available in SVG (at least Carl-Daniel has it AFAIK), but it looks a bit inanimate. The major problems I have with it are that it is not even nearly rectangular and it is very complex. There is the text with the lightning bolt replacing the h character and the DIP32 chip. Both is ok for posters and other big displays but sucks for other uses where simple, rectangular icons are required. I have spent the last weekend with playing around with Blender and its freestyle renderer that is able to output SVG directly. I have managed to render a 3D model of a SOIC8 chip that way as a base for a possible new logo. It required some cleanup afterwards but it looks way better than everything I could draw by hand ;) I have made two logos that I think are worth sharing. They are quite similar and the only major difference is the orientation of the chip... I have created 3 versions of each: one fully colored, one with outlines only and a two-colored simple version (e.g. for PCB silkscreens). I have attached the Inkscape SVGs as well as 96 pixel-wide PNG exports. I have not decided on an appropriate license... probably something similar to how the coreboot hare is licensed. What do you think about my suggestions and the whole matter? I would love to see proposals for alternatives as well! -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

5 years

6
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Automated test system: Nominations wanted

by Carl-Daniel Hailfinger

Hi, I am currently planning to set up a test system with 5 (later up to 10) machines boot testing each new coreboot commit. This test system will be serviced (i.e. recovery from bricking) Mo-Fr during CET/CEST office hours. Current goals for every commit: - Check if coreboot + SeaBIOS are able to boot Linux to a point where network is up and running Current goals for every work day: - Check if screen, keyboard and touchpad/mouse work - Check if USB works and has the expected transfer speed (i.e. if USB High and Super Speed both work) Future goals for every work day: - Run memtest86+ (short run) - Run GRUB2 and boot Linux - Check if USB works (see above) Once any test running once per work day can be automated with reasonable effort (i.e. not requiring robots or human interaction), it can be moved to a per-commit goal. The selection of target systems should include: 1. at least one x86 laptop without an active ME (present but inactive would be OK) 2. at least one x86 laptop which can boot x86-blob-free (except microcode) 3. at least one x86 board or laptop which needs neither blobs (except microcode) nor ME 4. at least one x86 board with reasonable (past or present) business market penetration 5. if the first two laptops use the same CPU vendor, a board using a different x86 CPU vendor 1+2 are designed to partially remove the potential for nasty surprises, 3 should remove nasty surprises completely, 4 is the one I need to show that the test system is actually relevant for our goals, 5 should give us better coverage outside the most common systems used by coreboot developers. Please nominate machines (e.g. "Thinkpad T60 with Intel graphics") and tell me to which category they belong. If a system fits into multiple categories, please specify that as well. I will try to consolidate the recommendations and buy those machines. Once the system is up and running (hopefully in May), I will add more machines suggested by the community as time permits. The time window for suggestions will close at the end of February. Fire away! Regards, Carl-Daniel

5 years

7
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Re: [coreboot] Plans for upcoming Broadwell Thinkpads

by Zaolin

Hi, let's say goodbye to all Intel notebooks produced by OEM's which are not Google ( Chromebooks ). Maybe the haswell/broadwell notebooks of Lenovo without U/Y processor can be used ( Thinkpad tXX xXX ). It depends if they are supporting Intel Boot Guard on the southbridge... Regards Zaolin > On 02/06/2015 06:29 AM, Zaolin wrote: > > Hi, > > > > new thinkpad's can't be used anymore for coreboot. Especially the U and > > Y Intel CPU Series. > > They come with Intel Boot Guard and you are won't be able to boot > > anything which is unsigned and > > not approved by OEM. This means the OEM are fusing SHA256 public key > > hashes into the southbridge. > > > > For more details take a look at Intel Boot Guard architecture. It could > > be also confirmed by Secunet AG and Google. > > > > Regards Zaolin > > That's scary to say the least. No more Thinkpads for us... >

5 years

2
1
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Re: [coreboot] x201t + windows7

by Zaolin

Hi, have seen the same problem on all thinkpad product types supported by coreboot. Maybe someone should get a Windows Developer Edition and solve this bug ;) . Regards Zaolin > Hi, > > I tried today a windows 7 installation usb stick and a cd disc. > Both 32bit and 64bit. > > Both Windows' stopping at disk.sys and the hdd led on. > 32bit: sometimes windows boots, most time not. > > Any ideas, what's wrong? > > Best, > lynxis > >

5 years

3
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Re: [coreboot] Unifying IO accessor macros

by Julius Werner

Okay, the doodle has been up for a while now and it seems that write32(address, value) is preferred by a clear majority of people. I've prepared a set of patches starting at https://chromium-review.googlesource.com/#/c/254862 to enact that change in the Chromium repo. As mentioned before, I think due to the fact that there's much more active ARM(64) development going on in Chromium right now I should only land it there for the time being and wait until it naturally bubbles up to mainline coreboot as part of the current upstreaming effort... trying to apply it to both trees at once would just require a lot of pointless conflict resolution effort to down the road.

5 years

1
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Re: [coreboot] Building ARM toolchain fails with `cc1: fatal error: .vis: No such file or directory`

by Paul Menzel

Am Donnerstag, den 26.02.2015, 22:15 +0100 schrieb Patrick Georgi: > 2015-02-26 21:56 GMT+01:00 Aaron Durbin <adurbin(a)chromium.org>: > > I reproduced the error. I was trying to figure out how to debug it. I > > entered into the util/crossgcc/build-armv7-a-eabi-gcc directory and > > typed make. Everything worked... I'm trying again. I'm not really sure > > why one way would fail and the other not. > > Interesting. > > Paul, could you try executing buildgcc manually (not through a make rule)? Just for the archive, running `./buildgcc -G -p armv7a-eabi` worked. > If that works, there's some make environment stuff that survives and > breaks things. Thank you for providing a patch [1]! I’ll test that tomorrow. Thanks, Paul [1] http://review.coreboot.org/8545

5 years

1
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New Defects reported by Coverity Scan for coreboot

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 3 new defect(s) introduced to coreboot found with Coverity Scan. 10 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 3 of 3 defect(s) ** CID 1271711: (DEADCODE) /src/include/device/hypertransport_def.h: 25 in offset_unit_id() /src/include/device/hypertransport_def.h: 25 in offset_unit_id() ________________________________________________________________________________________________________ *** CID 1271711: (DEADCODE) /src/include/device/hypertransport_def.h: 25 in offset_unit_id() 19 #define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */ 20 21 22 static inline bool offset_unit_id(bool is_sb_ht_chain) 23 { 24 bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); >>> CID 1271711: (DEADCODE) >>> Execution cannot reach the expression "0" inside this statement: "return need_offset && (0 ||...". 25 return need_offset && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY || is_sb_ht_chain); 26 } 27 /src/include/device/hypertransport_def.h: 25 in offset_unit_id() 19 #define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */ 20 21 22 static inline bool offset_unit_id(bool is_sb_ht_chain) 23 { 24 bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); >>> CID 1271711: (DEADCODE) >>> Execution cannot reach the expression "1" inside this statement: "return need_offset && (1 ||...". 25 return need_offset && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY || is_sb_ht_chain); 26 } 27 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/1016?tab=overview To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://scan.coverity.com/subscriptions/edit?email=coreboot%40coreboot.org&… .

5 years

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coreboot February 2015