coreboot April 2013

coreboot@coreboot.org

42 participants
125 discussions

Re: [coreboot] Summer project
by Stefan Tauner 15 Apr '13

15 Apr '13

Hello Martijn, On Sun, 14 Apr 2013 22:23:54 +0200 Martijn Bastiaan <martijn.bastiaan(a)gmail.com> wrote: > For a while now, I've been interested in the development of Coreboot. > I really like the idea of an open-source firmware, which could > possibly replace all the current propriertary ones. At the same time > I'm looking for a project I can make a (ever so small) contribution > to. I hope to do that this summer vacation, in order to expand my > current skillset. You have not mentioned it at all although it might suit you very well: http://www.coreboot.org/GSoC > That last sentence implies why I'm writing to this mailing list > instead of starting right away: I feel like I (currently) lack the > necessary skills to make a meaningful contribution, or to understand > the codebase at all. I would however like to make an effort to change > that situation, but I don't know where to start. Let me start by > introducting myself so you can decide whether I'm even remotely suited > :-). Anyone putting some effort into learning some basics can help in one way or another. This is true for any (FOSS) project IMHO. The main question is usually if the open tasks that are interesting to you can be solved by you. > AmCAT allowed me to develop my Python skills to a point > where I can call myself experienced. I have no significant experience > writing in C, apart from the operating systems course[3] I took and > passed last term. Understanding and writing C is naturally one of the most important skills when working on the core parts of coreboot. But OTOH this means that one is forced to learn that quickly when trying to solve related problems. > I would love to hear your advice on the matter. What literature do you > recommend? Or would I be better suited for another project maybe? I found my lack of x86 knowledge way more challenging than anything else. The hardware in use today evolved over a very long period of time and much of this history including numerous tiny, awkward details are the reason for how things (have to) work in coreboot. Take a look at these links to understand what I mean with "challenging" :) http://www.coreboot.org/Datasheets#Intel http://lennartb.home.xs4all.nl/coreboot/coreboot.html -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Trac reminder: list of new ticket(s)
by coreboot tracker 15 Apr '13

15 Apr '13

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[i915] Screen corruptions
by Denis 'GNUtoo' Carikli 15 Apr '13

15 Apr '13

Hi, I'm still working on replacing the i915 option rom. The current code is here: http://review.coreboot.org/#/c/2998/ At the time of writing the Patch Set is the 5th. The status is the following: * I can set the screen color in coreboot. * During the boot, the screen is corrupted multiples times: -> the first time it is corrupted here: src/southbridge/intel/i82801gx/smi.c: void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { /* The GDT or coreboot table is going to live here. But a long time * after we relocated the GNVS, so this is not troublesome. */ *(u32 *)0x500 = (u32)gnvs; *(u32 *)0x504 = (u32)tcg; *(u32 *)0x508 = (u32)smi1; outb(0xea, 0xb2); } more precisely, before the outb it's totally red(an arbitrary color I chose in order to distinguish it from corruptions), and after there is a line in the middle of the screen that is not red. That function is called by new_high_table_pointer = write_acpi_tables(high_table_pointer) in src/mainboard/lenovo/x60/acpi_tables.c which is called by lb_mem = write_tables(); in hardwaremain(). acpi_tables.c has a strange comment: /* Fix up global NVS region for SMI handler. The GNVS region lives * in the (high) table area. The low memory map looks like this: [...] * 0x000a0000 - 0x000bffff VGA memory * 0x000c0000 - 0x000cffff VGA option rom [...] Maybe it's related? Then the next corruptions happen in SeaBIOS, I didn't investigate them yet... Denis.

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Summer project
by Martijn Bastiaan 14 Apr '13

14 Apr '13

Hi Coreboot developers, For a while now, I've been interested in the development of Coreboot. I really like the idea of an open-source firmware, which could possibly replace all the current propriertary ones. At the same time I'm looking for a project I can make a (ever so small) contribution to. I hope to do that this summer vacation, in order to expand my current skillset. That last sentence implies why I'm writing to this mailing list instead of starting right away: I feel like I (currently) lack the necessary skills to make a meaningful contribution, or to understand the codebase at all. I would however like to make an effort to change that situation, but I don't know where to start. Let me start by introducting myself so you can decide whether I'm even remotely suited :-). I'm currently attending the University of Twente[1]. I'm in my second year, and I hope to gain my bachelor's degree in computer science there in the not too distant future. At the same time I collaborate with Dr. Wouter van Atteveldt (boss, collegue, friend) and VU University Amsterdam to create AmCAT[2], a toolkit for document analysis. AmCAT allowed me to develop my Python skills to a point where I can call myself experienced. I have no significant experience writing in C, apart from the operating systems course[3] I took and passed last term. (Speaking of which: that's the course which motivated me to write to you.) I would love to hear your advice on the matter. What literature do you recommend? Or would I be better suited for another project maybe? Kind regards, Martijn Bastiaan [1] http://www.utwente.nl/en/ [2] https://code.google.com/p/amcat/ [3] http://wwwhome.ewi.utwente.nl/~pieter/OS/

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AMD SB800 AHCI: How to enable Staggered Spin-up?
by Paul Menzel 12 Apr '13

12 Apr '13

Dear coreboot folks, investigating, why GRUB is not able to find my SATA drive when the SATA controller is in AHCI mode [1], Vladimir pointed out that the controller does not advertise support of staggered spin-up as described in section 10.10 of the AHCI specification [2]. Looking at the SeaBIOS serial log with the debug level set to 8, the flags are printed as follows. AHCI: cap 0xf332ff05, ports_impl 0x3f With the following SeaBIOS code $ nl -ba src/ahci.h […] 97 /* global controller registers */ 98 #define HOST_CAP 0x00 /* host capabilities */ […] 109 /* HOST_CAP bits */ 110 #define HOST_CAP_SSC (1 << 14) /* Slumber capable */ 111 #define HOST_CAP_AHCI (1 << 18) /* AHCI only */ 112 #define HOST_CAP_CLO (1 << 24) /* Command List Override support */ 113 #define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */ […] $ nl -ba src/ahci.c […] 601 ctrl->caps = ahci_ctrl_readl(ctrl, HOST_CAP); 602 ctrl->ports = ahci_ctrl_readl(ctrl, HOST_PORTS_IMPL); 603 dprintf(2, "AHCI: cap 0x%x, ports_impl 0x%x\n", 604 ctrl->caps, ctrl->ports); […] this means, that for `HOST_CAP_SSS` we have to look at the 7th digit from the right of the hex number 0xf332ff05, which is 3, which is in 0011b, and now at the fourth digit from the right which is 0. So this is disabled. (SeaBIOS does not seem to care about the flag though.) Reading the code in `src/vendorcode/amd/cimx/sb800/SATA.c` [3] I do not find where this bit might be set. So any idea, why the CIMx code does not allow to enable staggered spin-up? Are there known problems with the hardware or is it just not implemented in CIMx yet and should simply be added? Thanks, Paul [1] http://lists.gnu.org/archive/html/grub-devel/2013-04/msg00058.html [2] http://www.intel.com/content/www/us/en/io/serial-ata/serial-ata-ahci-spec-r… [3] http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/vendorcode/am…

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coreboot project analysis request
by Антон Кочков 12 Apr '13

12 Apr '13

Good day! As I did not get a reply to my message from April 3rd I am trying it again. Is it possible to add the coreboot project https://www.coreboot.org to your free analysis of FOSS projects? As an alternative to the BIOS and UEFI, coreboot and its payloads need and want to be as secure as possible to also outdo UEFI in the security aspect. So code analysis to find out any issues would help coreboot very much. Here is the code git clone http://review.coreboot.org/p/coreboot.git Under the directory `payloads/` there are some programs which are started after coreboot has finished. Under the directory `util/` there are several utilities needed for image creation or for board porting. As a build system, a customized Kconfig is used and there is also the build tool named abuild.. If you have any question, please do not hesitate to ask us. Either on our mailing list http://www.coreboot.org/Mailinglist or myself. The coreboot project and I hope, you are going to help us and are looking forward to what you are going to find. Best regards, Anton Kochkov. PS: If you know any students interested in low level stuff please tell them, that coreboot is participating in Google Summer of Code 2013 http://www.coreboot.org/GSoC .

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Re: [coreboot] coreboot: make crossgcc - Failed to download acpica-unix-20121114.tar.gz.
by Björn Busse 11 Apr '13

11 Apr '13

It could be that the link to the download needs to be updated. https://acpica.org/sites/acpica/files/acpica-unix-20121114.tar.gz works for me. You can manually download it and place it in util/crossgcc/tarballs, 'make crossgcc' should then pick it up. On Thu, Apr 11, 2013 at 11:18:43AM +0530, Pradish M P, ERS, HCLTech wrote: > Dear coreboot folks > > i downloaded the latest source code form coreboot.org , when i tried to build the cross compiler > using the command make crossgcc > > it gives the following error > > root@test-VirtualBox:~/coreboot# make crossgcc > Warning: no suitable GCC for armv7. > Welcome to the coreboot cross toolchain builder v1.20 (December 4th, 2012) > > Will skip GDB ... ok > Downloading tar balls ... > * gmp-5.0.5.tar.bz2 (downloading) > * mpfr-3.1.1.tar.bz2 (downloading) > * mpc-1.0.1.tar.gz (downloading) > * libelf-0.8.13.tar.gz (downloading) > * gcc-4.7.2.tar.bz2 (downloading) > * binutils-2.23.tar.gz (downloading) > * acpica-unix-20121114.tar.gz (downloading) > Failed to download acpica-unix-20121114.tar.gz. > make[1]: *** [build-without-gdb] Error 1 > make: *** [crossgcc] Error 2 > > can anyone guide me how to fix. > > regards > pradish > > ________________________________________ > > > ::DISCLAIMER:: > ---------------------------------------------------------------------------------------------------------------------------------------------------- > > The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. > E-mail transmission is not guaranteed to be secure or error-free as information could be intercepted, corrupted, > lost, destroyed, arrive late or incomplete, or may contain viruses in transmission. The e mail and its contents > (with or without referred errors) shall therefore not attach any liability on the originator or HCL or its affiliates. > Views or opinions, if any, presented in this email are solely those of the author and may not necessarily reflect the > views or opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification, > distribution and / or publication of this message without the prior written consent of authorized representative of > HCL is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately. > Before opening any email and/or attachments, please check them for viruses and other defects. > > ---------------------------------------------------------------------------------------------------------------------------------------------------- > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot --

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OT: GSoC project idea: Replacement of Video BIOS for native graphics initialization in coreboot
by Paul Menzel 11 Apr '13

11 Apr '13

(Sent to dri-devel and intel-gfx lists.) Dear Linux graphics folks, coreboot has been accepted to participate in Google Summer of Code 2013 [1]. coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. Please find more information about GSoC in our Wiki [3], where some project ideas are already listed [4]. But you can of course propose your own ideas. A nice project for you graphics folks might be to work on native graphics initialization to replace the Video BIOS [5][6]. For example on the Chromebook Pixel (Google Link) the Video BIOS takes 1.5 s and the native graphics initialization just 200 ms [7]. So if you are interested, please join the coreboot list and the IRC channel, ask questions and submit your proposal. We are looking forward to it! Thanks and happy coding, Paul PS: If you know somebody interested in this, please spread the word. [1] http://blogs.coreboot.org/blog/2013/03/30/google-summer-of-code-2013/ [2] http://www.coreboot.org/ [3] http://www.coreboot.org/GSoC [4] http://www.coreboot.org/Project_Ideas [5] https://docs.google.com/document/d/1g8FMob25VZYxbWri2iFB8YiSL8gwF9vKJH3HGxr… [6] http://www.coreboot.org/pipermail/coreboot/2013-March/075512.html [7] http://review.coreboot.org/#/c/2531/5//COMMIT_MSG

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Re: [coreboot] coreboot: make crossgcc - Failed to download acpica-unix-20121114.tar.gz.
by Idwer Vollering 11 Apr '13

11 Apr '13

2013/4/11 Pradish M P, ERS, HCLTech <pradishmp(a)hcl.com>: > Dear coreboot folks > > i downloaded the latest source code form coreboot.org , when i tried to build the cross compiler > using the command make crossgcc > > it gives the following error > > root@test-VirtualBox:~/coreboot# make crossgcc > Warning: no suitable GCC for armv7. > Welcome to the coreboot cross toolchain builder v1.20 (December 4th, 2012) > > Will skip GDB ... ok > Downloading tar balls ... > * gmp-5.0.5.tar.bz2 (downloading) > * mpfr-3.1.1.tar.bz2 (downloading) > * mpc-1.0.1.tar.gz (downloading) > * libelf-0.8.13.tar.gz (downloading) > * gcc-4.7.2.tar.bz2 (downloading) > * binutils-2.23.tar.gz (downloading) > * acpica-unix-20121114.tar.gz (downloading) > Failed to download acpica-unix-20121114.tar.gz. > make[1]: *** [build-without-gdb] Error 1 > make: *** [crossgcc] Error 2 > > can anyone guide me how to fix. This could have been a certificate (SSL) error, network error (host not found) or HTTP 404 (file not found). Can you show the content of crossgcc-build.log, found (somewhere) in the acpica-unix-20121114/ dir? I'll try to reproduce this. > > regards > pradish > > ________________________________________ > > > ::DISCLAIMER:: > ---------------------------------------------------------------------------------------------------------------------------------------------------- > > The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. > E-mail transmission is not guaranteed to be secure or error-free as information could be intercepted, corrupted, > lost, destroyed, arrive late or incomplete, or may contain viruses in transmission. The e mail and its contents > (with or without referred errors) shall therefore not attach any liability on the originator or HCL or its affiliates. > Views or opinions, if any, presented in this email are solely those of the author and may not necessarily reflect the > views or opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification, > distribution and / or publication of this message without the prior written consent of authorized representative of > HCL is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately. > Before opening any email and/or attachments, please check them for viruses and other defects. > > ---------------------------------------------------------------------------------------------------------------------------------------------------- > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] coreboot: make crossgcc - Failed to download acpica-unix-20121114.tar.gz.
by David Hendricks 11 Apr '13

11 Apr '13

My first intuition is to "make clean" and "rm -f .xcompile", then attempt to "make" again. You should not need to make crossgcc manually. On Wed, Apr 10, 2013 at 10:48 PM, Pradish M P, ERS, HCLTech < pradishmp(a)hcl.com> wrote: > Dear coreboot folks > > i downloaded the latest source code form coreboot.org , when i tried to > build the cross compiler > using the command make crossgcc > > it gives the following error > > root@test-VirtualBox:~/coreboot# make crossgcc > Warning: no suitable GCC for armv7. > Welcome to the coreboot cross toolchain builder v1.20 (December 4th, 2012) > > Will skip GDB ... ok > Downloading tar balls ... > * gmp-5.0.5.tar.bz2 (downloading) > * mpfr-3.1.1.tar.bz2 (downloading) > * mpc-1.0.1.tar.gz (downloading) > * libelf-0.8.13.tar.gz (downloading) > * gcc-4.7.2.tar.bz2 (downloading) > * binutils-2.23.tar.gz (downloading) > * acpica-unix-20121114.tar.gz (downloading) > Failed to download acpica-unix-20121114.tar.gz. > make[1]: *** [build-without-gdb] Error 1 > make: *** [crossgcc] Error 2 > > can anyone guide me how to fix. > > regards > pradish > > ________________________________________ > > > ::DISCLAIMER:: > > ---------------------------------------------------------------------------------------------------------------------------------------------------- > > The contents of this e-mail and any attachment(s) are confidential and > intended for the named recipient(s) only. > E-mail transmission is not guaranteed to be secure or error-free as > information could be intercepted, corrupted, > lost, destroyed, arrive late or incomplete, or may contain viruses in > transmission. The e mail and its contents > (with or without referred errors) shall therefore not attach any liability > on the originator or HCL or its affiliates. > Views or opinions, if any, presented in this email are solely those of the > author and may not necessarily reflect the > views or opinions of HCL or its affiliates. Any form of reproduction, > dissemination, copying, disclosure, modification, > distribution and / or publication of this message without the prior > written consent of authorized representative of > HCL is strictly prohibited. If you have received this email in error > please delete it and notify the sender immediately. > Before opening any email and/or attachments, please check them for viruses > and other defects. > > > ---------------------------------------------------------------------------------------------------------------------------------------------------- > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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coreboot April 2013