coreboot April 2013

coreboot@coreboot.org

42 participants
125 discussions

coreboot-libpayload 'size_t' conflicting type error
by Pradish M P, ERS, HCLTech 09 Apr '13

09 Apr '13

Dear Coreboot Folks I see that this issues is still not resolved, can you guys give me some steps so that I can do those changes in my local copy And build libpayload. Regards Pradish -----Original Message----- From: Pradish M P, ERS, HCLTech Sent: Monday, April 01, 2013 1:22 PM To: Paul Menzel; coreboot(a)coreboot.org Subject: RE: [coreboot] coreboot-libpayload 'size_t' conflicting type error Dear Paul and Coreboot Folks i have followed all the steps you have mention in this mail and still i am getting the same error. bpci/libpci.libpci.o In file included from include/libpayload.h:54:0, from libpci/libpci.c:30: include/x86/arch/types.h:56:23: error: conflicting types for 'size_t' /usr/lib/gcc/i686-linux-gnu/4.6.1/include/stddef.h:212:23: note: previous declaration of 'size_t' was here make: *** [build/libpci/libpci.libpci.o] Error 1 regards pradish _______________________________________ From: coreboot-bounces(a)coreboot.org [coreboot-bounces(a)coreboot.org] On Behalf Of Paul Menzel [paulepanter(a)users.sourceforge.net] Sent: Wednesday, March 27, 2013 3:02 PM To: coreboot(a)coreboot.org Subject: Re: [coreboot] coreboot-libpayload 'size_t' conflicting type error Dear Pradish, in my last message I asked you *not* to send any HTML messages! Additionally you did not reply to the list. Please use a decent mail client which has the option to reply to the list. (As a workaround you might use the reply to all feature. Am Mittwoch, den 27.03.2013, 13:08 +0530 schrieb Pradish MP: [...] > but i get new errors > > pradish@pradish-VirtualBox:~/coreboot/payloads/libpayload$ make > install build/libpayload-config.h build/config.h differ: byte 93, line 4 > CC libpci/libpci.libpci.o > AR build/libpci.a > CC arch/x86/main.libc.o > CC arch/x86/sysinfo.libc.o > CC arch/x86/timer.libc.o > CC arch/x86/coreboot.libc.o > CC arch/x86/util.libc.o > CC arch/x86/exec.libc.o > CC arch/x86/virtual.libc.o > CC arch/x86/string.libc.o > CC arch/x86/multiboot.libc.o > CC crypto/sha1.libc.o > CC libc/malloc.libc.o > CC libc/printf.libc.o > CC libc/console.libc.o > CC libc/string.libc.o > In file included from libc/string.c:35:0: > include/inttypes.h:250:2: error: unknown type name 'intmax_t' > include/inttypes.h:251:2: error: unknown type name 'intmax_t' > include/inttypes.h:255:1: error: unknown type name 'intmax_t' > include/inttypes.h:255:1: warning: parameter names (without types) in > function declaration [enabled by default] > include/inttypes.h:256:1: warning: parameter names (without types) in > function declaration [enabled by default] > include/inttypes.h:257:1: error: unknown type name 'intmax_t' > include/inttypes.h:258:1: error: unknown type name 'uintmax_t' > libc/string.c: In function 'strtoul': > libc/string.c:542:12: error: 'UINT32_MAX' undeclared (first use in > this function) > libc/string.c:542:12: note: each undeclared identifier is reported > only once for each function it appears in > make: *** [build/libc/string.libc.o] Error 1 > > how to resolve this one? Thanks to Stefan Reinauer these errors should be fixed with the following commit. commit c7b6d7db092cfd925f1fb6333e166a54663310e7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 25 15:03:41 2013 -0700 libpayload: Fix type issues There were a number of type issues in libpayload that sneaked in with 903f8e0. - size_t and ssize_t were conflicting with gcc builtins - some stdint types were used in libpayload but not defined in our stdint.h [...] Reviewed-on: http://review.coreboot.org/2903 Please do `git remote update` and `git rebase origin/master` to get the latest revision and everything should be fine. [...] Thanks, Paul ::DISCLAIMER:: ---------------------------------------------------------------------------------------------------------------------------------------------------- The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. E-mail transmission is not guaranteed to be secure or error-free as information could be intercepted, corrupted, lost, destroyed, arrive late or incomplete, or may contain viruses in transmission. The e mail and its contents (with or without referred errors) shall therefore not attach any liability on the originator or HCL or its affiliates. Views or opinions, if any, presented in this email are solely those of the author and may not necessarily reflect the views or opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification, distribution and / or publication of this message without the prior written consent of authorized representative of HCL is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately. Before opening any email and/or attachments, please check them for viruses and other defects. ----------------------------------------------------------------------------------------------------------------------------------------------------

1 0

Reasons for `Boot failed` message?
by Paul Menzel 08 Apr '13

08 Apr '13

Dear coreboot folks, on the ASRock E350M1 I build coreboot (hash 44af3db) with the VGA ROM and GRUB as payload. $ build/cbfstool build/coreboot.rom print coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, offset 0x0 alignment: 64 bytes Name Offset Type Size cmos_layout.bin 0x0 cmos_layout 1776 pci1002,9802.rom 0x740 optionrom 65536 fallback/romstage 0x10780 stage 347052 fallback/coreboot_ram 0x65380 stage 205897 fallback/payload 0x97840 payload 195518 (empty) 0xc7440 null 337698 And now it fails and I only updated the coreboot code revision. […] SMBIOS tables: 275 bytes. Adding CBMEM entry as no. 6 Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 57df Table forward entry ends at 0x00000528. ... aligned to 0x00001000 Writing coreboot table at 0xc7fee000 rom_table_end = 0xc7fee000 ... aligned to 0xc7ff0000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-00000000c7fdffff: RAM 3. 00000000c7fe0000-00000000c7ffffff: CONFIGURATION TABLES 4. 00000000c8000000-00000000dfffffff: RESERVED 5. 00000000f8000000-00000000f8ffffff: RESERVED 6. 0000000100000000-000000021effffff: RAM Wrote coreboot table at: c7fee000, 0x200 bytes, checksum c1b6 coreboot table: 536 bytes. Multiboot Information structure has been written. FREE SPACE 0. c7ff6000 0000a000 GDT 1. c7fe0200 00000200 IRQ TABLE 2. c7fe0400 00001000 SMP TABLE 3. c7fe1400 00001000 ACPI 4. c7fe2400 0000b400 SMBIOS 5. c7fed800 00000800 COREBOOT 6. c7fee000 00008000 CBFS: Looking for 'fallback/payload' starting from 0x0. CBFS: (unmatched file @0x0: cmos_layout.bin) CBFS: (unmatched file @0x740: pci1002,9802.rom) CBFS: (unmatched file @0x10780: fallback/romstage) CBFS: (unmatched file @0x65380: fallback/coreboot_ram) CBFS: Found file (offset=0x97878, len=195518). Loading segment from rom address 0xffc97878 code (compression=1) New segment dstaddr 0x8200 memsize 0xe504 srcaddr 0xffc978cc filesize 0x417d (cleaned up) New segment addr 0x8200 size 0xe504 offset 0xffc978cc filesize 0x417d Loading segment from rom address 0xffc97894 code (compression=1) New segment dstaddr 0x100000 memsize 0x85b64 srcaddr 0xffc9ba49 filesize 0x2b9ed (cleaned up) New segment addr 0x100000 size 0x85b64 offset 0xffc9ba49 filesize 0x2b9ed Loading segment from rom address 0xffc978b0 Entry Point 0x00008200 Loading Segment: addr: 0x0000000000008200 memsz: 0x000000000000e504 filesz: 0x000000000000417d lb: [0x0000000000200000, 0x0000000000370038) Post relocation: addr: 0x0000000000008200 memsz: 0x000000000000e504 filesz: 0x000000000000417d using LZMA [ 0x00008200, 0000f14f, 0x00016704) <- ffc978cc Clearing Segment: addr: 0x000000000000f14f memsz: 0x00000000000075b5 dest 00008200, end 00016704, bouncebuffer c7cfff90 Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000085b64 filesz: 0x000000000002b9ed lb: [0x0000000000200000, 0x0000000000370038) Post relocation: addr: 0x0000000000100000 memsz: 0x0000000000085b64 filesz: 0x000000000002b9ed using LZMA Boot failed Unfortunately I do not understand what is happening above. Could you give me a hint, what went wrong, please? Thanks, Paul coreboot-4.0-3980-g44af3db Fri Apr 5 14:04:48 CEST 2013 starting... BSP Family_Model: 00500f10 cpu_init_detectedx = 00000000 agesawrapper_amdinitmmio passed. agesawrapper_amdinitreset passed. agesawrapper_amdinitearly BSP Family_Model: 00500f10 cpu_init_detectedx = 00000001 agesawrapper_amdinitmmio passed. agesawrapper_amdinitreset passed. agesawrapper_amdinitearly passed. agesawrapper_amdinitpost passed. agesawrapper_amdinitenv passed. Loading image. CBFS: Looking for 'fallback/coreboot_ram' starting from 0x0. CBFS: (unmatched file @0x0: cmos_layout.bin) CBFS: (unmatched file @0x740: pci1002,9802.rom) CBFS: (unmatched file @0x10780: fallback/romstage) CBFS: Found file (offset=0x653b8, len=205897). CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1507384 bytes), entry @ 0x200000 Jumping to image. coreboot-4.0-3980-g44af3db Fri Apr 5 14:04:48 CEST 2013 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 0 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 0 PCI: 00:16.0: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:18.6: enabled 1 PCI: 00:18.7: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 0 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 0 PCI: 00:16.0: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:18.6: enabled 1 PCI: 00:18.7: enabled 1 Mainboard E350M1 Enable. scan_static_bus for Root Device setup_bsp_ramtop, TOP MEM: msr.lo = 0xe0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x1f000000, msr.hi = 0x00000002 setup_uma_memory: uma size 0x18000000, memory start 0xc8000000 CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled CPU_CLUSTER: 0 scanning... AP siblings=1 CPU: APIC: 00 enabled CPU: APIC: 01 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [1022/1510] ops PCI: 00:00.0 [1022/1510] enabled PCI: 00:01.0 [1002/9802] enabled PCI: 00:01.1 [1002/1314] enabled PCI: Static device PCI: 00:04.0 not found, disabling it. sb800_enable() SB800 - Smbus.c - alink_ab_indx - Start. SB800 - Smbus.c - alink_ab_indx - End. PCI: 00:11.0 [1002/4390] enabled sb800_enable() PCI: 00:12.0 [1002/4397] ops PCI: 00:12.0 [1002/4397] enabled sb800_enable() PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled sb800_enable() PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb800_enable() PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled sb800_enable() sm_init(). IOAPIC: Clearing IOAPIC at 0xfec00000 IOAPIC: 24 interrupts IOAPIC: reg 0x00000000 value 0x00000000 0x00010000 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x02 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 PCI: 00:14.0 [1002/4385] enabled sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it. sb800_enable() hda enabled PCI: 00:14.2 [1002/4383] ops PCI: 00:14.2 [1002/4383] enabled sb800_enable() PCI: 00:14.3 [1002/439d] bus ops PCI: 00:14.3 [1002/439d] enabled sb800_enable() PCI: 00:14.4 [1002/4384] bus ops PCI: 00:14.4 [1002/4384] enabled sb800_enable() PCI: 00:14.5 [1002/4399] ops PCI: 00:14.5 [1002/4399] enabled sb800_enable() Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:15.0 subordinate bus PCI Express PCI: 00:15.0 [1002/43a0] enabled sb800_enable() PCI: 00:16.0 [1002/4397] ops PCI: 00:16.0 [1002/4397] disabled sb800_enable() SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. SB800 - Late.c - sb800_callout_entry - Start. SB800 - Late.c - sb800_callout_entry - End. PCI: 00:18.0 [1022/1700] enabled PCI: 00:18.1 [1022/1701] enabled PCI: 00:18.2 [1022/1702] enabled PCI: 00:18.3 [1022/1703] enabled PCI: 00:18.4 [1022/1704] enabled PCI: 00:18.5 [1022/1718] enabled PCI: 00:18.6 [1022/1716] enabled PCI: 00:18.7 [1022/1719] enabled PCI: Left over static devices: PCI: 00:15.1 PCI: 00:15.2 PCI: 00:15.3 PCI: Check your devicetree.cb. scan_static_bus for PCI: 00:14.3 PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a enabled PNP: 002e.b enabled scan_static_bus for PCI: 00:14.3 done do_pci_scan_bridge for PCI: 00:14.4 PCI: pci_scan_bus for bus 01 PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:15.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 PCI: pci_scan_bus returning with max=002 scan_static_bus for Root Device done done found VGA at PCI: 00:01.0 Setting up VGA for PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC: 01 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done Fam14h - domain_read_resources DOMAIN: 0000 read_resources bus 0 link: 0 Fam14h - nb_read_resources PCI: 00:14.0 read_resources bus 0 link: 0 I2C: 00:50 missing read_resources I2C: 00:51 missing read_resources PCI: 00:14.0 read_resources bus 0 link: 0 done SB800 - Lpc.c - lpc_read_resources - Start. SB800 - Lpc.c - lpc_read_resources - End. PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done PCI: 00:14.4 read_resources bus 1 link: 0 PCI: 00:14.4 read_resources bus 1 link: 0 done PCI: 00:15.0 register 10(ffffffff), read-only ignoring it PCI: 00:15.0 register 14(ffffffff), read-only ignoring it PCI: 00:15.0 register 38(ffffffff), read-only ignoring it PCI: 00:15.0 read_resources bus 2 link: 0 PCI: 00:15.0 read_resources bus 2 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base f8000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14 PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 18 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:04.0 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:11.0 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:14.0 child on link 0 I2C: 00:50 I2C: 00:50 I2C: 00:51 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.3 child on link 0 PNP: 002e.0 PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 200 index a0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.6 PNP: 002e.6 resource base 100 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 220 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.7 resource base 300 size 2 align 1 gran 1 limit 7ff flags c0000100 index 62 PNP: 002e.7 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.8 PNP: 002e.9 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:14.4 PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:14.5 PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.0 PCI: 00:16.0 PCI: 00:16.2 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 PCI: 00:18.6 PCI: 00:18.7 DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:01.0 14 * [0x0 - 0xff] io PCI: 00:11.0 20 * [0x400 - 0x40f] io PCI: 00:11.0 10 * [0x410 - 0x417] io PCI: 00:11.0 18 * [0x418 - 0x41f] io PCI: 00:11.0 14 * [0x420 - 0x423] io PCI: 00:11.0 1c * [0x424 - 0x427] io DOMAIN: 0000 compute_resources_io: base: 428 size: 428 align: 8 gran: 0 limit: ffff done DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:01.0 18 * [0x10000000 - 0x1003ffff] mem PCI: 00:01.1 10 * [0x10040000 - 0x10043fff] mem PCI: 00:14.2 10 * [0x10044000 - 0x10047fff] mem PCI: 00:12.0 10 * [0x10048000 - 0x10048fff] mem PCI: 00:13.0 10 * [0x10049000 - 0x10049fff] mem PCI: 00:14.5 10 * [0x1004a000 - 0x1004afff] mem PCI: 00:11.0 24 * [0x1004b000 - 0x1004b3ff] mem PCI: 00:12.2 10 * [0x1004b400 - 0x1004b4ff] mem PCI: 00:13.2 10 * [0x1004b500 - 0x1004b5ff] mem PCI: 00:14.3 a0 * [0x1004b600 - 0x1004b600] mem DOMAIN: 0000 compute_resources_mem: base: 1004b601 size: 1004b601 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 00:01.1 constrain_resources: PCI: 00:11.0 constrain_resources: PCI: 00:12.0 constrain_resources: PCI: 00:12.2 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 00:13.2 constrain_resources: PCI: 00:14.0 constrain_resources: I2C: 00:50 constrain_resources: I2C: 00:51 constrain_resources: PCI: 00:14.2 constrain_resources: PCI: 00:14.3 constrain_resources: PNP: 002e.2 constrain_resources: PNP: 002e.5 constrain_resources: PNP: 002e.a constrain_resources: PNP: 002e.b constrain_resources: PCI: 00:14.4 constrain_resources: PCI: 00:14.5 constrain_resources: PCI: 00:15.0 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 constrain_resources: PCI: 00:18.5 constrain_resources: PCI: 00:18.6 constrain_resources: PCI: 00:18.7 avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit f7ffffff Setting resources... DOMAIN: 0000 allocate_resources_io: base:1000 size:428 align:8 gran:0 limit:ffff Assigned: PCI: 00:01.0 14 * [0x1000 - 0x10ff] io Assigned: PCI: 00:11.0 20 * [0x1400 - 0x140f] io Assigned: PCI: 00:11.0 10 * [0x1410 - 0x1417] io Assigned: PCI: 00:11.0 18 * [0x1418 - 0x141f] io Assigned: PCI: 00:11.0 14 * [0x1420 - 0x1423] io Assigned: PCI: 00:11.0 1c * [0x1424 - 0x1427] io DOMAIN: 0000 allocate_resources_io: next_base: 1428 size: 428 align: 8 gran: 0 done PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:1004b601 align:28 gran:0 limit:f7ffffff Assigned: PCI: 00:01.0 10 * [0xe0000000 - 0xefffffff] prefmem Assigned: PCI: 00:01.0 18 * [0xf0000000 - 0xf003ffff] mem Assigned: PCI: 00:01.1 10 * [0xf0040000 - 0xf0043fff] mem Assigned: PCI: 00:14.2 10 * [0xf0044000 - 0xf0047fff] mem Assigned: PCI: 00:12.0 10 * [0xf0048000 - 0xf0048fff] mem Assigned: PCI: 00:13.0 10 * [0xf0049000 - 0xf0049fff] mem Assigned: PCI: 00:14.5 10 * [0xf004a000 - 0xf004afff] mem Assigned: PCI: 00:11.0 24 * [0xf004b000 - 0xf004b3ff] mem Assigned: PCI: 00:12.2 10 * [0xf004b400 - 0xf004b4ff] mem Assigned: PCI: 00:13.2 10 * [0xf004b500 - 0xf004b5ff] mem Assigned: PCI: 00:14.3 a0 * [0xf004b600 - 0xf004b600] mem DOMAIN: 0000 allocate_resources_mem: next_base: f004b601 size: 1004b601 align: 28 gran: 0 done PCI: 00:14.4 allocate_resources_prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:14.4 allocate_resources_prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:14.4 allocate_resources_mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:14.4 allocate_resources_mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 Fam14h - domain_set_resources amsr - incoming dev = 0027a960 adsr: (before) basek = 0, limitk = 21effffff. adsr: (after) basek = 0, limitk = 87bfff, sizek = 87c000. adsr - 0xa0000 to 0xbffff resource. adsr: mmio_basek=00380000, basek=00000300, limitk=0087bfff split: 128K table at =c7fe0000 0: mmio_basek=00380000, basek=00400000, limitk=0087bfff adsr - mmio_basek = 380000. adsr - high_tables_size = 20000. DOMAIN: 0000 assign_resources, bus 0 link: 0 Fam14h - nb_set_resources Fam14h - create_vga_resource Fam14h - set_resource PCI: 00:00.0 c0010058 <- [0x00f8000000 - 0x00f8ffffff] size 0x01000000 gran 0x00 mem <mmconfig> PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:01.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 18 <- [0x00f0000000 - 0x00f003ffff] size 0x00040000 gran 0x12 mem PCI: 00:01.1 10 <- [0x00f0040000 - 0x00f0043fff] size 0x00004000 gran 0x0e mem PCI: 00:11.0 10 <- [0x0000001410 - 0x0000001417] size 0x00000008 gran 0x03 io PCI: 00:11.0 14 <- [0x0000001420 - 0x0000001423] size 0x00000004 gran 0x02 io PCI: 00:11.0 18 <- [0x0000001418 - 0x000000141f] size 0x00000008 gran 0x03 io PCI: 00:11.0 1c <- [0x0000001424 - 0x0000001427] size 0x00000004 gran 0x02 io PCI: 00:11.0 20 <- [0x0000001400 - 0x000000140f] size 0x00000010 gran 0x04 io PCI: 00:11.0 24 <- [0x00f004b000 - 0x00f004b3ff] size 0x00000400 gran 0x0a mem PCI: 00:12.0 10 <- [0x00f0048000 - 0x00f0048fff] size 0x00001000 gran 0x0c mem PCI: 00:12.2 10 <- [0x00f004b400 - 0x00f004b4ff] size 0x00000100 gran 0x08 mem PCI: 00:13.0 10 <- [0x00f0049000 - 0x00f0049fff] size 0x00001000 gran 0x0c mem PCI: 00:13.2 10 <- [0x00f004b500 - 0x00f004b5ff] size 0x00000100 gran 0x08 mem PCI: 00:14.2 10 <- [0x00f0044000 - 0x00f0047fff] size 0x00004000 gran 0x0e mem64 SB800 - Lpc.c - lpc_set_resources - Start. PCI: 00:14.3 a0 <- [0x00f004b602 - 0x00f004b602] size 0x00000001 gran 0x00 mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq PCI: 00:14.3 assign_resources, bus 0 link: 0 SB800 - Lpc.c - lpc_set_resources - End. PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:14.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:14.4 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:14.5 10 <- [0x00f004a000 - 0x00f004afff] size 0x00001000 gran 0x0c mem DOMAIN: 0000 assign_resources, bus 0 link: 0 adsr - leaving this lovely routine. Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 428 align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base e0000000 size 1004b601 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base c0000 size dff40000 align 0 gran 0 limit 0 flags e0004200 index 20 DOMAIN: 0000 resource base 100000000 size 11efffc00 align 0 gran 0 limit 0 flags e0004200 index 30 DOMAIN: 0000 resource base c8000000 size 18000000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:00.0 PCI: 00:00.0 resource base f8000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:01.0 PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28 limit f7ffffff flags 60001200 index 10 PCI: 00:01.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 14 PCI: 00:01.0 resource base f0000000 size 40000 align 18 gran 18 limit f7ffffff flags 60000200 index 18 PCI: 00:01.1 PCI: 00:01.1 resource base f0040000 size 4000 align 14 gran 14 limit f7ffffff flags 60000200 index 10 PCI: 00:04.0 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:11.0 PCI: 00:11.0 resource base 1410 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:11.0 resource base 1420 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:11.0 resource base 1418 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:11.0 resource base 1424 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:11.0 resource base 1400 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:11.0 resource base f004b000 size 400 align 10 gran 10 limit f7ffffff flags 60000200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base f0048000 size 1000 align 12 gran 12 limit f7ffffff flags 60000200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base f004b400 size 100 align 8 gran 8 limit f7ffffff flags 60000200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base f0049000 size 1000 align 12 gran 12 limit f7ffffff flags 60000200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base f004b500 size 100 align 8 gran 8 limit f7ffffff flags 60000200 index 10 PCI: 00:14.0 child on link 0 I2C: 00:50 I2C: 00:50 I2C: 00:51 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.2 resource base f0044000 size 4000 align 14 gran 14 limit f7ffffff flags 60000201 index 10 PCI: 00:14.3 child on link 0 PNP: 002e.0 PCI: 00:14.3 resource base f004b602 size 1 align 0 gran 0 limit f7ffffff flags 60000200 index a0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 PNP: 002e.6 PNP: 002e.6 resource base 100 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 220 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.7 resource base 300 size 2 align 1 gran 1 limit 7ff flags c0000100 index 62 PNP: 002e.7 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.8 PNP: 002e.9 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags e0000100 index 60 PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PCI: 00:14.4 PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:14.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:14.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20 PCI: 00:14.5 PCI: 00:14.5 resource base f004a000 size 1000 align 12 gran 12 limit f7ffffff flags 60000200 index 10 PCI: 00:15.0 PCI: 00:16.0 PCI: 00:16.2 PCI: 00:18.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 PCI: 00:18.6 PCI: 00:18.7 Done allocating resources. Enabling resources... Fam14h - domain_enable_resources agesawrapper_amdinitmid passed. ader - leaving domain_enable_resources. PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 subsystem <- 1022/1510 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 subsystem <- 1022/1510 PCI: 00:01.1 cmd <- 02 PCI: 00:11.0 subsystem <- 1022/1510 PCI: 00:11.0 cmd <- 03 PCI: 00:12.0 subsystem <- 1022/1510 PCI: 00:12.0 cmd <- 02 PCI: 00:12.2 subsystem <- 1022/1510 PCI: 00:12.2 cmd <- 02 PCI: 00:13.0 subsystem <- 1022/1510 PCI: 00:13.0 cmd <- 02 PCI: 00:13.2 subsystem <- 1022/1510 PCI: 00:13.2 cmd <- 02 PCI: 00:14.0 subsystem <- 1022/1510 PCI: 00:14.0 cmd <- 403 PCI: 00:14.2 subsystem <- 1022/1510 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 subsystem <- 1022/1510 PCI: 00:14.3 cmd <- 0f PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 subsystem <- 1022/1510 PCI: 00:14.4 cmd <- 21 PCI: 00:14.5 subsystem <- 1022/1510 PCI: 00:14.5 cmd <- 02 PCI: 00:15.0 bridge ctrl <- ffff PCI: 00:15.0 cmd <- ffff PCI: 00:18.0 subsystem <- 1022/1510 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1022/1510 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/1510 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 subsystem <- 1022/1510 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/1510 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 subsystem <- 1022/1510 PCI: 00:18.5 cmd <- 00 PCI: 00:18.6 subsystem <- 1022/1510 PCI: 00:18.6 cmd <- 00 PCI: 00:18.7 subsystem <- 1022/1510 PCI: 00:18.7 cmd <- 00 W83627HF HWM SMBus enabled done. Initializing devices... Root Device init CPU_CLUSTER: 0 init start_eip=0x00001000, code_size=0x00000031 Initializing CPU #0 CPU: vendor AMD device 500f10 CPU: family 14, model 01, stepping 00 Model 14 Init. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Enabling cache Setting up local apic... apic_id: 0x00 done. model_14_init done. CPU #0 initialized CPU1: stack_base 00290000, stack_end 0029fff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 1. After apic_write. Startup point 1. Waiting for send to finish... +Sending STARTUP #2 to 1. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #1 Waiting for 1 CPUS to stop CPU: vendor AMD device 500f10 CPU: family 14, model 01, stepping 00 Model 14 Init. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Enabling cache Setting up local apic... apic_id: 0x01 done. model_14_init done. CPU #1 initialized All AP CPUs stopped (2222 loops) CPU1: stack: 00290000 - 002a0000, lowest used address 0029fda8, stack used: 600 bytes PCI: 00:00.0 init Northbridge init PCI: 00:01.0 init CBFS: Looking for 'pci1002,9802.rom' starting from 0x0. CBFS: (unmatched file @0x0: cmos_layout.bin) CBFS: Found file (offset=0x778, len=65536). In CBFS, ROM address for PCI: 00:01.0 = ffc00778 PCI expansion ROM, signature 0xaa55, INIT size 0xe200, data ptr 0x01b4 PCI ROM image, vendor ID 1002, device ID 9802, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from ffc00778 to 0xc0000, 0xe200 bytes Real mode stub @00000600: 867 bytes Calling Option ROM... ... Option ROM returned. PCI: 00:01.1 init PCI: 00:11.0 init PCI: 00:14.0 init PCI: 00:14.3 init SB800 - Late.c - lpc_init - Start. RTC Init SB800 - Late.c - lpc_init - End. PCI: 00:14.4 init PCI: 00:18.0 init PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init PCI: 00:18.4 init PCI: 00:18.5 init PCI: 00:18.6 init PCI: 00:18.7 init PNP: 002e.2 init PNP: 002e.5 init PNP: 002e.a init PNP: 002e.b init base = 0x0295, reg = 0x40, value = 0x83 base = 0x0295, reg = 0x48, value = 0x2a base = 0x0295, reg = 0x4a, value = 0x21 base = 0x0295, reg = 0x4e, value = 0x80 base = 0x0295, reg = 0x43, value = 0xff base = 0x0295, reg = 0x44, value = 0x3f base = 0x0295, reg = 0x4c, value = 0x18 base = 0x0295, reg = 0x4d, value = 0x95 Devices initialized Show all devs...After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:04.0: enabled 0 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 PCI: 00:14.1: enabled 0 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 0 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:14.4: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 0 PCI: 00:16.0: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:18.6: enabled 1 PCI: 00:18.7: enabled 1 APIC: 01: enabled 1 Re-Initializing CBMEM area to 0xc7fe0000 Initializing CBMEM area to 0xc7fe0000 (131072 bytes) dword=c7fe0000 nvram_pos=f8, dword>>(8*i)=0 nvram_pos=f9, dword>>(8*i)=0 nvram_pos=fa, dword>>(8*i)=fe nvram_pos=fb, dword>>(8*i)=c7 Adding CBMEM entry as no. 1 Moving GDT to c7fe0200...ok High Tables Base is c7fe0000. agesawrapper_amdinitlate: AmdLateParamsPtr = 2003C Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done. Adding CBMEM entry as no. 2 Writing IRQ routing tables to 0xc7fe0400...write_pirq_routing_table done. PIRQ table: 48 bytes. Wrote the mp table end at: 000f0410 - 000f0514 Adding CBMEM entry as no. 3 Wrote the mp table end at: c7fe1410 - c7fe1514 MP table: 276 bytes. Adding CBMEM entry as no. 4 ACPI: Writing ACPI tables at c7fe2400... ACPI: * DSDT at c7fe24c8 ACPI: * DSDT @ c7fe24c8 Length 28e6 ACPI: * FACS at c7fe4db0 ACPI: * FADT at c7fe4df0 ACPI_BLK_BASE: 0x0800 ACPI: added table 1/32, length now 40 ACPI: * HPET at c7fe4ee8 ACPI: added table 2/32, length now 44 ACPI: * MADT at c7fe4f20 ACPI: added table 3/32, length now 48 ACPI: added table 4/32, length now 52 ACPI: * SRAT at c7fe4fa8 AGESA SRAT table NULL. Skipping. ACPI: * SLIT at c7fe4fa8 AGESA SLIT table NULL. Skipping. ACPI: * AGESA ALIB SSDT at c7fe4fb0 ACPI: added table 5/32, length now 56 ACPI: * AGESA SSDT Pstate at c7fe6640 ACPI: added table 6/32, length now 60 ACPI: * coreboot TOM SSDT2 at c7fe6a20 ACPI: added table 7/32, length now 64 ACPI: done. ACPI tables: 18021 bytes. Adding CBMEM entry as no. 5 smbios_write_tables: c7fed800 Root Device (ASROCK E350M1) CPU_CLUSTER: 0 (AMD Family 14h Root Complex) APIC: 00 (AMD CPU Family 14h) DOMAIN: 0000 (AMD Family 14h Root Complex) PCI: 00:00.0 (AMD Family 14h Northbridge) PCI: 00:01.0 (AMD Family 14h Northbridge) PCI: 00:01.1 (AMD Family 14h Northbridge) PCI: 00:04.0 (AMD Family 14h Northbridge) PCI: 00:05.0 (AMD Family 14h Northbridge) PCI: 00:06.0 (AMD Family 14h Northbridge) PCI: 00:07.0 (AMD Family 14h Northbridge) PCI: 00:08.0 (AMD Family 14h Northbridge) PCI: 00:11.0 (ATI SB800) PCI: 00:12.0 (ATI SB800) PCI: 00:12.2 (ATI SB800) PCI: 00:13.0 (ATI SB800) PCI: 00:13.2 (ATI SB800) PCI: 00:14.0 (ATI SB800) I2C: 00:50 (unknown) I2C: 00:51 (unknown) PCI: 00:14.1 (ATI SB800) PCI: 00:14.2 (ATI SB800) PCI: 00:14.3 (ATI SB800) PNP: 002e.0 (Winbond W83627HF Super I/O) PNP: 002e.1 (Winbond W83627HF Super I/O) PNP: 002e.2 (Winbond W83627HF Super I/O) PNP: 002e.3 (Winbond W83627HF Super I/O) PNP: 002e.5 (Winbond W83627HF Super I/O) PNP: 002e.6 (Winbond W83627HF Super I/O) PNP: 002e.7 (Winbond W83627HF Super I/O) PNP: 002e.8 (Winbond W83627HF Super I/O) PNP: 002e.9 (Winbond W83627HF Super I/O) PNP: 002e.a (Winbond W83627HF Super I/O) PNP: 002e.b (Winbond W83627HF Super I/O) PCI: 00:14.4 (ATI SB800) PCI: 00:14.5 (ATI SB800) PCI: 00:15.0 (ATI SB800) PCI: 00:15.1 (ATI SB800) PCI: 00:15.2 (ATI SB800) PCI: 00:15.3 (ATI SB800) PCI: 00:16.0 (ATI SB800) PCI: 00:16.2 (ATI SB800) PCI: 00:18.0 (AMD Family 14h Northbridge) PCI: 00:18.1 (AMD Family 14h Northbridge) PCI: 00:18.2 (AMD Family 14h Northbridge) PCI: 00:18.3 (AMD Family 14h Northbridge) PCI: 00:18.4 (AMD Family 14h Northbridge) PCI: 00:18.5 (AMD Family 14h Northbridge) PCI: 00:18.6 (AMD Family 14h Northbridge) PCI: 00:18.7 (AMD Family 14h Northbridge) APIC: 01 (unknown) SMBIOS tables: 275 bytes. Adding CBMEM entry as no. 6 Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 57df Table forward entry ends at 0x00000528. ... aligned to 0x00001000 Writing coreboot table at 0xc7fee000 rom_table_end = 0xc7fee000 ... aligned to 0xc7ff0000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-00000000c7fdffff: RAM 3. 00000000c7fe0000-00000000c7ffffff: CONFIGURATION TABLES 4. 00000000c8000000-00000000dfffffff: RESERVED 5. 00000000f8000000-00000000f8ffffff: RESERVED 6. 0000000100000000-000000021effffff: RAM Wrote coreboot table at: c7fee000, 0x200 bytes, checksum c1b6 coreboot table: 536 bytes. Multiboot Information structure has been written. FREE SPACE 0. c7ff6000 0000a000 GDT 1. c7fe0200 00000200 IRQ TABLE 2. c7fe0400 00001000 SMP TABLE 3. c7fe1400 00001000 ACPI 4. c7fe2400 0000b400 SMBIOS 5. c7fed800 00000800 COREBOOT 6. c7fee000 00008000 CBFS: Looking for 'fallback/payload' starting from 0x0. CBFS: (unmatched file @0x0: cmos_layout.bin) CBFS: (unmatched file @0x740: pci1002,9802.rom) CBFS: (unmatched file @0x10780: fallback/romstage) CBFS: (unmatched file @0x65380: fallback/coreboot_ram) CBFS: Found file (offset=0x97878, len=195518). Loading segment from rom address 0xffc97878 code (compression=1) New segment dstaddr 0x8200 memsize 0xe504 srcaddr 0xffc978cc filesize 0x417d (cleaned up) New segment addr 0x8200 size 0xe504 offset 0xffc978cc filesize 0x417d Loading segment from rom address 0xffc97894 code (compression=1) New segment dstaddr 0x100000 memsize 0x85b64 srcaddr 0xffc9ba49 filesize 0x2b9ed (cleaned up) New segment addr 0x100000 size 0x85b64 offset 0xffc9ba49 filesize 0x2b9ed Loading segment from rom address 0xffc978b0 Entry Point 0x00008200 Loading Segment: addr: 0x0000000000008200 memsz: 0x000000000000e504 filesz: 0x000000000000417d lb: [0x0000000000200000, 0x0000000000370038) Post relocation: addr: 0x0000000000008200 memsz: 0x000000000000e504 filesz: 0x000000000000417d using LZMA [ 0x00008200, 0000f14f, 0x00016704) <- ffc978cc Clearing Segment: addr: 0x000000000000f14f memsz: 0x00000000000075b5 dest 00008200, end 00016704, bouncebuffer c7cfff90 Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000085b64 filesz: 0x000000000002b9ed lb: [0x0000000000200000, 0x0000000000370038) Post relocation: addr: 0x0000000000100000 memsz: 0x0000000000085b64 filesz: 0x000000000002b9ed using LZMA Boot failed

3 5

Trac reminder: list of new ticket(s)
by coreboot tracker 08 Apr '13

08 Apr '13

1 0

DSDT: New warnings after adding _OSC method
by Paul Menzel 07 Apr '13

07 Apr '13

Dear coreboot folks, the patches adding the _OSC method to the DSDT, like [1][2][3], introduce the following ACPI warnings [4][5], which went unnoticed by the reviewers, myself included. IASL coreboot-builds/amd_persimmon/mainboard/amd/persimmon/dsdt.ramstage.o CC mainboard/amd/persimmon/get_bus_conf.ramstage.o Intel ACPI Component Architecture ASL Optimizing Compiler version 20100528 [Oct 15 2010] Copyright (c) 2000 - 2010 Intel Corporation Supports ACPI Specification Revision 4.0a dsdt.ramstage.asl 1143: Method(_OSC,4) Warning 1088 - ^ Not all control paths return a value (_OSC) dsdt.ramstage.asl 1143: Method(_OSC,4) Warning 1081 - ^ Reserved method must return a value (Buffer required for _OSC) ASL Input: dsdt.ramstage.asl - 1724 lines, 34917 bytes, 889 keywords AML Output: dsdt.ramstage.aml - 10470 bytes, 409 named objects, 480 executable opcodes Compilation complete. 0 Errors, 2 Warnings, 0 Remarks, 494 Optimizations It should be as simple as adding the following as commented in [1 (Mar 14 12:23 AM)] already. } Else { Or(CDW1,4,CDW1) // Unrecognized UUID Return(Arg3) } I am not submitting a patch, as the Sage folks are currently doing some unification work, I do not want to interfere with. Thanks, Paul [1] http://review.coreboot.org/#/c/2684/ [2] http://review.coreboot.org/#/c/2739/ [3] http://review.coreboot.org/#/c/2714/ [4] http://qa.coreboot.org/job/coreboot-gerrit/5591/testReport/(root)/board/i38… [5] http://qa.coreboot.org/job/coreboot-gerrit/5591/testReport/(root)/board/i38… (logs will not be archived forever, so URL might be invalid)

2 2

Re: [coreboot] server board support - Supermicro H8DGi-F ?
by Idwer Vollering 07 Apr '13

07 Apr '13

2013/4/6 Marc Jones <marcj303(a)gmail.com>: > Hi Ward, > > I think that the H8QGI has fairly good support (the one SMP late init bug > noted). I didn't look at the details, but similar boards should be a "easy" > port. The supermicro boards will often have the pads for the debug header > for when the going gets tough. When you replace the stock (AMI)BIOS with coreboot, do you stick to supermicro's memory QVL ('Tested Memory List') or will/can agesa code handle any (non-)registered (non-)ECC (unbuffered) DIMM? I've investigated H8SGL and H8SCM (single processor, either with or without IPMI), the last one already already is supported by coreboot. > > Marc > > > On Wed, Apr 3, 2013 at 10:52 AM, Ward Vandewege <ward(a)gnu.org> wrote: >> >> Hi, >> >> We're looking at selecting a server board for our next generation of >> servers. >> >> We tend to use 2-CPU AMD boards. The Supermicro H8DGi-F seems promising. I >> know Konstantin is working on the H8QGi+F which is very similar. >> Konstantin - >> how far along is your port? I read about the memory speed issue with AGESA >> 1.0.3. >> >> Anyone else interested in working on a port of H8DGi-F or a similar board? >> >> Thanks, >> Ward. >> >> -- >> Ward Vandewege | CTO, Free Software Foundation >> GPG Key: 25F774AB | http://identi.ca/cure | http://fsf.org/blogs/RSS >> >> Do you use free software? Donate to join the FSF and support freedom at >> http://www.fsf.org/register_form?referrer=859 >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > > > > -- > http://se-eng.com > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

1 0

Obtaining IOMMU Functionality on AMD Fusion?
by Stu 07 Apr '13

07 Apr '13

Hello, I have recently obtained an Asus C60M1-I motherboard, based on the C60 Fusion APU and Hudson A50M chipset. As it appears that adapting E350-based motherboards using the same chipset was relatively straightforward, I would like to explore getting it to work with my motherboard also. There is one thing that I would like to confirm though: Although my motherboard does have SVM (CPU virtualisation) available, after testing with Xen Community Platform I have found that I haven't got IOMMU (I/O virtualisation) available. The thing is, similar motherboards based on the E350/450 do have this feature. Reading around, it is considered that IOMMU is a feature of the chipset which has to be exposed by the EFI firmware in the form of the "DMAR" ACPI table. Asus doesn't provide this except on certain server-oriented motherboards, other manufacturers do. So would implementing coreboot for my motherboard help with this?

1 0

Microcodes
by Denis 'GNUtoo' Carikli 06 Apr '13

06 Apr '13

Hi, In src/cpu/intel/model_6fx/model_6fx_init.c there is: /* * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, * MA 02110-1301 USA */ [...] static const uint32_t microcode_updates[] = { #include "microcode-1624-m206e839.h" #include "microcode-1729-m206ec54.h" #include "microcode-1869-m806ec59.h" /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, }; [...] static void model_6ex_init(device_t cpu) { [...] /* Update the microcode */ intel_update_microcode(microcode_updates); [...] } [...] That raises some questions: The first one is the following: Is the inclusion of the microcode in GPLv2 source code compatible with the GPLv2? Because the microcode-1624-m206e839.h has: //+++ // Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are // permitted provided that the following conditions are met: // .Redistributions must reproduce the above copyright notice and the following // disclaimer in the documentation and/or other materials provided with the // distribution. // .Neither the name of Intel Corporation nor the names of its suppliers may be used // to endorse or promote products derived from this software without specific prior // written permission. // .No reverse engineering, decompilation, or disassembly of this software is // permitted. // ."Binary form" includes any format commonly used for electronic conveyance // which is a reversible, bit-exact translation of binary representation to ASCII or // ISO text, for example, "uuencode." // // DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT // HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED // WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER // OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT // NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; // LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF // ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // //--- /* Tue Feb 9 12:54:50 CST 2010 */ /* 1624-m206e839.inc */ which prevents: * modification * reverse engineering, decompilation, disassembly The second question is about Kconfig: In the CPU section in make menuconfig there is a choice about microcode: Include CPU microcode in CBFS (Do not include microcode updates) ---> That is misleading, because according to the code that is before, it does include the microcode,not even in CBFS(but included in the code like before), and it also updates it. The third question is the following: Which CPU(or laptop, or mainboard+CPU) still work without the microcode and which doesn't. Denis.

2 1

server board support - Supermicro H8DGi-F ?
by Ward Vandewege 06 Apr '13

06 Apr '13

Hi, We're looking at selecting a server board for our next generation of servers. We tend to use 2-CPU AMD boards. The Supermicro H8DGi-F seems promising. I know Konstantin is working on the H8QGi+F which is very similar. Konstantin - how far along is your port? I read about the memory speed issue with AGESA 1.0.3. Anyone else interested in working on a port of H8DGi-F or a similar board? Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://identi.ca/cure | http://fsf.org/blogs/RSS Do you use free software? Donate to join the FSF and support freedom at http://www.fsf.org/register_form?referrer=859

2 1

AMI bios source leak
by Василий Анонимов 06 Apr '13

06 Apr '13

Just FYI: http://adamcaudill.com/2013/04/04/security-done-wrong-leaky-ftp-server/ //wbr Vasily

1 0

f2a85-m related topics
by Rudolf Marek 06 Apr '13

06 Apr '13

Hi all The board is finally in. I'm aware that David bought it (i think he has f2a85-m CSM version which is USA specific), is there anyone else? PaulePanter maybe? Has anyone tried "hot flashing" ? It seems linux crashes if I simply unplug the flash. I tried to work around and disabled SMI by software. But I want to be sure it happens also to other people. The issue with SeaBIOS is gone. I will post some coded verb fix. Is there a way how to extract verbs for codec from original system? I did simple: cat /sys/class/sound/hwC1D0/init_pin_configs Is it all? The last, so far known issue is that SeaBIOS likes to boot only from first AHCI port. I need to check this. Thanks Rudolf

6 12

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot April 2013