coreboot April 2013

coreboot@coreboot.org

42 participants
125 discussions

coreboot: make crossgcc - Failed to download acpica-unix-20121114.tar.gz.
by Pradish M P, ERS, HCLTech 11 Apr '13

11 Apr '13

Dear coreboot folks i downloaded the latest source code form coreboot.org , when i tried to build the cross compiler using the command make crossgcc it gives the following error root@test-VirtualBox:~/coreboot# make crossgcc Warning: no suitable GCC for armv7. Welcome to the coreboot cross toolchain builder v1.20 (December 4th, 2012) Will skip GDB ... ok Downloading tar balls ... * gmp-5.0.5.tar.bz2 (downloading) * mpfr-3.1.1.tar.bz2 (downloading) * mpc-1.0.1.tar.gz (downloading) * libelf-0.8.13.tar.gz (downloading) * gcc-4.7.2.tar.bz2 (downloading) * binutils-2.23.tar.gz (downloading) * acpica-unix-20121114.tar.gz (downloading) Failed to download acpica-unix-20121114.tar.gz. make[1]: *** [build-without-gdb] Error 1 make: *** [crossgcc] Error 2 can anyone guide me how to fix. regards pradish ________________________________________ ::DISCLAIMER:: ---------------------------------------------------------------------------------------------------------------------------------------------------- The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. E-mail transmission is not guaranteed to be secure or error-free as information could be intercepted, corrupted, lost, destroyed, arrive late or incomplete, or may contain viruses in transmission. The e mail and its contents (with or without referred errors) shall therefore not attach any liability on the originator or HCL or its affiliates. Views or opinions, if any, presented in this email are solely those of the author and may not necessarily reflect the views or opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification, distribution and / or publication of this message without the prior written consent of authorized representative of HCL is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately. Before opening any email and/or attachments, please check them for viruses and other defects. ----------------------------------------------------------------------------------------------------------------------------------------------------

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Re: [coreboot] coreboot has been accepted for GSoC 2013
by Peter Stuge 11 Apr '13

11 Apr '13

Marc Jones wrote: > Many students are not familiar with the complexity and issues > involved in firmware and bootloaders. Nor with open source processes and tools, unfortunately. :\ > If you know any students, tell them about GSoC and promote coreboot! What's the executive sales pitch for a student in Europe? Get paid $n * 1000 EUR for working full time on the project for one and a half monts? //PEter

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X201 bootblock unlocking
by Vladimir 'φ-coder/phcoder' Serbinenko 11 Apr '13

11 Apr '13

Hello all. On X201 top 192K are locked. Fortunately the original BIOS has a way to update this region. If you extract a X201 image you'll find a lzint compressed file which makes 192K decompressed. It's the update. In it you can simply replace 74f8d1fe (PR0) with 74f8d0ff (harmless address with the same checksum), recompress, correct checksum, update, reboot and PR0 is inactive. tools to do all this were posted previously (x201_analyze and x201_reconstruct) except compressor. You need compressor at least as performant as original. I attach here my own version which is about 2% underperformant. If you want to have a try, be my guest Otherwise I simply use external flashing.

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porting to GA-945GCM
by CTO of SPCTNC 10 Apr '13

10 Apr '13

Hello. Dear Coreboot team. Thank you for your effort for Coreboot. I'm from China. My name is Guangzhe Lee. and I'm new in Coreboot. I'm porting Coreboot to Gigabyte GA-945GCM board( LGA775socket / i945GC / ICH7 / IT8718F ). Romstage passed successfully, but after jumping to Ramstage console message don't appear any more. I tried to debug by GDB (using ttyS0), but it also fail. I try the POST code, but the post card always displays "2C"->"2D"->"2E" -> "2F". My post codes don't appear on the post card. Please help me. - How can I fix the problem. - How can I fix gdb problem. I'm sending - gdb message and - the console log of the booting. Thanks and regards. Guangzhe Lee <<<<<<<<<<<<<<<<<<<< console message >>>>>>>>>>>>>>>>>>> [root@localhost ~]# gdb GNU gdb (GDB) Red Hat Enterprise Linux (7.0.1-23.el5) Copyright (C) 2009 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "i386-redhat-linux-gnu". For bug reporting instructions, please see: <http://www.gnu.org/software/gdb/bugs/>. (gdb) file fallback/coreboot_ram.debug Reading symbols from /root/fallback/coreboot_ram.debug...done. (gdb) set remotebaud 115200 (gdb) target remote /dev/ttyS0 Remote debugging using /dev/ttyS0 Ignoring packet error, continuing... warning: unrecognized item "timeout" in "qSupported" response Ignoring packet error, continuing... Ignoring packet error, continuing... Ignoring packet error, continuing... Ignoring packet error, continuing... Quit (gdb). <<<<<<<<<<<<<<<<<<<< console message >>>>>>>>>>>>>>>>>>> coreboot-4.0-3784-g1cc4737-dirty Fri Apr 5 22:44:35 BOT 2013 starting... Intel(R) 82945GC Chipset (G)MCH capable of up to DDR2-533 Setting up static southbridge registers... GPIOS... done. Disabling Watchdog reboot... done. Setting up static northbridge registers... done. Waiting for MCHBAR to come up...ok PM1_CNT: 00001c00 SMBus controller enabled. Setting up RAM controller. This mainboard supports Dual Channel Operation. DDR II Channel 0 Socket 0: x8DDS DDR II Channel 0 Socket 1: N/A DDR II Channel 1 Socket 0: N/A DDR II Channel 1 Socket 1: N/A lowest common cas = 4 Probing Speed 2 DIMM: 0 Current CAS mask: 0070; idx=1, tCLK=30, tAC=45: OK DIMM: 1 DIMM: 2 DIMM: 3 freq_cas_mask for speed 2: 0030 Memory will be driven at 667MHz with CAS=4 clocks tRAS = 15 cycles tRP = 5 cycles tRCD = 5 cycles Refresh: 7.8us tWR = 5 cycles DIMM 0 side 0 = 1024 MB DIMM 0 side 1 = 1024 MB tRFC = 43 cycles Setting Graphics Frequency... FSB: 800 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz Setting Memory Frequency... CLKCFG=0x20000002, CLKCFG=0x20000002, ok Setting mode of operation for memory channels...Single Channel 0 only. DCC=0x00000400 Programming Clock Crossing...MEM=memclk: unknown register value 0 memclk: unknown register value 0 RSVD ffffffffSetting RAM size... C0DRB = 0x40404020 C1DRB = 0x40404040 TOLUD = 0x0080 Setting row attributes... C0DRA = 0x0033 C1DRA = 0x0000 DIMM0 has 8 banks. one dimm per channel config.. Initializing System Memory IO... Programming Dual Channel RCOMP Table Index: 19 Programming DLL Timings... Enabling System Memory IO... jedec enable sequence: bank 0 Apply NOP Sending RAM command 0x00010400...done ram read: 00000000 All Banks Precharge Sending RAM command 0x00020400...done ram read: 00000000 Extended Mode Register Set(2) Sending RAM command 0x00240400...done ram read: 00000000 Extended Mode Register Set(3) Sending RAM command 0x00440400...done ram read: 00000000 Extended Mode Register Set Sending RAM command 0x00040400...done ram read: 00000200 MRS: Reset DLLs Sending RAM command 0x00030400...done ram read: 00004a58 All Banks Precharge Sending RAM command 0x00020400...done ram read: 00000000 CAS before RAS Sending RAM command 0x00060400...done ram read: 00000000 ram read: 00000000 MRS: Enable DLLs Sending RAM command 0x00030400...done ram read: 00004258 Extended Mode Register Set: ODT/OCD Sending RAM command 0x00040400...done ram read: 00001e00 Extended Mode Register Set: OCD Exit Sending RAM command 0x00040400...done ram read: 00000200 jedec enable sequence: bank 1 bankaddr from bank size of rank 0 Apply NOP Sending RAM command 0x00010400...done ram read: 40000000 All Banks Precharge Sending RAM command 0x00020400...done ram read: 40000000 Extended Mode Register Set(2) Sending RAM command 0x00240400...done ram read: 40000000 Extended Mode Register Set(3) Sending RAM command 0x00440400...done ram read: 40000000 Extended Mode Register Set Sending RAM command 0x00040400...done ram read: 40000200 MRS: Reset DLLs Sending RAM command 0x00030400...done ram read: 40004a58 All Banks Precharge Sending RAM command 0x00020400...done ram read: 40000000 CAS before RAS Sending RAM command 0x00060400...done ram read: 40000000 ram read: 40000000 MRS: Enable DLLs Sending RAM command 0x00030400...done ram read: 40004258 Extended Mode Register Set: ODT/OCD Sending RAM command 0x00040400...done ram read: 40001e00 Extended Mode Register Set: OCD Exit Sending RAM command 0x00040400...done ram read: 40000200 Normal Operation Sending RAM command 0x000f0400...done receive_enable_autoconfig() for channel 0 find_strobes_low() set_receive_enable() medium=0x3, coarse=0x4 set_receive_enable() medium=0x1, coarse=0x4 set_receive_enable() medium=0x1, coarse=0x4 find_strobes_edge() set_receive_enable() medium=0x1, coarse=0x4 add_quarter_clock() mediumcoarse=11 fine=73 find_preamble() set_receive_enable() medium=0x1, coarse=0x3 set_receive_enable() medium=0x1, coarse=0x2 add_quarter_clock() mediumcoarse=09 fine=f3 set_receive_enable() medium=0x3, coarse=0x2 normalize() RAM initialization finished. Setting up Egress Port RCRB Loading port arbitration table ...ok Wait for VC1 negotiation ...ok Setting up DMI RCRB Wait for VC1 negotiation ...done.. Internal graphics: enabled Waiting for DMI hardware...ok Enabling PCI Express x16 Link SLOTSTS: 0000 Disabling PCI Express x16 Link Wait for link to enter detect state... ok Setting up Root Complex Topology <-Setting up Root Complex Topology high_ram_base: 0x 7f6e0000, 0x 120000 Loading image. CBFS: CBFS_HEADER_ROM_ADDRESS: 0xffffefe0/0x80000 CBFS: CBFS location: 0x0~0x7f000, align: 64 CBFS: Looking for 'fallback/coreboot_ram' starting from 0x0. CBFS: - load entry 0x0 file name (16 bytes)... CBFS: (unmatched file @0x0: cmos_layout.bin) CBFS: - load entry 0x540 file name (32 bytes)... CBFS: (unmatched file @0x540: fallback/romstage) CBFS: - load entry 0xca00 file name (32 bytes)... CBFS: Found file (offset=0xca38, len=367928). CBFS: loading stage fallback/coreboot_ram @ 0x100000 (417880 bytes), entry @ 0x1 00000 CBFS: cbfs_decompress, algo=0, src=fff8ca54, dst=100000, len=367900 CBFS: src=10f2efa, dst=10f2efa CBFS: stage loaded. Jumping to image.

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cbfstoool: Cppcheck 1.59 warnings with hash 33e83ca
by Paul Menzel 10 Apr '13

10 Apr '13

Dear coreboot folks, if somebody is bored ;-), here is the output of Cppcheck for cbfstool to fix. :P $ cppcheck --version Cppcheck 1.59 $ git describe 4.0-3991-g33e83ca $ cppcheck --enable=all . Checking cbfs-mkpayload.c... Checking cbfs-mkpayload.c: __APPLE__... 1/11 files checked 4% done Checking cbfs-mkstage.c... [cbfs-mkstage.c:170]: (error) Memory leak: buffer Checking cbfs-mkstage.c: __APPLE__... 2/11 files checked 7% done Checking cbfs_image.c... Checking cbfs_image.c: __APPLE__... 3/11 files checked 21% done Checking cbfstool.c... Checking cbfstool.c: __APPLE__... 4/11 files checked 28% done Checking common.c... [common.c:36] -> [common.c:37]: (style) Mismatching assignment and comparison, comparison 'inttest_lsb==18' is always false. [common.c:141]: (error) Resource leak: file [common.c:270]: (error) Resource leak: file Checking common.c: __APPLE__... 5/11 files checked 40% done Checking compress.c... Checking compress.c: __APPLE__... 6/11 files checked 40% done Checking fit.c... Checking fit.c: __APPLE__... 7/11 files checked 44% done Checking lzma/C/LzFind.c... Checking lzma/C/LzFind.c: _LZMA_NO_SYSTEM_SIZE_T... Checking lzma/C/LzFind.c: _LZMA_UINT32_IS_ULONG... Checking lzma/C/LzFind.c: _MSC_VER... Checking lzma/C/LzFind.c: _SZ_NO_INT_64... Checking lzma/C/LzFind.c: _WIN32... Checking lzma/C/LzFind.c: __cplusplus... 8/11 files checked 54% done Checking lzma/C/LzmaDec.c... [lzma/C/LzmaDec.c:673]: (style) Variable 'range' is assigned a value that is never used. [lzma/C/LzmaDec.c:673]: (style) Variable 'code' is assigned a value that is never used. Checking lzma/C/LzmaDec.c: _LZMA_NO_SYSTEM_SIZE_T... Checking lzma/C/LzmaDec.c: _LZMA_PROB32... Checking lzma/C/LzmaDec.c: _LZMA_SIZE_OPT... Checking lzma/C/LzmaDec.c: _LZMA_UINT32_IS_ULONG... Checking lzma/C/LzmaDec.c: _MSC_VER... Checking lzma/C/LzmaDec.c: _SZ_NO_INT_64... Checking lzma/C/LzmaDec.c: _WIN32... Checking lzma/C/LzmaDec.c: __cplusplus... 9/11 files checked 67% done Checking lzma/C/LzmaEnc.c... [lzma/C/LzmaEnc.c:1345]: (style) The scope of the variable 'nextRepMatchPrice' can be reduced. [lzma/C/LzmaEnc.c:1435]: (style) The scope of the variable 'nextRepMatchPrice' can be reduced. [lzma/C/LzmaEnc.c:2164]: (style) Variable 'allocaDummy' is assigned a value that is never used. Checking lzma/C/LzmaEnc.c: LZMA_LOG_BSR... [lzma/C/LzmaEnc.c:398] -> [lzma/C/LzmaEnc.c:398]: (style) Same expression on both sides of '||'. Checking lzma/C/LzmaEnc.c: SHOW_STAT... [lzma/C/LzmaEnc.c:807]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list. Checking lzma/C/LzmaEnc.c: SHOW_STAT2... [lzma/C/LzmaEnc.c:1775]: (warning) %d in format string (no. 2) requires a signed integer given in the argument list. [lzma/C/LzmaEnc.c:1775]: (warning) %d in format string (no. 3) requires a signed integer given in the argument list. [lzma/C/LzmaEnc.c:1115]: (style) Unsigned variable 'position' can't be negative so it is unnecessary to test it. Checking lzma/C/LzmaEnc.c: _7ZIP_ST... [lzma/C/LzmaEnc.c:2083]: (warning) Redundant assignment of 'pp' to itself. [lzma/C/LzmaEnc.c:2083]: (warning) Assignment of function parameter has no effect outside the function. Checking lzma/C/LzmaEnc.c: _LZMA_NO_SYSTEM_SIZE_T... Checking lzma/C/LzmaEnc.c: _LZMA_PROB32... Checking lzma/C/LzmaEnc.c: _LZMA_UINT32_IS_ULONG... Checking lzma/C/LzmaEnc.c: _MSC_VER... Checking lzma/C/LzmaEnc.c: _SZ_NO_INT_64... Checking lzma/C/LzmaEnc.c: _WIN32... Checking lzma/C/LzmaEnc.c: __cplusplus... 10/11 files checked 97% done Checking lzma/lzma.c... Checking lzma/lzma.c: _LZMA_NO_SYSTEM_SIZE_T... Checking lzma/lzma.c: _LZMA_PROB32... Checking lzma/lzma.c: _LZMA_UINT32_IS_ULONG... Checking lzma/lzma.c: _MSC_VER... Checking lzma/lzma.c: _SZ_NO_INT_64... Checking lzma/lzma.c: _WIN32... Checking lzma/lzma.c: __APPLE__... Checking lzma/lzma.c: __cplusplus... 11/11 files checked 100% done Checking usage of global functions.. [lzma/C/LzFind.c:495]: (style) The function 'Bt3Zip_MatchFinder_GetMatches' is never used. [lzma/C/LzFind.c:660]: (style) The function 'Bt3Zip_MatchFinder_Skip' is never used. [lzma/C/LzFind.c:635]: (style) The function 'Hc3Zip_MatchFinder_GetMatches' is never used. [lzma/C/LzFind.c:721]: (style) The function 'Hc3Zip_MatchFinder_Skip' is never used. [lzma/C/LzmaDec.c:947]: (style) The function 'LzmaDec_Allocate' is never used. [lzma/C/LzmaDec.c:840]: (style) The function 'LzmaDec_DecodeToBuf' is never used. [lzma/C/LzmaDec.c:892]: (style) The function 'LzmaDec_Free' is never used. [lzma/C/LzmaEnc.c:76]: (style) The function 'LzmaEncProps_GetDictSize' is never used. [lzma/C/LzmaEnc.c:2250]: (style) The function 'LzmaEncode' is never used. [lzma/C/LzFind.c:108]: (style) The function 'MatchFinder_ReadIfRequired' is never used. [common.c:497]: (style) The function 'add_file_to_cbfs' is never used. [common.c:791]: (style) The function 'cbfs_find_location' is never used. [cbfs_image.c:782]: (style) The function 'cbfs_init_entry' is never used. [common.c:630]: (style) The function 'create_cbfs_file' is never used. [common.c:666]: (style) The function 'create_cbfs_image' is never used. [lzma/lzma.c:169]: (style) The function 'do_lzma_uncompress' is never used. [common.c:438]: (style) The function 'extract_file_from_cbfs' is never used. [cbfs_image.c:102]: (style) The function 'get_cbfs_compression' is never used. [cbfs_image.c:92]: (style) The function 'get_cbfs_entry_type' is never used. [common.c:106]: (style) The function 'getfilesize' is never used. [cbfs-mkstage.c:31]: (style) The function 'idemp' is never used. [common.c:348]: (style) The function 'print_cbfs_directory' is never used. [common.c:597]: (style) The function 'remove_file_from_cbfs' is never used. (information) Cppcheck cannot find all the include files (use --check-config for details) Thanks, Paul

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link trainning of rs780e is x2
by yili0568＠gmail.com 10 Apr '13

10 Apr '13

Hello: everyone, the gfx configured as 2 x8 slot, after link trained successfully, I printed the width , the value of which is 4. Does it means the link width is x8? from the function dual_port_configuration ...... switch (width) { case 1: case 2: nbpcie_ind_write_index(nb_dev, 0x65, cfg->gfx_lane_reversal ? 0x0000 : 0x0000); tgt_printf("file %s, func %s, line %d, dev_ind %d width %d\n", __FILE__, __func__, __LINE__, dev_ind, width); break; case 4: tgt_printf("file %s, func %s, line %d, dev_ind %d width %d\n", __FILE__, __func__, __LINE__, dev_ind, width); nbpcie_ind_write_index(nb_dev, 0x65, cfg->gfx_lane_reversal ? 0x0000 : 0x0000); break; ...... Both dev2 and dev3's link width are 4 (x8?). Then I boot linux use lspci -vvv as root, the result is 00:02.0 ...... LnkCap: Port #0, Speed 5GT/s, Width x8,...... ...... LnkSta: Speed 2.5GT/s, Width x2,...... It is the same to the dev3. The cb file is from src/mainboard/amd/mahogany_fam10/devicetree.cb Anyone know about the link training of gfx of rs780e? Thanks.

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About rs780 CIM
by yili0568＠gmail.com 10 Apr '13

10 Apr '13

Hello: Everyone, the code of rs780 refers to CIM several times. For example, "In CIMx 4.5.0 and RPR, 4c is done before 5 & 6. But in this way", "Compliant with CIM_33's PCIEPowerOffGppPorts", etc. Does CIM means Common Information Model of DMTF? But I can't find the part about rs780. Anyone konw about it? thanks.

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Re: [coreboot] coreboot-libpayload 'size_t' conflicting type error
by Stefan Reinauer 10 Apr '13

10 Apr '13

* Pradish M P, ERS, HCLTech <pradishmp(a)hcl.com> [130409 10:00]: > Dear Coreboot Folks > > I see that this issues is still not resolved, can you guys give me some steps so that I can do those changes in my local copy > And build libpayload. > > > Regards > Pradish Please take a look at http://review.coreboot.org/#/c/3058/

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coreboot has been accepted for GSoC 2013
by Marc Jones 09 Apr '13

09 Apr '13

Hello coreboot! coreboot has been accepted for GSoC 2013. There are details on how to apply and project ideas on the coreboot wiki. http://www.coreboot.org/GSoC https://www.google-melange.com/gsoc/org/google/gsoc2013/coreboot I expect that there will be some new interest from students and that they will join IRC and ask lots of interesting questions. Please try to be kind, helpful, and encouraging. Many students are not familiar with the complexity and issues involved in firmware and bootloaders. Please feel free to direct students towards any of the mentors listed on the wiki or to me directly. Please let me know if you are interested in being a mentor. If you have ideas, the projects page can be updated. If you know any students, tell them about GSoC and promote coreboot! Regards, Marc -- http://se-eng.com

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Resets with AGESA on SB800 and errors in `agesawrapper_amdinitpost`
by Paul Menzel 09 Apr '13

09 Apr '13

Dear coreboot folks, using an ASRock E350M1 with coreboot built from commit 120d4bd8e644fc26f367022f3338264150a7ac4a Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Apr 6 21:03:22 2013 +0200 Revert "cbfstool: Replace C++ code with C code" This reverts commit aa3f7ba36ebe3a933aa664f826382f60b31e86f1. commit 161ccc76ea0f8941a34c5bed323cc9ba1fe0221d Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Apr 5 13:35:29 2013 -0700 exynos5250: add a chip.h file for the display register settings Reviewed-on: http://review.coreboot.org/3031 and a GRUB payload $ build/cbfstool build/coreboot.rom print coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, offset 0x0 alignment: 64 bytes Name Offset Type Size cmos_layout.bin 0x0 cmos_layout 1776 pci1002,9802.rom 0x740 optionrom 65536 fallback/romstage 0x10780 stage 347052 fallback/coreboot_ram 0x65380 stage 205910 fallback/payload 0x97840 payload 197874 (empty) 0xc7d80 null 3374616 it worked the first time after restarting the system (serial cable *not* connected) and therefore testing the newly written image. Then shutting it down and turning it on again it reset in several boot attempts after loading the GRUB payload(?) *with* the serial cable connected (PSU turned off each time for one or two seconds) until it finally successfully started again. […] Loading Linux 3.7.5+ ... error: disk `mduuid/fb7f3dc5d183cab6121231201a2207b9' not found. Loading initial ramdisk ... coreboot-4.0-3984-g120d4bd Sat Apr 6 21:20:24 CEST 2013 starting... BSP Family_Model: 00500f10 cpu_init_detectedx = 00000000 agesawrapper_amdinitmmio passed. agesawrapper_amdinitreset passed. agesawrapper_amdinitearly passed. agesawrapper_amdinitpost EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 7, EventInfo = 4011c00. Param1 = 0, Param2 = 0. Param3 = 0, Param4 = 0. error level: 7 agesawrapper_amdinitenv I think I had already seen this some weeks ago, but did not have time yet to report this issue. Thanks, Paul

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coreboot April 2013