coreboot March 2013

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New patch to review for coreboot: 27c57e2 AMD Hudson-E1: document Broadcom BCM57xx secret sauce Selfboot Patch format
by Jens Rottmann 04 Mar '13

04 Mar '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2581 -gerrit commit 27c57e24602cdedb5b779cb26e66b23ae121a39f Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Fri Mar 1 19:41:41 2013 +0100 AMD Hudson-E1: document Broadcom BCM57xx secret sauce Selfboot Patch format The Broadcom BCM5785 integrated in the AMD Hudson-E1 requires a proprietary firmware blob to work. As Broadcom wasn't willing to send us any documentation (or a firmware adapted to our Micrel PHY) I had to figure out everything by myself in weeks of hard detective work. In the end we had to settle for a different solution, this file is now only needed for Ethernet support on our early FrontRunner-AF prototypes. However the information contained here may be very useful for others, for example it can easily be used in place of the usual firmware blob to get Ethernet on AMD Inagua. The fun thing is: as Broadcom refused to do any business with us at all, or send us any documentation, we never had to sign an NDA with them. This leaves me free to publish everything I have found out. :-) Change-Id: Ifa628751d14143f277b27cfd34b1d2771ca1302f Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/mainboard/lippert/frontrunner-af/broadcom.c | 319 +++++++++++++++++++++++ src/mainboard/lippert/frontrunner-af/mainboard.c | 6 + 2 files changed, 325 insertions(+) diff --git a/src/mainboard/lippert/frontrunner-af/broadcom.c b/src/mainboard/lippert/frontrunner-af/broadcom.c new file mode 100644 index 0000000..941b454 --- /dev/null +++ b/src/mainboard/lippert/frontrunner-af/broadcom.c @@ -0,0 +1,319 @@ +/* + * Initialize Broadcom 5785 GbE MAC embedded in AMD A55E (Hudson-E1) Southbridge + * by uploading a Selfboot Patch to the A55E's shadow ROM area. The patch itself + * supports the Micrel KSZ9021 PHY that was used on LiPPERT CFR-AF revision 0v0, + * now it serves mainly to document Broadcom's proprietary Selfboot Patch format. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2012 LiPPERT ADLINK Technology GmbH + * (Written by Jens Rottmann <JRottmann(a)LiPPERTembedded.de>) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <arch/byteorder.h> +#include <console/console.h> +#include <device/device.h> //Coreboot device access +#include <device/pci.h> +#include <delay.h> + +#define be16(x) cpu_to_be16(x) //a little easier to type +#define be(x) cpu_to_be32(x) //this is used a lot! + +/* C forces us to specify these before defining struct selfboot_patch :-( */ +#define INIT1_LENGTH 13 +#define INIT2_LENGTH 6 +#define INIT3_LENGTH 3 +#define INIT4_LENGTH 11 //this one may be 0 +#define PWRDN_LENGTH 4 + + +/* The AMD A55E (Hudson-E1) Southbridge contains an integrated Gigabit Ethernet + * MAC, however AMD's documentation merely defines the related balls (without + * fully describing their function) and states that only Broadcom 50610(M) PHYs + * will be supported, that's all. The Hudson register reference skips all MAC + * registers entirely, even AMD support doesn't seem to know more about it. + * + * As Broadcom refused to sell us any 50610 chips or provide any docs (or indeed + * even a price list) below $100K expected sales we had to figure out everything + * by ourselves. *Everything* below is the result of months of detective work, + * documented here lest it get lost: + * + * The AMD A55E's GbE MAC is a Broadcom 5785, which AMD obviously licensed as IP + * core. It uses a standard RGMII/MII interface and the Broadcom drivers will + * recognize it by its unchanged PCI ID 14E4:1699, however there are some + * specialties. + * + * The 5785 MAC can detect the link with 4 additional inputs, "phy_status[3:0]", + * 'snooping' on the PHY's LED outputs. Interpretation of the LEDs' patterns is + * programmed with register 0x5A4 of the MAC. AMD renamed them to "GBE_STAT" and + * won't say anything about their purpose. Appearently hardware designers are + * expected to blindly copy the Inagua reference schematic: GBE_STAT2: + * 0=activity; GBE_STAT[1:0]: 11=no link, 10=10Mbit, 01=100Mbit, 00=1Gbit. + * + * For package processing the 5785 also features a MIPS-based RISC CPU, booting + * from an internal ROM. The firmware loads config data and supplements (e.g. to + * support specific PHYs), named "Selfboot Patches", via the "NVRAM Interface", + * usually from an external EEPROM. The A55E doesn't have any balls for an ext. + * EEPROM, instead AMD added a small internal RAM. The BIOS is expected to copy + * the correct contents into this RAM (which only supports byte access!) upon + * each powerup. The A55E can trigger an SMI upon writes, enabling the BIOS to + * forward any changes to an actually 'NV' location, e.g. the BIOS's SPI flash, + * behind the scenes. AMD calls it "GEC shadow ROM", not describing what it's + * for nor mentioning the term "NVRAM". broadcom_init() below documents a + * procedure how to upload the patch. No SMI magic is installed, therefore + * 'NV'RAM writes won't be persistent. + * + * The "Selfboot Patch" can execute simple commands at various points during + * main firmware execution. This can be used to change config registers, + * initialize a specific PHY or work around firmware bugs. Broadcom provides + * suitable Patches only for their AC131 and 50610 PHYs (as binary blobs). I + * found them in DOS\sb_patch\5785\*\sb5785*.* in Driver_14_6_4_2.zip. (Note + * that every 32bit-word of these files must be byte-swapped before uploading + * them to the A55E.) + * + * Below is a derived Patch supporting the Micrel KSZ9021 PHY used on the + * LiPPERT CFR-AF PC/104 SBC instead, with detailled description of the format. + * (Here in correct order for upload.) + * + * This Patch made Ethernet work with Linux 3.3 - without having to modify the + * tg3.ko driver. Broadcom's Windows-Drivers still fail with "Code 10" however; + * disassembly showed they check the PHY ID and abort, because the Micrel PHY is + * not supported. + */ + +static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! + + struct { /* Global header */ + u8 signature; //0xA5 + u8 format; //bits 7-3: patch format; 2-0: revision + u8 mac_addr[6]; + u16 subsys_device; //IDs will be loaded into PCI config space + u16 subsys_vendor; + u16 pci_device; //PCI device ID; vendor is always Broadcom (0x14E4) + u8 unknown1[8]; //?, noticed no effect + u16 basic_config; //?, see below + u8 checksum; //byte sum of header == 0 + u8 unknown2; //?, patch rejected if changed + u16 patch_version; //10-8: major; 7-0: minor; 15-11: variant (1=a, 2=b, ...) + } header; + + struct { /* Init code */ + u8 checksum; //byte sum of init == 0 + u8 unknown; //?, looks unused + u8 num_hunks; //0x60 = 3 hunks, 0x80 = 4 hunks, other values not supported + u8 size; //total size of all hunk#_code[] in bytes + u8 hunk1_when; //mark when hunk1_code gets executed + u8 hunk1_size; //sizeof(hunk1_code) + u8 hunk2_when; + u8 hunk2_size; + u8 hunk3_when; + u8 hunk3_size; + u8 hunk4_when; //0x00 (padding) if only 3 hunks + u8 hunk4_size; //dito + u32 hunk1_code[INIT1_LENGTH]; //actual commands, see below + u32 hunk2_code[INIT2_LENGTH]; + u32 hunk3_code[INIT3_LENGTH]; + u32 hunk4_code[INIT4_LENGTH]; //missing (zero length) if only 3 hunks + } init; + + struct { /* Power down code */ + u8 checksum; //byte sum of powerdown == 0 + u8 unknown; //?, looks unused + u8 num_hunks; //0x20 = 1 hunk, other values not supported + u8 size; //total size of all hunk#_code[] in bytes + u8 hunk1_when; //mark when hunk1_code gets executed + u8 hunk1_size; //sizeof(hunk1_code) + u16 padding; //0x0000, hunk2 is not supported + u32 hunk1_code[PWRDN_LENGTH]; //commands, see below + } powerdown; + +} selfboot_patch = { + +/* Keep the following invariant for valid Selfboot patches */ + .header.signature = 0xA5, + .header.format = 0x23, //format 1 revision 3 + .header.unknown1 = { 0x61, 0xB1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + .header.checksum = 0, //calculated later + .header.unknown2 = 0x30, + .init.checksum = 0, //calculated later + .init.unknown = 0x00, + .init.num_hunks = sizeof(selfboot_patch.init.hunk4_code) ? 0x80 : 0x60, + .init.size = sizeof(selfboot_patch.init.hunk1_code) + + sizeof(selfboot_patch.init.hunk2_code) + + sizeof(selfboot_patch.init.hunk3_code) + + sizeof(selfboot_patch.init.hunk4_code), + .init.hunk1_size = sizeof(selfboot_patch.init.hunk1_code), + .init.hunk2_size = sizeof(selfboot_patch.init.hunk2_code), + .init.hunk3_size = sizeof(selfboot_patch.init.hunk3_code), + .init.hunk4_size = sizeof(selfboot_patch.init.hunk4_code), + .powerdown.checksum = 0, //calculated later + .powerdown.unknown = 0x00, + .powerdown.num_hunks = 0x20, + .powerdown.size = sizeof(selfboot_patch.powerdown.hunk1_code), + .powerdown.hunk1_size = sizeof(selfboot_patch.powerdown.hunk1_code), + .powerdown.padding = be16(0x0000), + +/* Only the lines below may be adapted to your needs ... */ + .header.mac_addr = { 0x00, 0x20, 0x9D, 0x00, 0x00, 0x00 }, //LiPPERT + .header.subsys_device = be16(0x1699), //simply kept this + .header.subsys_vendor = be16(0x121D), //LiPPERT + .header.pci_device = be16(0x1699), //Broadcom 5785 with GbE PHY + .header.patch_version = be16(0x110B), //1.11b, as this was based on Broadcom's sb5785m1.11 patch + /* Bitfield enabling general features/codepaths in the firmware or + * selecting support for one of several supported PHYs? + * Bits not listed had no appearent effect: + * 14-11: any bit 1=firmware execution seemed delayed + * 10: 0=firmware execution seemed delayed + * 9,2,0: select PHY type, affects these registers, probably more + * 9 2 0 | reg 0x05A4 PHY reg 31 PHY 23,24,28 Notes + * -------+---------------------------------------------------------- + * 0 0 0 | 0x331C71C1 - changed Inband Status enabled + * 0 1 0 | 0x3210C500 - changed - + * 0 X 1 | 0x33FF66C0 changed - 10/100 Mbit only + * 1 X 0 | 0x330C5180 - - - + * 1 X 1 | 0x391C6140 - - - + */ + .header.basic_config = be16(0x0604), //bit 9 set so not to mess up PHY regs, kept other bits unchanged + + /* Tag that defines when / on what occasion the commands are interpreted. + * Bits 2-0 = 0 i.e. possible values are 0x00, 08, 10, ..., F8. + * On a RISC CPU reset every tag except 0x38, A0, F0, F8 is used. 0x38 + * seems to be run before a reset is performed(?), the other 3 I have + * never seen used. Generally, lower values appear to be run earlier. + * An "ifconfig up" with Linux' "tg3" driver causes the tags 0x50, 60, + * 68, 20, 70, 80 to be interpreted in this order. + * All tests were performed with .basic_config=0x0604. + */ + .init.hunk1_when = 0x10, //only once at RISC CPU reset? + /* Instructions are obviously a specialized bytecode interpreted by the + * main firmware, rather than MIPS machine code. Commands consist of 1-3 + * 32-bit words. In the following, 0-9,A-F = hex literals, a-z,_ = variable + * parts, each character = 4 bits. + * 0610offs newvalue: write (32-bit) <newvalue> to 5785-internal shared mem at <offs> + * 08rgvalu: write <valu> to PHY register, <rg> = 0x20 + register number + * C610rgnr newvalue: write <newvalue> to MAC register <rgnr> + * C1F0rgnr andvalue or_value: modify MAC register <rgnr> by ANDing with <andvalue> and then ORing with <or_value> + * C4btrgnr: clear bit in 32-bit MAC register <rgnr>, <bt> = bit number << 3 + * C3btrgnr: set bit, see C4...; example: command 0xC3200454 sets bit 4 of 32-bit register 0x0454 + * CBbtrgnr: run next command only if bit (see C4...) == 1 (so far only seen before F7F0...) + * F7F0skip: unconditional jump i.e. skip next <skip> code bytes (only seen small positive <skip>) + * F7Fxaddr: call function at <addr> in main firmware? <x> = 3 or 4, bool parameter?? Wild guess! + * F7FFFadr somvalue: also call func. at <adr>, but with <somvalue> as parameter?? More guessing! + * More commands probably exist, but all code I've ever seen was kept + * included below, commented out if not suitable for the CFR-AF. v1.xx + * is Broadcom's Selfboot patch version sb5785m1.xx where the command + * was added, for reference see Broadcom's changelog. + */ + .init.hunk1_code = { + be(0x082B8104), //CFR-AF: PHY0B: KSZ9021 select PHY104 + be(0x082CF0F0), //CFR-AF: PHY0C: KSZ9021 clk/ctl skew (advised by Micrel) + be(0x082B8105), //CFR-AF: PHY0B: KSZ9021 select PHY105 + be(0x082C3333), //CFR-AF: PHY0C: KSZ9021 RX data skew (empirical) + be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), //v1.05 : 5A0.24,12=1: auto-clock-switch + be(0x06100D34), be(0x00000000), //v1.03 : MemD34: clear config vars + be(0x06100D38), be(0x00000000), //v1.03 : - | + be(0x06100D3C), be(0x00000000), //v1.03 : MemD3F| + }, //-->INIT1_LENGTH! + + .init.hunk2_when = 0x30, //after global reset, PHY reset + .init.hunk2_code = { + //be(0x08370F08), //v1.06 : PHY17: B50610 select reg. 08 + //be(0x08350001), //v1.06 : PHY15: B50610 slow link fix + //be(0x08370F00), //v1.06 : PHY17: B50610 disable reg. 08 + //be(0x083C2C00), //v1.11 : PHY1C: B50610 Shadow 0B + be(0xF7F301E6), //v1.09+: ?: subroutine calls to + be(0xF7FFF0B6), be(0x0000FFE7), //v1.09+: ?| restore Port Mode ??? + be(0xF7FFF0F6), be(0x00008000), //v1.09+: ?| + be(0xF7F401E6), //v1.09+: ?| + }, //-->INIT2_LENGTH! + + .init.hunk3_when = 0xA8, //?, I'd guess quite late + .init.hunk3_code = { + be(0xC1F03604), be(0xFFE0FFFF), be(0x00110000), //v1.08 : 3604.20-16: 10Mb clock = 12.5MHz + }, //-->INIT3_LENGTH! + + //.init.hunk4_when = 0xD8, //was used in B50610 GPHY Selfboot patch v1.11 this is based on + .init.hunk4_when = 0x80, //run last, after Linux' "ifconfig up" + .init.hunk4_code = { + be(0x083F4300), //CFR-AF: PHY1F: IRQ active high + be(0x083C0000), //CFR-AF: PHY1C: revert driver writes + be(0x08380000), //CFR-AF: PHY18| + be(0x083C0000), //CFR-AF: PHY1C| + be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0==1 -->skip next 12 bytes + //be(0xC61005A4), be(0x3210C500), //v1.01 : 5A4: PHY LED mode + be(0xC61005A4), be(0x331C71CE), //CFR-AF: 5A4: fake LED mode + be(0xF7F00008), //v1.01 : -->skip next 8 bytes + be(0xC61005A4), be(0x331C71C1), //v1.01 : 5A4: inband LED mode + //be(0xC3200454), //CFR-AF: 454.4: auto link polling + }, //-->INIT4_LENGTH! + + .powerdown.hunk1_when = 0x50, //prior to IDDQ MAC + .powerdown.hunk1_code = { + //be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY + be(0xF7F30116), // IDDQ PHY + be(0xC40005A0), //v1.09 : 5A0.0=0: Port Mode = MII + be(0xC4180400), //v1.09 : 400.3=0| + be(0xC3100400), //v1.09 : 400.2=1| + }, //-->PWRDN_LENGTH! + +}; + +/* Upload 'NV'RAM contents for BCM5785 GbE MAC integrated in A55E. + * Call this from mainboard.c. + */ +void broadcom_init(void) +{ + volatile u32 *gec_base; //Gigabit Ethernet Controller base addr + u8 *gec_shadow; //base addr of shadow 'NV'RAM for GbE MAC in A55E + u8 sum; + int i; + + gec_base = (u32*)(long)dev_find_slot(0, PCI_DEVFN(0x14, 6))->resource_list->base; + gec_shadow = (u8*)(pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x14, 3)), 0x9C) & 0xFFFFFC00); + printk(BIOS_DEBUG, "Upload GbE 'NV'RAM contents @ 0x%08lx\n", (unsigned long)gec_shadow); + + /* Halt RISC CPU before uploading the firmware patch */ + for (i=10000; i > 0; i--) { + gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state + gec_base[0x5000/4] |= (1<<10); //issue RISC halt + if (gec_base[0x5000/4] | (1<<10)) + break; + udelay(10); + } + if (!i) + printk(BIOS_ERR, "Failed to halt RISC CPU!\n"); + + /* Calculate checksums (standard byte sum) */ + for (sum = 0, i = 0; i < sizeof(selfboot_patch.header); i++) + sum -= ((u8*)&selfboot_patch.header)[i]; + selfboot_patch.header.checksum = sum; + for (sum = 0, i = 0; i < sizeof(selfboot_patch.init); i++) + sum -= ((u8*)&selfboot_patch.init)[i]; + selfboot_patch.init.checksum = sum; + for (sum = 0, i = 0; i < sizeof(selfboot_patch.powerdown); i++) + sum -= ((u8*)&selfboot_patch.powerdown)[i]; + selfboot_patch.powerdown.checksum = sum; + + /* Upload firmware patch to shadow 'NV'RAM */ + for (i = 0; i < sizeof(selfboot_patch); i++) + gec_shadow[i] = ((u8*)&selfboot_patch)[i]; //access byte-wise! + + /* Restart BCM5785's CPU */ + gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state + gec_base[0x5000/4] = 0x00000001; //reset RISC processor + //usually we'd have to wait for the reset bit to clear again ... +} diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 83c90f3..ed91a03 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -32,6 +32,8 @@ #include "SBPLATFORM.h" #include "OEM.h" /* SMBUS0_BASE_ADDRESS */ +//#include "broadcom.c" /* only needed for CFR-AF 0v0 prototype */ + /* Init SIO GPIOs. */ #define SIO_RUNTIME_BASE 0x0E00 static const u16 sio_init_table[] = { // hi=offset, lo=value @@ -123,6 +125,10 @@ static void init(struct device *dev) outb((u8)val, SIO_RUNTIME_BASE + (val >> 8)); } + /* Upload AMD A55E GbE 'NV'RAM contents. Only needed on CFR-AF revision + * 0v0 (prototype), not for any later production versions. */ + //broadcom_init(); + /* Notify the SMC we're alive and kicking, or after a while it will * effect a power cycle and switch to the alternate BIOS chip. * Should be done as late as possible. */

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Re: [coreboot] i915 status on x60.
by Denis 'GNUtoo' Carikli 04 Mar '13

04 Mar '13

On Sun, 3 Mar 2013 22:58:46 -0500 ron minnich <rminnich(a)gmail.com> wrote: > setgtt is only for hardware with a gtt. Again, I'm not familiar with > the hardware on this laptop. Does it have a gtt? it seems so(from the xf86-video-intel mentioned before): if (IS_G4X(pI830)) gtt = (unsigned char *)(pI830->mmio + MB(2)); else if (IS_I965G(pI830)) gtt = (unsigned char *)(pI830->mmio + KB(512)); else { /* 915/945 chips has GTT range in bar 3*/ int err = 0; err = pci_device_map_range (pI830->pci_dev, pI830->pci_dev->regions[3].base_addr, pI830->pci_dev->regions[3].size, PCI_DEV_MAP_FLAG_WRITABLE, (void **)&gtt); if (err != 0) { fprintf(stderr, "mapping GTT bar failed\n"); exit(1); } } So the GTT would be on the bar 3: # lspci -s 00:02.0 -vvvv 00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller (rev 03) (prog-if 00 [VGA controller]) Subsystem: Lenovo ThinkPad T60/R60 series Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx+ Latency: 0 Interrupt: pin A routed to IRQ 11 Region 0: Memory at e4200000 (32-bit, non-prefetchable) [size=512K] Region 1: I/O ports at 50a0 [size=8] Region 2: Memory at d0000000 (32-bit, prefetchable) [size=256M] Region 3: Memory at e4300000 (32-bit, non-prefetchable) [size=256K] Expansion ROM at <unassigned> [disabled] Capabilities: [90] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- And the datasheets for the 945G also talks about the GTT like the GTTADR registers etc... Denis.

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Patch merged into coreboot/master: 1a43309 bump SeaBIOS to 1.7.2.1
by gerrit＠coreboot.org 04 Mar '13

04 Mar '13

the following patch was just integrated into master: commit 1a43309bf7222fc25e8583d128c9685ec251dd76 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sat Mar 2 18:27:05 2013 +0100 bump SeaBIOS to 1.7.2.1 Update coreboot to use SeaBIOS' tag rel-1.7.2.1 Change-Id: I01969407964a7cf64f7c4800b59c6aed845b24f9 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Reviewed-on: http://review.coreboot.org/2575 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Mon Mar 4 11:00:17 2013, giving +2 See http://review.coreboot.org/2575 for details. -gerrit

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Patch set updated for coreboot: 0fd9295 Google Link: Add remaining code to support native graphics
by Paul Menzel 04 Mar '13

04 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2531 -gerrit commit 0fd9295968ec5ec619923fa39239fd6f92f657a5 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Feb 26 10:07:40 2013 -0800 Google Link: Add remaining code to support native graphics The Link native graphics commit 49428d84 [1] Add support for Google's Chromebook Pixel was missing some of the higher level bits, and hence could not be used. This is not new code -- it has been working since last August -- so the effort now is to get it into the tree and structure it in a way compatible with upstream coreboot. 1. Add options to src/device/Kconfig to enable native graphics. 2. Export the MTRR function for setting variable MTRRs. 3. Clean up some of the comments and white space. While I realize that the product name is Pixel, the mainboard in the coreboot tree is called Link, and that name is what we will use in our commits. [1] http://review.coreboot.org/2482 Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/boot/coreboot_table.c | 2 +- src/cpu/x86/mtrr/mtrr.c | 2 +- src/device/Kconfig | 26 ++++++++++++++----- src/device/oprom/realmode/x86.c | 4 +-- src/include/cpu/x86/mtrr.h | 7 ++++++ src/northbridge/intel/sandybridge/gma.c | 44 +++++++++++++++++++++++++++------ 6 files changed, 67 insertions(+), 18 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index e456e1e..d6d579f 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -172,7 +172,7 @@ static void lb_console(struct lb_header *header) static void lb_framebuffer(struct lb_header *header) { -#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE +#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE || defined(CONFIG_MAINBOARD_DO_NATIVE_INIT) void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); int vbe_mode_info_valid(void); diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index a061b54..5051904 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -83,7 +83,7 @@ static void enable_var_mtrr(void) } /* setting variable mtrr, comes from linux kernel source */ -static void set_var_mtrr( +void set_var_mtrr( unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type, unsigned address_bits) { diff --git a/src/device/Kconfig b/src/device/Kconfig index 8e1265f..f7eac8d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -19,12 +19,26 @@ ## menu "Devices" + +# Only set this in the mainboard +config MAINBOARD_HAS_NATIVE_VGA_INIT + bool + default n + +config MAINBOARD_DO_NATIVE_VGA_INIT + bool "use Native graphics setup code" + depends on MAINBOARD_HAS_NATIVE_VGA_INIT + default n + help + Enable mainboard code to turn on graphics, but without needing a video BIOS. + This mode is only supported on some mainboards, such as the Google Link. + # TODO: Explain differences (if any) for onboard cards. config VGA_ROM_RUN bool "Run VGA Option ROMs" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !PAYLOAD_SEABIOS || EXPERT + depends on (!MAINBOARD_DO_NATIVE_VGA_INIT) && PCI && !PAYLOAD_SEABIOS || EXPERT help Execute VGA Option ROMs in coreboot if found. This is required to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS @@ -94,7 +108,7 @@ choice config PCI_OPTION_ROM_RUN_REALMODE prompt "Native mode" bool - depends on ARCH_X86 + depends on ARCH_X86 && !MAINBOARD_DO_NATIVE_VGA_INIT help If you select this option, PCI Option ROMs will be executed natively on the CPU in real mode. No CPU emulation is involved, @@ -104,7 +118,7 @@ config PCI_OPTION_ROM_RUN_REALMODE config PCI_OPTION_ROM_RUN_YABEL prompt "Secure mode" bool - depends on !GEODE_VSA + depends on !GEODE_VSA && !MAINBOARD_DO_NATIVE_VGA_INIT help If you select this option, the x86emu CPU emulator will be used to execute PCI Option ROMs. @@ -282,12 +296,12 @@ config MBI_FILE endmenu menu "Display" - depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT config FRAMEBUFFER_SET_VESA_MODE prompt "Set VESA framebuffer mode" bool - depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT help Set VESA framebuffer mode (needed for bootsplash) @@ -425,7 +439,7 @@ config FRAMEBUFFER_VESA_MODE config FRAMEBUFFER_KEEP_VESA_MODE prompt "Keep VESA framebuffer" bool - depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT help This option keeps the framebuffer mode set after coreboot finishes execution. If this option is enabled, coreboot will pass a diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 5fd11b5..6a8bdfc 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -191,7 +191,7 @@ static void setup_realmode_idt(void) write_idt_stub((void *)0xffe6e, 0x1a); } -#if CONFIG_FRAMEBUFFER_SET_VESA_MODE +#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT vbe_mode_info_t mode_info; static int mode_info_valid; @@ -322,7 +322,7 @@ void run_bios(struct device *dev, unsigned long addr) realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, 0x0); printk(BIOS_DEBUG, "... Option ROM returned.\n"); -#if CONFIG_FRAMEBUFFER_SET_VESA_MODE +#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT if ((dev->class >> 8)== PCI_CLASS_DISPLAY_VGA) vbe_set_graphics(); #endif diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 58bee04..dcb7075 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -40,6 +40,13 @@ #if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__) #include <device/device.h> +/* You should almost NEVER use this function. + * N.B. We worked on a lot of ways to make this continue as static, + * but just making it available ended up being the simplest solution. + */ +void set_var_mtrr( + unsigned int reg, unsigned long basek, unsigned long sizek, + unsigned char type, unsigned address_bits); void enable_fixed_mtrr(void); void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); void x86_setup_mtrrs(void); diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index f35299e..1770710 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -23,6 +23,9 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include "chip.h" #include "sandybridge.h" @@ -619,20 +622,44 @@ static void gma_pm_init_post_vbios(struct device *dev) static void gma_func0_init(struct device *dev) { u32 reg32; + u32 graphics_base, graphics_size; /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); + /* Set up an MTRR to make anything the VBIOS does run fast. */ + /* We have agreed on MTRR #8. */ + graphics_base = dev->resource_list[1].base; + graphics_size = dev->resource_list[1].size; + printk(BIOS_DEBUG, "Set graphics %p size 0x%x\n", + (void *)graphics_base, graphics_size); + set_var_mtrr(8, graphics_base>>10, graphics_size>>10, MTRR_TYPE_WRCOMB, 0x24); + /* Init graphics power management */ gma_pm_init_pre_vbios(dev); /* PCI Init, will run VBIOS */ +#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + printk(BIOS_SPEW, "Run the VBIOS init\n"); pci_dev_init(dev); +#endif /* Post VBIOS init */ gma_pm_init_post_vbios(dev); + +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); + u32 iobase, mmiobase, physbase; + iobase = dev->resource_list[2].base; + mmiobase = dev->resource_list[0].base; + physbase = pci_read_config32(dev, 0x5c) & ~0xf; + + int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); + i915lightup(physbase, iobase, mmiobase, graphics_base); +#endif + } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -660,12 +687,13 @@ static struct device_operations gma_func0_ops = { .ops_pci = &gma_pci_ops, }; -static const unsigned short gma_ids[] = { - 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, 0x0156, 0x166, - 0, -}; -static const struct pci_driver gma_gt1_desktop __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices= gma_ids, +static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112, + 0x0116, 0x0122, 0x0126, 0x0156, + 0x0166, + 0 }; + +static const struct pci_driver pch_lpc __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, };

1 0

Patch set updated for coreboot: 565c619 Google/Link: Add remaining code to support native link graphics
by Ronald G. Minnich 04 Mar '13

04 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2531 -gerrit commit 565c619c064e1baed34414be5b666a8ef8965b7a Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Feb 26 10:07:40 2013 -0800 Google/Link: Add remaining code to support native link graphics The link native graphics commit was missing some of the higher level bits, and hence could not be used. This is not new code -- it has been working since last August -- so the effort now is to get it into the tree and structure it in a way compatible with upstream coreboot. Add options to src/device/Kconfig to enable native graphics. Export the mtrr function for setting variable mtrrs. Clean up some of the comments and white space. While I realize that the product name is Pixel, the mainboard in the coreboot tree is called link, and that name is what we will use in our commits. Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/boot/coreboot_table.c | 2 +- src/cpu/x86/mtrr/mtrr.c | 2 +- src/device/Kconfig | 26 ++++++++++++++----- src/device/oprom/realmode/x86.c | 4 +-- src/include/cpu/x86/mtrr.h | 7 ++++++ src/northbridge/intel/sandybridge/gma.c | 44 +++++++++++++++++++++++++++------ 6 files changed, 67 insertions(+), 18 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index e456e1e..d6d579f 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -172,7 +172,7 @@ static void lb_console(struct lb_header *header) static void lb_framebuffer(struct lb_header *header) { -#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE +#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE || defined(CONFIG_MAINBOARD_DO_NATIVE_INIT) void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); int vbe_mode_info_valid(void); diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index a061b54..5051904 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -83,7 +83,7 @@ static void enable_var_mtrr(void) } /* setting variable mtrr, comes from linux kernel source */ -static void set_var_mtrr( +void set_var_mtrr( unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type, unsigned address_bits) { diff --git a/src/device/Kconfig b/src/device/Kconfig index 8e1265f..f7eac8d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -19,12 +19,26 @@ ## menu "Devices" + +# Only set this in the mainboard +config MAINBOARD_HAS_NATIVE_VGA_INIT + bool + default n + +config MAINBOARD_DO_NATIVE_VGA_INIT + bool "use Native graphics setup code" + depends on MAINBOARD_HAS_NATIVE_VGA_INIT + default n + help + Enable mainboard code to turn on graphics, but without needing a video BIOS. + This mode is only supported on some mainboards, such as the Google Link. + # TODO: Explain differences (if any) for onboard cards. config VGA_ROM_RUN bool "Run VGA Option ROMs" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !PAYLOAD_SEABIOS || EXPERT + depends on (!MAINBOARD_DO_NATIVE_VGA_INIT) && PCI && !PAYLOAD_SEABIOS || EXPERT help Execute VGA Option ROMs in coreboot if found. This is required to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS @@ -94,7 +108,7 @@ choice config PCI_OPTION_ROM_RUN_REALMODE prompt "Native mode" bool - depends on ARCH_X86 + depends on ARCH_X86 && !MAINBOARD_DO_NATIVE_VGA_INIT help If you select this option, PCI Option ROMs will be executed natively on the CPU in real mode. No CPU emulation is involved, @@ -104,7 +118,7 @@ config PCI_OPTION_ROM_RUN_REALMODE config PCI_OPTION_ROM_RUN_YABEL prompt "Secure mode" bool - depends on !GEODE_VSA + depends on !GEODE_VSA && !MAINBOARD_DO_NATIVE_VGA_INIT help If you select this option, the x86emu CPU emulator will be used to execute PCI Option ROMs. @@ -282,12 +296,12 @@ config MBI_FILE endmenu menu "Display" - depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT config FRAMEBUFFER_SET_VESA_MODE prompt "Set VESA framebuffer mode" bool - depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT help Set VESA framebuffer mode (needed for bootsplash) @@ -425,7 +439,7 @@ config FRAMEBUFFER_VESA_MODE config FRAMEBUFFER_KEEP_VESA_MODE prompt "Keep VESA framebuffer" bool - depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT help This option keeps the framebuffer mode set after coreboot finishes execution. If this option is enabled, coreboot will pass a diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 5fd11b5..6a8bdfc 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -191,7 +191,7 @@ static void setup_realmode_idt(void) write_idt_stub((void *)0xffe6e, 0x1a); } -#if CONFIG_FRAMEBUFFER_SET_VESA_MODE +#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT vbe_mode_info_t mode_info; static int mode_info_valid; @@ -322,7 +322,7 @@ void run_bios(struct device *dev, unsigned long addr) realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, 0x0); printk(BIOS_DEBUG, "... Option ROM returned.\n"); -#if CONFIG_FRAMEBUFFER_SET_VESA_MODE +#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT if ((dev->class >> 8)== PCI_CLASS_DISPLAY_VGA) vbe_set_graphics(); #endif diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 58bee04..dcb7075 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -40,6 +40,13 @@ #if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__) #include <device/device.h> +/* You should almost NEVER use this function. + * N.B. We worked on a lot of ways to make this continue as static, + * but just making it available ended up being the simplest solution. + */ +void set_var_mtrr( + unsigned int reg, unsigned long basek, unsigned long sizek, + unsigned char type, unsigned address_bits); void enable_fixed_mtrr(void); void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); void x86_setup_mtrrs(void); diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index f35299e..1770710 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -23,6 +23,9 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include "chip.h" #include "sandybridge.h" @@ -619,20 +622,44 @@ static void gma_pm_init_post_vbios(struct device *dev) static void gma_func0_init(struct device *dev) { u32 reg32; + u32 graphics_base, graphics_size; /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); + /* Set up an MTRR to make anything the VBIOS does run fast. */ + /* We have agreed on MTRR #8. */ + graphics_base = dev->resource_list[1].base; + graphics_size = dev->resource_list[1].size; + printk(BIOS_DEBUG, "Set graphics %p size 0x%x\n", + (void *)graphics_base, graphics_size); + set_var_mtrr(8, graphics_base>>10, graphics_size>>10, MTRR_TYPE_WRCOMB, 0x24); + /* Init graphics power management */ gma_pm_init_pre_vbios(dev); /* PCI Init, will run VBIOS */ +#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + printk(BIOS_SPEW, "Run the VBIOS init\n"); pci_dev_init(dev); +#endif /* Post VBIOS init */ gma_pm_init_post_vbios(dev); + +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); + u32 iobase, mmiobase, physbase; + iobase = dev->resource_list[2].base; + mmiobase = dev->resource_list[0].base; + physbase = pci_read_config32(dev, 0x5c) & ~0xf; + + int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); + i915lightup(physbase, iobase, mmiobase, graphics_base); +#endif + } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -660,12 +687,13 @@ static struct device_operations gma_func0_ops = { .ops_pci = &gma_pci_ops, }; -static const unsigned short gma_ids[] = { - 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, 0x0156, 0x166, - 0, -}; -static const struct pci_driver gma_gt1_desktop __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices= gma_ids, +static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112, + 0x0116, 0x0122, 0x0126, 0x0156, + 0x0166, + 0 }; + +static const struct pci_driver pch_lpc __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, };

1 0

Patch set updated for coreboot: 0e7c837 Google/Link: Add remaining code to support native link graphics
by Ronald G. Minnich 04 Mar '13

04 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2531 -gerrit commit 0e7c8379a36bc4bdb1ab19ba62d48adc3ee51bdd Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Feb 26 10:07:40 2013 -0800 Google/Link: Add remaining code to support native link graphics The link native graphics commit was missing some of the higher level bits, and hence could not be used. This is not new code -- it has been working since last August -- so the effort now is to get it into the tree and structure it in a way compatible with upstream coreboot. Add options to src/device/Kconfig to enable native graphics. Export the mtrr function for setting variable mtrrs. Clean up some of the comments and white space. While I realize that the produce name is Pixel, the mainboard in the coreboot tree is called link, and that name is what we will use in our commits. Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/boot/coreboot_table.c | 2 +- src/cpu/x86/mtrr/mtrr.c | 2 +- src/device/Kconfig | 26 ++++++++++++++----- src/device/oprom/realmode/x86.c | 4 +-- src/include/cpu/x86/mtrr.h | 7 ++++++ src/northbridge/intel/sandybridge/gma.c | 44 +++++++++++++++++++++++++++------ 6 files changed, 67 insertions(+), 18 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index e456e1e..d6d579f 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -172,7 +172,7 @@ static void lb_console(struct lb_header *header) static void lb_framebuffer(struct lb_header *header) { -#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE +#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE || defined(CONFIG_MAINBOARD_DO_NATIVE_INIT) void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); int vbe_mode_info_valid(void); diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index a061b54..5051904 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -83,7 +83,7 @@ static void enable_var_mtrr(void) } /* setting variable mtrr, comes from linux kernel source */ -static void set_var_mtrr( +void set_var_mtrr( unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type, unsigned address_bits) { diff --git a/src/device/Kconfig b/src/device/Kconfig index 8e1265f..f7eac8d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -19,12 +19,26 @@ ## menu "Devices" + +# Only set this in the mainboard +config MAINBOARD_HAS_NATIVE_VGA_INIT + bool + default n + +config MAINBOARD_DO_NATIVE_VGA_INIT + bool "use Native graphics setup code" + depends on MAINBOARD_HAS_NATIVE_VGA_INIT + default n + help + Enable mainboard code to turn on graphics, but without needing a video BIOS. + This mode is only supported on some mainboards, such as the Google Link. + # TODO: Explain differences (if any) for onboard cards. config VGA_ROM_RUN bool "Run VGA Option ROMs" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !PAYLOAD_SEABIOS || EXPERT + depends on (!MAINBOARD_DO_NATIVE_VGA_INIT) && PCI && !PAYLOAD_SEABIOS || EXPERT help Execute VGA Option ROMs in coreboot if found. This is required to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS @@ -94,7 +108,7 @@ choice config PCI_OPTION_ROM_RUN_REALMODE prompt "Native mode" bool - depends on ARCH_X86 + depends on ARCH_X86 && !MAINBOARD_DO_NATIVE_VGA_INIT help If you select this option, PCI Option ROMs will be executed natively on the CPU in real mode. No CPU emulation is involved, @@ -104,7 +118,7 @@ config PCI_OPTION_ROM_RUN_REALMODE config PCI_OPTION_ROM_RUN_YABEL prompt "Secure mode" bool - depends on !GEODE_VSA + depends on !GEODE_VSA && !MAINBOARD_DO_NATIVE_VGA_INIT help If you select this option, the x86emu CPU emulator will be used to execute PCI Option ROMs. @@ -282,12 +296,12 @@ config MBI_FILE endmenu menu "Display" - depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT config FRAMEBUFFER_SET_VESA_MODE prompt "Set VESA framebuffer mode" bool - depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT help Set VESA framebuffer mode (needed for bootsplash) @@ -425,7 +439,7 @@ config FRAMEBUFFER_VESA_MODE config FRAMEBUFFER_KEEP_VESA_MODE prompt "Keep VESA framebuffer" bool - depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT help This option keeps the framebuffer mode set after coreboot finishes execution. If this option is enabled, coreboot will pass a diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 5fd11b5..6a8bdfc 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -191,7 +191,7 @@ static void setup_realmode_idt(void) write_idt_stub((void *)0xffe6e, 0x1a); } -#if CONFIG_FRAMEBUFFER_SET_VESA_MODE +#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT vbe_mode_info_t mode_info; static int mode_info_valid; @@ -322,7 +322,7 @@ void run_bios(struct device *dev, unsigned long addr) realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, 0x0); printk(BIOS_DEBUG, "... Option ROM returned.\n"); -#if CONFIG_FRAMEBUFFER_SET_VESA_MODE +#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT if ((dev->class >> 8)== PCI_CLASS_DISPLAY_VGA) vbe_set_graphics(); #endif diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 58bee04..dcb7075 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -40,6 +40,13 @@ #if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__) #include <device/device.h> +/* You should almost NEVER use this function. + * N.B. We worked on a lot of ways to make this continue as static, + * but just making it available ended up being the simplest solution. + */ +void set_var_mtrr( + unsigned int reg, unsigned long basek, unsigned long sizek, + unsigned char type, unsigned address_bits); void enable_fixed_mtrr(void); void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); void x86_setup_mtrrs(void); diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index f35299e..1770710 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -23,6 +23,9 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include "chip.h" #include "sandybridge.h" @@ -619,20 +622,44 @@ static void gma_pm_init_post_vbios(struct device *dev) static void gma_func0_init(struct device *dev) { u32 reg32; + u32 graphics_base, graphics_size; /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); + /* Set up an MTRR to make anything the VBIOS does run fast. */ + /* We have agreed on MTRR #8. */ + graphics_base = dev->resource_list[1].base; + graphics_size = dev->resource_list[1].size; + printk(BIOS_DEBUG, "Set graphics %p size 0x%x\n", + (void *)graphics_base, graphics_size); + set_var_mtrr(8, graphics_base>>10, graphics_size>>10, MTRR_TYPE_WRCOMB, 0x24); + /* Init graphics power management */ gma_pm_init_pre_vbios(dev); /* PCI Init, will run VBIOS */ +#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + printk(BIOS_SPEW, "Run the VBIOS init\n"); pci_dev_init(dev); +#endif /* Post VBIOS init */ gma_pm_init_post_vbios(dev); + +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); + u32 iobase, mmiobase, physbase; + iobase = dev->resource_list[2].base; + mmiobase = dev->resource_list[0].base; + physbase = pci_read_config32(dev, 0x5c) & ~0xf; + + int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); + i915lightup(physbase, iobase, mmiobase, graphics_base); +#endif + } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -660,12 +687,13 @@ static struct device_operations gma_func0_ops = { .ops_pci = &gma_pci_ops, }; -static const unsigned short gma_ids[] = { - 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, 0x0156, 0x166, - 0, -}; -static const struct pci_driver gma_gt1_desktop __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices= gma_ids, +static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112, + 0x0116, 0x0122, 0x0126, 0x0156, + 0x0166, + 0 }; + +static const struct pci_driver pch_lpc __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, };

1 0

Patch set updated for coreboot: 3216a32 libpayload: Turn on thumb interworking in libpayload.
by Ronald G. Minnich 04 Mar '13

04 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2567 -gerrit commit 3216a32d385ddb481a58f4e96a6fd82beebe13de Author: Gabe Black <gabeblack(a)google.com> Date: Fri Mar 1 03:22:22 2013 -0800 libpayload: Turn on thumb interworking in libpayload. Things work better with it turned on, and the overhead should be negligable. Built and booted into depthcharge on Snow. Verified that calling between various bits of thumb and ARM code worked correctly. Change-Id: I08d1006e113d2cca08634bf19240aca138a449d9 Signed-off-by: Gabe Black <gabeblack(a)google.com> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- payloads/libpayload/util/xcompile/xcompile | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/payloads/libpayload/util/xcompile/xcompile b/payloads/libpayload/util/xcompile/xcompile index b431d8a..62e7a38 100644 --- a/payloads/libpayload/util/xcompile/xcompile +++ b/payloads/libpayload/util/xcompile/xcompile @@ -109,11 +109,9 @@ detect_special_flags() { arm ) # testcc "$CC" "$CFLAGS -mcpu=cortex-a9" && # CFLAGS="$CFLAGS -mcpu=cortex-a9" - testcc "$CC" "\ -$CFLAGS -ffixed-r8 -msoft-float -marm -mabi=aapcs-linux \ --mno-thumb-interwork -march=armv7 -mno-thumb-interwork" && CFLAGS="\ -$CFLAGS -ffixed-r8 -msoft-float -marm -mabi=aapcs-linux \ --mno-thumb-interwork -march=armv7 -mno-thumb-interwork" + testcc "$CC" \ +"$CFLAGS -ffixed-r8 -msoft-float -marm -mabi=aapcs-linux -march=armv7" && +CFLAGS="$CFLAGS -ffixed-r8 -msoft-float -marm -mabi=aapcs-linux -march=armv7" ;; esac }

1 0

Patch set updated for coreboot: 2d32fdd libpayload: Catch exceptions and print out an error message.
by Ronald G. Minnich 04 Mar '13

04 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2569 -gerrit commit 2d32fddd3636034f4dadf3f8c477fb732e284a82 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sun Mar 3 20:52:05 2013 -0800 libpayload: Catch exceptions and print out an error message. Give some indication what happened instead of just crashing. As part of setup, cause an exception and make sure that we get the right one, and that we recover correctly. Hence we have some assurance that if they really happen we can handle them. Built and booted into test payload on Snow. Saw the built in test function worked correctly. Artificially added code which got an exception and saw that the error information print correctly. Change-Id: I2e0d022f090ee422fb988074fbb197afa2485caa Signed-off-by: Gabe Black <gabeblack(a)google.com> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- payloads/libpayload/arch/armv7/Makefile.inc | 1 + payloads/libpayload/arch/armv7/exception.c | 155 +++++++++++++++++++++ payloads/libpayload/arch/armv7/exception_asm.S | 115 +++++++++++++++ payloads/libpayload/arch/armv7/main.c | 3 + payloads/libpayload/include/armv7/arch/exception.h | 38 +++++ 5 files changed, 312 insertions(+) diff --git a/payloads/libpayload/arch/armv7/Makefile.inc b/payloads/libpayload/arch/armv7/Makefile.inc index 6d9e6c5..da0030e 100644 --- a/payloads/libpayload/arch/armv7/Makefile.inc +++ b/payloads/libpayload/arch/armv7/Makefile.inc @@ -32,4 +32,5 @@ libc-y += main.c sysinfo.c libc-y += timer.c coreboot.c util.S libc-y += virtual.c libc-y += memcpy.S memset.S +libc-y += exception_asm.S exception.c diff --git a/payloads/libpayload/arch/armv7/exception.c b/payloads/libpayload/arch/armv7/exception.c new file mode 100644 index 0000000..8462b11 --- /dev/null +++ b/payloads/libpayload/arch/armv7/exception.c @@ -0,0 +1,155 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/exception.h> +#include <libpayload.h> +#include <stdint.h> + +void exception_test(void); + +static int test_abort; + +void exception_undefined_instruction(uint32_t *); +void exception_software_interrupt(uint32_t *); +void exception_prefetch_abort(uint32_t *); +void exception_data_abort(uint32_t *); +void exception_not_used(uint32_t *); +void exception_irq(uint32_t *); +void exception_fiq(uint32_t *); + +static void print_regs(uint32_t *regs) +{ + /* Don't print the link register and stack pointer since we don't have their + * actual value. They are hidden by the 'shadow' registers provided + * by the trap hardware. + */ + for (int i = 0; i < 16; i++) { + if (i == 15) + printf("PC"); + else if (i == 14) + continue; /* LR */ + else if (i == 13) + continue; /* SP */ + else if (i == 12) + printf("IP"); + else + printf("R%d", i); + printf(" = 0x%08x\n", regs[i]); + } +} + +void exception_undefined_instruction(uint32_t *regs) +{ + printf("exception _undefined_instruction\n"); + print_regs(regs); + halt(); +} + +void exception_software_interrupt(uint32_t *regs) +{ + printf("exception _software_interrupt\n"); + print_regs(regs); + halt(); +} + +void exception_prefetch_abort(uint32_t *regs) +{ + printf("exception _prefetch_abort\n"); + print_regs(regs); + halt(); +} + +void exception_data_abort(uint32_t *regs) +{ + if (test_abort) { + regs[15] = regs[0]; + return; + } else { + printf("exception _data_abort\n"); + print_regs(regs); + } + halt(); +} + +void exception_not_used(uint32_t *regs) +{ + printf("exception _not_used\n"); + print_regs(regs); + halt(); +} + +void exception_irq(uint32_t *regs) +{ + printf("exception _irq\n"); + print_regs(regs); + halt(); +} + +void exception_fiq(uint32_t *regs) +{ + printf("exception _fiq\n"); + print_regs(regs); + halt(); +} + +static inline uint32_t get_sctlr(void) +{ + uint32_t val; + asm("mrc p15, 0, %0, c1, c0, 0" : "=r" (val)); + return val; +} + +static inline void set_sctlr(uint32_t val) +{ + asm volatile("mcr p15, 0, %0, c1, c0, 0" :: "r" (val)); + asm volatile("" ::: "memory"); +} + +void exception_init(void) +{ + static const uint32_t sctlr_te = (0x1 << 30); + static const uint32_t sctlr_v = (0x1 << 13); + static const uint32_t sctlr_a = (0x1 << 1); + + uint32_t sctlr = get_sctlr(); + /* Handle exceptions in ARM mode. */ + sctlr &= ~sctlr_te; + /* Set V=0 in SCTLR so VBAR points to the exception vector table. */ + sctlr &= ~sctlr_v; + /* Enforce alignment. */ + sctlr |= sctlr_a; + set_sctlr(sctlr); + + extern uint32_t exception_table[]; + set_vbar((uintptr_t)exception_table); + + test_abort = 1; + exception_test(); + test_abort = 0; +} diff --git a/payloads/libpayload/arch/armv7/exception_asm.S b/payloads/libpayload/arch/armv7/exception_asm.S new file mode 100644 index 0000000..696df38 --- /dev/null +++ b/payloads/libpayload/arch/armv7/exception_asm.S @@ -0,0 +1,115 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +exception_stack: + .align 5 + .skip 0x2000, 0xa5 +exception_stack_end: + .word exception_stack_end + +exception_handler: + .word 0 + + + .align 6 + .arm + .global exception_table +exception_table: + b 1f + b 2f + b 3f + b 4f + b 5f + b 6f + b 7f + b 8f + +1: + ldr sp, _not_used + b exception_common +2: + ldr sp, _undefined_instruction + b exception_common +3: + ldr sp, _software_interrupt + b exception_common +4: + ldr sp, _prefetch_abort + b exception_common +5: + ldr sp, _data_abort + b exception_common +6: + ldr sp, _not_used + b exception_common +7: + ldr sp, _irq + b exception_common +8: + ldr sp, _fiq + b exception_common + +exception_common: + str sp, exception_handler + ldr sp, exception_stack_end + push { lr } + sub sp, sp, $8 + push { r0 - r12 } + mov r0, sp + mov lr, pc + ldr pc, exception_handler + pop { r0 - r12 } + add sp, sp, $8 + ldm sp!, { pc }^ + + +_undefined_instruction: .word exception_undefined_instruction +_software_interrupt: .word exception_software_interrupt +_prefetch_abort: .word exception_prefetch_abort +_data_abort: .word exception_data_abort +_not_used: .word exception_not_used +_irq: .word exception_irq +_fiq: .word exception_fiq + + .thumb + .global set_vbar + .thumb_func +set_vbar: + mcr p15, 0, r0, c12, c0, 0 + bx lr + + .global exception_test + .thumb_func +exception_test: + mov r1, $1 + mov r0, pc + add r0, $3 + ldr r1, [r1] + bx lr + diff --git a/payloads/libpayload/arch/armv7/main.c b/payloads/libpayload/arch/armv7/main.c index 6b54b27..93cfce5 100644 --- a/payloads/libpayload/arch/armv7/main.c +++ b/payloads/libpayload/arch/armv7/main.c @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +#include <arch/exception.h> #include <libpayload.h> unsigned int main_argc; /**< The argc value to pass to main() */ @@ -51,6 +52,8 @@ void start_main(void) console_init(); #endif + exception_init(); + /* * Any other system init that has to happen before the * user gets control goes here. diff --git a/payloads/libpayload/include/armv7/arch/exception.h b/payloads/libpayload/include/armv7/arch/exception.h new file mode 100644 index 0000000..57076bd --- /dev/null +++ b/payloads/libpayload/include/armv7/arch/exception.h @@ -0,0 +1,38 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARCH_EXCEPTION_H +#define _ARCH_EXCEPTION_H + +#include <stdint.h> + +void exception_init(void); +void set_vbar(uint32_t vbar); + +#endif

1 0

Re: [coreboot] i915 status on x60.
by Denis 'GNUtoo' Carikli 04 Mar '13

04 Mar '13

On Sun, 3 Mar 2013 09:21:11 -0800 ron minnich <rminnich(a)gmail.com> wrote: > I did not have time to read all your code, will try later. > > To get to the frame buffer on sandybridge, you just read one of the > BARs, I think i't BAR 4. That won't work on the x60? I just found out that the bar2 where the framebuffer is on the x60 isn't mapped correctly: common.c maps the framebuffer and then I do that with the virtual address: (gdb) set {int}0xa7d38000 = 0xff (gdb) p/x {int}0xa7d38000 $1 = 0x0 0xa7d38000 points or at the beginning of the bar, or at address of the framebuffer(I took it from the kernel with kgdb). I am told by phcoder on IRC that I've to activate the access to VRAM... Denis.

2 3

Patch set updated for coreboot: 2a2e8c6 samsung/exynos5: add display port and framebuffer defines and initialization
by Ronald G. Minnich 04 Mar '13

04 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2570 -gerrit commit 2a2e8c6c00826033c464086c0b3499f1a9ab8b1b Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Mar 1 10:18:14 2013 -0800 samsung/exynos5: add display port and framebuffer defines and initialization These are essential functions for setting up the display port and framebuffer, and also enable such things as aux channel communications. We do some very simple initialization in romstage, mainly set a GPIO so that the graphics is powering up, but the complex parts are done in the ramstage. This mirrors the way in which graphics is done in the x86 size. I do not know if 0x10000000 is the correct LCD base. I've added a first pass at a real device, and put it in the mainboard Kconfig, hoping for corrections. I'm way out of practive with the device model. Change-Id: I56400ec9016ecb8716ec5a5dae41fdfbfff4817a Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5-common/Makefile.inc | 4 + src/cpu/samsung/exynos5-common/displayport/Kconfig | 3 + .../exynos5-common/displayport/Makefile.inc | 1 + src/cpu/samsung/exynos5-common/displayport/chip.h | 27 + .../exynos5-common/displayport/displayport.c | 56 ++ src/cpu/samsung/exynos5-common/exynos-fb.c | 597 +++++++++++++++++++++ src/cpu/samsung/exynos5-common/s5p-dp-core.h | 256 +++++++++ src/cpu/samsung/exynos5-common/s5p-dp-reg.c | 481 +++++++++++++++++ src/mainboard/google/snow/Kconfig | 3 +- src/mainboard/google/snow/devicetree.cb | 2 + src/mainboard/google/snow/ramstage.c | 23 + src/mainboard/google/snow/romstage.c | 8 +- 12 files changed, 1459 insertions(+), 2 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/Makefile.inc b/src/cpu/samsung/exynos5-common/Makefile.inc index 47abe0f..7abd75c 100644 --- a/src/cpu/samsung/exynos5-common/Makefile.inc +++ b/src/cpu/samsung/exynos5-common/Makefile.inc @@ -19,3 +19,7 @@ ramstage-y += pwm.c # needed by timer.c ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += i2c.c +ramstage-y += s5p-dp-reg.c +ramstage-y += exynos-fb.c + +subdirs-y += displayport diff --git a/src/cpu/samsung/exynos5-common/displayport/Kconfig b/src/cpu/samsung/exynos5-common/displayport/Kconfig new file mode 100644 index 0000000..b9af850 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/Kconfig @@ -0,0 +1,3 @@ +config EXYNOS_DISPLAYPORT + bool + diff --git a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc new file mode 100644 index 0000000..0a8e99c --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c diff --git a/src/cpu/samsung/exynos5-common/displayport/chip.h b/src/cpu/samsung/exynos5-common/displayport/chip.h new file mode 100644 index 0000000..77a82cb --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/chip.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H +#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H + +struct cpu_samsung_exynos5_common_displayport__config { + int mode; +}; + +#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */ diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c new file mode 100644 index 0000000..28ebc9c --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/displayport.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <stdlib.h> +#include <string.h> +#include <arch/io.h> + +#include <device/device.h> + +static void exynos_displayport_init(void) +{ + //int width=640, height=480, depth=8; + + printk(BIOS_DEBUG, "Initializing exynos VGA\n"); + +} + +static void exynos_displayport_noop(device_t dummy) +{ +} + +static struct device_operations exynos_displayport_operations = { + .read_resources = exynos_displayport_noop, + .set_resources = exynos_displayport_noop, + .enable_resources = exynos_displayport_noop, + .init = exynos_displayport_init, + .scan_bus = exynos_displayport_noop, +}; + +static void exynos_displayport_enable(struct device *dev) +{ + if (dev->link_list != NULL) + dev->ops = &exynos_displayport_operations; +} + +struct chip_operations drivers_i2c_exynos_displayport_ops = { + CHIP_NAME("exynos displayport") + .enable_dev = exynos_displayport_enable; +}; diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c new file mode 100644 index 0000000..0ff7c24 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -0,0 +1,597 @@ +/* + * LCD driver for Exynos + * + * Copyright 2013 Google Inc. + * Copyright (C) 2012 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <arch/io.h> +#include <stdlib.h> +#include <string.h> +#include <console/console.h> +#include <cpu/samsung/exynos5250/cpu.h> +#include <cpu/samsung/exynos5250/power.h> +#include <cpu/samsung/exynos5250/sysreg.h> +#include <drivers/maxim/max77686/max77686.h> + +#include "device/i2c.h" +#include "cpu/samsung/exynos5-common/i2c.h" +#include "cpu/samsung/exynos5250/dsim.h" +#include "cpu/samsung/exynos5250/fimd.h" + +#include "cpu/samsung/exynos5250/s5p-dp.h" +#include "s5p-dp-core.h" + +/* To help debug any init errors here, define a list of possible errors */ +enum { + ERR_PLL_NOT_UNLOCKED = 2, + ERR_VIDEO_CLOCK_BAD, + ERR_VIDEO_STREAM_BAD, + ERR_DPCD_READ_ERROR1, /* 5 */ + + ERR_DPCD_WRITE_ERROR1, + ERR_DPCD_READ_ERROR2, + ERR_DPCD_WRITE_ERROR2, + ERR_INVALID_LANE, + ERR_PLL_NOT_LOCKED, /* 10 */ + + ERR_PRE_EMPHASIS_LEVELS, + ERR_LINK_RATE_ABNORMAL, + ERR_MAX_LANE_COUNT_ABNORMAL, + ERR_LINK_TRAINING_FAILURE, + ERR_MISSING_DP_BASE, /* 15 */ + + ERR_NO_FDT_NODE, +}; +/* ok, this is stupid, but we're going to leave the variables in here until we know it works. + * one cleanup task at a time. + */ +enum stage_t { + STAGE_START = 0, + STAGE_LCD_VDD, + STAGE_BRIDGE_SETUP, + STAGE_BRIDGE_INIT, + STAGE_BRIDGE_RESET, + STAGE_HOTPLUG, + STAGE_DP_CONTROLLER, + STAGE_BACKLIGHT_VDD, + STAGE_BACKLIGHT_PWM, + STAGE_BACKLIGHT_EN, + STAGE_DONE, +}; + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +short console_col; +short console_row; + + +#ifdef CONFIG_EXYNOS_DISPLAYPORT +static struct s5p_dp_device dp_device; + +#endif + +/* Bypass FIMD of DISP1_BLK */ +static void fimd_bypass(void) +{ +#if 0 + struct exynos5_sysreg *sysreg = + (struct exynos5_sysreg *)samsung_get_base_sysreg(); + + setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); +#endif +} + +/* Calculate the size of Framebuffer from the resolution */ +static u32 calc_fbsize(vidinfo_t *panel_info) +{ + /* They had PAGE_SIZE here instead of 4096. + * but that's a totally arbitrary number -- everything nowadays + * has lots of page sizes. + * So keep it obvious. + */ + return ALIGN((panel_info->vl_col * panel_info->vl_row * + ((1<<panel_info->vl_bpix) / 8)), 4096); +} + +/* + * Initialize display controller. + * + * @param lcdbase pointer to the base address of framebuffer. + * @pd pointer to the main panel_data structure + */ +void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd) +{ + unsigned int val; + u32 fbsize; + struct exynos5_fimd *fimd = + (struct exynos5_fimd *)samsung_get_base_fimd(); + struct exynos5_disp_ctrl *disp_ctrl = + (struct exynos5_disp_ctrl *)samsung_get_base_disp_ctrl(); + + writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); + val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); + writel(val, &fimd->vidcon0); + + val = (pd->vsync << VSYNC_PULSE_WIDTH_OFFSET) | + (pd->lower_margin << V_FRONT_PORCH_OFFSET) | + (pd->upper_margin << V_BACK_PORCH_OFFSET); + writel(val, &disp_ctrl->vidtcon0); + + val = (pd->hsync << HSYNC_PULSE_WIDTH_OFFSET) | + (pd->right_margin << H_FRONT_PORCH_OFFSET) | + (pd->left_margin << H_BACK_PORCH_OFFSET); + writel(val, &disp_ctrl->vidtcon1); + + val = ((pd->xres - 1) << HOZVAL_OFFSET) | + ((pd->yres - 1) << LINEVAL_OFFSET); + writel(val, &disp_ctrl->vidtcon2); + + writel((unsigned int)lcd_base, &fimd->vidw00add0b0); + + fbsize = calc_fbsize(panel_info); + writel((unsigned int)lcd_base + fbsize, &fimd->vidw00add1b0); + + writel(pd->xres * 2, &fimd->vidw00add2); + + val = ((pd->xres - 1) << OSD_RIGHTBOTX_F_OFFSET); + val |= ((pd->yres - 1) << OSD_RIGHTBOTY_F_OFFSET); + writel(val, &fimd->vidosd0b); + writel(pd->xres * pd->yres, &fimd->vidosd0c); + + setbits_le32(&fimd->shadowcon, CHANNEL0_EN); + + val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; + val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; + writel(val, &fimd->wincon0); + + /* DPCLKCON_ENABLE */ + writel(1 << 1, &fimd->dpclkcon); +} + +#if 0 +static void exynos_fimd_disable(void) +{ + struct exynos5_fimd *fimd = + (struct exynos5_fimd *)samsung_get_base_fimd(); + + writel(0, &fimd->wincon0); + clrbits_le32(&fimd->shadowcon, CHANNEL0_EN); +} +#endif +/* + * Configure DP in slave mode and wait for video stream. + * + * param dp pointer to main s5p-dp structure + * param video_info pointer to main video_info structure. + * return status + */ +static int s5p_dp_config_video(struct s5p_dp_device *dp, + struct video_info *video_info) +{ + int timeout = 0; + u32 start; + struct exynos5_dp *base = dp->base; + + s5p_dp_config_video_slave_mode(dp, video_info); + + s5p_dp_set_video_color_format(dp, video_info->color_depth, + video_info->color_space, + video_info->dynamic_range, + video_info->ycbcr_coeff); + + if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + debug("PLL is not locked yet.\n"); + return -ERR_PLL_NOT_UNLOCKED; + } + + start = get_timer(0); + do { + if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { + timeout++; + break; + } + } while (get_timer(start) <= STREAM_ON_TIMEOUT); + + if (!timeout) { + debug("Video Clock Not ok\n"); + return -ERR_VIDEO_CLOCK_BAD; + } + + /* Set to use the register calculated M/N video */ + s5p_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); + + clrbits_le32(&base->video_ctl_10, FORMAT_SEL); + + /* Disable video mute */ + clrbits_le32(&base->video_ctl_1, HDCP_VIDEO_MUTE); + + /* Configure video slave mode */ + s5p_dp_enable_video_master(dp); + + /* Enable video */ + setbits_le32(&base->video_ctl_1, VIDEO_EN); + timeout = s5p_dp_is_video_stream_on(dp); + + if (timeout) { + debug("Video Stream Not on\n"); + return -ERR_VIDEO_STREAM_BAD; + } + + return 0; +} + +/* + * Set DP to enhanced mode. We use this for EVT1 + * param dp pointer to main s5p-dp structure + * return status + */ +static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp) +{ + u8 data; + + if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data)) { + debug("DPCD read error\n"); + return -ERR_DPCD_READ_ERROR1; + } + + if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, + DPCD_ENHANCED_FRAME_EN | + (data & DPCD_LANE_COUNT_SET_MASK))) { + debug("DPCD write error\n"); + return -ERR_DPCD_WRITE_ERROR1; + } + + return 0; +} + +/* + * Enable scrambles mode. We use this for EVT1 + * param dp pointer to main s5p-dp structure + * return status + */ +static int s5p_dp_enable_scramble(struct s5p_dp_device *dp) +{ + u8 data; + struct exynos5_dp *base = dp->base; + + clrbits_le32(&base->dp_training_ptn_set, SCRAMBLING_DISABLE); + + if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, + &data)) { + debug("DPCD read error\n"); + return -ERR_DPCD_READ_ERROR2; + } + + if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, + (u8)(data & ~DPCD_SCRAMBLING_DISABLED))) { + debug("DPCD write error\n"); + return -ERR_DPCD_WRITE_ERROR2; + } + + return 0; +} + +/* + * Reset DP and prepare DP for init training + * param dp pointer to main s5p-dp structure + */ +static int s5p_dp_init_dp(struct s5p_dp_device *dp) +{ + int ret, i; + struct exynos5_dp *base = dp->base; + + for (i = 0; i < DP_INIT_TRIES; i++) { + s5p_dp_reset(dp); + + /* SW defined function Normal operation */ + clrbits_le32(&base->func_en_1, SW_FUNC_EN_N); + + ret = s5p_dp_init_analog_func(dp); + if (!ret) + break; + + udelay(5000); + debug("LCD retry init, attempt=%d ret=%d\n", i, ret); + } + if (i == DP_INIT_TRIES) { + debug("LCD initialization failed, ret=%d\n", ret); + return ret; + } + + s5p_dp_init_aux(dp); + + return ret; +} + +/* + * Set pre-emphasis level + * param dp pointer to main s5p-dp structure + * param pre_emphasis pre-emphasis level + * param lane lane number(0 - 3) + * return status + */ +static int s5p_dp_set_lane_lane_pre_emphasis(struct s5p_dp_device *dp, + int pre_emphasis, int lane) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = pre_emphasis << PRE_EMPHASIS_SET_SHIFT; + switch (lane) { + case 0: + writel(reg, &base->ln0_link_trn_ctl); + break; + case 1: + writel(reg, &base->ln1_link_trn_ctl); + break; + + case 2: + writel(reg, &base->ln2_link_trn_ctl); + break; + + case 3: + writel(reg, &base->ln3_link_trn_ctl); + break; + default: + debug("%s: Invalid lane %d\n", __func__, lane); + return -ERR_INVALID_LANE; + } + return 0; +} + +/* + * Read supported bandwidth type + * param dp pointer to main s5p-dp structure + * param bandwidth pointer to variable holding bandwidth type + */ +static void s5p_dp_get_max_rx_bandwidth(struct s5p_dp_device *dp, + u8 *bandwidth) +{ + u8 data; + + /* + * For DP rev.1.1, Maximum link rate of Main Link lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps + */ + s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data); + *bandwidth = data; +} + +/* + * Reset DP and prepare DP for init training + * param dp pointer to main s5p-dp structure + * param lane_count pointer to variable holding no of lanes + */ +static void s5p_dp_get_max_rx_lane_count(struct s5p_dp_device *dp, + u8 *lane_count) +{ + u8 data; + + /* + * For DP rev.1.1, Maximum number of Main Link lanes + * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes + */ + s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data); + *lane_count = data & DPCD_MAX_LANE_COUNT_MASK; +} + +/* + * DP H/w Link Training. Set DPCD link rate and bandwidth. + * param dp pointer to main s5p-dp structure + * param max_lane No of lanes + * param max_rate bandwidth + * return status + */ +static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, + unsigned int max_lane, + unsigned int max_rate) +{ + u32 data; + u32 start; + int lane; + struct exynos5_dp *base = dp->base; + + /* Stop Video */ + clrbits_le32(&base->video_ctl_1, VIDEO_EN); + + start = get_timer(0); + while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + if (get_timer(start) > PLL_LOCK_TIMEOUT) { + /* Ignore this error, and try to continue */ + printk(BIOS_ERR, "PLL is not locked yet.\n"); + break; + } + } + + /* Reset Macro */ + setbits_le32(&base->dp_phy_test, MACRO_RST); + + /* 10 us is the minimum reset time. */ + udelay(10); + + clrbits_le32(&base->dp_phy_test, MACRO_RST); + + /* Set TX pre-emphasis to minimum */ + for (lane = 0; lane < max_lane; lane++) + if (s5p_dp_set_lane_lane_pre_emphasis(dp, + PRE_EMPHASIS_LEVEL_0, lane)) { + debug("Unable to set pre emphasis level\n"); + return -ERR_PRE_EMPHASIS_LEVELS; + } + + /* All DP analog module power up */ + writel(0x00, &base->dp_phy_pd); + + /* Initialize by reading RX's DPCD */ + s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); + s5p_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); + + if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && + (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { + debug("Rx Max Link Rate is abnormal :%x !\n", + dp->link_train.link_rate); + /* Not Retrying */ + return -ERR_LINK_RATE_ABNORMAL; + } + + if (dp->link_train.lane_count == 0) { + debug("Rx Max Lane count is abnormal :%x !\n", + dp->link_train.lane_count); + /* Not retrying */ + return -ERR_MAX_LANE_COUNT_ABNORMAL; + } + + /* Setup TX lane count & rate */ + if (dp->link_train.lane_count > max_lane) + dp->link_train.lane_count = max_lane; + if (dp->link_train.link_rate > max_rate) + dp->link_train.link_rate = max_rate; + + /* Set link rate and count as you want to establish*/ + writel(dp->link_train.lane_count, &base->lane_count_set); + writel(dp->link_train.link_rate, &base->link_bw_set); + + /* Set sink to D0 (Sink Not Ready) mode. */ + s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, + DPCD_SET_POWER_STATE_D0); + + /* Start HW link training */ + writel(HW_TRAINING_EN, &base->dp_hw_link_training); + + /* Wait unitl HW link training done */ + s5p_dp_wait_hw_link_training_done(dp); + + /* Get hardware link training status */ + data = readl(&base->dp_hw_link_training); + if (data != 0) { + debug(" H/W link training failure: 0x%x\n", data); + return -ERR_LINK_TRAINING_FAILURE; + } + + /* Get Link Bandwidth */ + data = readl(&base->link_bw_set); + + dp->link_train.link_rate = data; + + data = readl(&base->lane_count_set); + dp->link_train.lane_count = data; + + return 0; +} + +/* + * Initialize DP display + */ +int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) +{ + int ret; + struct s5p_dp_device *dp = dp_device; + struct exynos5_dp *base; + + //dp->base = (struct exynos5_dp *)addr; + /* yes. we're a snow. Yet somehow our config is from a development kit? + * This Must Change */ + //dp->video_info = &smdk5250_dp_config; + + clock_init_dp_clock(); + + power_enable_dp_phy(); + ret = s5p_dp_init_dp(dp); + if (ret) { + debug("%s: Could not initialize dp\n", __func__); + return ret; + } + + ret = s5p_dp_hw_link_training(dp, dp->video_info->lane_count, + dp->video_info->link_rate); + if (ret) { + debug("unable to do link train\n"); + return ret; + } + /* Minimum delay after H/w Link training */ + udelay(1000); + + ret = s5p_dp_enable_scramble(dp); + if (ret) { + debug("unable to set scramble mode\n"); + return ret; + } + + ret = s5p_dp_enable_rx_to_enhanced_mode(dp); + if (ret) { + debug("unable to set enhanced mode\n"); + return ret; + } + + + base = dp->base; + /* Enable enhanced mode */ + setbits_le32(&base->sys_ctl_4, ENHANCED); + + writel(dp->link_train.lane_count, &base->lane_count_set); + writel(dp->link_train.link_rate, &base->link_bw_set); + + s5p_dp_init_video(dp); + ret = s5p_dp_config_video(dp, dp->video_info); + if (ret) { + debug("unable to config video\n"); + return ret; + } + + /* + * This delay is T3 in the LCD timing spec (defined as >200ms). We set + * this down to 60ms since that's the approximate maximum amount of time + * it'll take a bridge to start outputting LVDS data. The delay of + * >200ms is just a conservative value to avoid turning on the backlight + * when there's random LCD data on the screen. Shaving 140ms off the + * boot is an acceptable trade-off. + */ + *wait_ms = 60; + return 0; +} + +/** + * Init the LCD controller + * + * @param lcdbase Base address of LCD frame buffer + * @return 0 if ok, -ve error code on error + */ +int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase) +{ + int ret = 0; + + //vi->res = panel_info->vl_col; + //vi->yres = panel_info->vl_row; + + fimd_bypass(); + fb_init(panel_info, lcdbase, panel_data); + + /* Enable flushing after LCD writes if requested */ + // forget it. lcd_set_flush_dcache(1); + return ret; +} diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h new file mode 100644 index 0000000..67c1990 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h @@ -0,0 +1,256 @@ +/* + * Header file for Samsung DP (Display Port) interface driver. + * + * Copyright 2013 Google Inc. + * Copyright (C) 2012 Samsung Electronics Co., Ltd. + * Author: Jingoo Han <jg1.han(a)samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef _S5P_DP_CORE_H +#define _S5P_DP_CORE_H + +#define STREAM_ON_TIMEOUT 100 +#define PLL_LOCK_TIMEOUT 10 +#define DP_INIT_TRIES 10 +#define MAX_CR_LOOP 5 +#define MAX_EQ_LOOP 4 + +/* Link tare type */ +enum link_rate { + LINK_RATE_1_62GBPS = 0x06, + LINK_RATE_2_70GBPS = 0x0a +}; + +/* Number of lanes supported */ +enum link_lane_count { + LANE_COUNT1 = 1, + LANE_COUNT2 = 2, + LANE_COUNT4 = 4 +}; + +/* Pre emphasis level */ +enum pre_emphasis_level { + PRE_EMPHASIS_LEVEL_0, + PRE_EMPHASIS_LEVEL_1, + PRE_EMPHASIS_LEVEL_2, + PRE_EMPHASIS_LEVEL_3, +}; + +/* Type of color space */ +enum color_space { + COLOR_RGB, + COLOR_YCBCR422, + COLOR_YCBCR444 +}; + +/* Video input Bit Per Color */ +enum color_depth { + COLOR_6, + COLOR_8, + COLOR_10, + COLOR_12 +}; + +/* Type of YCbCr coefficient */ +enum color_coefficient { + COLOR_YCBCR601, + COLOR_YCBCR709 +}; + +/* Color range */ +enum dynamic_range { + VESA, + CEA +}; + +/* Status of PLL clock */ +enum pll_status { + PLL_UNLOCKED, + PLL_LOCKED +}; + +/* To choose type of m_value */ +enum clock_recovery_m_value_type { + CALCULATED_M, + REGISTER_M +}; + +struct video_info { + enum color_space color_space; + enum dynamic_range dynamic_range; + enum color_coefficient ycbcr_coeff; + enum color_depth color_depth; + + enum link_rate link_rate; + enum link_lane_count lane_count; + + char *name; + + unsigned int h_sync_polarity:1; + unsigned int v_sync_polarity:1; + unsigned int interlaced:1; +}; + +struct link_train { + u8 link_rate; + u8 lane_count; +}; + +struct s5p_dp_device { + unsigned int irq; + struct exynos5_dp *base; + struct video_info *video_info; + struct link_train link_train; +}; + +/* this struct is used by mainboards to pass mode info to the driver */ +typedef struct vidinfo { + u16 vl_col; + u16 vl_row; + u8 vl_bpix; + u16 *cmap; +} vidinfo_t; + +/* s5p_dp_reg.c */ + +/* + * Reset DP module + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_reset(struct s5p_dp_device *dp); +/* + * Initialize DP to recieve video stream + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_init_video(struct s5p_dp_device *dp); +/* + * Check whether PLL is locked + * + * param dp pointer to main s5p-dp structure + * return Lock status + */ +unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp); +/* + * Initialize analog functions of DP + * + * param dp pointer to main s5p-dp structure + * return 0 on success + */ +int s5p_dp_init_analog_func(struct s5p_dp_device *dp); +/* + * Initialize DP for AUX transaction + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_init_aux(struct s5p_dp_device *dp); + +/* + * Start an AUX transaction. + * + * param dp pointer to main s5p-dp structure + */ +int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp); + +/* + * Write a byte to DPCD register + * + * param dp pointer to main s5p-dp structure + * param reg_addr DPCD register to be written + * param data byte data to be written + * return write status + */ +int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char data); +/* + * Read a byte from DPCD register + * + * param dp pointer to main s5p-dp structure + * param reg_addr DPCD register to read + * param data read byte data + * return read status + */ +int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char *data); +/* + * Initialize DP video functions + * + * param dp pointer to main s5p-dp structure + */ +//void s5p_dp_init_video(struct s5p_dp_device *dp); + +/* + * Set color parameters for display + * + * param dp pointer to main s5p-dp structure + * param color_depth Video input Bit Per Color + * param color_space Colorimetric format of input video + * param dynamic_range VESA range or CEA range + * param coeff YCbCr Coefficients of input video + */ +void s5p_dp_set_video_color_format(struct s5p_dp_device *dp, + unsigned int color_depth, + unsigned int color_space, + unsigned int dynamic_range, + unsigned int coeff); +/* + * Check whether video clock is on + * + * param dp pointer to main s5p-dp structure + * return clock status + */ +int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp); +/* + * Check whether video clock is on + * + * param dp pointer to main s5p-dp structure + * param type clock_recovery_m_value_type + * param m_value to caluculate m_vid value + * param n_value to caluculate n_vid value + */ +void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, + enum clock_recovery_m_value_type type, + unsigned int m_value, + unsigned int n_value); +/* + * Set DP to video slave mode thereby enabling video master + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_enable_video_master(struct s5p_dp_device *dp); +/* + * Check whether video stream is on + * + * param dp pointer to main s5p-dp structure + * return video stream status + */ +int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp); +/* + * Configure DP in slave mode + * + * param dp pointer to main s5p-dp structure + * param video_info pointer to main video_info structure. + */ +void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, + struct video_info *video_info); + +/* + * Wait unitl HW link training done + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); + +/* startup and init */ +void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd); +int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms); +int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase); +#endif /* _S5P_DP_CORE_H */ diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c new file mode 100644 index 0000000..adb64a8 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c @@ -0,0 +1,481 @@ +/* + * Samsung DP (Display port) register interface driver. + * + * Copyright (C) 2012 Samsung Electronics Co., Ltd. + * Author: Jingoo Han <jg1.han(a)samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <common.h> +#include <arch/io.h> +#include <cpu/samsung/exynos5-common/clk.h> +#include <cpu/samsung/exynos5250/cpu.h> +#include <cpu/samsung/exynos5250/periph.h> +#include <cpu/samsung/exynos5250/s5p-dp.h> +#include "cpu/samsung/exynos5250/fimd.h" +#include "s5p-dp-core.h" + +void s5p_dp_reset(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + writel(RESET_DP_TX, &base->dp_tx_sw_reset); + + /* Stop Video */ + clrbits_le32(&base->video_ctl_1, VIDEO_EN); + clrbits_le32(&base->video_ctl_1, HDCP_VIDEO_MUTE); + + reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | + AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | + HDCP_FUNC_EN_N | SW_FUNC_EN_N; + writel(reg, &base->func_en_1); + + reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | + SERDES_FIFO_FUNC_EN_N | + LS_CLK_DOMAIN_FUNC_EN_N; + writel(reg, &base->func_en_2); + + udelay(20); + + reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | + LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; + + writel(reg, &base->lane_map); + + writel(0x0, &base->sys_ctl_1); + writel(0x40, &base->sys_ctl_2); + writel(0x0, &base->sys_ctl_3); + writel(0x0, &base->sys_ctl_4); + + writel(0x0, &base->pkt_send_ctl); + writel(0x0, &base->dp_hdcp_ctl); + + writel(0x5e, &base->dp_hpd_deglitch_l); + writel(0x1a, &base->dp_hpd_deglitch_h); + + writel(0x10, &base->dp_debug_ctl); + + writel(0x0, &base->dp_phy_test); + + writel(0x0, &base->dp_video_fifo_thrd); + writel(0x20, &base->dp_audio_margin); + + writel(0x4, &base->m_vid_gen_filter_th); + writel(0x2, &base->m_aud_gen_filter_th); + + writel(0x00000101, &base->soc_general_ctl); + + /* Set Analog Parameters */ + writel(0x10, &base->analog_ctl_1); + writel(0x0C, &base->analog_ctl_2); + writel(0x85, &base->analog_ctl_3); + writel(0x66, &base->pll_filter_ctl_1); + writel(0x0, &base->tx_amp_tuning_ctl); + + /* Set interrupt pin assertion polarity as high */ + writel(INT_POL0 | INT_POL1, &base->int_ctl); + + /* Clear pending regisers */ + writel(0xff, &base->common_int_sta_1); + writel(0x4f, &base->common_int_sta_2); + writel(0xe0, &base->common_int_sta_3); + writel(0xe7, &base->common_int_sta_4); + writel(0x63, &base->dp_int_sta); + + /* 0:mask,1: unmask */ + writel(0x00, &base->common_int_mask_1); + writel(0x00, &base->common_int_mask_2); + writel(0x00, &base->common_int_mask_3); + writel(0x00, &base->common_int_mask_4); + writel(0x00, &base->int_sta_mask); +} + +unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp) +{ + u32 reg; + + reg = readl(&dp->base->dp_debug_ctl); + if (reg & PLL_LOCK) + return PLL_LOCKED; + else + return PLL_UNLOCKED; +} + +int s5p_dp_init_analog_func(struct s5p_dp_device *dp) +{ + u32 reg; + u32 start; + struct exynos5_dp *base = dp->base; + + writel(0x00, &base->dp_phy_pd); + + reg = PLL_LOCK_CHG; + writel(reg, &base->common_int_sta_1); + + clrbits_le32(&base->dp_debug_ctl, (F_PLL_LOCK | PLL_LOCK_CTRL)); + + /* Power up PLL */ + if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + + clrbits_le32(&base->dp_pll_ctl, DP_PLL_PD); + + start = get_timer(0); + while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + if (get_timer(start) > PLL_LOCK_TIMEOUT) { + debug("%s: PLL is not locked yet\n", __func__); + return -1; + } + } + } + + /* Enable Serdes FIFO function and Link symbol clock domain module */ + clrbits_le32(&base->func_en_2, (SERDES_FIFO_FUNC_EN_N | + LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N)); + return 0; +} + +void s5p_dp_init_aux(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + /* Clear inerrupts related to AUX channel */ + reg = RPLY_RECEIV | AUX_ERR; + writel(reg, &base->dp_int_sta); + + /* Disable AUX channel module */ + setbits_le32(&base->func_en_2, AUX_FUNC_EN_N); + + /* Disable AUX transaction H/W retry */ + reg = (3 & AUX_BIT_PERIOD_MASK) << AUX_BIT_PERIOD_SHIFT; + reg |= (0 & AUX_HW_RETRY_COUNT_MASK) << AUX_HW_RETRY_COUNT_SHIFT; + reg |= (AUX_HW_RETRY_INTERVAL_600_US << AUX_HW_RETRY_INTERVAL_SHIFT); + writel(reg, &base->aux_hw_retry_ctl) ; + + /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ + reg = DEFER_CTRL_EN; + reg |= (1 & DEFER_COUNT_MASK) << DEFER_COUNT_SHIFT; + writel(reg, &base->aux_ch_defer_dtl); + + /* Enable AUX channel module */ + clrbits_le32(&base->func_en_2, AUX_FUNC_EN_N); +} + +int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) +{ + int reg; + struct exynos5_dp *base = dp->base; + + /* Enable AUX CH operation */ + setbits_le32(&base->aux_ch_ctl_2, AUX_EN); + + /* Is AUX CH command reply received? */ + reg = readl(&base->dp_int_sta); + while (!(reg & RPLY_RECEIV)) + reg = readl(&base->dp_int_sta); + + /* Clear interrupt source for AUX CH command reply */ + writel(RPLY_RECEIV, &base->dp_int_sta); + + /* Clear interrupt source for AUX CH access error */ + reg = readl(&base->dp_int_sta); + if (reg & AUX_ERR) { + writel(AUX_ERR, &base->dp_int_sta); + return -1; + } + + /* Check AUX CH error access status */ + reg = readl(&base->dp_int_sta); + if ((reg & AUX_STATUS_MASK) != 0) { + debug("AUX CH error happens: %d\n\n", + reg & AUX_STATUS_MASK); + return -1; + } + + return 0; +} + +int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char data) +{ + u32 reg; + int i; + int retval; + struct exynos5_dp *base = dp->base; + + for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) { + /* Clear AUX CH data buffer */ + writel(BUF_CLR, &base->buf_data_ctl); + + /* Select DPCD device address */ + reg = reg_addr >> AUX_ADDR_7_0_SHIFT; + reg &= AUX_ADDR_7_0_MASK; + writel(reg, &base->aux_addr_7_0); + reg = reg_addr >> AUX_ADDR_15_8_SHIFT; + reg &= AUX_ADDR_15_8_MASK; + writel(reg, &base->aux_addr_15_8); + reg = reg_addr >> AUX_ADDR_19_16_SHIFT; + reg &= AUX_ADDR_19_16_MASK; + writel(reg, &base->aux_addr_19_16); + + /* Write data buffer */ + reg = (unsigned int)data; + writel(reg, &base->buf_data_0); + + /* + * Set DisplayPort transaction and write 1 byte + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; + writel(reg, &base->aux_ch_ctl_1); + + /* Start AUX transaction */ + retval = s5p_dp_start_aux_transaction(dp); + if (retval == 0) + break; + else + debug("Aux Transaction fail!\n"); + } + + return retval; +} + +int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char *data) +{ + u32 reg; + int i; + int retval; + struct exynos5_dp *base = dp->base; + + for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) { + /* Clear AUX CH data buffer */ + writel(BUF_CLR, &base->buf_data_ctl); + + /* Select DPCD device address */ + reg = reg_addr >> AUX_ADDR_7_0_SHIFT; + reg &= AUX_ADDR_7_0_MASK; + writel(reg, &base->aux_addr_7_0); + reg = reg_addr >> AUX_ADDR_15_8_SHIFT; + reg &= AUX_ADDR_15_8_MASK; + writel(reg, &base->aux_addr_15_8); + reg = reg_addr >> AUX_ADDR_19_16_SHIFT; + reg &= AUX_ADDR_19_16_MASK; + writel(reg, &base->aux_addr_19_16); + + /* + * Set DisplayPort transaction and read 1 byte + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; + writel(reg, &base->aux_ch_ctl_1); + + /* Start AUX transaction */ + retval = s5p_dp_start_aux_transaction(dp); + if (retval == 0) + break; + else + debug("Aux Transaction fail!\n"); + } + + /* Read data buffer */ + if (!retval) { + reg = readl(&base->buf_data_0); + *data = (unsigned char)(reg & 0xff); + } + + return retval; +} + +void s5p_dp_init_video(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; + writel(reg, &base->common_int_sta_1); + + reg = 0x0; + writel(reg, &base->sys_ctl_1); + + reg = (4 & CHA_CRI_MASK) << CHA_CRI_SHIFT; + reg |= CHA_CTRL; + writel(reg, &base->sys_ctl_2); + + reg = 0x0; + writel(reg, &base->sys_ctl_3); +} + +void s5p_dp_set_video_color_format(struct s5p_dp_device *dp, + unsigned int color_depth, + unsigned int color_space, + unsigned int dynamic_range, + unsigned int coeff) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + /* Configure the input color depth, color space, dynamic range */ + reg = (dynamic_range << IN_D_RANGE_SHIFT) | + (color_depth << IN_BPC_SHIFT) | + (color_space << IN_COLOR_F_SHIFT); + writel(reg, &base->video_ctl_2); + + /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ + reg = readl(&base->video_ctl_3); + reg &= ~IN_YC_COEFFI_MASK; + if (coeff) + reg |= IN_YC_COEFFI_ITU709; + else + reg |= IN_YC_COEFFI_ITU601; + writel(reg, &base->video_ctl_3); +} + +int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->sys_ctl_1); + writel(reg, &base->sys_ctl_1); + + reg = readl(&base->sys_ctl_1); + + if (!(reg & DET_STA)) + return -1; + + reg = readl(&base->sys_ctl_2); + writel(reg, &base->sys_ctl_2); + + reg = readl(&base->sys_ctl_2); + + if (reg & CHA_STA) { + debug("Input stream clk is changing\n"); + return -1; + } + + return 0; +} + +void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, + enum clock_recovery_m_value_type type, + unsigned int m_value, + unsigned int n_value) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + if (type == REGISTER_M) { + setbits_le32(&base->sys_ctl_4, FIX_M_VID); + + reg = m_value >> M_VID_0_VALUE_SHIFT; + writel(reg, &base->m_vid_0); + + reg = (m_value >> M_VID_1_VALUE_SHIFT); + writel(reg, &base->m_vid_1); + + reg = (m_value >> M_VID_2_VALUE_SHIFT); + writel(reg, &base->m_vid_2); + + reg = n_value >> N_VID_0_VALUE_SHIFT; + writel(reg, &base->n_vid_0); + + reg = (n_value >> N_VID_1_VALUE_SHIFT); + writel(reg, &base->n_vid_1); + + reg = (n_value >> N_VID_2_VALUE_SHIFT); + writel(reg, &base->n_vid_2); + } else { + clrbits_le32(&base->sys_ctl_4, FIX_M_VID); + + writel(0x00, &base->n_vid_0); + writel(0x80, &base->n_vid_1); + writel(0x00, &base->n_vid_2); + } +} + +void s5p_dp_enable_video_master(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->soc_general_ctl); + reg &= ~VIDEO_MODE_MASK; + reg |= VIDEO_MODE_SLAVE_MODE; + writel(reg, &base->soc_general_ctl); +} + +int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp) +{ + u32 reg, i = 0; + u32 start; + struct exynos5_dp *base = dp->base; + + /* Wait for 4 VSYNC_DET interrupts */ + start = get_timer(0); + do { + reg = readl(&base->common_int_sta_1); + if (reg & VSYNC_DET) { + i++; + writel(reg | VSYNC_DET, &base->common_int_sta_1); + } + if (i == 4) + break; + } while (get_timer(start) <= STREAM_ON_TIMEOUT); + + if (i != 4) { + debug("s5p_dp_is_video_stream_on timeout\n"); + return -1; + } + + return 0; +} + +void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, + struct video_info *video_info) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->func_en_1); + reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); + reg |= MASTER_VID_FUNC_EN_N; + writel(reg, &base->func_en_1); + + reg = readl(&base->video_ctl_10); + reg &= ~INTERACE_SCAN_CFG; + reg |= (video_info->interlaced << 2); + writel(reg, &base->video_ctl_10); + + reg = readl(&base->video_ctl_10); + reg &= ~VSYNC_POLARITY_CFG; + reg |= (video_info->v_sync_polarity << 1); + writel(reg, &base->video_ctl_10); + + reg = readl(&base->video_ctl_10); + reg &= ~HSYNC_POLARITY_CFG; + reg |= (video_info->h_sync_polarity << 0); + writel(reg, &base->video_ctl_10); + + reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; + writel(reg, &base->soc_general_ctl); +} + +void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->dp_hw_link_training); + while (reg & HW_TRAINING_EN) + reg = readl(&base->dp_hw_link_training); +} diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index 6face94..85b90a5 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## Copyright 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DRIVER_MAXIM_MAX77686 # select HAVE_ACPI_TABLES # select MMCONF_SUPPORT + select EXYNOS_DISPLAYPORT select CHROMEOS config MAINBOARD_DIR diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index 4c88ea8..58e4bc3 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -28,5 +28,7 @@ device domain 0 on device i2c 6 on end # ? device i2c 9 on end # ? end + chip cpu/samsung/exynos5-common/displayport/ + end end end diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 5970357..8f5efb5 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -19,6 +19,29 @@ #include <console/console.h> #include <cbmem.h> +#include <cpu/samsung/exynos5250/fimd.h> +#include <cpu/samsung/exynos5-common/s5p-dp-core.h> + +vidinfo_t snow_panel_info = { + .vl_col = 1366, + .vl_row = 768, + .vl_bpix = 16, + +}; +struct exynos5_fimd_panel snow_panel = { + /* Display I/F is eDP */ + .is_dp = 1, + .is_mipi = 0, + .fixvclk = 0, + .ivclk = 0, + .clkval_f = 2, + .upper_margin = 14, + .lower_margin = 3, + .vsync = 5, + .left_margin = 80, + .right_margin = 48, + .hsync = 32, +}; void hardwaremain(int boot_complete); void main(void) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7e1cd57..639c2ef 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -31,7 +31,6 @@ #include <cpu/samsung/exynos5250/setup.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/clock_init.h> - #include <console/console.h> #include <arch/stages.h> @@ -70,6 +69,11 @@ static void initialize_s5p_mshc(void) { exynos_pinmux_config(PERIPH_ID_SDMMC2, 0); } +static void graphics(void) +{ + + exynos_pinmux_config(PERIPH_ID_DPHPD, 0); +} void main(void) { struct mem_timings *mem; @@ -108,6 +112,8 @@ void main(void) initialize_s5p_mshc(); + graphics(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);

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coreboot March 2013