coreboot March 2013

coreboot@coreboot.org

46 participants
782 discussions

Re: [coreboot] i915 status on x60.
by Peter Stuge 03 Mar '13

03 Mar '13

ron minnich wrote: > you need to get the physical frame buffer address from the hardware > and then mmap that in user mode. Yes, that's what he has been doing. The BAR points to some address which doesn't remember writes. //Peter

1 0

SB800: Linux hangs with `#define SB_GPP_UNHIDE_PORTS TRUE`
by Paul Menzel 03 Mar '13

03 Mar '13

Dear coreboot folks, working on the ASRock E350M1 and trying to find out why the PCI devices 0:15.0 to 0:15.2 are not enabled, I am looking into the setup of the General Purpose Ports (GPP). In short, setting `SB_GPP_UNHIDE_PORTS` to `TRUE`, coreboot (based on commit f91c8f29), commit f91c8f290b2a723d1bda9a5dd7d668390672317e Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Fri Mar 1 19:01:00 2013 +0100 FrontRunner/Toucan-AF: work around AGESA RAM init crashing on reboot SeaBIOS 1.7.1 and GRUB 2 load fine, but then booting Debian Sid/unstable with Linux 3.2.39 686 PAE kernel linux-image-3.2.0-4-686-pae 3.2.39-2 Linux hangs after printing the following error message. pci 0000:00:15.0: can't handle 64-bit address space for bridge See [1] and [2]. A 64-bit Linux kernel 3.3.6 (Grml 2012.05 [3]) hangs too. [ 0.000000] Linux version 3.3.0-2-grml-amd64 (Debian 3.3.6-1+grml.1) (team(a)grml.org) (gcc version 4.6.3 (Debian 4.6.3-5) ) #1 SMP Mon May 14 19:06:58 UTC 2012 [ 0.000000] Command line: initrd=/boot/grml64full_testing/initrd.img boot=live apm=power-off vga=791 nomce toram=grml64-full_testing.squashfs live-media-path=/live/grml64-full_testing/ boot=live bootid=8aa1383f-8bcd-472a-9a1a-e6e944a4bf80 console=ttyS0,115200n8 console=tty1 BOOT_IMAGE=/boot/grml64full_testing/vmlinuz […] [ 0.332027] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 0.336160] [Firmware Bug]: ACPI: no secondary bus range in _CRS [ 0.340055] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) [ 0.344192] pci_root PNP0A03:00: host bridge window [io 0x0000-0x0cf7] [ 0.348026] pci_root PNP0A03:00: host bridge window [io 0x0d00-0xffff] [ 0.352025] pci_root PNP0A03:00: host bridge window [mem 0x000a0000-0x000bffff] [ 0.356028] pci_root PNP0A03:00: host bridge window [mem 0xe0000000-0xffffffff] [ 0.360112] PCI host bridge to bus 0000:00 [ 0.364030] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7] [ 0.368026] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff] [ 0.372026] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] [ 0.376026] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xffffffff] [ 0.385186] pci 0000:00:14.4: PCI bridge to [bus 01-01] (subtractive decode) [ 0.388134] pci 0000:00:15.0: PCI bridge to [bus 02-02] and then just hangs. Looking at the following working log, the PCI devices are not found. With coreboot-4.0-2441-gbdca153 commit bdca15337bc9337f399b43290dc74cb598c5ec4d Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon May 21 14:01:52 2012 +0200 libpayload: Remove orphaned delay from USB mass storage the Linux kernel ring buffer contains the following. $ uname -a Linux myhostname 3.2.0-4-686-pae #1 SMP Debian 3.2.39-2 i686 GNU/Linux $ dmesg […] [ 0.000000] Kernel command line: BOOT_IMAGE=/vmlinuz-3.2.0-4-686-pae root=/dev/mapper/bla-root ro rdinitrd=/sbin/bootchartd initcall_debug printk.time=y init=/sbin/bootchartd drm_kms_helper.poll=0 drm.debug=0x06 quiet noisapnp […] [ 0.175212] calling acpi_pci_root_init+0x0/0x26 @ 1 [ 0.175217] HEST: Table parsing has been initialized. [ 0.175224] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 0.175324] [Firmware Bug]: ACPI: no secondary bus range in _CRS [ 0.175343] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) [ 0.175538] pci_root PNP0A03:00: host bridge window [io 0x0000-0x0cf7] [ 0.175543] pci_root PNP0A03:00: host bridge window [io 0x0d00-0xffff] [ 0.175548] pci_root PNP0A03:00: host bridge window [mem 0x000a0000-0x000bffff] [ 0.175553] pci_root PNP0A03:00: host bridge window [mem 0xe0000000-0xffffffff] [ 0.175575] pci 0000:00:00.0: [1022:1510] type 0 class 0x000600 [ 0.175637] pci 0000:00:01.0: [1002:9802] type 0 class 0x000300 [ 0.175654] pci 0000:00:01.0: reg 10: [mem 0xe0000000-0xefffffff pref] [ 0.175665] pci 0000:00:01.0: reg 14: [io 0x1000-0x10ff] [ 0.175676] pci 0000:00:01.0: reg 18: [mem 0xf0000000-0xf003ffff] [ 0.175741] pci 0000:00:01.0: supports D1 D2 [ 0.175768] pci 0000:00:01.1: [1002:1314] type 0 class 0x000403 [ 0.175783] pci 0000:00:01.1: reg 10: [mem 0xf0040000-0xf0043fff] [ 0.175859] pci 0000:00:01.1: supports D1 D2 [ 0.176022] pci 0000:00:11.0: [1002:4390] type 0 class 0x000101 [ 0.176050] pci 0000:00:11.0: reg 10: [io 0x1410-0x1417] [ 0.176065] pci 0000:00:11.0: reg 14: [io 0x1420-0x1423] [ 0.176080] pci 0000:00:11.0: reg 18: [io 0x1418-0x141f] [ 0.176094] pci 0000:00:11.0: reg 1c: [io 0x1424-0x1427] [ 0.176108] pci 0000:00:11.0: reg 20: [io 0x1400-0x140f] [ 0.176123] pci 0000:00:11.0: reg 24: [mem 0xf004b000-0xf004b3ff] [ 0.176153] pci 0000:00:11.0: set SATA to AHCI mode [ 0.176222] pci 0000:00:12.0: [1002:4397] type 0 class 0x000c03 [ 0.176242] pci 0000:00:12.0: reg 10: [mem 0xf0048000-0xf0048fff] [ 0.176343] pci 0000:00:12.2: [1002:4396] type 0 class 0x000c03 [ 0.176371] pci 0000:00:12.2: reg 10: [mem 0xf004b400-0xf004b4ff] [ 0.176483] pci 0000:00:12.2: supports D1 D2 [ 0.176487] pci 0000:00:12.2: PME# supported from D0 D1 D2 D3hot [ 0.176522] pci 0000:00:13.0: [1002:4397] type 0 class 0x000c03 [ 0.176543] pci 0000:00:13.0: reg 10: [mem 0xf0049000-0xf0049fff] [ 0.176643] pci 0000:00:13.2: [1002:4396] type 0 class 0x000c03 [ 0.176671] pci 0000:00:13.2: reg 10: [mem 0xf004b500-0xf004b5ff] [ 0.176783] pci 0000:00:13.2: supports D1 D2 [ 0.176787] pci 0000:00:13.2: PME# supported from D0 D1 D2 D3hot [ 0.176821] pci 0000:00:14.0: [1002:4385] type 0 class 0x000c05 [ 0.176932] pci 0000:00:14.2: [1002:4383] type 0 class 0x000403 [ 0.176963] pci 0000:00:14.2: reg 10: [mem 0xf0044000-0xf0047fff 64bit] [ 0.177053] pci 0000:00:14.2: PME# supported from D0 D3hot D3cold [ 0.177077] pci 0000:00:14.3: [1002:439d] type 0 class 0x000601 [ 0.177184] pci 0000:00:14.4: [1002:4384] type 1 class 0x000604 [ 0.177246] pci 0000:00:14.5: [1002:4399] type 0 class 0x000c03 [ 0.177266] pci 0000:00:14.5: reg 10: [mem 0xf004a000-0xf004afff] [ 0.177369] pci 0000:00:15.0: [1002:43a0] type 1 class 0x000604 [ 0.177479] pci 0000:00:15.0: supports D1 D2 [ 0.177518] pci 0000:00:15.1: [1002:43a1] type 1 class 0x000604 [ 0.177627] pci 0000:00:15.1: supports D1 D2 [ 0.177671] pci 0000:00:18.0: [1022:1700] type 0 class 0x000600 [ 0.177723] pci 0000:00:18.1: [1022:1701] type 0 class 0x000600 [ 0.177771] pci 0000:00:18.2: [1022:1702] type 0 class 0x000600 [ 0.177821] pci 0000:00:18.3: [1022:1703] type 0 class 0x000600 [ 0.177884] pci 0000:00:18.4: [1022:1704] type 0 class 0x000600 [ 0.177931] pci 0000:00:18.5: [1022:1718] type 0 class 0x000600 [ 0.177979] pci 0000:00:18.6: [1022:1716] type 0 class 0x000600 [ 0.178026] pci 0000:00:18.7: [1022:1719] type 0 class 0x000600 [ 0.178225] pci 0000:00:14.4: PCI bridge to [bus 01-01] (subtractive decode) [ 0.178240] pci 0000:00:14.4: bridge window [io 0x0000-0x0cf7] (subtractive decode) [ 0.178246] pci 0000:00:14.4: bridge window [io 0x0d00-0xffff] (subtractive decode) [ 0.178251] pci 0000:00:14.4: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode) [ 0.178256] pci 0000:00:14.4: bridge window [mem 0xe0000000-0xffffffff] (subtractive decode) [ 0.178266] pci 0000:00:15.0: bridge configuration invalid ([bus 00-00]), reconfiguring [ 0.178277] pci 0000:00:15.1: bridge configuration invalid ([bus 00-00]), reconfiguring [ 0.178363] pci 0000:00:15.0: PCI bridge to [bus 02-ff] [ 0.178477] pci 0000:03:00.0: [10ec:8168] type 0 class 0x000200 [ 0.178502] pci 0000:03:00.0: reg 10: [io 0x0000-0x00ff] [ 0.178542] pci 0000:03:00.0: reg 18: [mem 0x00000000-0x00000fff 64bit pref] [ 0.178569] pci 0000:03:00.0: reg 20: [mem 0x00000000-0x00003fff 64bit pref] [ 0.178674] pci 0000:03:00.0: supports D1 D2 [ 0.178678] pci 0000:03:00.0: PME# supported from D0 D1 D2 D3hot D3cold [ 0.184152] pci 0000:00:15.1: PCI bridge to [bus 03-ff] [ 0.184183] pci_bus 0000:00: on NUMA node 0 [ 0.184197] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT] [ 0.184567] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.AGPB._PRT] [ 0.184633] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PE20._PRT] [ 0.184689] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PE21._PRT] [ 0.184751] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PIBR._PRT] [ 0.184922] pci0000:00: Requesting ACPI _OSC control (0x1d) [ 0.184929] pci0000:00: ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d [ 0.184933] ACPI _OSC control for PCIe not granted, disabling ASPM [ 0.194987] initcall acpi_pci_root_init+0x0/0x26 returned 0 after 19532 usecs [ 0.194995] calling acpi_pci_link_init+0x0/0x36 @ 1 [ 0.195153] ACPI: PCI Interrupt Link [INTA] (IRQs 3 4 5 7 10 11 12 15) *0 [ 0.195378] ACPI: PCI Interrupt Link [INTB] (IRQs 3 4 5 7 10 11 12 15) *0 [ 0.195530] ACPI: PCI Interrupt Link [INTC] (IRQs 3 4 5 7 10 11 12 15) *0 [ 0.195683] ACPI: PCI Interrupt Link [INTD] (IRQs 3 4 5 7 10 11 12 15) *0 [ 0.195833] ACPI: PCI Interrupt Link [INTE] (IRQs 3 4 5 7 10 11 12 15) *0 [ 0.195983] ACPI: PCI Interrupt Link [INTF] (IRQs 9) *0 [ 0.196143] ACPI: PCI Interrupt Link [INTG] (IRQs 3 4 5 7 10 11 12 15) *0 [ 0.196293] ACPI: PCI Interrupt Link [INTH] (IRQs 3 4 5 7 10 11 12 15) *0 […] The option/define `SB_GPP_UNHIDE_PORTS` was introduced in [4] commit f3b0500050050e4f103e42fdcf111af232fa874b Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Oct 12 12:06:23 2011 +0800 SB800: Hide unused gpp ports Add configure option SB_GPP_UNHIDE_PORTS for mainboard to hide/unhide the unused sb800 gpp ports. Certain gpp port should be hidden, if no device was detected and hotplug feature is disabled for such port. Hidden unused ports makes lspci -vvv get more accurate information under Linux. Test on avalue/eax-785e mainboard. Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Reviewed-on: http://review.coreboot.org/207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> and strangely the defaults for all boards were set from `TRUE` to `FALSE`. I guess that it worked with `TRUE` beforehand, so I do not know what happened in the meantime. The option is only used in `Gpp.c`. $ more src/vendorcode/amd/cimx/sb800/Gpp.c […] if ( pConfig->GppUnhidePorts == FALSE ) { if ((abValue & 0xF0) == 0) { abValue = BIT8; // if all ports are empty set GPP_RESET } else if ((abValue & 0xE0) != 0 && (abValue & 0x10) == 0) { abValue |= BIT4; // PortA should always be visible whenever other ports are exist } // Update GPP_Portx_Enable (abcfg:0xC0[7:5]) writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), abValue); } […] Could you please try setting #define SB_GPP_UNHIDE_PORTS TRUE in AMD Persimmon or some other SB800 board and see how it goes? Any other ideas are appreciated too. Thanks, Paul [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/driver… [2] https://patchwork.kernel.org/patch/1051462/ • not committed [3] http://grml.org/download/ • Go to »Older releases«. [4] http://review.coreboot.org/207

1 0

Patch merged into coreboot/master: 56ad905 AMD Persimmon, LiPPERT Fam14: Fix typo code*c* in comment
by gerrit＠coreboot.org 03 Mar '13

03 Mar '13

the following patch was just integrated into master: commit 56ad905e4ca5cf09a0b0d93ee6586e7ac02ad8fc Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 3 12:01:15 2013 +0100 AMD Persimmon, LiPPERT Fam14: Fix typo code*c* in comment Commit f154c018 Author: Marc Jones <marcj303(a)gmail.com> Date: Wed Dec 14 11:24:00 2011 -0700 Persimmon audio codec verb patch. Reviewed-on: http://review.coreboot.org/490 has a typo code*c* in the comments for `AZALIA_OEM_VERB_TABLE`. As this was copied over to the LiPPERT Fam14 boards, use the following command to fix the typo. $ git grep -l cocec | xargs sed -i s,cocec,codec, Change-Id: I1525b0445edab81ab136b3adece52b78ba7abc71 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2576 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Build-Tested: build bot (Jenkins) at Sun Mar 3 14:49:57 2013, giving +1 Reviewed-By: Martin Roth <martin.roth(a)se-eng.com> at Sun Mar 3 18:40:15 2013, giving +2 See http://review.coreboot.org/2576 for details. -gerrit

1 0

i915 status on x60.
by Denis 'GNUtoo' Carikli 03 Mar '13

03 Mar '13

Hi, I've been working with ron minnich on trying to avoid the non-free vga option rom for the i915. Personally I target the x60 for now. After porting to the x60 I'll probably try to find a T60 with an intel card in order to port to it. Right now, I've got the screen that powers on, and even backlight if I add the option rom generated by SeaBIOS(it freezes after it though), however I've only a strange pattern on the screen...and my goal is to have graphics in SeaBIOS and grub(most important),by whatever mean,but without using the non-free i915 option rom. The code is here: http://review.coreboot.org/#/c/2559/ And the SeaBIOS code will also follow. As stated it isn't usable yet so it shouldn't be merged. Denis.

3 7

Patch set updated for coreboot: 207063a AMD Persimmon, LiPPERT Fam14: Fix typo code*c* in comment
by Paul Menzel 03 Mar '13

03 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2576 -gerrit commit 207063af9955693b0b86b44171849dc00823af55 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 3 12:01:15 2013 +0100 AMD Persimmon, LiPPERT Fam14: Fix typo code*c* in comment Commit f154c018 Author: Marc Jones <marcj303(a)gmail.com> Date: Wed Dec 14 11:24:00 2011 -0700 Persimmon audio codec verb patch. Reviewed-on: http://review.coreboot.org/490 has a typo code*c* in the comments for `AZALIA_OEM_VERB_TABLE`. As this was copied over to the LiPPERT Fam14 boards, use the following command to fix the typo. $ git grep -l cocec | xargs sed -i s,cocec,codec, Change-Id: I1525b0445edab81ab136b3adece52b78ba7abc71 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/persimmon/platform_cfg.h | 2 +- src/mainboard/lippert/frontrunner-af/platform_cfg.h | 2 +- src/mainboard/lippert/toucan-af/platform_cfg.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index b0ac180..0578e27 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -252,7 +252,7 @@ static const CODECTBLLIST codec_tablelist[] = /** * @def AZALIA_OEM_VERB_TABLE - * Mainboard specific cocec verb table list + * Mainboard specific codec verb table list */ #define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) diff --git a/src/mainboard/lippert/frontrunner-af/platform_cfg.h b/src/mainboard/lippert/frontrunner-af/platform_cfg.h index b94d3e3..1e6617b 100644 --- a/src/mainboard/lippert/frontrunner-af/platform_cfg.h +++ b/src/mainboard/lippert/frontrunner-af/platform_cfg.h @@ -254,7 +254,7 @@ static const CODECTBLLIST codec_tablelist[] = /** * @def AZALIA_OEM_VERB_TABLE - * Mainboard specific cocec verb table list + * Mainboard specific codec verb table list */ #define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) diff --git a/src/mainboard/lippert/toucan-af/platform_cfg.h b/src/mainboard/lippert/toucan-af/platform_cfg.h index 3c09713..1c2a044 100644 --- a/src/mainboard/lippert/toucan-af/platform_cfg.h +++ b/src/mainboard/lippert/toucan-af/platform_cfg.h @@ -254,7 +254,7 @@ static const CODECTBLLIST codec_tablelist[] = /** * @def AZALIA_OEM_VERB_TABLE - * Mainboard specific cocec verb table list + * Mainboard specific codec verb table list */ #define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0])

1 0

New patch to review for coreboot: 7641891 AMD Persimmon, LiPPERT: Fix typo code*c*
by Paul Menzel 03 Mar '13

03 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2576 -gerrit commit 7641891096058d6fe491e5fd657a4c58f19483fa Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 3 12:01:15 2013 +0100 AMD Persimmon, LiPPERT: Fix typo code*c* The following commit commit f154c01802992dd98227c069937f63373ef35f42 Author: Marc Jones <marcj303(a)gmail.com> Date: Wed Dec 14 11:24:00 2011 -0700 Persimmon audio codec verb patch. Reviewed-on: http://review.coreboot.org/490 had a typo in »codec«. As this was copied over to the LiPPERT Fam14 boards, use the following command to fix the typo. $ git grep -l cocec | xargs sed -i s,cocec,codec, Change-Id: I1525b0445edab81ab136b3adece52b78ba7abc71 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/persimmon/platform_cfg.h | 2 +- src/mainboard/lippert/frontrunner-af/platform_cfg.h | 2 +- src/mainboard/lippert/toucan-af/platform_cfg.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index b0ac180..0578e27 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -252,7 +252,7 @@ static const CODECTBLLIST codec_tablelist[] = /** * @def AZALIA_OEM_VERB_TABLE - * Mainboard specific cocec verb table list + * Mainboard specific codec verb table list */ #define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) diff --git a/src/mainboard/lippert/frontrunner-af/platform_cfg.h b/src/mainboard/lippert/frontrunner-af/platform_cfg.h index b94d3e3..1e6617b 100644 --- a/src/mainboard/lippert/frontrunner-af/platform_cfg.h +++ b/src/mainboard/lippert/frontrunner-af/platform_cfg.h @@ -254,7 +254,7 @@ static const CODECTBLLIST codec_tablelist[] = /** * @def AZALIA_OEM_VERB_TABLE - * Mainboard specific cocec verb table list + * Mainboard specific codec verb table list */ #define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) diff --git a/src/mainboard/lippert/toucan-af/platform_cfg.h b/src/mainboard/lippert/toucan-af/platform_cfg.h index 3c09713..1c2a044 100644 --- a/src/mainboard/lippert/toucan-af/platform_cfg.h +++ b/src/mainboard/lippert/toucan-af/platform_cfg.h @@ -254,7 +254,7 @@ static const CODECTBLLIST codec_tablelist[] = /** * @def AZALIA_OEM_VERB_TABLE - * Mainboard specific cocec verb table list + * Mainboard specific codec verb table list */ #define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0])

1 0

Patch set updated for coreboot: 8203e70 bump SeaBIOS to 1.7.2.1
by Idwer Vollering 02 Mar '13

02 Mar '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2575 -gerrit commit 8203e7025994a7b21cb6ea595585ae46665a99de Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sat Mar 2 18:27:05 2013 +0100 bump SeaBIOS to 1.7.2.1 Update coreboot to use SeaBIOS' tag rel-1.7.2.1 Change-Id: I01969407964a7cf64f7c4800b59c6aed845b24f9 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- src/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 5e1df47..022e012 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,7 +1,7 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=51755c3b5ed9dcdfdef8cee56631d68642bde416 +TAG-$(CONFIG_SEABIOS_STABLE)=88cb66ea542906ffff8a80ef397b9e3adbb33116 unexport KCONFIG_AUTOCONFIG diff --git a/src/Kconfig b/src/Kconfig index 4d929da..3e24967 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -504,7 +504,7 @@ choice depends on PAYLOAD_SEABIOS config SEABIOS_STABLE - bool "1.7.1" + bool "1.7.2.1" help Stable SeaBIOS version config SEABIOS_MASTER

1 0

New patch to review for coreboot: 2cf78f7 bump SeaBIOS to 1.7.2.1
by Idwer Vollering 02 Mar '13

02 Mar '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2575 -gerrit commit 2cf78f73f2e61f87c6bf5f6de13e8c318998c026 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Feb 10 17:02:33 2013 +0100 bump SeaBIOS to 1.7.2.1 Update coreboot to use SeaBIOS' tag rel-1.7.2.1 Change-Id: I01969407964a7cf64f7c4800b59c6aed845b24f9 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- src/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 5e1df47..022e012 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,7 +1,7 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=51755c3b5ed9dcdfdef8cee56631d68642bde416 +TAG-$(CONFIG_SEABIOS_STABLE)=88cb66ea542906ffff8a80ef397b9e3adbb33116 unexport KCONFIG_AUTOCONFIG diff --git a/src/Kconfig b/src/Kconfig index 726fa39..81b3325 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -516,7 +516,7 @@ choice depends on PAYLOAD_SEABIOS config SEABIOS_STABLE - bool "1.7.1" + bool "1.7.2.1" help Stable SeaBIOS version config SEABIOS_MASTER

1 0

Re: [coreboot] [PATCH 1/2] Add i915 VGA test Driver.
by Denis 'GNUtoo' Carikli 02 Mar '13

02 Mar '13

On Fri, 1 Mar 2013 19:41:16 -0800 ron minnich <rminnich(a)gmail.com> wrote: > Assuming this stuff is set up in coreboot, it should not be necessary > to bring it into seabios, so I'm not sure what's going on here. > > ron > I was ask by Paul Menzel to do it(for the purpose of documentation): http://review.coreboot.org/#/c/2559/1//COMMIT_MSG Denis.

1 0

New patch to review for coreboot: 7627550 ASRock E350M1: Disable absent IDE device 0:14.1
by Paul Menzel 02 Mar '13

02 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2574 -gerrit commit 7627550cecf01dd5676133b3dea7145911d28a54 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 2 11:21:06 2013 +0100 ASRock E350M1: Disable absent IDE device 0:14.1 The ASRock E350M1 [1] does not have any IDE connectors, so disable that PCI device, which coreboot also does not find. coreboot-4.0-3583-gf91c8f2 Sat Mar 2 09:04:55 CET 2013 starting... […] PCI: 00:14.0 [1002/4385] enabled sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it. sb800_enable() hda enabled PCI: 00:14.2 [1002/4383] ops This PCI device does not even have code for being enabled and is just skipped. $ more src/southbridge/amd/cimx/sb800/late.c […] static void sb800_enable(device_t dev) { case (0x14 << 3) | 1: /* 0:14:1 IDE */ break; […] } [1] http://www.asrock.com/MB/overview.asp?Model=E350M1 Change-Id: I2bbc683b1faccc513bb4c24dce05f3a9892b817b Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index d47f207..23a218e 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -53,7 +53,7 @@ chip northbridge/amd/agesa/family14/root_complex device i2c 51 on end end end # SM - device pci 14.1 on end # IDE 0x439c + device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/winbond/w83627hf

1 0

← Newer
1
...
72
73
74
75
76
77
78
79
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2013