coreboot March 2013

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New patch to review for coreboot: 98c4af8 FrontRunner/Toucan-AF: drop unnecessary compile time CPU model selection
by Jens Rottmann 04 Mar '13

04 Mar '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2584 -gerrit commit 98c4af86f296f4d086204c902f309e383d7b42cd Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Mon Mar 4 21:13:57 2013 +0100 FrontRunner/Toucan-AF: drop unnecessary compile time CPU model selection The first reason for selecting the CPU model at compile time was a multi-second pause if booting a single core Fusion T40R with MAX_CPUS=2. Recent tests show the pause has disappeared, someone must have fixed it. The second reason was me not knowing how to make a single vgabios image work with two different PCI IDs. Many thanks to Martin Roth for educating me! Quote: "The way to make coreboot use the same vbios for different video device IDs is through the map_oprom_vendev function. In family 14 it's in northbridge/amd/agesa/family14/amdfam14_conf.c You would name your video bios 1002,9802 in the config and all the other device/vendor IDs for the family 14h processors will fall through the initial check for the video bios and will get remapped to use that vbios. This only works if you're initializing the vbios inside coreboot. I don't know if you're using SeaBios as a payload, but if you are you can add the vbios to cbfs as vgaroms/vbios.rom and the rom will always be initialized." I'd like to add the vgabios is added as type 'optionrom' when Coreboot make adds it, however to work with SeaBios it has to be added manually with cbfstool and with type 'raw', or it will hang. Change-Id: I8190d0c3202a60dfccb77dde232f9ba7ce5ce318 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/mainboard/lippert/Kconfig | 31 ---------------------------- src/mainboard/lippert/frontrunner-af/Kconfig | 6 ++---- src/mainboard/lippert/toucan-af/Kconfig | 6 ++---- 3 files changed, 4 insertions(+), 39 deletions(-) diff --git a/src/mainboard/lippert/Kconfig b/src/mainboard/lippert/Kconfig index cf5288e..1765460 100644 --- a/src/mainboard/lippert/Kconfig +++ b/src/mainboard/lippert/Kconfig @@ -20,37 +20,6 @@ config BOARD_LIPPERT_TOUCAN_AF endchoice -if BOARD_LIPPERT_FRONTRUNNER_AF || BOARD_LIPPERT_TOUCAN_AF -# No code, but two Kconfig options need to know this ... -choice - prompt "AMD Fusion CPU model" - default FUSION_G_T56N - help - The actual CPU model the board is fitted with: - - G-T40R: 1 GHz, single core - G-T56N: 1.65 GHz, dual core - - If unsure check with "grep model /proc/cpuinfo". -config FUSION_G_T40R - bool "G-T40R" - help - The actual CPU model the board is fitted with: - - G-T40R: 1 GHz, single core - - If unsure check with "grep model /proc/cpuinfo". -config FUSION_G_T56N - bool "G-T56N" - help - The actual CPU model the board is fitted with: - - G-T56N: 1.65 GHz, dual core - - If unsure check with "grep model /proc/cpuinfo". -endchoice -endif # BOARD_LIPPERT_FRONTRUNNER_AF || BOARD_LIPPERT_TOUCAN_AF - source "src/mainboard/lippert/frontrunner/Kconfig" source "src/mainboard/lippert/frontrunner-af/Kconfig" source "src/mainboard/lippert/hurricane-lx/Kconfig" diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 0cdf365..f56c048 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -62,8 +62,7 @@ config HW_MEM_HOLE_SIZEK config MAX_CPUS int - default 1 if FUSION_G_T40R - default 2 if FUSION_G_T56N + default 2 config MAX_PHYSICAL_CPUS int @@ -116,8 +115,7 @@ config VGA_BIOS config VGA_BIOS_ID string - default "1002,9804" if FUSION_G_T40R - default "1002,9806" if FUSION_G_T56N + default "1002,9802" config SB800_AHCI_ROM bool diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index 72e6a3b..6696ca6 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -64,8 +64,7 @@ config HW_MEM_HOLE_SIZEK config MAX_CPUS int - default 1 if FUSION_G_T40R - default 2 if FUSION_G_T56N + default 2 config MAX_PHYSICAL_CPUS int @@ -118,8 +117,7 @@ config VGA_BIOS config VGA_BIOS_ID string - default "1002,9804" if FUSION_G_T40R - default "1002,9806" if FUSION_G_T56N + default "1002,9802" config SB800_AHCI_ROM bool

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Patch set updated for coreboot: b18685e samsung/exynos5: add display port and framebuffer defines and initialization
by Ronald G. Minnich 04 Mar '13

04 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2570 -gerrit commit b18685e3979cd4fff0f9f5517a02e7d285a1e6ca Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Mar 1 10:18:14 2013 -0800 samsung/exynos5: add display port and framebuffer defines and initialization These are essential functions for setting up the display port and framebuffer, and also enable such things as aux channel communications. We do some very simple initialization in romstage, mainly set a GPIO so that the graphics is powering up, but the complex parts are done in the ramstage. This mirrors the way in which graphics is done in the x86 size. I've added a first pass at a real device, and put it in the mainboard Kconfig, hoping for corrections. Because startup is so complex, depending on device type, I've created a 'displayport' device that removes some of the complexity and makes the flow *much* clearer. You can actually follow the flow by looking at the code, which is not true on other implementations. Since display port is perhaps the main port used on these chips, that's a reasonable compromise. All parameters of importance are now in the device tree. Change-Id: I56400ec9016ecb8716ec5a5dae41fdfbfff4817a Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5-common/Makefile.inc | 4 + src/cpu/samsung/exynos5-common/displayport/Kconfig | 3 + .../exynos5-common/displayport/Makefile.inc | 1 + src/cpu/samsung/exynos5-common/displayport/chip.h | 40 ++ .../exynos5-common/displayport/displayport.c | 108 ++++ src/cpu/samsung/exynos5-common/exynos-fb.c | 596 +++++++++++++++++++++ src/cpu/samsung/exynos5-common/s5p-dp-core.h | 256 +++++++++ src/cpu/samsung/exynos5-common/s5p-dp-reg.c | 481 +++++++++++++++++ src/mainboard/google/snow/Kconfig | 3 +- src/mainboard/google/snow/devicetree.cb | 14 + src/mainboard/google/snow/ramstage.c | 2 + src/mainboard/google/snow/romstage.c | 8 +- 12 files changed, 1514 insertions(+), 2 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/Makefile.inc b/src/cpu/samsung/exynos5-common/Makefile.inc index 47abe0f..7abd75c 100644 --- a/src/cpu/samsung/exynos5-common/Makefile.inc +++ b/src/cpu/samsung/exynos5-common/Makefile.inc @@ -19,3 +19,7 @@ ramstage-y += pwm.c # needed by timer.c ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += i2c.c +ramstage-y += s5p-dp-reg.c +ramstage-y += exynos-fb.c + +subdirs-y += displayport diff --git a/src/cpu/samsung/exynos5-common/displayport/Kconfig b/src/cpu/samsung/exynos5-common/displayport/Kconfig new file mode 100644 index 0000000..b9af850 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/Kconfig @@ -0,0 +1,3 @@ +config EXYNOS_DISPLAYPORT + bool + diff --git a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc new file mode 100644 index 0000000..0a8e99c --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c diff --git a/src/cpu/samsung/exynos5-common/displayport/chip.h b/src/cpu/samsung/exynos5-common/displayport/chip.h new file mode 100644 index 0000000..275d00b --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H +#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H + +struct cpu_samsung_exynos5_common_displayport__config { + /* special magic numbers! */ + int clkval_f; + int upper_margin; + int lower_margin; + int vsync; + int left_margin; + int right_margin; + int hsync; + + int xres; + int yres; + int bpp; + + u32 lcdbase; +}; + +#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */ diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c new file mode 100644 index 0000000..1bb0770 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/displayport.c @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <stdlib.h> +#include <string.h> +#include <arch/io.h> + +#include <device/device.h> + +/* we distinguish a display port device from a raw graphics device because there are + * dramatic differences in startup depending on graphics usage. To make startup fast + * and easier to understand and debug we explicitly name this common case. The alternate + * approach, involving lots of machine and callbacks, is hard to debug and verify. + */ +static void exynos_displayport_init(void) +{ + struct cpu_samsung_exynos5_common_displayport__config *conf = dev->chip_info; + /* put these on the stack. If, at some point, we want to move this code to a + * pre-ram stage, it will be much easier. + */ + vidinfo_t vi; + struct exynos5_fimd_panel panel; + void *lcdbase; + + memset(vi, 0, sizeof(vi)); + memset(panel, 0, sizeof(panel)); + + panel.is_dp = 1; /* Display I/F is eDP */ + /* while it is true that we did a memset to zero, + * we leave some 'set to zero' entries here to make + * it clear what's going on. Graphics is confusing. + */ + panel.is_mipi = 0; + panel.fixvclk = 0; + panel.ivclk = 0; + panel.clkval_f = conf->clkval_f; + panel.upper_margin = conf->upper_margin; + panel.lower_margin = conf->lower_margin; + panel.vsync = conf->vsync; + panel.left_margin = conf->left_margin; + panel.right_margin = conf->right_margin; + panel.hsync = conf->hsync; + + vi->vl_col = conf->xres; + vi->fl_row = conf->yres; + vi->vl_bpix = conf->bpp; + vi->cmap = cbmem_reserve(64*1024); /* The size is a magic number from hardware. */ + + lcdbase = conf->lcdbase; + printk(BIOS_DEBUG, "Initializing exynos VGA\n"); + ret = lcd_ctrl_init(&vi, &panel, lcdbase); +#if 0 + ret = board_dp_lcd_vdd(blob, &wait_ms); + ret = board_dp_bridge_setup(blob, &wait_ms); + while (tries < 5){ + ret = board_dp_bridge_init(blob, &wait_ms); + ret = board_dp_hotplug(blob, &wait_ms); + if (ret){ + ret = board_dp_bridge_reset(blob, &wait_ms); + continue; + } + ret = dp_controller_init(blob, &wait_ms); + ret = board_dp_backlight_vdd(blob, &wait_ms); + ret = board_dp_backlight_pwm(blob, &wait_ms); + ret = board_dp_backlight_en(blob, &wait_ms); + } +#endif +} + +static void exynos_displayport_noop(device_t dummy) +{ +} + +static struct device_operations exynos_displayport_operations = { + .read_resources = exynos_displayport_noop, + .set_resources = exynos_displayport_noop, + .enable_resources = exynos_displayport_noop, + .init = exynos_displayport_init, + .scan_bus = exynos_displayport_noop, +}; + +static void exynos_displayport_enable(struct device *dev) +{ + if (dev->link_list != NULL) + dev->ops = &exynos_displayport_operations; +} + +struct chip_operations drivers_i2c_exynos_displayport_ops = { + CHIP_NAME("exynos displayport") + .enable_dev = exynos_displayport_enable; +}; diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c new file mode 100644 index 0000000..322a42a --- /dev/null +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -0,0 +1,596 @@ +/* + * LCD driver for Exynos + * + * Copyright 2013 Google Inc. + * Copyright (C) 2012 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <arch/io.h> +#include <stdlib.h> +#include <string.h> +#include <console/console.h> +#include <cpu/samsung/exynos5250/cpu.h> +#include <cpu/samsung/exynos5250/power.h> +#include <cpu/samsung/exynos5250/sysreg.h> +#include <drivers/maxim/max77686/max77686.h> + +#include "device/i2c.h" +#include "cpu/samsung/exynos5-common/i2c.h" +#include "cpu/samsung/exynos5250/dsim.h" +#include "cpu/samsung/exynos5250/fimd.h" + +#include "cpu/samsung/exynos5250/s5p-dp.h" +#include "s5p-dp-core.h" + +/* To help debug any init errors here, define a list of possible errors */ +enum { + ERR_PLL_NOT_UNLOCKED = 2, + ERR_VIDEO_CLOCK_BAD, + ERR_VIDEO_STREAM_BAD, + ERR_DPCD_READ_ERROR1, /* 5 */ + + ERR_DPCD_WRITE_ERROR1, + ERR_DPCD_READ_ERROR2, + ERR_DPCD_WRITE_ERROR2, + ERR_INVALID_LANE, + ERR_PLL_NOT_LOCKED, /* 10 */ + + ERR_PRE_EMPHASIS_LEVELS, + ERR_LINK_RATE_ABNORMAL, + ERR_MAX_LANE_COUNT_ABNORMAL, + ERR_LINK_TRAINING_FAILURE, + ERR_MISSING_DP_BASE, /* 15 */ + + ERR_NO_FDT_NODE, +}; +/* ok, this is stupid, but we're going to leave the variables in here until we know it works. + * one cleanup task at a time. + */ +enum stage_t { + STAGE_START = 0, + STAGE_LCD_VDD, + STAGE_BRIDGE_SETUP, + STAGE_BRIDGE_INIT, + STAGE_BRIDGE_RESET, + STAGE_HOTPLUG, + STAGE_DP_CONTROLLER, + STAGE_BACKLIGHT_VDD, + STAGE_BACKLIGHT_PWM, + STAGE_BACKLIGHT_EN, + STAGE_DONE, +}; + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +short console_col; +short console_row; + + +#ifdef CONFIG_EXYNOS_DISPLAYPORT +static struct s5p_dp_device dp_device; + +#endif + +/* Bypass FIMD of DISP1_BLK */ +static void fimd_bypass(void) +{ + struct exynos5_sysreg *sysreg = samsung_get_base_sysreg(); + + /*setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);*/ + sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1; +} + +/* Calculate the size of Framebuffer from the resolution */ +static u32 calc_fbsize(vidinfo_t *panel_info) +{ + /* They had PAGE_SIZE here instead of 4096. + * but that's a totally arbitrary number -- everything nowadays + * has lots of page sizes. + * So keep it obvious. + */ + return ALIGN((panel_info->vl_col * panel_info->vl_row * + ((1<<panel_info->vl_bpix) / 8)), 4096); +} + +/* + * Initialize display controller. + * + * @param lcdbase pointer to the base address of framebuffer. + * @pd pointer to the main panel_data structure + */ +void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd) +{ + unsigned int val; + u32 fbsize; + struct exynos5_fimd *fimd = + samsung_get_base_fimd(); + struct exynos5_disp_ctrl *disp_ctrl = + samsung_get_base_disp_ctrl(); + + writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); + val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); + writel(val, &fimd->vidcon0); + + val = (pd->vsync << VSYNC_PULSE_WIDTH_OFFSET) | + (pd->lower_margin << V_FRONT_PORCH_OFFSET) | + (pd->upper_margin << V_BACK_PORCH_OFFSET); + writel(val, &disp_ctrl->vidtcon0); + + val = (pd->hsync << HSYNC_PULSE_WIDTH_OFFSET) | + (pd->right_margin << H_FRONT_PORCH_OFFSET) | + (pd->left_margin << H_BACK_PORCH_OFFSET); + writel(val, &disp_ctrl->vidtcon1); + + val = ((pd->xres - 1) << HOZVAL_OFFSET) | + ((pd->yres - 1) << LINEVAL_OFFSET); + writel(val, &disp_ctrl->vidtcon2); + + writel((unsigned int)lcd_base, &fimd->vidw00add0b0); + + fbsize = calc_fbsize(panel_info); + writel((unsigned int)lcd_base + fbsize, &fimd->vidw00add1b0); + + writel(pd->xres * 2, &fimd->vidw00add2); + + val = ((pd->xres - 1) << OSD_RIGHTBOTX_F_OFFSET); + val |= ((pd->yres - 1) << OSD_RIGHTBOTY_F_OFFSET); + writel(val, &fimd->vidosd0b); + writel(pd->xres * pd->yres, &fimd->vidosd0c); + + setbits_le32(&fimd->shadowcon, CHANNEL0_EN); + + val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; + val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; + writel(val, &fimd->wincon0); + + /* DPCLKCON_ENABLE */ + writel(1 << 1, &fimd->dpclkcon); +} + +#if 0 +it's not clear when or if we'll need this, but until we know, +leave it here. +void exynos_fimd_disable(void) +{ + struct exynos5_fimd *fimd = samsung_get_base_fimd(); + + memset(&fimd->wincon0, 0, sizeof(fimd->wincon0)); + /*clrbits_le32(&fimd->shadowcon, CHANNEL0_EN);*/ +} +#endif +/* + * Configure DP in slave mode and wait for video stream. + * + * param dp pointer to main s5p-dp structure + * param video_info pointer to main video_info structure. + * return status + */ +static int s5p_dp_config_video(struct s5p_dp_device *dp, + struct video_info *video_info) +{ + int timeout = 0; + u32 start; + struct exynos5_dp *base = dp->base; + + s5p_dp_config_video_slave_mode(dp, video_info); + + s5p_dp_set_video_color_format(dp, video_info->color_depth, + video_info->color_space, + video_info->dynamic_range, + video_info->ycbcr_coeff); + + if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + debug("PLL is not locked yet.\n"); + return -ERR_PLL_NOT_UNLOCKED; + } + + start = get_timer(0); + do { + if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { + timeout++; + break; + } + } while (get_timer(start) <= STREAM_ON_TIMEOUT); + + if (!timeout) { + debug("Video Clock Not ok\n"); + return -ERR_VIDEO_CLOCK_BAD; + } + + /* Set to use the register calculated M/N video */ + s5p_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); + + clrbits_le32(&base->video_ctl_10, FORMAT_SEL); + + /* Disable video mute */ + clrbits_le32(&base->video_ctl_1, HDCP_VIDEO_MUTE); + + /* Configure video slave mode */ + s5p_dp_enable_video_master(dp); + + /* Enable video */ + setbits_le32(&base->video_ctl_1, VIDEO_EN); + timeout = s5p_dp_is_video_stream_on(dp); + + if (timeout) { + debug("Video Stream Not on\n"); + return -ERR_VIDEO_STREAM_BAD; + } + + return 0; +} + +/* + * Set DP to enhanced mode. We use this for EVT1 + * param dp pointer to main s5p-dp structure + * return status + */ +static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp) +{ + u8 data; + + if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data)) { + debug("DPCD read error\n"); + return -ERR_DPCD_READ_ERROR1; + } + + if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, + DPCD_ENHANCED_FRAME_EN | + (data & DPCD_LANE_COUNT_SET_MASK))) { + debug("DPCD write error\n"); + return -ERR_DPCD_WRITE_ERROR1; + } + + return 0; +} + +/* + * Enable scrambles mode. We use this for EVT1 + * param dp pointer to main s5p-dp structure + * return status + */ +static int s5p_dp_enable_scramble(struct s5p_dp_device *dp) +{ + u8 data; + struct exynos5_dp *base = dp->base; + + clrbits_le32(&base->dp_training_ptn_set, SCRAMBLING_DISABLE); + + if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, + &data)) { + debug("DPCD read error\n"); + return -ERR_DPCD_READ_ERROR2; + } + + if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, + (u8)(data & ~DPCD_SCRAMBLING_DISABLED))) { + debug("DPCD write error\n"); + return -ERR_DPCD_WRITE_ERROR2; + } + + return 0; +} + +/* + * Reset DP and prepare DP for init training + * param dp pointer to main s5p-dp structure + */ +static int s5p_dp_init_dp(struct s5p_dp_device *dp) +{ + int ret, i; + struct exynos5_dp *base = dp->base; + + for (i = 0; i < DP_INIT_TRIES; i++) { + s5p_dp_reset(dp); + + /* SW defined function Normal operation */ + clrbits_le32(&base->func_en_1, SW_FUNC_EN_N); + + ret = s5p_dp_init_analog_func(dp); + if (!ret) + break; + + udelay(5000); + debug("LCD retry init, attempt=%d ret=%d\n", i, ret); + } + if (i == DP_INIT_TRIES) { + debug("LCD initialization failed, ret=%d\n", ret); + return ret; + } + + s5p_dp_init_aux(dp); + + return ret; +} + +/* + * Set pre-emphasis level + * param dp pointer to main s5p-dp structure + * param pre_emphasis pre-emphasis level + * param lane lane number(0 - 3) + * return status + */ +static int s5p_dp_set_lane_lane_pre_emphasis(struct s5p_dp_device *dp, + int pre_emphasis, int lane) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = pre_emphasis << PRE_EMPHASIS_SET_SHIFT; + switch (lane) { + case 0: + writel(reg, &base->ln0_link_trn_ctl); + break; + case 1: + writel(reg, &base->ln1_link_trn_ctl); + break; + + case 2: + writel(reg, &base->ln2_link_trn_ctl); + break; + + case 3: + writel(reg, &base->ln3_link_trn_ctl); + break; + default: + debug("%s: Invalid lane %d\n", __func__, lane); + return -ERR_INVALID_LANE; + } + return 0; +} + +/* + * Read supported bandwidth type + * param dp pointer to main s5p-dp structure + * param bandwidth pointer to variable holding bandwidth type + */ +static void s5p_dp_get_max_rx_bandwidth(struct s5p_dp_device *dp, + u8 *bandwidth) +{ + u8 data; + + /* + * For DP rev.1.1, Maximum link rate of Main Link lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps + */ + s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data); + *bandwidth = data; +} + +/* + * Reset DP and prepare DP for init training + * param dp pointer to main s5p-dp structure + * param lane_count pointer to variable holding no of lanes + */ +static void s5p_dp_get_max_rx_lane_count(struct s5p_dp_device *dp, + u8 *lane_count) +{ + u8 data; + + /* + * For DP rev.1.1, Maximum number of Main Link lanes + * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes + */ + s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data); + *lane_count = data & DPCD_MAX_LANE_COUNT_MASK; +} + +/* + * DP H/w Link Training. Set DPCD link rate and bandwidth. + * param dp pointer to main s5p-dp structure + * param max_lane No of lanes + * param max_rate bandwidth + * return status + */ +static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, + unsigned int max_lane, + unsigned int max_rate) +{ + u32 data; + u32 start; + int lane; + struct exynos5_dp *base = dp->base; + + /* Stop Video */ + clrbits_le32(&base->video_ctl_1, VIDEO_EN); + + start = get_timer(0); + while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + if (get_timer(start) > PLL_LOCK_TIMEOUT) { + /* Ignore this error, and try to continue */ + printk(BIOS_ERR, "PLL is not locked yet.\n"); + break; + } + } + + /* Reset Macro */ + setbits_le32(&base->dp_phy_test, MACRO_RST); + + /* 10 us is the minimum reset time. */ + udelay(10); + + clrbits_le32(&base->dp_phy_test, MACRO_RST); + + /* Set TX pre-emphasis to minimum */ + for (lane = 0; lane < max_lane; lane++) + if (s5p_dp_set_lane_lane_pre_emphasis(dp, + PRE_EMPHASIS_LEVEL_0, lane)) { + debug("Unable to set pre emphasis level\n"); + return -ERR_PRE_EMPHASIS_LEVELS; + } + + /* All DP analog module power up */ + writel(0x00, &base->dp_phy_pd); + + /* Initialize by reading RX's DPCD */ + s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); + s5p_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); + + if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && + (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { + debug("Rx Max Link Rate is abnormal :%x !\n", + dp->link_train.link_rate); + /* Not Retrying */ + return -ERR_LINK_RATE_ABNORMAL; + } + + if (dp->link_train.lane_count == 0) { + debug("Rx Max Lane count is abnormal :%x !\n", + dp->link_train.lane_count); + /* Not retrying */ + return -ERR_MAX_LANE_COUNT_ABNORMAL; + } + + /* Setup TX lane count & rate */ + if (dp->link_train.lane_count > max_lane) + dp->link_train.lane_count = max_lane; + if (dp->link_train.link_rate > max_rate) + dp->link_train.link_rate = max_rate; + + /* Set link rate and count as you want to establish*/ + writel(dp->link_train.lane_count, &base->lane_count_set); + writel(dp->link_train.link_rate, &base->link_bw_set); + + /* Set sink to D0 (Sink Not Ready) mode. */ + s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, + DPCD_SET_POWER_STATE_D0); + + /* Start HW link training */ + writel(HW_TRAINING_EN, &base->dp_hw_link_training); + + /* Wait unitl HW link training done */ + s5p_dp_wait_hw_link_training_done(dp); + + /* Get hardware link training status */ + data = readl(&base->dp_hw_link_training); + if (data != 0) { + debug(" H/W link training failure: 0x%x\n", data); + return -ERR_LINK_TRAINING_FAILURE; + } + + /* Get Link Bandwidth */ + data = readl(&base->link_bw_set); + + dp->link_train.link_rate = data; + + data = readl(&base->lane_count_set); + dp->link_train.lane_count = data; + + return 0; +} + +/* + * Initialize DP display + */ +int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) +{ + int ret; + struct s5p_dp_device *dp = dp_device; + struct exynos5_dp *base; + + //dp->base = (struct exynos5_dp *)addr; + /* yes. we're a snow. Yet somehow our config is from a development kit? + * This Must Change */ + //dp->video_info = &smdk5250_dp_config; + + clock_init_dp_clock(); + + power_enable_dp_phy(); + ret = s5p_dp_init_dp(dp); + if (ret) { + debug("%s: Could not initialize dp\n", __func__); + return ret; + } + + ret = s5p_dp_hw_link_training(dp, dp->video_info->lane_count, + dp->video_info->link_rate); + if (ret) { + debug("unable to do link train\n"); + return ret; + } + /* Minimum delay after H/w Link training */ + udelay(1000); + + ret = s5p_dp_enable_scramble(dp); + if (ret) { + debug("unable to set scramble mode\n"); + return ret; + } + + ret = s5p_dp_enable_rx_to_enhanced_mode(dp); + if (ret) { + debug("unable to set enhanced mode\n"); + return ret; + } + + + base = dp->base; + /* Enable enhanced mode */ + setbits_le32(&base->sys_ctl_4, ENHANCED); + + writel(dp->link_train.lane_count, &base->lane_count_set); + writel(dp->link_train.link_rate, &base->link_bw_set); + + s5p_dp_init_video(dp); + ret = s5p_dp_config_video(dp, dp->video_info); + if (ret) { + debug("unable to config video\n"); + return ret; + } + + /* + * This delay is T3 in the LCD timing spec (defined as >200ms). We set + * this down to 60ms since that's the approximate maximum amount of time + * it'll take a bridge to start outputting LVDS data. The delay of + * >200ms is just a conservative value to avoid turning on the backlight + * when there's random LCD data on the screen. Shaving 140ms off the + * boot is an acceptable trade-off. + */ + *wait_ms = 60; + return 0; +} + +/** + * Init the LCD controller + * + * @param lcdbase Base address of LCD frame buffer + * @return 0 if ok, -ve error code on error + */ +int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase) +{ + int ret = 0; + + //vi->res = panel_info->vl_col; + //vi->yres = panel_info->vl_row; + + fimd_bypass(); + fb_init(panel_info, lcdbase, panel_data); + + /* Enable flushing after LCD writes if requested */ + // forget it. lcd_set_flush_dcache(1); + return ret; +} diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h new file mode 100644 index 0000000..67c1990 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h @@ -0,0 +1,256 @@ +/* + * Header file for Samsung DP (Display Port) interface driver. + * + * Copyright 2013 Google Inc. + * Copyright (C) 2012 Samsung Electronics Co., Ltd. + * Author: Jingoo Han <jg1.han(a)samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef _S5P_DP_CORE_H +#define _S5P_DP_CORE_H + +#define STREAM_ON_TIMEOUT 100 +#define PLL_LOCK_TIMEOUT 10 +#define DP_INIT_TRIES 10 +#define MAX_CR_LOOP 5 +#define MAX_EQ_LOOP 4 + +/* Link tare type */ +enum link_rate { + LINK_RATE_1_62GBPS = 0x06, + LINK_RATE_2_70GBPS = 0x0a +}; + +/* Number of lanes supported */ +enum link_lane_count { + LANE_COUNT1 = 1, + LANE_COUNT2 = 2, + LANE_COUNT4 = 4 +}; + +/* Pre emphasis level */ +enum pre_emphasis_level { + PRE_EMPHASIS_LEVEL_0, + PRE_EMPHASIS_LEVEL_1, + PRE_EMPHASIS_LEVEL_2, + PRE_EMPHASIS_LEVEL_3, +}; + +/* Type of color space */ +enum color_space { + COLOR_RGB, + COLOR_YCBCR422, + COLOR_YCBCR444 +}; + +/* Video input Bit Per Color */ +enum color_depth { + COLOR_6, + COLOR_8, + COLOR_10, + COLOR_12 +}; + +/* Type of YCbCr coefficient */ +enum color_coefficient { + COLOR_YCBCR601, + COLOR_YCBCR709 +}; + +/* Color range */ +enum dynamic_range { + VESA, + CEA +}; + +/* Status of PLL clock */ +enum pll_status { + PLL_UNLOCKED, + PLL_LOCKED +}; + +/* To choose type of m_value */ +enum clock_recovery_m_value_type { + CALCULATED_M, + REGISTER_M +}; + +struct video_info { + enum color_space color_space; + enum dynamic_range dynamic_range; + enum color_coefficient ycbcr_coeff; + enum color_depth color_depth; + + enum link_rate link_rate; + enum link_lane_count lane_count; + + char *name; + + unsigned int h_sync_polarity:1; + unsigned int v_sync_polarity:1; + unsigned int interlaced:1; +}; + +struct link_train { + u8 link_rate; + u8 lane_count; +}; + +struct s5p_dp_device { + unsigned int irq; + struct exynos5_dp *base; + struct video_info *video_info; + struct link_train link_train; +}; + +/* this struct is used by mainboards to pass mode info to the driver */ +typedef struct vidinfo { + u16 vl_col; + u16 vl_row; + u8 vl_bpix; + u16 *cmap; +} vidinfo_t; + +/* s5p_dp_reg.c */ + +/* + * Reset DP module + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_reset(struct s5p_dp_device *dp); +/* + * Initialize DP to recieve video stream + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_init_video(struct s5p_dp_device *dp); +/* + * Check whether PLL is locked + * + * param dp pointer to main s5p-dp structure + * return Lock status + */ +unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp); +/* + * Initialize analog functions of DP + * + * param dp pointer to main s5p-dp structure + * return 0 on success + */ +int s5p_dp_init_analog_func(struct s5p_dp_device *dp); +/* + * Initialize DP for AUX transaction + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_init_aux(struct s5p_dp_device *dp); + +/* + * Start an AUX transaction. + * + * param dp pointer to main s5p-dp structure + */ +int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp); + +/* + * Write a byte to DPCD register + * + * param dp pointer to main s5p-dp structure + * param reg_addr DPCD register to be written + * param data byte data to be written + * return write status + */ +int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char data); +/* + * Read a byte from DPCD register + * + * param dp pointer to main s5p-dp structure + * param reg_addr DPCD register to read + * param data read byte data + * return read status + */ +int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char *data); +/* + * Initialize DP video functions + * + * param dp pointer to main s5p-dp structure + */ +//void s5p_dp_init_video(struct s5p_dp_device *dp); + +/* + * Set color parameters for display + * + * param dp pointer to main s5p-dp structure + * param color_depth Video input Bit Per Color + * param color_space Colorimetric format of input video + * param dynamic_range VESA range or CEA range + * param coeff YCbCr Coefficients of input video + */ +void s5p_dp_set_video_color_format(struct s5p_dp_device *dp, + unsigned int color_depth, + unsigned int color_space, + unsigned int dynamic_range, + unsigned int coeff); +/* + * Check whether video clock is on + * + * param dp pointer to main s5p-dp structure + * return clock status + */ +int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp); +/* + * Check whether video clock is on + * + * param dp pointer to main s5p-dp structure + * param type clock_recovery_m_value_type + * param m_value to caluculate m_vid value + * param n_value to caluculate n_vid value + */ +void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, + enum clock_recovery_m_value_type type, + unsigned int m_value, + unsigned int n_value); +/* + * Set DP to video slave mode thereby enabling video master + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_enable_video_master(struct s5p_dp_device *dp); +/* + * Check whether video stream is on + * + * param dp pointer to main s5p-dp structure + * return video stream status + */ +int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp); +/* + * Configure DP in slave mode + * + * param dp pointer to main s5p-dp structure + * param video_info pointer to main video_info structure. + */ +void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, + struct video_info *video_info); + +/* + * Wait unitl HW link training done + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); + +/* startup and init */ +void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd); +int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms); +int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase); +#endif /* _S5P_DP_CORE_H */ diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c new file mode 100644 index 0000000..adb64a8 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c @@ -0,0 +1,481 @@ +/* + * Samsung DP (Display port) register interface driver. + * + * Copyright (C) 2012 Samsung Electronics Co., Ltd. + * Author: Jingoo Han <jg1.han(a)samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <common.h> +#include <arch/io.h> +#include <cpu/samsung/exynos5-common/clk.h> +#include <cpu/samsung/exynos5250/cpu.h> +#include <cpu/samsung/exynos5250/periph.h> +#include <cpu/samsung/exynos5250/s5p-dp.h> +#include "cpu/samsung/exynos5250/fimd.h" +#include "s5p-dp-core.h" + +void s5p_dp_reset(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + writel(RESET_DP_TX, &base->dp_tx_sw_reset); + + /* Stop Video */ + clrbits_le32(&base->video_ctl_1, VIDEO_EN); + clrbits_le32(&base->video_ctl_1, HDCP_VIDEO_MUTE); + + reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | + AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | + HDCP_FUNC_EN_N | SW_FUNC_EN_N; + writel(reg, &base->func_en_1); + + reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | + SERDES_FIFO_FUNC_EN_N | + LS_CLK_DOMAIN_FUNC_EN_N; + writel(reg, &base->func_en_2); + + udelay(20); + + reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | + LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; + + writel(reg, &base->lane_map); + + writel(0x0, &base->sys_ctl_1); + writel(0x40, &base->sys_ctl_2); + writel(0x0, &base->sys_ctl_3); + writel(0x0, &base->sys_ctl_4); + + writel(0x0, &base->pkt_send_ctl); + writel(0x0, &base->dp_hdcp_ctl); + + writel(0x5e, &base->dp_hpd_deglitch_l); + writel(0x1a, &base->dp_hpd_deglitch_h); + + writel(0x10, &base->dp_debug_ctl); + + writel(0x0, &base->dp_phy_test); + + writel(0x0, &base->dp_video_fifo_thrd); + writel(0x20, &base->dp_audio_margin); + + writel(0x4, &base->m_vid_gen_filter_th); + writel(0x2, &base->m_aud_gen_filter_th); + + writel(0x00000101, &base->soc_general_ctl); + + /* Set Analog Parameters */ + writel(0x10, &base->analog_ctl_1); + writel(0x0C, &base->analog_ctl_2); + writel(0x85, &base->analog_ctl_3); + writel(0x66, &base->pll_filter_ctl_1); + writel(0x0, &base->tx_amp_tuning_ctl); + + /* Set interrupt pin assertion polarity as high */ + writel(INT_POL0 | INT_POL1, &base->int_ctl); + + /* Clear pending regisers */ + writel(0xff, &base->common_int_sta_1); + writel(0x4f, &base->common_int_sta_2); + writel(0xe0, &base->common_int_sta_3); + writel(0xe7, &base->common_int_sta_4); + writel(0x63, &base->dp_int_sta); + + /* 0:mask,1: unmask */ + writel(0x00, &base->common_int_mask_1); + writel(0x00, &base->common_int_mask_2); + writel(0x00, &base->common_int_mask_3); + writel(0x00, &base->common_int_mask_4); + writel(0x00, &base->int_sta_mask); +} + +unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp) +{ + u32 reg; + + reg = readl(&dp->base->dp_debug_ctl); + if (reg & PLL_LOCK) + return PLL_LOCKED; + else + return PLL_UNLOCKED; +} + +int s5p_dp_init_analog_func(struct s5p_dp_device *dp) +{ + u32 reg; + u32 start; + struct exynos5_dp *base = dp->base; + + writel(0x00, &base->dp_phy_pd); + + reg = PLL_LOCK_CHG; + writel(reg, &base->common_int_sta_1); + + clrbits_le32(&base->dp_debug_ctl, (F_PLL_LOCK | PLL_LOCK_CTRL)); + + /* Power up PLL */ + if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + + clrbits_le32(&base->dp_pll_ctl, DP_PLL_PD); + + start = get_timer(0); + while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + if (get_timer(start) > PLL_LOCK_TIMEOUT) { + debug("%s: PLL is not locked yet\n", __func__); + return -1; + } + } + } + + /* Enable Serdes FIFO function and Link symbol clock domain module */ + clrbits_le32(&base->func_en_2, (SERDES_FIFO_FUNC_EN_N | + LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N)); + return 0; +} + +void s5p_dp_init_aux(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + /* Clear inerrupts related to AUX channel */ + reg = RPLY_RECEIV | AUX_ERR; + writel(reg, &base->dp_int_sta); + + /* Disable AUX channel module */ + setbits_le32(&base->func_en_2, AUX_FUNC_EN_N); + + /* Disable AUX transaction H/W retry */ + reg = (3 & AUX_BIT_PERIOD_MASK) << AUX_BIT_PERIOD_SHIFT; + reg |= (0 & AUX_HW_RETRY_COUNT_MASK) << AUX_HW_RETRY_COUNT_SHIFT; + reg |= (AUX_HW_RETRY_INTERVAL_600_US << AUX_HW_RETRY_INTERVAL_SHIFT); + writel(reg, &base->aux_hw_retry_ctl) ; + + /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ + reg = DEFER_CTRL_EN; + reg |= (1 & DEFER_COUNT_MASK) << DEFER_COUNT_SHIFT; + writel(reg, &base->aux_ch_defer_dtl); + + /* Enable AUX channel module */ + clrbits_le32(&base->func_en_2, AUX_FUNC_EN_N); +} + +int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) +{ + int reg; + struct exynos5_dp *base = dp->base; + + /* Enable AUX CH operation */ + setbits_le32(&base->aux_ch_ctl_2, AUX_EN); + + /* Is AUX CH command reply received? */ + reg = readl(&base->dp_int_sta); + while (!(reg & RPLY_RECEIV)) + reg = readl(&base->dp_int_sta); + + /* Clear interrupt source for AUX CH command reply */ + writel(RPLY_RECEIV, &base->dp_int_sta); + + /* Clear interrupt source for AUX CH access error */ + reg = readl(&base->dp_int_sta); + if (reg & AUX_ERR) { + writel(AUX_ERR, &base->dp_int_sta); + return -1; + } + + /* Check AUX CH error access status */ + reg = readl(&base->dp_int_sta); + if ((reg & AUX_STATUS_MASK) != 0) { + debug("AUX CH error happens: %d\n\n", + reg & AUX_STATUS_MASK); + return -1; + } + + return 0; +} + +int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char data) +{ + u32 reg; + int i; + int retval; + struct exynos5_dp *base = dp->base; + + for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) { + /* Clear AUX CH data buffer */ + writel(BUF_CLR, &base->buf_data_ctl); + + /* Select DPCD device address */ + reg = reg_addr >> AUX_ADDR_7_0_SHIFT; + reg &= AUX_ADDR_7_0_MASK; + writel(reg, &base->aux_addr_7_0); + reg = reg_addr >> AUX_ADDR_15_8_SHIFT; + reg &= AUX_ADDR_15_8_MASK; + writel(reg, &base->aux_addr_15_8); + reg = reg_addr >> AUX_ADDR_19_16_SHIFT; + reg &= AUX_ADDR_19_16_MASK; + writel(reg, &base->aux_addr_19_16); + + /* Write data buffer */ + reg = (unsigned int)data; + writel(reg, &base->buf_data_0); + + /* + * Set DisplayPort transaction and write 1 byte + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; + writel(reg, &base->aux_ch_ctl_1); + + /* Start AUX transaction */ + retval = s5p_dp_start_aux_transaction(dp); + if (retval == 0) + break; + else + debug("Aux Transaction fail!\n"); + } + + return retval; +} + +int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char *data) +{ + u32 reg; + int i; + int retval; + struct exynos5_dp *base = dp->base; + + for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) { + /* Clear AUX CH data buffer */ + writel(BUF_CLR, &base->buf_data_ctl); + + /* Select DPCD device address */ + reg = reg_addr >> AUX_ADDR_7_0_SHIFT; + reg &= AUX_ADDR_7_0_MASK; + writel(reg, &base->aux_addr_7_0); + reg = reg_addr >> AUX_ADDR_15_8_SHIFT; + reg &= AUX_ADDR_15_8_MASK; + writel(reg, &base->aux_addr_15_8); + reg = reg_addr >> AUX_ADDR_19_16_SHIFT; + reg &= AUX_ADDR_19_16_MASK; + writel(reg, &base->aux_addr_19_16); + + /* + * Set DisplayPort transaction and read 1 byte + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; + writel(reg, &base->aux_ch_ctl_1); + + /* Start AUX transaction */ + retval = s5p_dp_start_aux_transaction(dp); + if (retval == 0) + break; + else + debug("Aux Transaction fail!\n"); + } + + /* Read data buffer */ + if (!retval) { + reg = readl(&base->buf_data_0); + *data = (unsigned char)(reg & 0xff); + } + + return retval; +} + +void s5p_dp_init_video(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; + writel(reg, &base->common_int_sta_1); + + reg = 0x0; + writel(reg, &base->sys_ctl_1); + + reg = (4 & CHA_CRI_MASK) << CHA_CRI_SHIFT; + reg |= CHA_CTRL; + writel(reg, &base->sys_ctl_2); + + reg = 0x0; + writel(reg, &base->sys_ctl_3); +} + +void s5p_dp_set_video_color_format(struct s5p_dp_device *dp, + unsigned int color_depth, + unsigned int color_space, + unsigned int dynamic_range, + unsigned int coeff) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + /* Configure the input color depth, color space, dynamic range */ + reg = (dynamic_range << IN_D_RANGE_SHIFT) | + (color_depth << IN_BPC_SHIFT) | + (color_space << IN_COLOR_F_SHIFT); + writel(reg, &base->video_ctl_2); + + /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ + reg = readl(&base->video_ctl_3); + reg &= ~IN_YC_COEFFI_MASK; + if (coeff) + reg |= IN_YC_COEFFI_ITU709; + else + reg |= IN_YC_COEFFI_ITU601; + writel(reg, &base->video_ctl_3); +} + +int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->sys_ctl_1); + writel(reg, &base->sys_ctl_1); + + reg = readl(&base->sys_ctl_1); + + if (!(reg & DET_STA)) + return -1; + + reg = readl(&base->sys_ctl_2); + writel(reg, &base->sys_ctl_2); + + reg = readl(&base->sys_ctl_2); + + if (reg & CHA_STA) { + debug("Input stream clk is changing\n"); + return -1; + } + + return 0; +} + +void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, + enum clock_recovery_m_value_type type, + unsigned int m_value, + unsigned int n_value) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + if (type == REGISTER_M) { + setbits_le32(&base->sys_ctl_4, FIX_M_VID); + + reg = m_value >> M_VID_0_VALUE_SHIFT; + writel(reg, &base->m_vid_0); + + reg = (m_value >> M_VID_1_VALUE_SHIFT); + writel(reg, &base->m_vid_1); + + reg = (m_value >> M_VID_2_VALUE_SHIFT); + writel(reg, &base->m_vid_2); + + reg = n_value >> N_VID_0_VALUE_SHIFT; + writel(reg, &base->n_vid_0); + + reg = (n_value >> N_VID_1_VALUE_SHIFT); + writel(reg, &base->n_vid_1); + + reg = (n_value >> N_VID_2_VALUE_SHIFT); + writel(reg, &base->n_vid_2); + } else { + clrbits_le32(&base->sys_ctl_4, FIX_M_VID); + + writel(0x00, &base->n_vid_0); + writel(0x80, &base->n_vid_1); + writel(0x00, &base->n_vid_2); + } +} + +void s5p_dp_enable_video_master(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->soc_general_ctl); + reg &= ~VIDEO_MODE_MASK; + reg |= VIDEO_MODE_SLAVE_MODE; + writel(reg, &base->soc_general_ctl); +} + +int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp) +{ + u32 reg, i = 0; + u32 start; + struct exynos5_dp *base = dp->base; + + /* Wait for 4 VSYNC_DET interrupts */ + start = get_timer(0); + do { + reg = readl(&base->common_int_sta_1); + if (reg & VSYNC_DET) { + i++; + writel(reg | VSYNC_DET, &base->common_int_sta_1); + } + if (i == 4) + break; + } while (get_timer(start) <= STREAM_ON_TIMEOUT); + + if (i != 4) { + debug("s5p_dp_is_video_stream_on timeout\n"); + return -1; + } + + return 0; +} + +void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, + struct video_info *video_info) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->func_en_1); + reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); + reg |= MASTER_VID_FUNC_EN_N; + writel(reg, &base->func_en_1); + + reg = readl(&base->video_ctl_10); + reg &= ~INTERACE_SCAN_CFG; + reg |= (video_info->interlaced << 2); + writel(reg, &base->video_ctl_10); + + reg = readl(&base->video_ctl_10); + reg &= ~VSYNC_POLARITY_CFG; + reg |= (video_info->v_sync_polarity << 1); + writel(reg, &base->video_ctl_10); + + reg = readl(&base->video_ctl_10); + reg &= ~HSYNC_POLARITY_CFG; + reg |= (video_info->h_sync_polarity << 0); + writel(reg, &base->video_ctl_10); + + reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; + writel(reg, &base->soc_general_ctl); +} + +void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->dp_hw_link_training); + while (reg & HW_TRAINING_EN) + reg = readl(&base->dp_hw_link_training); +} diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index 6face94..85b90a5 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## Copyright 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DRIVER_MAXIM_MAX77686 # select HAVE_ACPI_TABLES # select MMCONF_SUPPORT + select EXYNOS_DISPLAYPORT select CHROMEOS config MAINBOARD_DIR diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index 4c88ea8..cc24cf7 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -28,5 +28,19 @@ device domain 0 on device i2c 6 on end # ? device i2c 9 on end # ? end + chip cpu/samsung/exynos5-common/displayport/ + register "xres" = "1366" + register "yres" = "768" + register "bpp" = "16" + # complex magic timing! + register "clkval_f" = "2" + register "upper_margin" = "14" + register "lower_margin" = "3" + register "vsync" = "5" + register "left_margin" = "80" + register "right_margin" = "48" + register "hsync" = "32" + register "lcdbase" = "0x10000000" + end end end diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 5970357..72434fc 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -19,6 +19,8 @@ #include <console/console.h> #include <cbmem.h> +#include <cpu/samsung/exynos5250/fimd.h> +#include <cpu/samsung/exynos5-common/s5p-dp-core.h> void hardwaremain(int boot_complete); void main(void) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7e1cd57..639c2ef 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -31,7 +31,6 @@ #include <cpu/samsung/exynos5250/setup.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/clock_init.h> - #include <console/console.h> #include <arch/stages.h> @@ -70,6 +69,11 @@ static void initialize_s5p_mshc(void) { exynos_pinmux_config(PERIPH_ID_SDMMC2, 0); } +static void graphics(void) +{ + + exynos_pinmux_config(PERIPH_ID_DPHPD, 0); +} void main(void) { struct mem_timings *mem; @@ -108,6 +112,8 @@ void main(void) initialize_s5p_mshc(); + graphics(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);

1 0

Patch merged into coreboot/master: 026bbda ARM: remove code that is IMHO a dangerous design
by gerrit＠coreboot.org 04 Mar '13

04 Mar '13

the following patch was just integrated into master: commit 026bbda071161ad56822dceaabea03bceefac9ac Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Mar 4 09:46:31 2013 -0800 ARM: remove code that is IMHO a dangerous design OK, this is tl;dr. But I need to write this in hopes we make sure we don't put code like this into coreboot. Ever. Our excuse in this case is that it was imported, not obviously wrong, and easily changed. It made sense to get it in, make it work, then do a cleanup pass, because changing everything up front is almost impossible to debug. The exynos code has bunch of base register values, e.g. These are base addresses of things that look like a memory-mapped struct. To get these to a pointer, they created the following macro, which creates an inline function. static inline unsigned int samsung_get_base_##device(void) \ { \ return cpu_is_exynos5() ? EXYNOS5_##base : 0; \ } And then invoke it 31 times in a .h file, e.g.: SAMSUNG_BASE(clock, CLOCK_BASE) to create 31 functions. And then use it: struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); OK, what's wrong with this? It's easier to ask what's right with it. Answer: nothing. I have a long list of what's wrong, and I may leave some things out, but here goes: 1. the "function" can return a NULL if we're not on exynos5. Most uses of the code don't check the return value. 2. And why would this function be running, if we're not on an exynos5? Why compile it in? 3. Note the cast everywhere a samsung_get_base_xxx is used. The function returns an untyped variable, requiring the *user* to get two things right: the cast, and the function invocation. One can replace that _clock(); with _power(); in the code above, and they will be referencing the wrong registers, and they'll never get an error! We have a C compiler; use it to type data. 4. You're generating 31 functions using cpp each and every time the file is included. The C compiler has to parse these each time. It's not at all like a simple cpp macro which is only generated on use. 5. You can't tags or etags this code 6. In fact, any kind of analysis tool will be unable to do anything with this cpp magic. That's only a partial list. So what's the right way to do it? Just make typed constants, viz: Or, since I expect people will want the lower case function syntax, I've left it that way: Now we've got something that is efficient, and we don't even need to protect with any more. Hence this change. We've got something that is type checked, does not require users to cast on each use, will catch simple programming errors, can be analyzed with standard tools, and builds faster. So if we make a mistake: struct exynos5_clock *clk = samsung_get_base_adc(); We'll see it: src/cpu/samsung/exynos5250/clock.c: In function 'get_pll_clk': src/cpu/samsung/exynos5250/clock.c:183:3: error: initialization from incompatible pointer type [-Werror] which we would not have seen before. As a minor benefit, it shaves most of a second off the compilation. Change-Id: Ie67bc4bc038a8dd1837b977d07332d7d7fd6be1f Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2582 Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Mon Mar 4 19:41:24 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Mar 4 19:43:19 2013, giving +2 See http://review.coreboot.org/2582 for details. -gerrit

1 0

Patch set updated for coreboot: 860bbd9 ARM: remove code that is IMHO a dangerous design
by Ronald G. Minnich 04 Mar '13

04 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2582 -gerrit commit 860bbd9ce42e6037b1bbfb5492a2235df55adb3a Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Mar 4 09:46:31 2013 -0800 ARM: remove code that is IMHO a dangerous design OK, this is tl;dr. But I need to write this in hopes we make sure we don't put code like this into coreboot. Ever. Our excuse in this case is that it was imported, not obviously wrong, and easily changed. It made sense to get it in, make it work, then do a cleanup pass, because changing everything up front is almost impossible to debug. The exynos code has bunch of base register values, e.g. These are base addresses of things that look like a memory-mapped struct. To get these to a pointer, they created the following macro, which creates an inline function. static inline unsigned int samsung_get_base_##device(void) \ { \ return cpu_is_exynos5() ? EXYNOS5_##base : 0; \ } And then invoke it 31 times in a .h file, e.g.: SAMSUNG_BASE(clock, CLOCK_BASE) to create 31 functions. And then use it: struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); OK, what's wrong with this? It's easier to ask what's right with it. Answer: nothing. I have a long list of what's wrong, and I may leave some things out, but here goes: 1. the "function" can return a NULL if we're not on exynos5. Most uses of the code don't check the return value. 2. And why would this function be running, if we're not on an exynos5? Why compile it in? 3. Note the cast everywhere a samsung_get_base_xxx is used. The function returns an untyped variable, requiring the *user* to get two things right: the cast, and the function invocation. One can replace that _clock(); with _power(); in the code above, and they will be referencing the wrong registers, and they'll never get an error! We have a C compiler; use it to type data. 4. You're generating 31 functions using cpp each and every time the file is included. The C compiler has to parse these each time. It's not at all like a simple cpp macro which is only generated on use. 5. You can't tags or etags this code 6. In fact, any kind of analysis tool will be unable to do anything with this cpp magic. That's only a partial list. So what's the right way to do it? Just make typed constants, viz: Or, since I expect people will want the lower case function syntax, I've left it that way: Now we've got something that is efficient, and we don't even need to protect with any more. Hence this change. We've got something that is type checked, does not require users to cast on each use, will catch simple programming errors, can be analyzed with standard tools, and builds faster. So if we make a mistake: struct exynos5_clock *clk = samsung_get_base_adc(); We'll see it: src/cpu/samsung/exynos5250/clock.c: In function 'get_pll_clk': src/cpu/samsung/exynos5250/clock.c:183:3: error: initialization from incompatible pointer type [-Werror] which we would not have seen before. As a minor benefit, it shaves most of a second off the compilation. Change-Id: Ie67bc4bc038a8dd1837b977d07332d7d7fd6be1f Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5-common/pwm.c | 10 ++-- src/cpu/samsung/exynos5-common/sromc.c | 2 +- src/cpu/samsung/exynos5-common/timer.c | 2 +- src/cpu/samsung/exynos5-common/wdt.c | 4 +- src/cpu/samsung/exynos5250/clock.c | 20 ++++---- src/cpu/samsung/exynos5250/cpu.h | 85 +++++++++++++--------------------- src/cpu/samsung/exynos5250/power.c | 22 ++++----- 7 files changed, 62 insertions(+), 83 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/pwm.c b/src/cpu/samsung/exynos5-common/pwm.c index da465d9..0fc571b 100644 --- a/src/cpu/samsung/exynos5-common/pwm.c +++ b/src/cpu/samsung/exynos5-common/pwm.c @@ -32,7 +32,7 @@ int pwm_enable(int pwm_id) { const struct s5p_timer *pwm = - (struct s5p_timer *)samsung_get_base_timer(); + samsung_get_base_timer(); unsigned long tcon; tcon = readl(&pwm->tcon); @@ -46,7 +46,7 @@ int pwm_enable(int pwm_id) int pwm_check_enabled(int pwm_id) { const struct s5p_timer *pwm = - (struct s5p_timer *)samsung_get_base_timer(); + samsung_get_base_timer(); const unsigned long tcon = readl(&pwm->tcon); return tcon & TCON_START(pwm_id); @@ -55,7 +55,7 @@ int pwm_check_enabled(int pwm_id) void pwm_disable(int pwm_id) { const struct s5p_timer *pwm = - (struct s5p_timer *)samsung_get_base_timer(); + samsung_get_base_timer(); unsigned long tcon; tcon = readl(&pwm->tcon); @@ -84,7 +84,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) int pwm_config(int pwm_id, int duty_ns, int period_ns) { const struct s5p_timer *pwm = - (struct s5p_timer *)samsung_get_base_timer(); + samsung_get_base_timer(); unsigned int offset; unsigned long tin_rate; unsigned long tin_ns; @@ -143,7 +143,7 @@ int pwm_init(int pwm_id, int div, int invert) { u32 val; const struct s5p_timer *pwm = - (struct s5p_timer *)samsung_get_base_timer(); + samsung_get_base_timer(); unsigned long ticks_per_period; unsigned int offset, prescaler; diff --git a/src/cpu/samsung/exynos5-common/sromc.c b/src/cpu/samsung/exynos5-common/sromc.c index 091e8d1..7bc93e7 100644 --- a/src/cpu/samsung/exynos5-common/sromc.c +++ b/src/cpu/samsung/exynos5-common/sromc.c @@ -36,7 +36,7 @@ void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf) { u32 tmp; struct s5p_sromc *srom = - (struct s5p_sromc *)samsung_get_base_sromc(); + samsung_get_base_sromc(); /* Configure SMC_BW register to handle proper SROMC bank */ tmp = srom->bw; diff --git a/src/cpu/samsung/exynos5-common/timer.c b/src/cpu/samsung/exynos5-common/timer.c index 6436da2..6cd5f5d 100644 --- a/src/cpu/samsung/exynos5-common/timer.c +++ b/src/cpu/samsung/exynos5-common/timer.c @@ -39,7 +39,7 @@ static unsigned long lastinc; /* macro to read the 16 bit timer */ static inline struct s5p_timer *s5p_get_base_timer(void) { - return (struct s5p_timer *)samsung_get_base_timer(); + return samsung_get_base_timer(); } /** diff --git a/src/cpu/samsung/exynos5-common/wdt.c b/src/cpu/samsung/exynos5-common/wdt.c index 6f435e5..dbeefec 100644 --- a/src/cpu/samsung/exynos5-common/wdt.c +++ b/src/cpu/samsung/exynos5-common/wdt.c @@ -30,7 +30,7 @@ void wdt_stop(void) { struct s5p_watchdog *wdt = - (struct s5p_watchdog *)samsung_get_base_watchdog(); + samsung_get_base_watchdog(); unsigned int wtcon; wtcon = readl(&wdt->wtcon); @@ -42,7 +42,7 @@ void wdt_stop(void) void wdt_start(unsigned int timeout) { struct s5p_watchdog *wdt = - (struct s5p_watchdog *)samsung_get_base_watchdog(); + samsung_get_base_watchdog(); unsigned int wtcon; wdt_stop(); diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c index 115d40d..6b79272 100644 --- a/src/cpu/samsung/exynos5250/clock.c +++ b/src/cpu/samsung/exynos5250/clock.c @@ -180,7 +180,7 @@ static struct st_epll_con_val epll_div[] = { unsigned long get_pll_clk(int pllreg) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; unsigned int freq; @@ -246,7 +246,7 @@ unsigned long get_pll_clk(int pllreg) unsigned long clock_get_periph_rate(enum periph_id peripheral) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; unsigned long sclk, sub_clk; unsigned int src, div, sub_div; @@ -341,7 +341,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) unsigned long get_arm_clk(void) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned long div; unsigned long armclk; unsigned int arm_ratio; @@ -378,7 +378,7 @@ struct arm_clk_ratios *get_arm_clk_ratios(void) void set_mmc_clk(int dev_index, unsigned int div) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned int addr; unsigned int val; @@ -404,7 +404,7 @@ void set_mmc_clk(int dev_index, unsigned int div) void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned shift; unsigned mask = 0xff; u32 *reg; @@ -449,7 +449,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned shift; unsigned mask = 0xff; u32 *reg; @@ -574,7 +574,7 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate) int clock_set_mshci(enum periph_id peripheral) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); u32 *addr; unsigned int clock; unsigned int tmp; @@ -635,7 +635,7 @@ int clock_epll_set_rate(unsigned long rate) unsigned int lockcnt; unsigned int start; struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); epll_con = readl(&clk->epll_con0); epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK << @@ -685,7 +685,7 @@ int clock_epll_set_rate(unsigned long rate) void clock_select_i2s_clk_source(void) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK, (CLK_SRC_SCLK_EPLL)); @@ -694,7 +694,7 @@ void clock_select_i2s_clk_source(void) int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned int div ; if ((dst_frq == 0) || (src_frq == 0)) { diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h index b859823..772e591 100644 --- a/src/cpu/samsung/exynos5250/cpu.h +++ b/src/cpu/samsung/exynos5250/cpu.h @@ -79,59 +79,38 @@ /* Distance between each Trust Zone PC register set */ #define TZPC_BASE_OFFSET 0x10000 -#ifndef __ASSEMBLER__ - -/* FIXME(dhendrix): cpu_is_exynos5() seems broken atm... */ -#if 0 -#define SAMSUNG_BASE(device, base) \ -static inline unsigned int samsung_get_base_##device(void) \ -{ \ - return cpu_is_exynos5() ? EXYNOS5_##base : 0; \ -} -#endif -#define SAMSUNG_BASE(device, base) \ -static inline unsigned int samsung_get_base_##device(void) \ -{ \ - return EXYNOS5_##base; \ -} - -SAMSUNG_BASE(adc, ADC_BASE) -SAMSUNG_BASE(clock, CLOCK_BASE) -SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE) -SAMSUNG_BASE(dsim, MIPI_DSI1_BASE) -SAMSUNG_BASE(disp_ctrl, DISP1_CTRL_BASE) -SAMSUNG_BASE(fimd, FIMD_BASE) -SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE) -SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE) -SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE) -SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE) -SAMSUNG_BASE(gpio_part5, GPIO_PART5_BASE) -SAMSUNG_BASE(gpio_part6, GPIO_PART6_BASE) -SAMSUNG_BASE(pro_id, PRO_ID) - -#ifndef CONFIG_OF_CONTROL -SAMSUNG_BASE(mmc, MMC_BASE) -SAMSUNG_BASE(mshci, MSHC_BASE) -#endif - -SAMSUNG_BASE(modem, MODEM_BASE) -SAMSUNG_BASE(sromc, SROMC_BASE) -SAMSUNG_BASE(swreset, SWRESET) -SAMSUNG_BASE(sysreg, SYSREG_BASE) -SAMSUNG_BASE(timer, PWMTIMER_BASE) -SAMSUNG_BASE(uart, UART_BASE) -SAMSUNG_BASE(usb_phy, USBPHY_BASE) -SAMSUNG_BASE(usb_otg, USBOTG_BASE) -SAMSUNG_BASE(watchdog, WATCHDOG_BASE) -SAMSUNG_BASE(power, POWER_BASE) -SAMSUNG_BASE(i2s, I2S_BASE) -SAMSUNG_BASE(spi1, SPI1_BASE) -#ifndef CONFIG_OF_CONTROL -SAMSUNG_BASE(i2c, I2C_BASE) -SAMSUNG_BASE(spi, SPI_BASE) -SAMSUNG_BASE(spi_isp, SPI_ISP_BASE) -#endif -#endif +#define samsung_get_base_adc() ((struct exynos5_adc *)EXYNOS5_ADC_BASE) +#define samsung_get_base_clock() ((struct exynos5_clock *)EXYNOS5_CLOCK_BASE) +#define samsung_get_base_ace_sfr() ((struct exynos5_ace_sfr *)EXYNOS5_ACE_SFR_BASE) +#define samsung_get_base_dsim() ((struct exynos5_dsim *)EXYNOS5_MIPI_DSI1_BASE) +#define samsung_get_base_disp_ctrl() ((struct exynos5_disp_ctrl *)EXYNOS5_DISP1_CTRL_BASE) +#define samsung_get_base_fimd() ((struct exynos5_fimd *)EXYNOS5_FIMD_BASE) +#define samsung_get_base_gpio_part1() ((struct exynos5_gpio_part1 *)EXYNOS5_GPIO_PART1_BASE) +#define samsung_get_base_gpio_part2() ((struct exynos5_gpio_part2 *)EXYNOS5_GPIO_PART2_BASE) +#define samsung_get_base_gpio_part3() ((struct exynos5_gpio_part3 *)EXYNOS5_GPIO_PART3_BASE) +#define samsung_get_base_gpio_part4() ((struct exynos5_gpio_part4 *)EXYNOS5_GPIO_PART4_BASE) +#define samsung_get_base_gpio_part5() ((struct exynos5_gpio_part5 *)EXYNOS5_GPIO_PART5_BASE) +#define samsung_get_base_gpio_part6() ((struct exynos5_gpio_part6 *)EXYNOS5_GPIO_PART6_BASE) +#define samsung_get_base_pro_id() ((struct exynos5_pro_id *)EXYNOS5_PRO_ID) + +#define samsung_get_base_mmc() ((struct exynos5_mmc *)EXYNOS5_MMC_BASE) +#define samsung_get_base_mshci() ((struct exynos5_mshci *)EXYNOS5_MSHC_BASE) + +#define samsung_get_base_modem() ((struct exynos5_modem *)EXYNOS5_MODEM_BASE) +#define samsung_get_base_sromc() ((struct exynos5_sromc *)EXYNOS5_SROMC_BASE) +#define samsung_get_base_swreset() ((struct exynos5_swreset *)EXYNOS5_SWRESET) +#define samsung_get_base_sysreg() ((struct exynos5_sysreg *)EXYNOS5_SYSREG_BASE) +#define samsung_get_base_timer() ((struct s5p_timer *)EXYNOS5_PWMTIMER_BASE) +#define samsung_get_base_uart() ((struct exynos5_uart *)EXYNOS5_UART_BASE) +#define samsung_get_base_usb_phy() ((struct exynos5_usb_phy *)EXYNOS5_USBPHY_BASE) +#define samsung_get_base_usb_otg() ((struct exynos5_usb_otg *)EXYNOS5_USBOTG_BASE) +#define samsung_get_base_watchdog() ((struct exynos5_watchdog *)EXYNOS5_WATCHDOG_BASE) +#define samsung_get_base_power() ((struct exynos5_power *)EXYNOS5_POWER_BASE) +#define samsung_get_base_i2s() ((struct exynos5_i2s *)EXYNOS5_I2S_BASE) +#define samsung_get_base_spi1() ((struct exynos5_spi1 *)EXYNOS5_SPI1_BASE) +#define samsung_get_base_i2c() ((struct exynos5_i2c *)EXYNOS5_I2C_BASE) +#define samsung_get_base_spi() ((struct exynos5_spi *)EXYNOS5_SPI_BASE) +#define samsung_get_base_spi_isp() ((struct exynos5_spi_isp *)EXYNOS5_SPI_ISP_BASE) #define EXYNOS5_SPI_NUM_CONTROLLERS 5 #define EXYNOS_I2C_MAX_CONTROLLERS 8 diff --git a/src/cpu/samsung/exynos5250/power.c b/src/cpu/samsung/exynos5250/power.c index 41e1e1b..953bf5c 100644 --- a/src/cpu/samsung/exynos5250/power.c +++ b/src/cpu/samsung/exynos5250/power.c @@ -38,7 +38,7 @@ static void ps_hold_setup(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); /* Set PS-Hold high */ setbits_le32(&power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); @@ -47,7 +47,7 @@ static void ps_hold_setup(void) void power_reset(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); /* Clear inform1 so there's no change we think we've got a wake reset */ power->inform1 = 0; @@ -59,7 +59,7 @@ void power_reset(void) void power_shutdown(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); clrbits_le32(&power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); @@ -69,7 +69,7 @@ void power_shutdown(void) void power_enable_dp_phy(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); setbits_le32(&power->dptx_phy_control, DPTX_PHY_ENABLE); } @@ -77,9 +77,9 @@ void power_enable_dp_phy(void) void power_enable_usb_phy(void) { struct exynos5_sysreg *sysreg = - (struct exynos5_sysreg *)samsung_get_base_sysreg(); + samsung_get_base_sysreg(); struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); unsigned int phy_cfg; /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */ @@ -98,7 +98,7 @@ void power_enable_usb_phy(void) void power_disable_usb_phy(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); /* Disabling USBHost_PHY */ clrbits_le32(&power->usb_host_phy_ctrl, POWER_USB_HOST_PHY_CTRL_EN); @@ -107,7 +107,7 @@ void power_disable_usb_phy(void) void power_enable_hw_thermal_trip(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); /* Enable HW thermal trip */ setbits_le32(&power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP); @@ -116,7 +116,7 @@ void power_enable_hw_thermal_trip(void) uint32_t power_read_reset_status(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); return power->inform1; } @@ -124,7 +124,7 @@ uint32_t power_read_reset_status(void) void power_exit_wakeup(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); typedef void (*resume_func)(void); ((resume_func)power->inform0)(); @@ -193,7 +193,7 @@ int power_init(void) void power_enable_xclkout(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); /* use xxti for xclk out */ clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,

1 0

Patch set updated for coreboot: ec08bd0 samsung/exynos5: add display port and framebuffer defines and initialization
by Ronald G. Minnich 04 Mar '13

04 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2570 -gerrit commit ec08bd04e0a2323845a414497900941e981c5d2e Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Mar 1 10:18:14 2013 -0800 samsung/exynos5: add display port and framebuffer defines and initialization These are essential functions for setting up the display port and framebuffer, and also enable such things as aux channel communications. We do some very simple initialization in romstage, mainly set a GPIO so that the graphics is powering up, but the complex parts are done in the ramstage. This mirrors the way in which graphics is done in the x86 size. I've added a first pass at a real device, and put it in the mainboard Kconfig, hoping for corrections. Because startup is so complex, depending on device type, I've created a 'displayport' device that removes some of the complexity and makes the flow *much* clearer. You can actually follow the flow by looking at the code, which is not true on other implementations. Since display port is perhaps the main port used on these chips, that's a reasonable compromise. All parameters of importance are now in the device tree. Change-Id: I56400ec9016ecb8716ec5a5dae41fdfbfff4817a Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5-common/Makefile.inc | 4 + src/cpu/samsung/exynos5-common/displayport/Kconfig | 3 + .../exynos5-common/displayport/Makefile.inc | 1 + src/cpu/samsung/exynos5-common/displayport/chip.h | 40 ++ .../exynos5-common/displayport/displayport.c | 108 ++++ src/cpu/samsung/exynos5-common/exynos-fb.c | 597 +++++++++++++++++++++ src/cpu/samsung/exynos5-common/s5p-dp-core.h | 256 +++++++++ src/cpu/samsung/exynos5-common/s5p-dp-reg.c | 481 +++++++++++++++++ src/mainboard/google/snow/Kconfig | 3 +- src/mainboard/google/snow/devicetree.cb | 14 + src/mainboard/google/snow/ramstage.c | 2 + src/mainboard/google/snow/romstage.c | 8 +- 12 files changed, 1515 insertions(+), 2 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/Makefile.inc b/src/cpu/samsung/exynos5-common/Makefile.inc index 47abe0f..7abd75c 100644 --- a/src/cpu/samsung/exynos5-common/Makefile.inc +++ b/src/cpu/samsung/exynos5-common/Makefile.inc @@ -19,3 +19,7 @@ ramstage-y += pwm.c # needed by timer.c ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += i2c.c +ramstage-y += s5p-dp-reg.c +ramstage-y += exynos-fb.c + +subdirs-y += displayport diff --git a/src/cpu/samsung/exynos5-common/displayport/Kconfig b/src/cpu/samsung/exynos5-common/displayport/Kconfig new file mode 100644 index 0000000..b9af850 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/Kconfig @@ -0,0 +1,3 @@ +config EXYNOS_DISPLAYPORT + bool + diff --git a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc new file mode 100644 index 0000000..0a8e99c --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c diff --git a/src/cpu/samsung/exynos5-common/displayport/chip.h b/src/cpu/samsung/exynos5-common/displayport/chip.h new file mode 100644 index 0000000..275d00b --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H +#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H + +struct cpu_samsung_exynos5_common_displayport__config { + /* special magic numbers! */ + int clkval_f; + int upper_margin; + int lower_margin; + int vsync; + int left_margin; + int right_margin; + int hsync; + + int xres; + int yres; + int bpp; + + u32 lcdbase; +}; + +#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */ diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c new file mode 100644 index 0000000..1bb0770 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/displayport.c @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <stdlib.h> +#include <string.h> +#include <arch/io.h> + +#include <device/device.h> + +/* we distinguish a display port device from a raw graphics device because there are + * dramatic differences in startup depending on graphics usage. To make startup fast + * and easier to understand and debug we explicitly name this common case. The alternate + * approach, involving lots of machine and callbacks, is hard to debug and verify. + */ +static void exynos_displayport_init(void) +{ + struct cpu_samsung_exynos5_common_displayport__config *conf = dev->chip_info; + /* put these on the stack. If, at some point, we want to move this code to a + * pre-ram stage, it will be much easier. + */ + vidinfo_t vi; + struct exynos5_fimd_panel panel; + void *lcdbase; + + memset(vi, 0, sizeof(vi)); + memset(panel, 0, sizeof(panel)); + + panel.is_dp = 1; /* Display I/F is eDP */ + /* while it is true that we did a memset to zero, + * we leave some 'set to zero' entries here to make + * it clear what's going on. Graphics is confusing. + */ + panel.is_mipi = 0; + panel.fixvclk = 0; + panel.ivclk = 0; + panel.clkval_f = conf->clkval_f; + panel.upper_margin = conf->upper_margin; + panel.lower_margin = conf->lower_margin; + panel.vsync = conf->vsync; + panel.left_margin = conf->left_margin; + panel.right_margin = conf->right_margin; + panel.hsync = conf->hsync; + + vi->vl_col = conf->xres; + vi->fl_row = conf->yres; + vi->vl_bpix = conf->bpp; + vi->cmap = cbmem_reserve(64*1024); /* The size is a magic number from hardware. */ + + lcdbase = conf->lcdbase; + printk(BIOS_DEBUG, "Initializing exynos VGA\n"); + ret = lcd_ctrl_init(&vi, &panel, lcdbase); +#if 0 + ret = board_dp_lcd_vdd(blob, &wait_ms); + ret = board_dp_bridge_setup(blob, &wait_ms); + while (tries < 5){ + ret = board_dp_bridge_init(blob, &wait_ms); + ret = board_dp_hotplug(blob, &wait_ms); + if (ret){ + ret = board_dp_bridge_reset(blob, &wait_ms); + continue; + } + ret = dp_controller_init(blob, &wait_ms); + ret = board_dp_backlight_vdd(blob, &wait_ms); + ret = board_dp_backlight_pwm(blob, &wait_ms); + ret = board_dp_backlight_en(blob, &wait_ms); + } +#endif +} + +static void exynos_displayport_noop(device_t dummy) +{ +} + +static struct device_operations exynos_displayport_operations = { + .read_resources = exynos_displayport_noop, + .set_resources = exynos_displayport_noop, + .enable_resources = exynos_displayport_noop, + .init = exynos_displayport_init, + .scan_bus = exynos_displayport_noop, +}; + +static void exynos_displayport_enable(struct device *dev) +{ + if (dev->link_list != NULL) + dev->ops = &exynos_displayport_operations; +} + +struct chip_operations drivers_i2c_exynos_displayport_ops = { + CHIP_NAME("exynos displayport") + .enable_dev = exynos_displayport_enable; +}; diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c new file mode 100644 index 0000000..0ff7c24 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -0,0 +1,597 @@ +/* + * LCD driver for Exynos + * + * Copyright 2013 Google Inc. + * Copyright (C) 2012 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <arch/io.h> +#include <stdlib.h> +#include <string.h> +#include <console/console.h> +#include <cpu/samsung/exynos5250/cpu.h> +#include <cpu/samsung/exynos5250/power.h> +#include <cpu/samsung/exynos5250/sysreg.h> +#include <drivers/maxim/max77686/max77686.h> + +#include "device/i2c.h" +#include "cpu/samsung/exynos5-common/i2c.h" +#include "cpu/samsung/exynos5250/dsim.h" +#include "cpu/samsung/exynos5250/fimd.h" + +#include "cpu/samsung/exynos5250/s5p-dp.h" +#include "s5p-dp-core.h" + +/* To help debug any init errors here, define a list of possible errors */ +enum { + ERR_PLL_NOT_UNLOCKED = 2, + ERR_VIDEO_CLOCK_BAD, + ERR_VIDEO_STREAM_BAD, + ERR_DPCD_READ_ERROR1, /* 5 */ + + ERR_DPCD_WRITE_ERROR1, + ERR_DPCD_READ_ERROR2, + ERR_DPCD_WRITE_ERROR2, + ERR_INVALID_LANE, + ERR_PLL_NOT_LOCKED, /* 10 */ + + ERR_PRE_EMPHASIS_LEVELS, + ERR_LINK_RATE_ABNORMAL, + ERR_MAX_LANE_COUNT_ABNORMAL, + ERR_LINK_TRAINING_FAILURE, + ERR_MISSING_DP_BASE, /* 15 */ + + ERR_NO_FDT_NODE, +}; +/* ok, this is stupid, but we're going to leave the variables in here until we know it works. + * one cleanup task at a time. + */ +enum stage_t { + STAGE_START = 0, + STAGE_LCD_VDD, + STAGE_BRIDGE_SETUP, + STAGE_BRIDGE_INIT, + STAGE_BRIDGE_RESET, + STAGE_HOTPLUG, + STAGE_DP_CONTROLLER, + STAGE_BACKLIGHT_VDD, + STAGE_BACKLIGHT_PWM, + STAGE_BACKLIGHT_EN, + STAGE_DONE, +}; + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +short console_col; +short console_row; + + +#ifdef CONFIG_EXYNOS_DISPLAYPORT +static struct s5p_dp_device dp_device; + +#endif + +/* Bypass FIMD of DISP1_BLK */ +static void fimd_bypass(void) +{ +#if 0 + struct exynos5_sysreg *sysreg = + (struct exynos5_sysreg *)samsung_get_base_sysreg(); + + setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); +#endif +} + +/* Calculate the size of Framebuffer from the resolution */ +static u32 calc_fbsize(vidinfo_t *panel_info) +{ + /* They had PAGE_SIZE here instead of 4096. + * but that's a totally arbitrary number -- everything nowadays + * has lots of page sizes. + * So keep it obvious. + */ + return ALIGN((panel_info->vl_col * panel_info->vl_row * + ((1<<panel_info->vl_bpix) / 8)), 4096); +} + +/* + * Initialize display controller. + * + * @param lcdbase pointer to the base address of framebuffer. + * @pd pointer to the main panel_data structure + */ +void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd) +{ + unsigned int val; + u32 fbsize; + struct exynos5_fimd *fimd = + (struct exynos5_fimd *)samsung_get_base_fimd(); + struct exynos5_disp_ctrl *disp_ctrl = + (struct exynos5_disp_ctrl *)samsung_get_base_disp_ctrl(); + + writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); + val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); + writel(val, &fimd->vidcon0); + + val = (pd->vsync << VSYNC_PULSE_WIDTH_OFFSET) | + (pd->lower_margin << V_FRONT_PORCH_OFFSET) | + (pd->upper_margin << V_BACK_PORCH_OFFSET); + writel(val, &disp_ctrl->vidtcon0); + + val = (pd->hsync << HSYNC_PULSE_WIDTH_OFFSET) | + (pd->right_margin << H_FRONT_PORCH_OFFSET) | + (pd->left_margin << H_BACK_PORCH_OFFSET); + writel(val, &disp_ctrl->vidtcon1); + + val = ((pd->xres - 1) << HOZVAL_OFFSET) | + ((pd->yres - 1) << LINEVAL_OFFSET); + writel(val, &disp_ctrl->vidtcon2); + + writel((unsigned int)lcd_base, &fimd->vidw00add0b0); + + fbsize = calc_fbsize(panel_info); + writel((unsigned int)lcd_base + fbsize, &fimd->vidw00add1b0); + + writel(pd->xres * 2, &fimd->vidw00add2); + + val = ((pd->xres - 1) << OSD_RIGHTBOTX_F_OFFSET); + val |= ((pd->yres - 1) << OSD_RIGHTBOTY_F_OFFSET); + writel(val, &fimd->vidosd0b); + writel(pd->xres * pd->yres, &fimd->vidosd0c); + + setbits_le32(&fimd->shadowcon, CHANNEL0_EN); + + val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; + val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; + writel(val, &fimd->wincon0); + + /* DPCLKCON_ENABLE */ + writel(1 << 1, &fimd->dpclkcon); +} + +#if 0 +static void exynos_fimd_disable(void) +{ + struct exynos5_fimd *fimd = + (struct exynos5_fimd *)samsung_get_base_fimd(); + + writel(0, &fimd->wincon0); + clrbits_le32(&fimd->shadowcon, CHANNEL0_EN); +} +#endif +/* + * Configure DP in slave mode and wait for video stream. + * + * param dp pointer to main s5p-dp structure + * param video_info pointer to main video_info structure. + * return status + */ +static int s5p_dp_config_video(struct s5p_dp_device *dp, + struct video_info *video_info) +{ + int timeout = 0; + u32 start; + struct exynos5_dp *base = dp->base; + + s5p_dp_config_video_slave_mode(dp, video_info); + + s5p_dp_set_video_color_format(dp, video_info->color_depth, + video_info->color_space, + video_info->dynamic_range, + video_info->ycbcr_coeff); + + if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + debug("PLL is not locked yet.\n"); + return -ERR_PLL_NOT_UNLOCKED; + } + + start = get_timer(0); + do { + if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { + timeout++; + break; + } + } while (get_timer(start) <= STREAM_ON_TIMEOUT); + + if (!timeout) { + debug("Video Clock Not ok\n"); + return -ERR_VIDEO_CLOCK_BAD; + } + + /* Set to use the register calculated M/N video */ + s5p_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); + + clrbits_le32(&base->video_ctl_10, FORMAT_SEL); + + /* Disable video mute */ + clrbits_le32(&base->video_ctl_1, HDCP_VIDEO_MUTE); + + /* Configure video slave mode */ + s5p_dp_enable_video_master(dp); + + /* Enable video */ + setbits_le32(&base->video_ctl_1, VIDEO_EN); + timeout = s5p_dp_is_video_stream_on(dp); + + if (timeout) { + debug("Video Stream Not on\n"); + return -ERR_VIDEO_STREAM_BAD; + } + + return 0; +} + +/* + * Set DP to enhanced mode. We use this for EVT1 + * param dp pointer to main s5p-dp structure + * return status + */ +static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp) +{ + u8 data; + + if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data)) { + debug("DPCD read error\n"); + return -ERR_DPCD_READ_ERROR1; + } + + if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, + DPCD_ENHANCED_FRAME_EN | + (data & DPCD_LANE_COUNT_SET_MASK))) { + debug("DPCD write error\n"); + return -ERR_DPCD_WRITE_ERROR1; + } + + return 0; +} + +/* + * Enable scrambles mode. We use this for EVT1 + * param dp pointer to main s5p-dp structure + * return status + */ +static int s5p_dp_enable_scramble(struct s5p_dp_device *dp) +{ + u8 data; + struct exynos5_dp *base = dp->base; + + clrbits_le32(&base->dp_training_ptn_set, SCRAMBLING_DISABLE); + + if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, + &data)) { + debug("DPCD read error\n"); + return -ERR_DPCD_READ_ERROR2; + } + + if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, + (u8)(data & ~DPCD_SCRAMBLING_DISABLED))) { + debug("DPCD write error\n"); + return -ERR_DPCD_WRITE_ERROR2; + } + + return 0; +} + +/* + * Reset DP and prepare DP for init training + * param dp pointer to main s5p-dp structure + */ +static int s5p_dp_init_dp(struct s5p_dp_device *dp) +{ + int ret, i; + struct exynos5_dp *base = dp->base; + + for (i = 0; i < DP_INIT_TRIES; i++) { + s5p_dp_reset(dp); + + /* SW defined function Normal operation */ + clrbits_le32(&base->func_en_1, SW_FUNC_EN_N); + + ret = s5p_dp_init_analog_func(dp); + if (!ret) + break; + + udelay(5000); + debug("LCD retry init, attempt=%d ret=%d\n", i, ret); + } + if (i == DP_INIT_TRIES) { + debug("LCD initialization failed, ret=%d\n", ret); + return ret; + } + + s5p_dp_init_aux(dp); + + return ret; +} + +/* + * Set pre-emphasis level + * param dp pointer to main s5p-dp structure + * param pre_emphasis pre-emphasis level + * param lane lane number(0 - 3) + * return status + */ +static int s5p_dp_set_lane_lane_pre_emphasis(struct s5p_dp_device *dp, + int pre_emphasis, int lane) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = pre_emphasis << PRE_EMPHASIS_SET_SHIFT; + switch (lane) { + case 0: + writel(reg, &base->ln0_link_trn_ctl); + break; + case 1: + writel(reg, &base->ln1_link_trn_ctl); + break; + + case 2: + writel(reg, &base->ln2_link_trn_ctl); + break; + + case 3: + writel(reg, &base->ln3_link_trn_ctl); + break; + default: + debug("%s: Invalid lane %d\n", __func__, lane); + return -ERR_INVALID_LANE; + } + return 0; +} + +/* + * Read supported bandwidth type + * param dp pointer to main s5p-dp structure + * param bandwidth pointer to variable holding bandwidth type + */ +static void s5p_dp_get_max_rx_bandwidth(struct s5p_dp_device *dp, + u8 *bandwidth) +{ + u8 data; + + /* + * For DP rev.1.1, Maximum link rate of Main Link lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps + */ + s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data); + *bandwidth = data; +} + +/* + * Reset DP and prepare DP for init training + * param dp pointer to main s5p-dp structure + * param lane_count pointer to variable holding no of lanes + */ +static void s5p_dp_get_max_rx_lane_count(struct s5p_dp_device *dp, + u8 *lane_count) +{ + u8 data; + + /* + * For DP rev.1.1, Maximum number of Main Link lanes + * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes + */ + s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data); + *lane_count = data & DPCD_MAX_LANE_COUNT_MASK; +} + +/* + * DP H/w Link Training. Set DPCD link rate and bandwidth. + * param dp pointer to main s5p-dp structure + * param max_lane No of lanes + * param max_rate bandwidth + * return status + */ +static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, + unsigned int max_lane, + unsigned int max_rate) +{ + u32 data; + u32 start; + int lane; + struct exynos5_dp *base = dp->base; + + /* Stop Video */ + clrbits_le32(&base->video_ctl_1, VIDEO_EN); + + start = get_timer(0); + while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + if (get_timer(start) > PLL_LOCK_TIMEOUT) { + /* Ignore this error, and try to continue */ + printk(BIOS_ERR, "PLL is not locked yet.\n"); + break; + } + } + + /* Reset Macro */ + setbits_le32(&base->dp_phy_test, MACRO_RST); + + /* 10 us is the minimum reset time. */ + udelay(10); + + clrbits_le32(&base->dp_phy_test, MACRO_RST); + + /* Set TX pre-emphasis to minimum */ + for (lane = 0; lane < max_lane; lane++) + if (s5p_dp_set_lane_lane_pre_emphasis(dp, + PRE_EMPHASIS_LEVEL_0, lane)) { + debug("Unable to set pre emphasis level\n"); + return -ERR_PRE_EMPHASIS_LEVELS; + } + + /* All DP analog module power up */ + writel(0x00, &base->dp_phy_pd); + + /* Initialize by reading RX's DPCD */ + s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); + s5p_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); + + if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && + (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { + debug("Rx Max Link Rate is abnormal :%x !\n", + dp->link_train.link_rate); + /* Not Retrying */ + return -ERR_LINK_RATE_ABNORMAL; + } + + if (dp->link_train.lane_count == 0) { + debug("Rx Max Lane count is abnormal :%x !\n", + dp->link_train.lane_count); + /* Not retrying */ + return -ERR_MAX_LANE_COUNT_ABNORMAL; + } + + /* Setup TX lane count & rate */ + if (dp->link_train.lane_count > max_lane) + dp->link_train.lane_count = max_lane; + if (dp->link_train.link_rate > max_rate) + dp->link_train.link_rate = max_rate; + + /* Set link rate and count as you want to establish*/ + writel(dp->link_train.lane_count, &base->lane_count_set); + writel(dp->link_train.link_rate, &base->link_bw_set); + + /* Set sink to D0 (Sink Not Ready) mode. */ + s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, + DPCD_SET_POWER_STATE_D0); + + /* Start HW link training */ + writel(HW_TRAINING_EN, &base->dp_hw_link_training); + + /* Wait unitl HW link training done */ + s5p_dp_wait_hw_link_training_done(dp); + + /* Get hardware link training status */ + data = readl(&base->dp_hw_link_training); + if (data != 0) { + debug(" H/W link training failure: 0x%x\n", data); + return -ERR_LINK_TRAINING_FAILURE; + } + + /* Get Link Bandwidth */ + data = readl(&base->link_bw_set); + + dp->link_train.link_rate = data; + + data = readl(&base->lane_count_set); + dp->link_train.lane_count = data; + + return 0; +} + +/* + * Initialize DP display + */ +int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) +{ + int ret; + struct s5p_dp_device *dp = dp_device; + struct exynos5_dp *base; + + //dp->base = (struct exynos5_dp *)addr; + /* yes. we're a snow. Yet somehow our config is from a development kit? + * This Must Change */ + //dp->video_info = &smdk5250_dp_config; + + clock_init_dp_clock(); + + power_enable_dp_phy(); + ret = s5p_dp_init_dp(dp); + if (ret) { + debug("%s: Could not initialize dp\n", __func__); + return ret; + } + + ret = s5p_dp_hw_link_training(dp, dp->video_info->lane_count, + dp->video_info->link_rate); + if (ret) { + debug("unable to do link train\n"); + return ret; + } + /* Minimum delay after H/w Link training */ + udelay(1000); + + ret = s5p_dp_enable_scramble(dp); + if (ret) { + debug("unable to set scramble mode\n"); + return ret; + } + + ret = s5p_dp_enable_rx_to_enhanced_mode(dp); + if (ret) { + debug("unable to set enhanced mode\n"); + return ret; + } + + + base = dp->base; + /* Enable enhanced mode */ + setbits_le32(&base->sys_ctl_4, ENHANCED); + + writel(dp->link_train.lane_count, &base->lane_count_set); + writel(dp->link_train.link_rate, &base->link_bw_set); + + s5p_dp_init_video(dp); + ret = s5p_dp_config_video(dp, dp->video_info); + if (ret) { + debug("unable to config video\n"); + return ret; + } + + /* + * This delay is T3 in the LCD timing spec (defined as >200ms). We set + * this down to 60ms since that's the approximate maximum amount of time + * it'll take a bridge to start outputting LVDS data. The delay of + * >200ms is just a conservative value to avoid turning on the backlight + * when there's random LCD data on the screen. Shaving 140ms off the + * boot is an acceptable trade-off. + */ + *wait_ms = 60; + return 0; +} + +/** + * Init the LCD controller + * + * @param lcdbase Base address of LCD frame buffer + * @return 0 if ok, -ve error code on error + */ +int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase) +{ + int ret = 0; + + //vi->res = panel_info->vl_col; + //vi->yres = panel_info->vl_row; + + fimd_bypass(); + fb_init(panel_info, lcdbase, panel_data); + + /* Enable flushing after LCD writes if requested */ + // forget it. lcd_set_flush_dcache(1); + return ret; +} diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h new file mode 100644 index 0000000..67c1990 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h @@ -0,0 +1,256 @@ +/* + * Header file for Samsung DP (Display Port) interface driver. + * + * Copyright 2013 Google Inc. + * Copyright (C) 2012 Samsung Electronics Co., Ltd. + * Author: Jingoo Han <jg1.han(a)samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef _S5P_DP_CORE_H +#define _S5P_DP_CORE_H + +#define STREAM_ON_TIMEOUT 100 +#define PLL_LOCK_TIMEOUT 10 +#define DP_INIT_TRIES 10 +#define MAX_CR_LOOP 5 +#define MAX_EQ_LOOP 4 + +/* Link tare type */ +enum link_rate { + LINK_RATE_1_62GBPS = 0x06, + LINK_RATE_2_70GBPS = 0x0a +}; + +/* Number of lanes supported */ +enum link_lane_count { + LANE_COUNT1 = 1, + LANE_COUNT2 = 2, + LANE_COUNT4 = 4 +}; + +/* Pre emphasis level */ +enum pre_emphasis_level { + PRE_EMPHASIS_LEVEL_0, + PRE_EMPHASIS_LEVEL_1, + PRE_EMPHASIS_LEVEL_2, + PRE_EMPHASIS_LEVEL_3, +}; + +/* Type of color space */ +enum color_space { + COLOR_RGB, + COLOR_YCBCR422, + COLOR_YCBCR444 +}; + +/* Video input Bit Per Color */ +enum color_depth { + COLOR_6, + COLOR_8, + COLOR_10, + COLOR_12 +}; + +/* Type of YCbCr coefficient */ +enum color_coefficient { + COLOR_YCBCR601, + COLOR_YCBCR709 +}; + +/* Color range */ +enum dynamic_range { + VESA, + CEA +}; + +/* Status of PLL clock */ +enum pll_status { + PLL_UNLOCKED, + PLL_LOCKED +}; + +/* To choose type of m_value */ +enum clock_recovery_m_value_type { + CALCULATED_M, + REGISTER_M +}; + +struct video_info { + enum color_space color_space; + enum dynamic_range dynamic_range; + enum color_coefficient ycbcr_coeff; + enum color_depth color_depth; + + enum link_rate link_rate; + enum link_lane_count lane_count; + + char *name; + + unsigned int h_sync_polarity:1; + unsigned int v_sync_polarity:1; + unsigned int interlaced:1; +}; + +struct link_train { + u8 link_rate; + u8 lane_count; +}; + +struct s5p_dp_device { + unsigned int irq; + struct exynos5_dp *base; + struct video_info *video_info; + struct link_train link_train; +}; + +/* this struct is used by mainboards to pass mode info to the driver */ +typedef struct vidinfo { + u16 vl_col; + u16 vl_row; + u8 vl_bpix; + u16 *cmap; +} vidinfo_t; + +/* s5p_dp_reg.c */ + +/* + * Reset DP module + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_reset(struct s5p_dp_device *dp); +/* + * Initialize DP to recieve video stream + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_init_video(struct s5p_dp_device *dp); +/* + * Check whether PLL is locked + * + * param dp pointer to main s5p-dp structure + * return Lock status + */ +unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp); +/* + * Initialize analog functions of DP + * + * param dp pointer to main s5p-dp structure + * return 0 on success + */ +int s5p_dp_init_analog_func(struct s5p_dp_device *dp); +/* + * Initialize DP for AUX transaction + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_init_aux(struct s5p_dp_device *dp); + +/* + * Start an AUX transaction. + * + * param dp pointer to main s5p-dp structure + */ +int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp); + +/* + * Write a byte to DPCD register + * + * param dp pointer to main s5p-dp structure + * param reg_addr DPCD register to be written + * param data byte data to be written + * return write status + */ +int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char data); +/* + * Read a byte from DPCD register + * + * param dp pointer to main s5p-dp structure + * param reg_addr DPCD register to read + * param data read byte data + * return read status + */ +int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char *data); +/* + * Initialize DP video functions + * + * param dp pointer to main s5p-dp structure + */ +//void s5p_dp_init_video(struct s5p_dp_device *dp); + +/* + * Set color parameters for display + * + * param dp pointer to main s5p-dp structure + * param color_depth Video input Bit Per Color + * param color_space Colorimetric format of input video + * param dynamic_range VESA range or CEA range + * param coeff YCbCr Coefficients of input video + */ +void s5p_dp_set_video_color_format(struct s5p_dp_device *dp, + unsigned int color_depth, + unsigned int color_space, + unsigned int dynamic_range, + unsigned int coeff); +/* + * Check whether video clock is on + * + * param dp pointer to main s5p-dp structure + * return clock status + */ +int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp); +/* + * Check whether video clock is on + * + * param dp pointer to main s5p-dp structure + * param type clock_recovery_m_value_type + * param m_value to caluculate m_vid value + * param n_value to caluculate n_vid value + */ +void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, + enum clock_recovery_m_value_type type, + unsigned int m_value, + unsigned int n_value); +/* + * Set DP to video slave mode thereby enabling video master + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_enable_video_master(struct s5p_dp_device *dp); +/* + * Check whether video stream is on + * + * param dp pointer to main s5p-dp structure + * return video stream status + */ +int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp); +/* + * Configure DP in slave mode + * + * param dp pointer to main s5p-dp structure + * param video_info pointer to main video_info structure. + */ +void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, + struct video_info *video_info); + +/* + * Wait unitl HW link training done + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); + +/* startup and init */ +void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd); +int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms); +int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase); +#endif /* _S5P_DP_CORE_H */ diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c new file mode 100644 index 0000000..adb64a8 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c @@ -0,0 +1,481 @@ +/* + * Samsung DP (Display port) register interface driver. + * + * Copyright (C) 2012 Samsung Electronics Co., Ltd. + * Author: Jingoo Han <jg1.han(a)samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <common.h> +#include <arch/io.h> +#include <cpu/samsung/exynos5-common/clk.h> +#include <cpu/samsung/exynos5250/cpu.h> +#include <cpu/samsung/exynos5250/periph.h> +#include <cpu/samsung/exynos5250/s5p-dp.h> +#include "cpu/samsung/exynos5250/fimd.h" +#include "s5p-dp-core.h" + +void s5p_dp_reset(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + writel(RESET_DP_TX, &base->dp_tx_sw_reset); + + /* Stop Video */ + clrbits_le32(&base->video_ctl_1, VIDEO_EN); + clrbits_le32(&base->video_ctl_1, HDCP_VIDEO_MUTE); + + reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | + AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | + HDCP_FUNC_EN_N | SW_FUNC_EN_N; + writel(reg, &base->func_en_1); + + reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | + SERDES_FIFO_FUNC_EN_N | + LS_CLK_DOMAIN_FUNC_EN_N; + writel(reg, &base->func_en_2); + + udelay(20); + + reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | + LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; + + writel(reg, &base->lane_map); + + writel(0x0, &base->sys_ctl_1); + writel(0x40, &base->sys_ctl_2); + writel(0x0, &base->sys_ctl_3); + writel(0x0, &base->sys_ctl_4); + + writel(0x0, &base->pkt_send_ctl); + writel(0x0, &base->dp_hdcp_ctl); + + writel(0x5e, &base->dp_hpd_deglitch_l); + writel(0x1a, &base->dp_hpd_deglitch_h); + + writel(0x10, &base->dp_debug_ctl); + + writel(0x0, &base->dp_phy_test); + + writel(0x0, &base->dp_video_fifo_thrd); + writel(0x20, &base->dp_audio_margin); + + writel(0x4, &base->m_vid_gen_filter_th); + writel(0x2, &base->m_aud_gen_filter_th); + + writel(0x00000101, &base->soc_general_ctl); + + /* Set Analog Parameters */ + writel(0x10, &base->analog_ctl_1); + writel(0x0C, &base->analog_ctl_2); + writel(0x85, &base->analog_ctl_3); + writel(0x66, &base->pll_filter_ctl_1); + writel(0x0, &base->tx_amp_tuning_ctl); + + /* Set interrupt pin assertion polarity as high */ + writel(INT_POL0 | INT_POL1, &base->int_ctl); + + /* Clear pending regisers */ + writel(0xff, &base->common_int_sta_1); + writel(0x4f, &base->common_int_sta_2); + writel(0xe0, &base->common_int_sta_3); + writel(0xe7, &base->common_int_sta_4); + writel(0x63, &base->dp_int_sta); + + /* 0:mask,1: unmask */ + writel(0x00, &base->common_int_mask_1); + writel(0x00, &base->common_int_mask_2); + writel(0x00, &base->common_int_mask_3); + writel(0x00, &base->common_int_mask_4); + writel(0x00, &base->int_sta_mask); +} + +unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp) +{ + u32 reg; + + reg = readl(&dp->base->dp_debug_ctl); + if (reg & PLL_LOCK) + return PLL_LOCKED; + else + return PLL_UNLOCKED; +} + +int s5p_dp_init_analog_func(struct s5p_dp_device *dp) +{ + u32 reg; + u32 start; + struct exynos5_dp *base = dp->base; + + writel(0x00, &base->dp_phy_pd); + + reg = PLL_LOCK_CHG; + writel(reg, &base->common_int_sta_1); + + clrbits_le32(&base->dp_debug_ctl, (F_PLL_LOCK | PLL_LOCK_CTRL)); + + /* Power up PLL */ + if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + + clrbits_le32(&base->dp_pll_ctl, DP_PLL_PD); + + start = get_timer(0); + while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + if (get_timer(start) > PLL_LOCK_TIMEOUT) { + debug("%s: PLL is not locked yet\n", __func__); + return -1; + } + } + } + + /* Enable Serdes FIFO function and Link symbol clock domain module */ + clrbits_le32(&base->func_en_2, (SERDES_FIFO_FUNC_EN_N | + LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N)); + return 0; +} + +void s5p_dp_init_aux(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + /* Clear inerrupts related to AUX channel */ + reg = RPLY_RECEIV | AUX_ERR; + writel(reg, &base->dp_int_sta); + + /* Disable AUX channel module */ + setbits_le32(&base->func_en_2, AUX_FUNC_EN_N); + + /* Disable AUX transaction H/W retry */ + reg = (3 & AUX_BIT_PERIOD_MASK) << AUX_BIT_PERIOD_SHIFT; + reg |= (0 & AUX_HW_RETRY_COUNT_MASK) << AUX_HW_RETRY_COUNT_SHIFT; + reg |= (AUX_HW_RETRY_INTERVAL_600_US << AUX_HW_RETRY_INTERVAL_SHIFT); + writel(reg, &base->aux_hw_retry_ctl) ; + + /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ + reg = DEFER_CTRL_EN; + reg |= (1 & DEFER_COUNT_MASK) << DEFER_COUNT_SHIFT; + writel(reg, &base->aux_ch_defer_dtl); + + /* Enable AUX channel module */ + clrbits_le32(&base->func_en_2, AUX_FUNC_EN_N); +} + +int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) +{ + int reg; + struct exynos5_dp *base = dp->base; + + /* Enable AUX CH operation */ + setbits_le32(&base->aux_ch_ctl_2, AUX_EN); + + /* Is AUX CH command reply received? */ + reg = readl(&base->dp_int_sta); + while (!(reg & RPLY_RECEIV)) + reg = readl(&base->dp_int_sta); + + /* Clear interrupt source for AUX CH command reply */ + writel(RPLY_RECEIV, &base->dp_int_sta); + + /* Clear interrupt source for AUX CH access error */ + reg = readl(&base->dp_int_sta); + if (reg & AUX_ERR) { + writel(AUX_ERR, &base->dp_int_sta); + return -1; + } + + /* Check AUX CH error access status */ + reg = readl(&base->dp_int_sta); + if ((reg & AUX_STATUS_MASK) != 0) { + debug("AUX CH error happens: %d\n\n", + reg & AUX_STATUS_MASK); + return -1; + } + + return 0; +} + +int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char data) +{ + u32 reg; + int i; + int retval; + struct exynos5_dp *base = dp->base; + + for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) { + /* Clear AUX CH data buffer */ + writel(BUF_CLR, &base->buf_data_ctl); + + /* Select DPCD device address */ + reg = reg_addr >> AUX_ADDR_7_0_SHIFT; + reg &= AUX_ADDR_7_0_MASK; + writel(reg, &base->aux_addr_7_0); + reg = reg_addr >> AUX_ADDR_15_8_SHIFT; + reg &= AUX_ADDR_15_8_MASK; + writel(reg, &base->aux_addr_15_8); + reg = reg_addr >> AUX_ADDR_19_16_SHIFT; + reg &= AUX_ADDR_19_16_MASK; + writel(reg, &base->aux_addr_19_16); + + /* Write data buffer */ + reg = (unsigned int)data; + writel(reg, &base->buf_data_0); + + /* + * Set DisplayPort transaction and write 1 byte + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; + writel(reg, &base->aux_ch_ctl_1); + + /* Start AUX transaction */ + retval = s5p_dp_start_aux_transaction(dp); + if (retval == 0) + break; + else + debug("Aux Transaction fail!\n"); + } + + return retval; +} + +int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char *data) +{ + u32 reg; + int i; + int retval; + struct exynos5_dp *base = dp->base; + + for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) { + /* Clear AUX CH data buffer */ + writel(BUF_CLR, &base->buf_data_ctl); + + /* Select DPCD device address */ + reg = reg_addr >> AUX_ADDR_7_0_SHIFT; + reg &= AUX_ADDR_7_0_MASK; + writel(reg, &base->aux_addr_7_0); + reg = reg_addr >> AUX_ADDR_15_8_SHIFT; + reg &= AUX_ADDR_15_8_MASK; + writel(reg, &base->aux_addr_15_8); + reg = reg_addr >> AUX_ADDR_19_16_SHIFT; + reg &= AUX_ADDR_19_16_MASK; + writel(reg, &base->aux_addr_19_16); + + /* + * Set DisplayPort transaction and read 1 byte + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; + writel(reg, &base->aux_ch_ctl_1); + + /* Start AUX transaction */ + retval = s5p_dp_start_aux_transaction(dp); + if (retval == 0) + break; + else + debug("Aux Transaction fail!\n"); + } + + /* Read data buffer */ + if (!retval) { + reg = readl(&base->buf_data_0); + *data = (unsigned char)(reg & 0xff); + } + + return retval; +} + +void s5p_dp_init_video(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; + writel(reg, &base->common_int_sta_1); + + reg = 0x0; + writel(reg, &base->sys_ctl_1); + + reg = (4 & CHA_CRI_MASK) << CHA_CRI_SHIFT; + reg |= CHA_CTRL; + writel(reg, &base->sys_ctl_2); + + reg = 0x0; + writel(reg, &base->sys_ctl_3); +} + +void s5p_dp_set_video_color_format(struct s5p_dp_device *dp, + unsigned int color_depth, + unsigned int color_space, + unsigned int dynamic_range, + unsigned int coeff) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + /* Configure the input color depth, color space, dynamic range */ + reg = (dynamic_range << IN_D_RANGE_SHIFT) | + (color_depth << IN_BPC_SHIFT) | + (color_space << IN_COLOR_F_SHIFT); + writel(reg, &base->video_ctl_2); + + /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ + reg = readl(&base->video_ctl_3); + reg &= ~IN_YC_COEFFI_MASK; + if (coeff) + reg |= IN_YC_COEFFI_ITU709; + else + reg |= IN_YC_COEFFI_ITU601; + writel(reg, &base->video_ctl_3); +} + +int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->sys_ctl_1); + writel(reg, &base->sys_ctl_1); + + reg = readl(&base->sys_ctl_1); + + if (!(reg & DET_STA)) + return -1; + + reg = readl(&base->sys_ctl_2); + writel(reg, &base->sys_ctl_2); + + reg = readl(&base->sys_ctl_2); + + if (reg & CHA_STA) { + debug("Input stream clk is changing\n"); + return -1; + } + + return 0; +} + +void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, + enum clock_recovery_m_value_type type, + unsigned int m_value, + unsigned int n_value) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + if (type == REGISTER_M) { + setbits_le32(&base->sys_ctl_4, FIX_M_VID); + + reg = m_value >> M_VID_0_VALUE_SHIFT; + writel(reg, &base->m_vid_0); + + reg = (m_value >> M_VID_1_VALUE_SHIFT); + writel(reg, &base->m_vid_1); + + reg = (m_value >> M_VID_2_VALUE_SHIFT); + writel(reg, &base->m_vid_2); + + reg = n_value >> N_VID_0_VALUE_SHIFT; + writel(reg, &base->n_vid_0); + + reg = (n_value >> N_VID_1_VALUE_SHIFT); + writel(reg, &base->n_vid_1); + + reg = (n_value >> N_VID_2_VALUE_SHIFT); + writel(reg, &base->n_vid_2); + } else { + clrbits_le32(&base->sys_ctl_4, FIX_M_VID); + + writel(0x00, &base->n_vid_0); + writel(0x80, &base->n_vid_1); + writel(0x00, &base->n_vid_2); + } +} + +void s5p_dp_enable_video_master(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->soc_general_ctl); + reg &= ~VIDEO_MODE_MASK; + reg |= VIDEO_MODE_SLAVE_MODE; + writel(reg, &base->soc_general_ctl); +} + +int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp) +{ + u32 reg, i = 0; + u32 start; + struct exynos5_dp *base = dp->base; + + /* Wait for 4 VSYNC_DET interrupts */ + start = get_timer(0); + do { + reg = readl(&base->common_int_sta_1); + if (reg & VSYNC_DET) { + i++; + writel(reg | VSYNC_DET, &base->common_int_sta_1); + } + if (i == 4) + break; + } while (get_timer(start) <= STREAM_ON_TIMEOUT); + + if (i != 4) { + debug("s5p_dp_is_video_stream_on timeout\n"); + return -1; + } + + return 0; +} + +void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, + struct video_info *video_info) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->func_en_1); + reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); + reg |= MASTER_VID_FUNC_EN_N; + writel(reg, &base->func_en_1); + + reg = readl(&base->video_ctl_10); + reg &= ~INTERACE_SCAN_CFG; + reg |= (video_info->interlaced << 2); + writel(reg, &base->video_ctl_10); + + reg = readl(&base->video_ctl_10); + reg &= ~VSYNC_POLARITY_CFG; + reg |= (video_info->v_sync_polarity << 1); + writel(reg, &base->video_ctl_10); + + reg = readl(&base->video_ctl_10); + reg &= ~HSYNC_POLARITY_CFG; + reg |= (video_info->h_sync_polarity << 0); + writel(reg, &base->video_ctl_10); + + reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; + writel(reg, &base->soc_general_ctl); +} + +void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->dp_hw_link_training); + while (reg & HW_TRAINING_EN) + reg = readl(&base->dp_hw_link_training); +} diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index 6face94..85b90a5 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## Copyright 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DRIVER_MAXIM_MAX77686 # select HAVE_ACPI_TABLES # select MMCONF_SUPPORT + select EXYNOS_DISPLAYPORT select CHROMEOS config MAINBOARD_DIR diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index 4c88ea8..cc24cf7 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -28,5 +28,19 @@ device domain 0 on device i2c 6 on end # ? device i2c 9 on end # ? end + chip cpu/samsung/exynos5-common/displayport/ + register "xres" = "1366" + register "yres" = "768" + register "bpp" = "16" + # complex magic timing! + register "clkval_f" = "2" + register "upper_margin" = "14" + register "lower_margin" = "3" + register "vsync" = "5" + register "left_margin" = "80" + register "right_margin" = "48" + register "hsync" = "32" + register "lcdbase" = "0x10000000" + end end end diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 5970357..72434fc 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -19,6 +19,8 @@ #include <console/console.h> #include <cbmem.h> +#include <cpu/samsung/exynos5250/fimd.h> +#include <cpu/samsung/exynos5-common/s5p-dp-core.h> void hardwaremain(int boot_complete); void main(void) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7e1cd57..639c2ef 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -31,7 +31,6 @@ #include <cpu/samsung/exynos5250/setup.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/clock_init.h> - #include <console/console.h> #include <arch/stages.h> @@ -70,6 +69,11 @@ static void initialize_s5p_mshc(void) { exynos_pinmux_config(PERIPH_ID_SDMMC2, 0); } +static void graphics(void) +{ + + exynos_pinmux_config(PERIPH_ID_DPHPD, 0); +} void main(void) { struct mem_timings *mem; @@ -108,6 +112,8 @@ void main(void) initialize_s5p_mshc(); + graphics(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);

1 0

Patch set updated for coreboot: 43c9125 ARM: remove code that is IMHO a dangerous design
by Ronald G. Minnich 04 Mar '13

04 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2582 -gerrit commit 43c91251865ede5167031048f99f073ccc175190 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Mar 4 09:46:31 2013 -0800 ARM: remove code that is IMHO a dangerous design OK, this is tl;dr. But I need to write this in hopes we make sure we don't put code like this into coreboot. Ever. Our excuse in this case is that it was imported, not obviously wrong, and easily changed. It made sense to get it in, make it work, then do a cleanup pass, because changing everything up front is almost impossible to debug. The exynos code has bunch of base register values, e.g. These are base addresses of things that look like a memory-mapped struct. To get these to a pointer, they created the following macro, which creates an inline function. static inline unsigned int samsung_get_base_##device(void) \ { \ return cpu_is_exynos5() ? EXYNOS5_##base : 0; \ } And then invoke it 31 times in a .h file, e.g.: SAMSUNG_BASE(clock, CLOCK_BASE) to create 31 functions. And then use it: struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); OK, what's wrong with this? It's easier to ask what's right with it. Answer: nothing. I have a long list of what's wrong, and I may leave some things out, but here goes: 1. the "function" can return a NULL if we're not on exynos5. Most uses of the code don't check the return value. 2. And why would this function be running, if we're not on an exynos5? Why compile it in? 3. Note the cast everywhere a samsung_get_base_xxx is used. The function returns an untyped variable, requiring the *user* to get two things right: the cast, and the function invocation. One can replace that _clock(); with _power(); in the code above, and they will be referencing the wrong registers, and they'll never get an error! We have a C compiler; use it to type data. 4. You're generating 31 functions using cpp each and every time the file is included. The C compiler has to parse these each time. It's not at all like a simple cpp macro which is only generated on use. 5. You can't tags or etags this code 6. In fact, any kind of analysis tool will be unable to do anything with this cpp magic. That's only a partial list. So what's the right way to do it? Just make typed constants, viz: Or, since I expect people will want the lower case function syntax, I've left it that way: Now we've got something that is efficient, and we don't even need to protect with any more. Hence this change. We've got something that is type checked, does not require users to cast on each use, will catch simple programming errors, can be analyzed with standard tools, and builds faster. So if we make a mistake: struct exynos5_clock *clk = samsung_get_base_adc(); We'll see it: src/cpu/samsung/exynos5250/clock.c: In function 'get_pll_clk': src/cpu/samsung/exynos5250/clock.c:183:3: error: initialization from incompatible pointer type [-Werror] which we would not have seen before. As a minor benefit, it shaves most of a second off the compilation. Change-Id: Ie67bc4bc038a8dd1837b977d07332d7d7fd6be1f Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 8 +-- src/cpu/samsung/exynos5-common/pwm.c | 10 ++-- src/cpu/samsung/exynos5-common/sromc.c | 2 +- src/cpu/samsung/exynos5-common/timer.c | 2 +- src/cpu/samsung/exynos5-common/wdt.c | 4 +- src/cpu/samsung/exynos5250/clock.c | 20 +++---- src/cpu/samsung/exynos5250/cpu.h | 85 +++++++++++------------------- src/cpu/samsung/exynos5250/power.c | 22 ++++---- 8 files changed, 66 insertions(+), 87 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 0ff7c24..b649aef 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -100,7 +100,7 @@ static void fimd_bypass(void) { #if 0 struct exynos5_sysreg *sysreg = - (struct exynos5_sysreg *)samsung_get_base_sysreg(); + samsung_get_base_sysreg(); setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); #endif @@ -129,9 +129,9 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd unsigned int val; u32 fbsize; struct exynos5_fimd *fimd = - (struct exynos5_fimd *)samsung_get_base_fimd(); + samsung_get_base_fimd(); struct exynos5_disp_ctrl *disp_ctrl = - (struct exynos5_disp_ctrl *)samsung_get_base_disp_ctrl(); + samsung_get_base_disp_ctrl(); writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); @@ -177,7 +177,7 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd static void exynos_fimd_disable(void) { struct exynos5_fimd *fimd = - (struct exynos5_fimd *)samsung_get_base_fimd(); + samsung_get_base_fimd(); writel(0, &fimd->wincon0); clrbits_le32(&fimd->shadowcon, CHANNEL0_EN); diff --git a/src/cpu/samsung/exynos5-common/pwm.c b/src/cpu/samsung/exynos5-common/pwm.c index da465d9..0fc571b 100644 --- a/src/cpu/samsung/exynos5-common/pwm.c +++ b/src/cpu/samsung/exynos5-common/pwm.c @@ -32,7 +32,7 @@ int pwm_enable(int pwm_id) { const struct s5p_timer *pwm = - (struct s5p_timer *)samsung_get_base_timer(); + samsung_get_base_timer(); unsigned long tcon; tcon = readl(&pwm->tcon); @@ -46,7 +46,7 @@ int pwm_enable(int pwm_id) int pwm_check_enabled(int pwm_id) { const struct s5p_timer *pwm = - (struct s5p_timer *)samsung_get_base_timer(); + samsung_get_base_timer(); const unsigned long tcon = readl(&pwm->tcon); return tcon & TCON_START(pwm_id); @@ -55,7 +55,7 @@ int pwm_check_enabled(int pwm_id) void pwm_disable(int pwm_id) { const struct s5p_timer *pwm = - (struct s5p_timer *)samsung_get_base_timer(); + samsung_get_base_timer(); unsigned long tcon; tcon = readl(&pwm->tcon); @@ -84,7 +84,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) int pwm_config(int pwm_id, int duty_ns, int period_ns) { const struct s5p_timer *pwm = - (struct s5p_timer *)samsung_get_base_timer(); + samsung_get_base_timer(); unsigned int offset; unsigned long tin_rate; unsigned long tin_ns; @@ -143,7 +143,7 @@ int pwm_init(int pwm_id, int div, int invert) { u32 val; const struct s5p_timer *pwm = - (struct s5p_timer *)samsung_get_base_timer(); + samsung_get_base_timer(); unsigned long ticks_per_period; unsigned int offset, prescaler; diff --git a/src/cpu/samsung/exynos5-common/sromc.c b/src/cpu/samsung/exynos5-common/sromc.c index 091e8d1..7bc93e7 100644 --- a/src/cpu/samsung/exynos5-common/sromc.c +++ b/src/cpu/samsung/exynos5-common/sromc.c @@ -36,7 +36,7 @@ void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf) { u32 tmp; struct s5p_sromc *srom = - (struct s5p_sromc *)samsung_get_base_sromc(); + samsung_get_base_sromc(); /* Configure SMC_BW register to handle proper SROMC bank */ tmp = srom->bw; diff --git a/src/cpu/samsung/exynos5-common/timer.c b/src/cpu/samsung/exynos5-common/timer.c index 6436da2..6cd5f5d 100644 --- a/src/cpu/samsung/exynos5-common/timer.c +++ b/src/cpu/samsung/exynos5-common/timer.c @@ -39,7 +39,7 @@ static unsigned long lastinc; /* macro to read the 16 bit timer */ static inline struct s5p_timer *s5p_get_base_timer(void) { - return (struct s5p_timer *)samsung_get_base_timer(); + return samsung_get_base_timer(); } /** diff --git a/src/cpu/samsung/exynos5-common/wdt.c b/src/cpu/samsung/exynos5-common/wdt.c index 6f435e5..dbeefec 100644 --- a/src/cpu/samsung/exynos5-common/wdt.c +++ b/src/cpu/samsung/exynos5-common/wdt.c @@ -30,7 +30,7 @@ void wdt_stop(void) { struct s5p_watchdog *wdt = - (struct s5p_watchdog *)samsung_get_base_watchdog(); + samsung_get_base_watchdog(); unsigned int wtcon; wtcon = readl(&wdt->wtcon); @@ -42,7 +42,7 @@ void wdt_stop(void) void wdt_start(unsigned int timeout) { struct s5p_watchdog *wdt = - (struct s5p_watchdog *)samsung_get_base_watchdog(); + samsung_get_base_watchdog(); unsigned int wtcon; wdt_stop(); diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c index 115d40d..6b79272 100644 --- a/src/cpu/samsung/exynos5250/clock.c +++ b/src/cpu/samsung/exynos5250/clock.c @@ -180,7 +180,7 @@ static struct st_epll_con_val epll_div[] = { unsigned long get_pll_clk(int pllreg) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; unsigned int freq; @@ -246,7 +246,7 @@ unsigned long get_pll_clk(int pllreg) unsigned long clock_get_periph_rate(enum periph_id peripheral) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; unsigned long sclk, sub_clk; unsigned int src, div, sub_div; @@ -341,7 +341,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) unsigned long get_arm_clk(void) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned long div; unsigned long armclk; unsigned int arm_ratio; @@ -378,7 +378,7 @@ struct arm_clk_ratios *get_arm_clk_ratios(void) void set_mmc_clk(int dev_index, unsigned int div) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned int addr; unsigned int val; @@ -404,7 +404,7 @@ void set_mmc_clk(int dev_index, unsigned int div) void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned shift; unsigned mask = 0xff; u32 *reg; @@ -449,7 +449,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned shift; unsigned mask = 0xff; u32 *reg; @@ -574,7 +574,7 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate) int clock_set_mshci(enum periph_id peripheral) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); u32 *addr; unsigned int clock; unsigned int tmp; @@ -635,7 +635,7 @@ int clock_epll_set_rate(unsigned long rate) unsigned int lockcnt; unsigned int start; struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); epll_con = readl(&clk->epll_con0); epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK << @@ -685,7 +685,7 @@ int clock_epll_set_rate(unsigned long rate) void clock_select_i2s_clk_source(void) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK, (CLK_SRC_SCLK_EPLL)); @@ -694,7 +694,7 @@ void clock_select_i2s_clk_source(void) int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned int div ; if ((dst_frq == 0) || (src_frq == 0)) { diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h index b859823..772e591 100644 --- a/src/cpu/samsung/exynos5250/cpu.h +++ b/src/cpu/samsung/exynos5250/cpu.h @@ -79,59 +79,38 @@ /* Distance between each Trust Zone PC register set */ #define TZPC_BASE_OFFSET 0x10000 -#ifndef __ASSEMBLER__ - -/* FIXME(dhendrix): cpu_is_exynos5() seems broken atm... */ -#if 0 -#define SAMSUNG_BASE(device, base) \ -static inline unsigned int samsung_get_base_##device(void) \ -{ \ - return cpu_is_exynos5() ? EXYNOS5_##base : 0; \ -} -#endif -#define SAMSUNG_BASE(device, base) \ -static inline unsigned int samsung_get_base_##device(void) \ -{ \ - return EXYNOS5_##base; \ -} - -SAMSUNG_BASE(adc, ADC_BASE) -SAMSUNG_BASE(clock, CLOCK_BASE) -SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE) -SAMSUNG_BASE(dsim, MIPI_DSI1_BASE) -SAMSUNG_BASE(disp_ctrl, DISP1_CTRL_BASE) -SAMSUNG_BASE(fimd, FIMD_BASE) -SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE) -SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE) -SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE) -SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE) -SAMSUNG_BASE(gpio_part5, GPIO_PART5_BASE) -SAMSUNG_BASE(gpio_part6, GPIO_PART6_BASE) -SAMSUNG_BASE(pro_id, PRO_ID) - -#ifndef CONFIG_OF_CONTROL -SAMSUNG_BASE(mmc, MMC_BASE) -SAMSUNG_BASE(mshci, MSHC_BASE) -#endif - -SAMSUNG_BASE(modem, MODEM_BASE) -SAMSUNG_BASE(sromc, SROMC_BASE) -SAMSUNG_BASE(swreset, SWRESET) -SAMSUNG_BASE(sysreg, SYSREG_BASE) -SAMSUNG_BASE(timer, PWMTIMER_BASE) -SAMSUNG_BASE(uart, UART_BASE) -SAMSUNG_BASE(usb_phy, USBPHY_BASE) -SAMSUNG_BASE(usb_otg, USBOTG_BASE) -SAMSUNG_BASE(watchdog, WATCHDOG_BASE) -SAMSUNG_BASE(power, POWER_BASE) -SAMSUNG_BASE(i2s, I2S_BASE) -SAMSUNG_BASE(spi1, SPI1_BASE) -#ifndef CONFIG_OF_CONTROL -SAMSUNG_BASE(i2c, I2C_BASE) -SAMSUNG_BASE(spi, SPI_BASE) -SAMSUNG_BASE(spi_isp, SPI_ISP_BASE) -#endif -#endif +#define samsung_get_base_adc() ((struct exynos5_adc *)EXYNOS5_ADC_BASE) +#define samsung_get_base_clock() ((struct exynos5_clock *)EXYNOS5_CLOCK_BASE) +#define samsung_get_base_ace_sfr() ((struct exynos5_ace_sfr *)EXYNOS5_ACE_SFR_BASE) +#define samsung_get_base_dsim() ((struct exynos5_dsim *)EXYNOS5_MIPI_DSI1_BASE) +#define samsung_get_base_disp_ctrl() ((struct exynos5_disp_ctrl *)EXYNOS5_DISP1_CTRL_BASE) +#define samsung_get_base_fimd() ((struct exynos5_fimd *)EXYNOS5_FIMD_BASE) +#define samsung_get_base_gpio_part1() ((struct exynos5_gpio_part1 *)EXYNOS5_GPIO_PART1_BASE) +#define samsung_get_base_gpio_part2() ((struct exynos5_gpio_part2 *)EXYNOS5_GPIO_PART2_BASE) +#define samsung_get_base_gpio_part3() ((struct exynos5_gpio_part3 *)EXYNOS5_GPIO_PART3_BASE) +#define samsung_get_base_gpio_part4() ((struct exynos5_gpio_part4 *)EXYNOS5_GPIO_PART4_BASE) +#define samsung_get_base_gpio_part5() ((struct exynos5_gpio_part5 *)EXYNOS5_GPIO_PART5_BASE) +#define samsung_get_base_gpio_part6() ((struct exynos5_gpio_part6 *)EXYNOS5_GPIO_PART6_BASE) +#define samsung_get_base_pro_id() ((struct exynos5_pro_id *)EXYNOS5_PRO_ID) + +#define samsung_get_base_mmc() ((struct exynos5_mmc *)EXYNOS5_MMC_BASE) +#define samsung_get_base_mshci() ((struct exynos5_mshci *)EXYNOS5_MSHC_BASE) + +#define samsung_get_base_modem() ((struct exynos5_modem *)EXYNOS5_MODEM_BASE) +#define samsung_get_base_sromc() ((struct exynos5_sromc *)EXYNOS5_SROMC_BASE) +#define samsung_get_base_swreset() ((struct exynos5_swreset *)EXYNOS5_SWRESET) +#define samsung_get_base_sysreg() ((struct exynos5_sysreg *)EXYNOS5_SYSREG_BASE) +#define samsung_get_base_timer() ((struct s5p_timer *)EXYNOS5_PWMTIMER_BASE) +#define samsung_get_base_uart() ((struct exynos5_uart *)EXYNOS5_UART_BASE) +#define samsung_get_base_usb_phy() ((struct exynos5_usb_phy *)EXYNOS5_USBPHY_BASE) +#define samsung_get_base_usb_otg() ((struct exynos5_usb_otg *)EXYNOS5_USBOTG_BASE) +#define samsung_get_base_watchdog() ((struct exynos5_watchdog *)EXYNOS5_WATCHDOG_BASE) +#define samsung_get_base_power() ((struct exynos5_power *)EXYNOS5_POWER_BASE) +#define samsung_get_base_i2s() ((struct exynos5_i2s *)EXYNOS5_I2S_BASE) +#define samsung_get_base_spi1() ((struct exynos5_spi1 *)EXYNOS5_SPI1_BASE) +#define samsung_get_base_i2c() ((struct exynos5_i2c *)EXYNOS5_I2C_BASE) +#define samsung_get_base_spi() ((struct exynos5_spi *)EXYNOS5_SPI_BASE) +#define samsung_get_base_spi_isp() ((struct exynos5_spi_isp *)EXYNOS5_SPI_ISP_BASE) #define EXYNOS5_SPI_NUM_CONTROLLERS 5 #define EXYNOS_I2C_MAX_CONTROLLERS 8 diff --git a/src/cpu/samsung/exynos5250/power.c b/src/cpu/samsung/exynos5250/power.c index 41e1e1b..953bf5c 100644 --- a/src/cpu/samsung/exynos5250/power.c +++ b/src/cpu/samsung/exynos5250/power.c @@ -38,7 +38,7 @@ static void ps_hold_setup(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); /* Set PS-Hold high */ setbits_le32(&power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); @@ -47,7 +47,7 @@ static void ps_hold_setup(void) void power_reset(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); /* Clear inform1 so there's no change we think we've got a wake reset */ power->inform1 = 0; @@ -59,7 +59,7 @@ void power_reset(void) void power_shutdown(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); clrbits_le32(&power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); @@ -69,7 +69,7 @@ void power_shutdown(void) void power_enable_dp_phy(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); setbits_le32(&power->dptx_phy_control, DPTX_PHY_ENABLE); } @@ -77,9 +77,9 @@ void power_enable_dp_phy(void) void power_enable_usb_phy(void) { struct exynos5_sysreg *sysreg = - (struct exynos5_sysreg *)samsung_get_base_sysreg(); + samsung_get_base_sysreg(); struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); unsigned int phy_cfg; /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */ @@ -98,7 +98,7 @@ void power_enable_usb_phy(void) void power_disable_usb_phy(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); /* Disabling USBHost_PHY */ clrbits_le32(&power->usb_host_phy_ctrl, POWER_USB_HOST_PHY_CTRL_EN); @@ -107,7 +107,7 @@ void power_disable_usb_phy(void) void power_enable_hw_thermal_trip(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); /* Enable HW thermal trip */ setbits_le32(&power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP); @@ -116,7 +116,7 @@ void power_enable_hw_thermal_trip(void) uint32_t power_read_reset_status(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); return power->inform1; } @@ -124,7 +124,7 @@ uint32_t power_read_reset_status(void) void power_exit_wakeup(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); typedef void (*resume_func)(void); ((resume_func)power->inform0)(); @@ -193,7 +193,7 @@ int power_init(void) void power_enable_xclkout(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); /* use xxti for xclk out */ clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,

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New patch to review for coreboot: 7a8f435 ARM: remove code that is IMHO a dangerous design
by Ronald G. Minnich 04 Mar '13

04 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2582 -gerrit commit 7a8f435e858835a6899dfe8011d1efbe87a3667f Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Mon Mar 4 09:46:31 2013 -0800 ARM: remove code that is IMHO a dangerous design OK, this is tl;dr. But I need to write this in hopes we make sure we don't put code like this into coreboot. Ever. Our excuse in this case is that it was imported, not obviously wrong, and easily changed. It made sense to get it in, make it work, then do a cleanup pass, because changing everything up front is almost impossible to debug. The exynos code has bunch of base register values, e.g. These are base addresses of things that look like a memory-mapped struct. To get these to a pointer, they created the following macro, which creates an inline function. static inline unsigned int samsung_get_base_##device(void) \ { \ return cpu_is_exynos5() ? EXYNOS5_##base : 0; \ } And then invoke it 31 times in a .h file, e.g.: SAMSUNG_BASE(clock, CLOCK_BASE) to create 31 functions. And then use it: struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); OK, what's wrong with this? It's easier to ask what's right with it. Answer: nothing. I have a long list of what's wrong, and I may leave some things out, but here goes: 1. the "function" can return a NULL if we're not on exynos5. Most uses of the code don't check the return value. 2. And why would this function be running, if we're not on an exynos5? Why compile it in? 3. Note the cast everywhere a samsung_get_base_xxx is used. The function returns an untyped variable, requiring the *user* to get two things right: the cast, and the function invocation. One can replace that _clock(); with _power(); in the code above, and they will be referencing the wrong registers, and they'll never get an error! We have a C compiler; use it to type data. 4. You're generating 31 functions using cpp each and every time the file is included. The C compiler has to parse these each time. It's not at all like a simple cpp macro which is only generated on use. 5. You can't tags or etags this code 6. In fact, any kind of analysis tool will be unable to do anything with this cpp magic. That's only a partial list. So what's the right way to do it? Just make typed constants, viz: Or, since I expect people will want the lower case function syntax, I've left it that way: Now we've got something that is efficient, and we don't even need to protect with any more. Hence this change. We've got something that is type checked, does not require users to cast on each use, will catch simple programming errors, can be analyzed with standard tools, and builds faster. So if we make a mistake: struct exynos5_clock *clk = samsung_get_base_adc(); We'll see it: src/cpu/samsung/exynos5250/clock.c: In function 'get_pll_clk': src/cpu/samsung/exynos5250/clock.c:183:3: error: initialization from incompatible pointer type [-Werror] which we would not have seen before. As a minor benefit, it shaves most of a second off the compilation. Change-Id: Ie67bc4bc038a8dd1837b977d07332d7d7fd6be1f Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 8 +-- src/cpu/samsung/exynos5-common/pwm.c | 10 ++-- src/cpu/samsung/exynos5-common/sromc.c | 2 +- src/cpu/samsung/exynos5-common/timer.c | 2 +- src/cpu/samsung/exynos5-common/wdt.c | 4 +- src/cpu/samsung/exynos5250/clock.c | 20 +++---- src/cpu/samsung/exynos5250/cpu.h | 85 +++++++++++------------------- src/cpu/samsung/exynos5250/power.c | 22 ++++---- 8 files changed, 66 insertions(+), 87 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 0ff7c24..b649aef 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -100,7 +100,7 @@ static void fimd_bypass(void) { #if 0 struct exynos5_sysreg *sysreg = - (struct exynos5_sysreg *)samsung_get_base_sysreg(); + samsung_get_base_sysreg(); setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); #endif @@ -129,9 +129,9 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd unsigned int val; u32 fbsize; struct exynos5_fimd *fimd = - (struct exynos5_fimd *)samsung_get_base_fimd(); + samsung_get_base_fimd(); struct exynos5_disp_ctrl *disp_ctrl = - (struct exynos5_disp_ctrl *)samsung_get_base_disp_ctrl(); + samsung_get_base_disp_ctrl(); writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); @@ -177,7 +177,7 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd static void exynos_fimd_disable(void) { struct exynos5_fimd *fimd = - (struct exynos5_fimd *)samsung_get_base_fimd(); + samsung_get_base_fimd(); writel(0, &fimd->wincon0); clrbits_le32(&fimd->shadowcon, CHANNEL0_EN); diff --git a/src/cpu/samsung/exynos5-common/pwm.c b/src/cpu/samsung/exynos5-common/pwm.c index da465d9..0fc571b 100644 --- a/src/cpu/samsung/exynos5-common/pwm.c +++ b/src/cpu/samsung/exynos5-common/pwm.c @@ -32,7 +32,7 @@ int pwm_enable(int pwm_id) { const struct s5p_timer *pwm = - (struct s5p_timer *)samsung_get_base_timer(); + samsung_get_base_timer(); unsigned long tcon; tcon = readl(&pwm->tcon); @@ -46,7 +46,7 @@ int pwm_enable(int pwm_id) int pwm_check_enabled(int pwm_id) { const struct s5p_timer *pwm = - (struct s5p_timer *)samsung_get_base_timer(); + samsung_get_base_timer(); const unsigned long tcon = readl(&pwm->tcon); return tcon & TCON_START(pwm_id); @@ -55,7 +55,7 @@ int pwm_check_enabled(int pwm_id) void pwm_disable(int pwm_id) { const struct s5p_timer *pwm = - (struct s5p_timer *)samsung_get_base_timer(); + samsung_get_base_timer(); unsigned long tcon; tcon = readl(&pwm->tcon); @@ -84,7 +84,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) int pwm_config(int pwm_id, int duty_ns, int period_ns) { const struct s5p_timer *pwm = - (struct s5p_timer *)samsung_get_base_timer(); + samsung_get_base_timer(); unsigned int offset; unsigned long tin_rate; unsigned long tin_ns; @@ -143,7 +143,7 @@ int pwm_init(int pwm_id, int div, int invert) { u32 val; const struct s5p_timer *pwm = - (struct s5p_timer *)samsung_get_base_timer(); + samsung_get_base_timer(); unsigned long ticks_per_period; unsigned int offset, prescaler; diff --git a/src/cpu/samsung/exynos5-common/sromc.c b/src/cpu/samsung/exynos5-common/sromc.c index 091e8d1..7bc93e7 100644 --- a/src/cpu/samsung/exynos5-common/sromc.c +++ b/src/cpu/samsung/exynos5-common/sromc.c @@ -36,7 +36,7 @@ void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf) { u32 tmp; struct s5p_sromc *srom = - (struct s5p_sromc *)samsung_get_base_sromc(); + samsung_get_base_sromc(); /* Configure SMC_BW register to handle proper SROMC bank */ tmp = srom->bw; diff --git a/src/cpu/samsung/exynos5-common/timer.c b/src/cpu/samsung/exynos5-common/timer.c index 6436da2..6cd5f5d 100644 --- a/src/cpu/samsung/exynos5-common/timer.c +++ b/src/cpu/samsung/exynos5-common/timer.c @@ -39,7 +39,7 @@ static unsigned long lastinc; /* macro to read the 16 bit timer */ static inline struct s5p_timer *s5p_get_base_timer(void) { - return (struct s5p_timer *)samsung_get_base_timer(); + return samsung_get_base_timer(); } /** diff --git a/src/cpu/samsung/exynos5-common/wdt.c b/src/cpu/samsung/exynos5-common/wdt.c index 6f435e5..dbeefec 100644 --- a/src/cpu/samsung/exynos5-common/wdt.c +++ b/src/cpu/samsung/exynos5-common/wdt.c @@ -30,7 +30,7 @@ void wdt_stop(void) { struct s5p_watchdog *wdt = - (struct s5p_watchdog *)samsung_get_base_watchdog(); + samsung_get_base_watchdog(); unsigned int wtcon; wtcon = readl(&wdt->wtcon); @@ -42,7 +42,7 @@ void wdt_stop(void) void wdt_start(unsigned int timeout) { struct s5p_watchdog *wdt = - (struct s5p_watchdog *)samsung_get_base_watchdog(); + samsung_get_base_watchdog(); unsigned int wtcon; wdt_stop(); diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c index 115d40d..6b79272 100644 --- a/src/cpu/samsung/exynos5250/clock.c +++ b/src/cpu/samsung/exynos5250/clock.c @@ -180,7 +180,7 @@ static struct st_epll_con_val epll_div[] = { unsigned long get_pll_clk(int pllreg) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; unsigned int freq; @@ -246,7 +246,7 @@ unsigned long get_pll_clk(int pllreg) unsigned long clock_get_periph_rate(enum periph_id peripheral) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; unsigned long sclk, sub_clk; unsigned int src, div, sub_div; @@ -341,7 +341,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) unsigned long get_arm_clk(void) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned long div; unsigned long armclk; unsigned int arm_ratio; @@ -378,7 +378,7 @@ struct arm_clk_ratios *get_arm_clk_ratios(void) void set_mmc_clk(int dev_index, unsigned int div) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned int addr; unsigned int val; @@ -404,7 +404,7 @@ void set_mmc_clk(int dev_index, unsigned int div) void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned shift; unsigned mask = 0xff; u32 *reg; @@ -449,7 +449,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned shift; unsigned mask = 0xff; u32 *reg; @@ -574,7 +574,7 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate) int clock_set_mshci(enum periph_id peripheral) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); u32 *addr; unsigned int clock; unsigned int tmp; @@ -635,7 +635,7 @@ int clock_epll_set_rate(unsigned long rate) unsigned int lockcnt; unsigned int start; struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); epll_con = readl(&clk->epll_con0); epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK << @@ -685,7 +685,7 @@ int clock_epll_set_rate(unsigned long rate) void clock_select_i2s_clk_source(void) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK, (CLK_SRC_SCLK_EPLL)); @@ -694,7 +694,7 @@ void clock_select_i2s_clk_source(void) int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) { struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + samsung_get_base_clock(); unsigned int div ; if ((dst_frq == 0) || (src_frq == 0)) { diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h index b859823..772e591 100644 --- a/src/cpu/samsung/exynos5250/cpu.h +++ b/src/cpu/samsung/exynos5250/cpu.h @@ -79,59 +79,38 @@ /* Distance between each Trust Zone PC register set */ #define TZPC_BASE_OFFSET 0x10000 -#ifndef __ASSEMBLER__ - -/* FIXME(dhendrix): cpu_is_exynos5() seems broken atm... */ -#if 0 -#define SAMSUNG_BASE(device, base) \ -static inline unsigned int samsung_get_base_##device(void) \ -{ \ - return cpu_is_exynos5() ? EXYNOS5_##base : 0; \ -} -#endif -#define SAMSUNG_BASE(device, base) \ -static inline unsigned int samsung_get_base_##device(void) \ -{ \ - return EXYNOS5_##base; \ -} - -SAMSUNG_BASE(adc, ADC_BASE) -SAMSUNG_BASE(clock, CLOCK_BASE) -SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE) -SAMSUNG_BASE(dsim, MIPI_DSI1_BASE) -SAMSUNG_BASE(disp_ctrl, DISP1_CTRL_BASE) -SAMSUNG_BASE(fimd, FIMD_BASE) -SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE) -SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE) -SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE) -SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE) -SAMSUNG_BASE(gpio_part5, GPIO_PART5_BASE) -SAMSUNG_BASE(gpio_part6, GPIO_PART6_BASE) -SAMSUNG_BASE(pro_id, PRO_ID) - -#ifndef CONFIG_OF_CONTROL -SAMSUNG_BASE(mmc, MMC_BASE) -SAMSUNG_BASE(mshci, MSHC_BASE) -#endif - -SAMSUNG_BASE(modem, MODEM_BASE) -SAMSUNG_BASE(sromc, SROMC_BASE) -SAMSUNG_BASE(swreset, SWRESET) -SAMSUNG_BASE(sysreg, SYSREG_BASE) -SAMSUNG_BASE(timer, PWMTIMER_BASE) -SAMSUNG_BASE(uart, UART_BASE) -SAMSUNG_BASE(usb_phy, USBPHY_BASE) -SAMSUNG_BASE(usb_otg, USBOTG_BASE) -SAMSUNG_BASE(watchdog, WATCHDOG_BASE) -SAMSUNG_BASE(power, POWER_BASE) -SAMSUNG_BASE(i2s, I2S_BASE) -SAMSUNG_BASE(spi1, SPI1_BASE) -#ifndef CONFIG_OF_CONTROL -SAMSUNG_BASE(i2c, I2C_BASE) -SAMSUNG_BASE(spi, SPI_BASE) -SAMSUNG_BASE(spi_isp, SPI_ISP_BASE) -#endif -#endif +#define samsung_get_base_adc() ((struct exynos5_adc *)EXYNOS5_ADC_BASE) +#define samsung_get_base_clock() ((struct exynos5_clock *)EXYNOS5_CLOCK_BASE) +#define samsung_get_base_ace_sfr() ((struct exynos5_ace_sfr *)EXYNOS5_ACE_SFR_BASE) +#define samsung_get_base_dsim() ((struct exynos5_dsim *)EXYNOS5_MIPI_DSI1_BASE) +#define samsung_get_base_disp_ctrl() ((struct exynos5_disp_ctrl *)EXYNOS5_DISP1_CTRL_BASE) +#define samsung_get_base_fimd() ((struct exynos5_fimd *)EXYNOS5_FIMD_BASE) +#define samsung_get_base_gpio_part1() ((struct exynos5_gpio_part1 *)EXYNOS5_GPIO_PART1_BASE) +#define samsung_get_base_gpio_part2() ((struct exynos5_gpio_part2 *)EXYNOS5_GPIO_PART2_BASE) +#define samsung_get_base_gpio_part3() ((struct exynos5_gpio_part3 *)EXYNOS5_GPIO_PART3_BASE) +#define samsung_get_base_gpio_part4() ((struct exynos5_gpio_part4 *)EXYNOS5_GPIO_PART4_BASE) +#define samsung_get_base_gpio_part5() ((struct exynos5_gpio_part5 *)EXYNOS5_GPIO_PART5_BASE) +#define samsung_get_base_gpio_part6() ((struct exynos5_gpio_part6 *)EXYNOS5_GPIO_PART6_BASE) +#define samsung_get_base_pro_id() ((struct exynos5_pro_id *)EXYNOS5_PRO_ID) + +#define samsung_get_base_mmc() ((struct exynos5_mmc *)EXYNOS5_MMC_BASE) +#define samsung_get_base_mshci() ((struct exynos5_mshci *)EXYNOS5_MSHC_BASE) + +#define samsung_get_base_modem() ((struct exynos5_modem *)EXYNOS5_MODEM_BASE) +#define samsung_get_base_sromc() ((struct exynos5_sromc *)EXYNOS5_SROMC_BASE) +#define samsung_get_base_swreset() ((struct exynos5_swreset *)EXYNOS5_SWRESET) +#define samsung_get_base_sysreg() ((struct exynos5_sysreg *)EXYNOS5_SYSREG_BASE) +#define samsung_get_base_timer() ((struct s5p_timer *)EXYNOS5_PWMTIMER_BASE) +#define samsung_get_base_uart() ((struct exynos5_uart *)EXYNOS5_UART_BASE) +#define samsung_get_base_usb_phy() ((struct exynos5_usb_phy *)EXYNOS5_USBPHY_BASE) +#define samsung_get_base_usb_otg() ((struct exynos5_usb_otg *)EXYNOS5_USBOTG_BASE) +#define samsung_get_base_watchdog() ((struct exynos5_watchdog *)EXYNOS5_WATCHDOG_BASE) +#define samsung_get_base_power() ((struct exynos5_power *)EXYNOS5_POWER_BASE) +#define samsung_get_base_i2s() ((struct exynos5_i2s *)EXYNOS5_I2S_BASE) +#define samsung_get_base_spi1() ((struct exynos5_spi1 *)EXYNOS5_SPI1_BASE) +#define samsung_get_base_i2c() ((struct exynos5_i2c *)EXYNOS5_I2C_BASE) +#define samsung_get_base_spi() ((struct exynos5_spi *)EXYNOS5_SPI_BASE) +#define samsung_get_base_spi_isp() ((struct exynos5_spi_isp *)EXYNOS5_SPI_ISP_BASE) #define EXYNOS5_SPI_NUM_CONTROLLERS 5 #define EXYNOS_I2C_MAX_CONTROLLERS 8 diff --git a/src/cpu/samsung/exynos5250/power.c b/src/cpu/samsung/exynos5250/power.c index 41e1e1b..953bf5c 100644 --- a/src/cpu/samsung/exynos5250/power.c +++ b/src/cpu/samsung/exynos5250/power.c @@ -38,7 +38,7 @@ static void ps_hold_setup(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); /* Set PS-Hold high */ setbits_le32(&power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); @@ -47,7 +47,7 @@ static void ps_hold_setup(void) void power_reset(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); /* Clear inform1 so there's no change we think we've got a wake reset */ power->inform1 = 0; @@ -59,7 +59,7 @@ void power_reset(void) void power_shutdown(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); clrbits_le32(&power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); @@ -69,7 +69,7 @@ void power_shutdown(void) void power_enable_dp_phy(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); setbits_le32(&power->dptx_phy_control, DPTX_PHY_ENABLE); } @@ -77,9 +77,9 @@ void power_enable_dp_phy(void) void power_enable_usb_phy(void) { struct exynos5_sysreg *sysreg = - (struct exynos5_sysreg *)samsung_get_base_sysreg(); + samsung_get_base_sysreg(); struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); unsigned int phy_cfg; /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */ @@ -98,7 +98,7 @@ void power_enable_usb_phy(void) void power_disable_usb_phy(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); /* Disabling USBHost_PHY */ clrbits_le32(&power->usb_host_phy_ctrl, POWER_USB_HOST_PHY_CTRL_EN); @@ -107,7 +107,7 @@ void power_disable_usb_phy(void) void power_enable_hw_thermal_trip(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); /* Enable HW thermal trip */ setbits_le32(&power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP); @@ -116,7 +116,7 @@ void power_enable_hw_thermal_trip(void) uint32_t power_read_reset_status(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); return power->inform1; } @@ -124,7 +124,7 @@ uint32_t power_read_reset_status(void) void power_exit_wakeup(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); typedef void (*resume_func)(void); ((resume_func)power->inform0)(); @@ -193,7 +193,7 @@ int power_init(void) void power_enable_xclkout(void) { struct exynos5_power *power = - (struct exynos5_power *)samsung_get_base_power(); + samsung_get_base_power(); /* use xxti for xclk out */ clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,

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Patch set updated for coreboot: c7e828b samsung/exynos5: add display port and framebuffer defines and initialization
by Ronald G. Minnich 04 Mar '13

04 Mar '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2570 -gerrit commit c7e828b2cbc63c175176209a6b5c9d46308f3aba Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Mar 1 10:18:14 2013 -0800 samsung/exynos5: add display port and framebuffer defines and initialization These are essential functions for setting up the display port and framebuffer, and also enable such things as aux channel communications. We do some very simple initialization in romstage, mainly set a GPIO so that the graphics is powering up, but the complex parts are done in the ramstage. This mirrors the way in which graphics is done in the x86 size. I've added a first pass at a real device, and put it in the mainboard Kconfig, hoping for corrections. Because startup is so complex, depending on device type, I've created a 'displayport' device that removes some of the complexity and makes the flow *much* clearer. You can actually follow the flow by looking at the code, which is not true on other implementations. Since display port is perhaps the main port used on these chips, that's a reasonable compromise. All parameters of importance are now in the device tree. Change-Id: I56400ec9016ecb8716ec5a5dae41fdfbfff4817a Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5-common/Makefile.inc | 4 + src/cpu/samsung/exynos5-common/displayport/Kconfig | 3 + .../exynos5-common/displayport/Makefile.inc | 1 + src/cpu/samsung/exynos5-common/displayport/chip.h | 40 ++ .../exynos5-common/displayport/displayport.c | 108 ++++ src/cpu/samsung/exynos5-common/exynos-fb.c | 597 +++++++++++++++++++++ src/cpu/samsung/exynos5-common/s5p-dp-core.h | 256 +++++++++ src/cpu/samsung/exynos5-common/s5p-dp-reg.c | 481 +++++++++++++++++ src/mainboard/google/snow/Kconfig | 3 +- src/mainboard/google/snow/devicetree.cb | 14 + src/mainboard/google/snow/ramstage.c | 2 + src/mainboard/google/snow/romstage.c | 8 +- 12 files changed, 1515 insertions(+), 2 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/Makefile.inc b/src/cpu/samsung/exynos5-common/Makefile.inc index 47abe0f..7abd75c 100644 --- a/src/cpu/samsung/exynos5-common/Makefile.inc +++ b/src/cpu/samsung/exynos5-common/Makefile.inc @@ -19,3 +19,7 @@ ramstage-y += pwm.c # needed by timer.c ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += i2c.c +ramstage-y += s5p-dp-reg.c +ramstage-y += exynos-fb.c + +subdirs-y += displayport diff --git a/src/cpu/samsung/exynos5-common/displayport/Kconfig b/src/cpu/samsung/exynos5-common/displayport/Kconfig new file mode 100644 index 0000000..b9af850 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/Kconfig @@ -0,0 +1,3 @@ +config EXYNOS_DISPLAYPORT + bool + diff --git a/src/cpu/samsung/exynos5-common/displayport/Makefile.inc b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc new file mode 100644 index 0000000..0a8e99c --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c diff --git a/src/cpu/samsung/exynos5-common/displayport/chip.h b/src/cpu/samsung/exynos5-common/displayport/chip.h new file mode 100644 index 0000000..275d00b --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H +#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H + +struct cpu_samsung_exynos5_common_displayport__config { + /* special magic numbers! */ + int clkval_f; + int upper_margin; + int lower_margin; + int vsync; + int left_margin; + int right_margin; + int hsync; + + int xres; + int yres; + int bpp; + + u32 lcdbase; +}; + +#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */ diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c new file mode 100644 index 0000000..1bb0770 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/displayport/displayport.c @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <stdlib.h> +#include <string.h> +#include <arch/io.h> + +#include <device/device.h> + +/* we distinguish a display port device from a raw graphics device because there are + * dramatic differences in startup depending on graphics usage. To make startup fast + * and easier to understand and debug we explicitly name this common case. The alternate + * approach, involving lots of machine and callbacks, is hard to debug and verify. + */ +static void exynos_displayport_init(void) +{ + struct cpu_samsung_exynos5_common_displayport__config *conf = dev->chip_info; + /* put these on the stack. If, at some point, we want to move this code to a + * pre-ram stage, it will be much easier. + */ + vidinfo_t vi; + struct exynos5_fimd_panel panel; + void *lcdbase; + + memset(vi, 0, sizeof(vi)); + memset(panel, 0, sizeof(panel)); + + panel.is_dp = 1; /* Display I/F is eDP */ + /* while it is true that we did a memset to zero, + * we leave some 'set to zero' entries here to make + * it clear what's going on. Graphics is confusing. + */ + panel.is_mipi = 0; + panel.fixvclk = 0; + panel.ivclk = 0; + panel.clkval_f = conf->clkval_f; + panel.upper_margin = conf->upper_margin; + panel.lower_margin = conf->lower_margin; + panel.vsync = conf->vsync; + panel.left_margin = conf->left_margin; + panel.right_margin = conf->right_margin; + panel.hsync = conf->hsync; + + vi->vl_col = conf->xres; + vi->fl_row = conf->yres; + vi->vl_bpix = conf->bpp; + vi->cmap = cbmem_reserve(64*1024); /* The size is a magic number from hardware. */ + + lcdbase = conf->lcdbase; + printk(BIOS_DEBUG, "Initializing exynos VGA\n"); + ret = lcd_ctrl_init(&vi, &panel, lcdbase); +#if 0 + ret = board_dp_lcd_vdd(blob, &wait_ms); + ret = board_dp_bridge_setup(blob, &wait_ms); + while (tries < 5){ + ret = board_dp_bridge_init(blob, &wait_ms); + ret = board_dp_hotplug(blob, &wait_ms); + if (ret){ + ret = board_dp_bridge_reset(blob, &wait_ms); + continue; + } + ret = dp_controller_init(blob, &wait_ms); + ret = board_dp_backlight_vdd(blob, &wait_ms); + ret = board_dp_backlight_pwm(blob, &wait_ms); + ret = board_dp_backlight_en(blob, &wait_ms); + } +#endif +} + +static void exynos_displayport_noop(device_t dummy) +{ +} + +static struct device_operations exynos_displayport_operations = { + .read_resources = exynos_displayport_noop, + .set_resources = exynos_displayport_noop, + .enable_resources = exynos_displayport_noop, + .init = exynos_displayport_init, + .scan_bus = exynos_displayport_noop, +}; + +static void exynos_displayport_enable(struct device *dev) +{ + if (dev->link_list != NULL) + dev->ops = &exynos_displayport_operations; +} + +struct chip_operations drivers_i2c_exynos_displayport_ops = { + CHIP_NAME("exynos displayport") + .enable_dev = exynos_displayport_enable; +}; diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c new file mode 100644 index 0000000..0ff7c24 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -0,0 +1,597 @@ +/* + * LCD driver for Exynos + * + * Copyright 2013 Google Inc. + * Copyright (C) 2012 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <arch/io.h> +#include <stdlib.h> +#include <string.h> +#include <console/console.h> +#include <cpu/samsung/exynos5250/cpu.h> +#include <cpu/samsung/exynos5250/power.h> +#include <cpu/samsung/exynos5250/sysreg.h> +#include <drivers/maxim/max77686/max77686.h> + +#include "device/i2c.h" +#include "cpu/samsung/exynos5-common/i2c.h" +#include "cpu/samsung/exynos5250/dsim.h" +#include "cpu/samsung/exynos5250/fimd.h" + +#include "cpu/samsung/exynos5250/s5p-dp.h" +#include "s5p-dp-core.h" + +/* To help debug any init errors here, define a list of possible errors */ +enum { + ERR_PLL_NOT_UNLOCKED = 2, + ERR_VIDEO_CLOCK_BAD, + ERR_VIDEO_STREAM_BAD, + ERR_DPCD_READ_ERROR1, /* 5 */ + + ERR_DPCD_WRITE_ERROR1, + ERR_DPCD_READ_ERROR2, + ERR_DPCD_WRITE_ERROR2, + ERR_INVALID_LANE, + ERR_PLL_NOT_LOCKED, /* 10 */ + + ERR_PRE_EMPHASIS_LEVELS, + ERR_LINK_RATE_ABNORMAL, + ERR_MAX_LANE_COUNT_ABNORMAL, + ERR_LINK_TRAINING_FAILURE, + ERR_MISSING_DP_BASE, /* 15 */ + + ERR_NO_FDT_NODE, +}; +/* ok, this is stupid, but we're going to leave the variables in here until we know it works. + * one cleanup task at a time. + */ +enum stage_t { + STAGE_START = 0, + STAGE_LCD_VDD, + STAGE_BRIDGE_SETUP, + STAGE_BRIDGE_INIT, + STAGE_BRIDGE_RESET, + STAGE_HOTPLUG, + STAGE_DP_CONTROLLER, + STAGE_BACKLIGHT_VDD, + STAGE_BACKLIGHT_PWM, + STAGE_BACKLIGHT_EN, + STAGE_DONE, +}; + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +short console_col; +short console_row; + + +#ifdef CONFIG_EXYNOS_DISPLAYPORT +static struct s5p_dp_device dp_device; + +#endif + +/* Bypass FIMD of DISP1_BLK */ +static void fimd_bypass(void) +{ +#if 0 + struct exynos5_sysreg *sysreg = + (struct exynos5_sysreg *)samsung_get_base_sysreg(); + + setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); +#endif +} + +/* Calculate the size of Framebuffer from the resolution */ +static u32 calc_fbsize(vidinfo_t *panel_info) +{ + /* They had PAGE_SIZE here instead of 4096. + * but that's a totally arbitrary number -- everything nowadays + * has lots of page sizes. + * So keep it obvious. + */ + return ALIGN((panel_info->vl_col * panel_info->vl_row * + ((1<<panel_info->vl_bpix) / 8)), 4096); +} + +/* + * Initialize display controller. + * + * @param lcdbase pointer to the base address of framebuffer. + * @pd pointer to the main panel_data structure + */ +void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd) +{ + unsigned int val; + u32 fbsize; + struct exynos5_fimd *fimd = + (struct exynos5_fimd *)samsung_get_base_fimd(); + struct exynos5_disp_ctrl *disp_ctrl = + (struct exynos5_disp_ctrl *)samsung_get_base_disp_ctrl(); + + writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); + val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); + writel(val, &fimd->vidcon0); + + val = (pd->vsync << VSYNC_PULSE_WIDTH_OFFSET) | + (pd->lower_margin << V_FRONT_PORCH_OFFSET) | + (pd->upper_margin << V_BACK_PORCH_OFFSET); + writel(val, &disp_ctrl->vidtcon0); + + val = (pd->hsync << HSYNC_PULSE_WIDTH_OFFSET) | + (pd->right_margin << H_FRONT_PORCH_OFFSET) | + (pd->left_margin << H_BACK_PORCH_OFFSET); + writel(val, &disp_ctrl->vidtcon1); + + val = ((pd->xres - 1) << HOZVAL_OFFSET) | + ((pd->yres - 1) << LINEVAL_OFFSET); + writel(val, &disp_ctrl->vidtcon2); + + writel((unsigned int)lcd_base, &fimd->vidw00add0b0); + + fbsize = calc_fbsize(panel_info); + writel((unsigned int)lcd_base + fbsize, &fimd->vidw00add1b0); + + writel(pd->xres * 2, &fimd->vidw00add2); + + val = ((pd->xres - 1) << OSD_RIGHTBOTX_F_OFFSET); + val |= ((pd->yres - 1) << OSD_RIGHTBOTY_F_OFFSET); + writel(val, &fimd->vidosd0b); + writel(pd->xres * pd->yres, &fimd->vidosd0c); + + setbits_le32(&fimd->shadowcon, CHANNEL0_EN); + + val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; + val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; + writel(val, &fimd->wincon0); + + /* DPCLKCON_ENABLE */ + writel(1 << 1, &fimd->dpclkcon); +} + +#if 0 +static void exynos_fimd_disable(void) +{ + struct exynos5_fimd *fimd = + (struct exynos5_fimd *)samsung_get_base_fimd(); + + writel(0, &fimd->wincon0); + clrbits_le32(&fimd->shadowcon, CHANNEL0_EN); +} +#endif +/* + * Configure DP in slave mode and wait for video stream. + * + * param dp pointer to main s5p-dp structure + * param video_info pointer to main video_info structure. + * return status + */ +static int s5p_dp_config_video(struct s5p_dp_device *dp, + struct video_info *video_info) +{ + int timeout = 0; + u32 start; + struct exynos5_dp *base = dp->base; + + s5p_dp_config_video_slave_mode(dp, video_info); + + s5p_dp_set_video_color_format(dp, video_info->color_depth, + video_info->color_space, + video_info->dynamic_range, + video_info->ycbcr_coeff); + + if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + debug("PLL is not locked yet.\n"); + return -ERR_PLL_NOT_UNLOCKED; + } + + start = get_timer(0); + do { + if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { + timeout++; + break; + } + } while (get_timer(start) <= STREAM_ON_TIMEOUT); + + if (!timeout) { + debug("Video Clock Not ok\n"); + return -ERR_VIDEO_CLOCK_BAD; + } + + /* Set to use the register calculated M/N video */ + s5p_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); + + clrbits_le32(&base->video_ctl_10, FORMAT_SEL); + + /* Disable video mute */ + clrbits_le32(&base->video_ctl_1, HDCP_VIDEO_MUTE); + + /* Configure video slave mode */ + s5p_dp_enable_video_master(dp); + + /* Enable video */ + setbits_le32(&base->video_ctl_1, VIDEO_EN); + timeout = s5p_dp_is_video_stream_on(dp); + + if (timeout) { + debug("Video Stream Not on\n"); + return -ERR_VIDEO_STREAM_BAD; + } + + return 0; +} + +/* + * Set DP to enhanced mode. We use this for EVT1 + * param dp pointer to main s5p-dp structure + * return status + */ +static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp) +{ + u8 data; + + if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data)) { + debug("DPCD read error\n"); + return -ERR_DPCD_READ_ERROR1; + } + + if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, + DPCD_ENHANCED_FRAME_EN | + (data & DPCD_LANE_COUNT_SET_MASK))) { + debug("DPCD write error\n"); + return -ERR_DPCD_WRITE_ERROR1; + } + + return 0; +} + +/* + * Enable scrambles mode. We use this for EVT1 + * param dp pointer to main s5p-dp structure + * return status + */ +static int s5p_dp_enable_scramble(struct s5p_dp_device *dp) +{ + u8 data; + struct exynos5_dp *base = dp->base; + + clrbits_le32(&base->dp_training_ptn_set, SCRAMBLING_DISABLE); + + if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, + &data)) { + debug("DPCD read error\n"); + return -ERR_DPCD_READ_ERROR2; + } + + if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, + (u8)(data & ~DPCD_SCRAMBLING_DISABLED))) { + debug("DPCD write error\n"); + return -ERR_DPCD_WRITE_ERROR2; + } + + return 0; +} + +/* + * Reset DP and prepare DP for init training + * param dp pointer to main s5p-dp structure + */ +static int s5p_dp_init_dp(struct s5p_dp_device *dp) +{ + int ret, i; + struct exynos5_dp *base = dp->base; + + for (i = 0; i < DP_INIT_TRIES; i++) { + s5p_dp_reset(dp); + + /* SW defined function Normal operation */ + clrbits_le32(&base->func_en_1, SW_FUNC_EN_N); + + ret = s5p_dp_init_analog_func(dp); + if (!ret) + break; + + udelay(5000); + debug("LCD retry init, attempt=%d ret=%d\n", i, ret); + } + if (i == DP_INIT_TRIES) { + debug("LCD initialization failed, ret=%d\n", ret); + return ret; + } + + s5p_dp_init_aux(dp); + + return ret; +} + +/* + * Set pre-emphasis level + * param dp pointer to main s5p-dp structure + * param pre_emphasis pre-emphasis level + * param lane lane number(0 - 3) + * return status + */ +static int s5p_dp_set_lane_lane_pre_emphasis(struct s5p_dp_device *dp, + int pre_emphasis, int lane) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = pre_emphasis << PRE_EMPHASIS_SET_SHIFT; + switch (lane) { + case 0: + writel(reg, &base->ln0_link_trn_ctl); + break; + case 1: + writel(reg, &base->ln1_link_trn_ctl); + break; + + case 2: + writel(reg, &base->ln2_link_trn_ctl); + break; + + case 3: + writel(reg, &base->ln3_link_trn_ctl); + break; + default: + debug("%s: Invalid lane %d\n", __func__, lane); + return -ERR_INVALID_LANE; + } + return 0; +} + +/* + * Read supported bandwidth type + * param dp pointer to main s5p-dp structure + * param bandwidth pointer to variable holding bandwidth type + */ +static void s5p_dp_get_max_rx_bandwidth(struct s5p_dp_device *dp, + u8 *bandwidth) +{ + u8 data; + + /* + * For DP rev.1.1, Maximum link rate of Main Link lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps + */ + s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data); + *bandwidth = data; +} + +/* + * Reset DP and prepare DP for init training + * param dp pointer to main s5p-dp structure + * param lane_count pointer to variable holding no of lanes + */ +static void s5p_dp_get_max_rx_lane_count(struct s5p_dp_device *dp, + u8 *lane_count) +{ + u8 data; + + /* + * For DP rev.1.1, Maximum number of Main Link lanes + * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes + */ + s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data); + *lane_count = data & DPCD_MAX_LANE_COUNT_MASK; +} + +/* + * DP H/w Link Training. Set DPCD link rate and bandwidth. + * param dp pointer to main s5p-dp structure + * param max_lane No of lanes + * param max_rate bandwidth + * return status + */ +static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, + unsigned int max_lane, + unsigned int max_rate) +{ + u32 data; + u32 start; + int lane; + struct exynos5_dp *base = dp->base; + + /* Stop Video */ + clrbits_le32(&base->video_ctl_1, VIDEO_EN); + + start = get_timer(0); + while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + if (get_timer(start) > PLL_LOCK_TIMEOUT) { + /* Ignore this error, and try to continue */ + printk(BIOS_ERR, "PLL is not locked yet.\n"); + break; + } + } + + /* Reset Macro */ + setbits_le32(&base->dp_phy_test, MACRO_RST); + + /* 10 us is the minimum reset time. */ + udelay(10); + + clrbits_le32(&base->dp_phy_test, MACRO_RST); + + /* Set TX pre-emphasis to minimum */ + for (lane = 0; lane < max_lane; lane++) + if (s5p_dp_set_lane_lane_pre_emphasis(dp, + PRE_EMPHASIS_LEVEL_0, lane)) { + debug("Unable to set pre emphasis level\n"); + return -ERR_PRE_EMPHASIS_LEVELS; + } + + /* All DP analog module power up */ + writel(0x00, &base->dp_phy_pd); + + /* Initialize by reading RX's DPCD */ + s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); + s5p_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); + + if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && + (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { + debug("Rx Max Link Rate is abnormal :%x !\n", + dp->link_train.link_rate); + /* Not Retrying */ + return -ERR_LINK_RATE_ABNORMAL; + } + + if (dp->link_train.lane_count == 0) { + debug("Rx Max Lane count is abnormal :%x !\n", + dp->link_train.lane_count); + /* Not retrying */ + return -ERR_MAX_LANE_COUNT_ABNORMAL; + } + + /* Setup TX lane count & rate */ + if (dp->link_train.lane_count > max_lane) + dp->link_train.lane_count = max_lane; + if (dp->link_train.link_rate > max_rate) + dp->link_train.link_rate = max_rate; + + /* Set link rate and count as you want to establish*/ + writel(dp->link_train.lane_count, &base->lane_count_set); + writel(dp->link_train.link_rate, &base->link_bw_set); + + /* Set sink to D0 (Sink Not Ready) mode. */ + s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, + DPCD_SET_POWER_STATE_D0); + + /* Start HW link training */ + writel(HW_TRAINING_EN, &base->dp_hw_link_training); + + /* Wait unitl HW link training done */ + s5p_dp_wait_hw_link_training_done(dp); + + /* Get hardware link training status */ + data = readl(&base->dp_hw_link_training); + if (data != 0) { + debug(" H/W link training failure: 0x%x\n", data); + return -ERR_LINK_TRAINING_FAILURE; + } + + /* Get Link Bandwidth */ + data = readl(&base->link_bw_set); + + dp->link_train.link_rate = data; + + data = readl(&base->lane_count_set); + dp->link_train.lane_count = data; + + return 0; +} + +/* + * Initialize DP display + */ +int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) +{ + int ret; + struct s5p_dp_device *dp = dp_device; + struct exynos5_dp *base; + + //dp->base = (struct exynos5_dp *)addr; + /* yes. we're a snow. Yet somehow our config is from a development kit? + * This Must Change */ + //dp->video_info = &smdk5250_dp_config; + + clock_init_dp_clock(); + + power_enable_dp_phy(); + ret = s5p_dp_init_dp(dp); + if (ret) { + debug("%s: Could not initialize dp\n", __func__); + return ret; + } + + ret = s5p_dp_hw_link_training(dp, dp->video_info->lane_count, + dp->video_info->link_rate); + if (ret) { + debug("unable to do link train\n"); + return ret; + } + /* Minimum delay after H/w Link training */ + udelay(1000); + + ret = s5p_dp_enable_scramble(dp); + if (ret) { + debug("unable to set scramble mode\n"); + return ret; + } + + ret = s5p_dp_enable_rx_to_enhanced_mode(dp); + if (ret) { + debug("unable to set enhanced mode\n"); + return ret; + } + + + base = dp->base; + /* Enable enhanced mode */ + setbits_le32(&base->sys_ctl_4, ENHANCED); + + writel(dp->link_train.lane_count, &base->lane_count_set); + writel(dp->link_train.link_rate, &base->link_bw_set); + + s5p_dp_init_video(dp); + ret = s5p_dp_config_video(dp, dp->video_info); + if (ret) { + debug("unable to config video\n"); + return ret; + } + + /* + * This delay is T3 in the LCD timing spec (defined as >200ms). We set + * this down to 60ms since that's the approximate maximum amount of time + * it'll take a bridge to start outputting LVDS data. The delay of + * >200ms is just a conservative value to avoid turning on the backlight + * when there's random LCD data on the screen. Shaving 140ms off the + * boot is an acceptable trade-off. + */ + *wait_ms = 60; + return 0; +} + +/** + * Init the LCD controller + * + * @param lcdbase Base address of LCD frame buffer + * @return 0 if ok, -ve error code on error + */ +int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase) +{ + int ret = 0; + + //vi->res = panel_info->vl_col; + //vi->yres = panel_info->vl_row; + + fimd_bypass(); + fb_init(panel_info, lcdbase, panel_data); + + /* Enable flushing after LCD writes if requested */ + // forget it. lcd_set_flush_dcache(1); + return ret; +} diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h new file mode 100644 index 0000000..67c1990 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h @@ -0,0 +1,256 @@ +/* + * Header file for Samsung DP (Display Port) interface driver. + * + * Copyright 2013 Google Inc. + * Copyright (C) 2012 Samsung Electronics Co., Ltd. + * Author: Jingoo Han <jg1.han(a)samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef _S5P_DP_CORE_H +#define _S5P_DP_CORE_H + +#define STREAM_ON_TIMEOUT 100 +#define PLL_LOCK_TIMEOUT 10 +#define DP_INIT_TRIES 10 +#define MAX_CR_LOOP 5 +#define MAX_EQ_LOOP 4 + +/* Link tare type */ +enum link_rate { + LINK_RATE_1_62GBPS = 0x06, + LINK_RATE_2_70GBPS = 0x0a +}; + +/* Number of lanes supported */ +enum link_lane_count { + LANE_COUNT1 = 1, + LANE_COUNT2 = 2, + LANE_COUNT4 = 4 +}; + +/* Pre emphasis level */ +enum pre_emphasis_level { + PRE_EMPHASIS_LEVEL_0, + PRE_EMPHASIS_LEVEL_1, + PRE_EMPHASIS_LEVEL_2, + PRE_EMPHASIS_LEVEL_3, +}; + +/* Type of color space */ +enum color_space { + COLOR_RGB, + COLOR_YCBCR422, + COLOR_YCBCR444 +}; + +/* Video input Bit Per Color */ +enum color_depth { + COLOR_6, + COLOR_8, + COLOR_10, + COLOR_12 +}; + +/* Type of YCbCr coefficient */ +enum color_coefficient { + COLOR_YCBCR601, + COLOR_YCBCR709 +}; + +/* Color range */ +enum dynamic_range { + VESA, + CEA +}; + +/* Status of PLL clock */ +enum pll_status { + PLL_UNLOCKED, + PLL_LOCKED +}; + +/* To choose type of m_value */ +enum clock_recovery_m_value_type { + CALCULATED_M, + REGISTER_M +}; + +struct video_info { + enum color_space color_space; + enum dynamic_range dynamic_range; + enum color_coefficient ycbcr_coeff; + enum color_depth color_depth; + + enum link_rate link_rate; + enum link_lane_count lane_count; + + char *name; + + unsigned int h_sync_polarity:1; + unsigned int v_sync_polarity:1; + unsigned int interlaced:1; +}; + +struct link_train { + u8 link_rate; + u8 lane_count; +}; + +struct s5p_dp_device { + unsigned int irq; + struct exynos5_dp *base; + struct video_info *video_info; + struct link_train link_train; +}; + +/* this struct is used by mainboards to pass mode info to the driver */ +typedef struct vidinfo { + u16 vl_col; + u16 vl_row; + u8 vl_bpix; + u16 *cmap; +} vidinfo_t; + +/* s5p_dp_reg.c */ + +/* + * Reset DP module + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_reset(struct s5p_dp_device *dp); +/* + * Initialize DP to recieve video stream + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_init_video(struct s5p_dp_device *dp); +/* + * Check whether PLL is locked + * + * param dp pointer to main s5p-dp structure + * return Lock status + */ +unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp); +/* + * Initialize analog functions of DP + * + * param dp pointer to main s5p-dp structure + * return 0 on success + */ +int s5p_dp_init_analog_func(struct s5p_dp_device *dp); +/* + * Initialize DP for AUX transaction + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_init_aux(struct s5p_dp_device *dp); + +/* + * Start an AUX transaction. + * + * param dp pointer to main s5p-dp structure + */ +int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp); + +/* + * Write a byte to DPCD register + * + * param dp pointer to main s5p-dp structure + * param reg_addr DPCD register to be written + * param data byte data to be written + * return write status + */ +int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char data); +/* + * Read a byte from DPCD register + * + * param dp pointer to main s5p-dp structure + * param reg_addr DPCD register to read + * param data read byte data + * return read status + */ +int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char *data); +/* + * Initialize DP video functions + * + * param dp pointer to main s5p-dp structure + */ +//void s5p_dp_init_video(struct s5p_dp_device *dp); + +/* + * Set color parameters for display + * + * param dp pointer to main s5p-dp structure + * param color_depth Video input Bit Per Color + * param color_space Colorimetric format of input video + * param dynamic_range VESA range or CEA range + * param coeff YCbCr Coefficients of input video + */ +void s5p_dp_set_video_color_format(struct s5p_dp_device *dp, + unsigned int color_depth, + unsigned int color_space, + unsigned int dynamic_range, + unsigned int coeff); +/* + * Check whether video clock is on + * + * param dp pointer to main s5p-dp structure + * return clock status + */ +int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp); +/* + * Check whether video clock is on + * + * param dp pointer to main s5p-dp structure + * param type clock_recovery_m_value_type + * param m_value to caluculate m_vid value + * param n_value to caluculate n_vid value + */ +void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, + enum clock_recovery_m_value_type type, + unsigned int m_value, + unsigned int n_value); +/* + * Set DP to video slave mode thereby enabling video master + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_enable_video_master(struct s5p_dp_device *dp); +/* + * Check whether video stream is on + * + * param dp pointer to main s5p-dp structure + * return video stream status + */ +int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp); +/* + * Configure DP in slave mode + * + * param dp pointer to main s5p-dp structure + * param video_info pointer to main video_info structure. + */ +void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, + struct video_info *video_info); + +/* + * Wait unitl HW link training done + * + * param dp pointer to main s5p-dp structure + */ +void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); + +/* startup and init */ +void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd); +int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms); +int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase); +#endif /* _S5P_DP_CORE_H */ diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c new file mode 100644 index 0000000..adb64a8 --- /dev/null +++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c @@ -0,0 +1,481 @@ +/* + * Samsung DP (Display port) register interface driver. + * + * Copyright (C) 2012 Samsung Electronics Co., Ltd. + * Author: Jingoo Han <jg1.han(a)samsung.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <common.h> +#include <arch/io.h> +#include <cpu/samsung/exynos5-common/clk.h> +#include <cpu/samsung/exynos5250/cpu.h> +#include <cpu/samsung/exynos5250/periph.h> +#include <cpu/samsung/exynos5250/s5p-dp.h> +#include "cpu/samsung/exynos5250/fimd.h" +#include "s5p-dp-core.h" + +void s5p_dp_reset(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + writel(RESET_DP_TX, &base->dp_tx_sw_reset); + + /* Stop Video */ + clrbits_le32(&base->video_ctl_1, VIDEO_EN); + clrbits_le32(&base->video_ctl_1, HDCP_VIDEO_MUTE); + + reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | + AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | + HDCP_FUNC_EN_N | SW_FUNC_EN_N; + writel(reg, &base->func_en_1); + + reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | + SERDES_FIFO_FUNC_EN_N | + LS_CLK_DOMAIN_FUNC_EN_N; + writel(reg, &base->func_en_2); + + udelay(20); + + reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | + LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; + + writel(reg, &base->lane_map); + + writel(0x0, &base->sys_ctl_1); + writel(0x40, &base->sys_ctl_2); + writel(0x0, &base->sys_ctl_3); + writel(0x0, &base->sys_ctl_4); + + writel(0x0, &base->pkt_send_ctl); + writel(0x0, &base->dp_hdcp_ctl); + + writel(0x5e, &base->dp_hpd_deglitch_l); + writel(0x1a, &base->dp_hpd_deglitch_h); + + writel(0x10, &base->dp_debug_ctl); + + writel(0x0, &base->dp_phy_test); + + writel(0x0, &base->dp_video_fifo_thrd); + writel(0x20, &base->dp_audio_margin); + + writel(0x4, &base->m_vid_gen_filter_th); + writel(0x2, &base->m_aud_gen_filter_th); + + writel(0x00000101, &base->soc_general_ctl); + + /* Set Analog Parameters */ + writel(0x10, &base->analog_ctl_1); + writel(0x0C, &base->analog_ctl_2); + writel(0x85, &base->analog_ctl_3); + writel(0x66, &base->pll_filter_ctl_1); + writel(0x0, &base->tx_amp_tuning_ctl); + + /* Set interrupt pin assertion polarity as high */ + writel(INT_POL0 | INT_POL1, &base->int_ctl); + + /* Clear pending regisers */ + writel(0xff, &base->common_int_sta_1); + writel(0x4f, &base->common_int_sta_2); + writel(0xe0, &base->common_int_sta_3); + writel(0xe7, &base->common_int_sta_4); + writel(0x63, &base->dp_int_sta); + + /* 0:mask,1: unmask */ + writel(0x00, &base->common_int_mask_1); + writel(0x00, &base->common_int_mask_2); + writel(0x00, &base->common_int_mask_3); + writel(0x00, &base->common_int_mask_4); + writel(0x00, &base->int_sta_mask); +} + +unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp) +{ + u32 reg; + + reg = readl(&dp->base->dp_debug_ctl); + if (reg & PLL_LOCK) + return PLL_LOCKED; + else + return PLL_UNLOCKED; +} + +int s5p_dp_init_analog_func(struct s5p_dp_device *dp) +{ + u32 reg; + u32 start; + struct exynos5_dp *base = dp->base; + + writel(0x00, &base->dp_phy_pd); + + reg = PLL_LOCK_CHG; + writel(reg, &base->common_int_sta_1); + + clrbits_le32(&base->dp_debug_ctl, (F_PLL_LOCK | PLL_LOCK_CTRL)); + + /* Power up PLL */ + if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + + clrbits_le32(&base->dp_pll_ctl, DP_PLL_PD); + + start = get_timer(0); + while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + if (get_timer(start) > PLL_LOCK_TIMEOUT) { + debug("%s: PLL is not locked yet\n", __func__); + return -1; + } + } + } + + /* Enable Serdes FIFO function and Link symbol clock domain module */ + clrbits_le32(&base->func_en_2, (SERDES_FIFO_FUNC_EN_N | + LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N)); + return 0; +} + +void s5p_dp_init_aux(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + /* Clear inerrupts related to AUX channel */ + reg = RPLY_RECEIV | AUX_ERR; + writel(reg, &base->dp_int_sta); + + /* Disable AUX channel module */ + setbits_le32(&base->func_en_2, AUX_FUNC_EN_N); + + /* Disable AUX transaction H/W retry */ + reg = (3 & AUX_BIT_PERIOD_MASK) << AUX_BIT_PERIOD_SHIFT; + reg |= (0 & AUX_HW_RETRY_COUNT_MASK) << AUX_HW_RETRY_COUNT_SHIFT; + reg |= (AUX_HW_RETRY_INTERVAL_600_US << AUX_HW_RETRY_INTERVAL_SHIFT); + writel(reg, &base->aux_hw_retry_ctl) ; + + /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ + reg = DEFER_CTRL_EN; + reg |= (1 & DEFER_COUNT_MASK) << DEFER_COUNT_SHIFT; + writel(reg, &base->aux_ch_defer_dtl); + + /* Enable AUX channel module */ + clrbits_le32(&base->func_en_2, AUX_FUNC_EN_N); +} + +int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) +{ + int reg; + struct exynos5_dp *base = dp->base; + + /* Enable AUX CH operation */ + setbits_le32(&base->aux_ch_ctl_2, AUX_EN); + + /* Is AUX CH command reply received? */ + reg = readl(&base->dp_int_sta); + while (!(reg & RPLY_RECEIV)) + reg = readl(&base->dp_int_sta); + + /* Clear interrupt source for AUX CH command reply */ + writel(RPLY_RECEIV, &base->dp_int_sta); + + /* Clear interrupt source for AUX CH access error */ + reg = readl(&base->dp_int_sta); + if (reg & AUX_ERR) { + writel(AUX_ERR, &base->dp_int_sta); + return -1; + } + + /* Check AUX CH error access status */ + reg = readl(&base->dp_int_sta); + if ((reg & AUX_STATUS_MASK) != 0) { + debug("AUX CH error happens: %d\n\n", + reg & AUX_STATUS_MASK); + return -1; + } + + return 0; +} + +int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char data) +{ + u32 reg; + int i; + int retval; + struct exynos5_dp *base = dp->base; + + for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) { + /* Clear AUX CH data buffer */ + writel(BUF_CLR, &base->buf_data_ctl); + + /* Select DPCD device address */ + reg = reg_addr >> AUX_ADDR_7_0_SHIFT; + reg &= AUX_ADDR_7_0_MASK; + writel(reg, &base->aux_addr_7_0); + reg = reg_addr >> AUX_ADDR_15_8_SHIFT; + reg &= AUX_ADDR_15_8_MASK; + writel(reg, &base->aux_addr_15_8); + reg = reg_addr >> AUX_ADDR_19_16_SHIFT; + reg &= AUX_ADDR_19_16_MASK; + writel(reg, &base->aux_addr_19_16); + + /* Write data buffer */ + reg = (unsigned int)data; + writel(reg, &base->buf_data_0); + + /* + * Set DisplayPort transaction and write 1 byte + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; + writel(reg, &base->aux_ch_ctl_1); + + /* Start AUX transaction */ + retval = s5p_dp_start_aux_transaction(dp); + if (retval == 0) + break; + else + debug("Aux Transaction fail!\n"); + } + + return retval; +} + +int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp, + unsigned int reg_addr, + unsigned char *data) +{ + u32 reg; + int i; + int retval; + struct exynos5_dp *base = dp->base; + + for (i = 0; i < MAX_AUX_RETRY_COUNT; i++) { + /* Clear AUX CH data buffer */ + writel(BUF_CLR, &base->buf_data_ctl); + + /* Select DPCD device address */ + reg = reg_addr >> AUX_ADDR_7_0_SHIFT; + reg &= AUX_ADDR_7_0_MASK; + writel(reg, &base->aux_addr_7_0); + reg = reg_addr >> AUX_ADDR_15_8_SHIFT; + reg &= AUX_ADDR_15_8_MASK; + writel(reg, &base->aux_addr_15_8); + reg = reg_addr >> AUX_ADDR_19_16_SHIFT; + reg &= AUX_ADDR_19_16_MASK; + writel(reg, &base->aux_addr_19_16); + + /* + * Set DisplayPort transaction and read 1 byte + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; + writel(reg, &base->aux_ch_ctl_1); + + /* Start AUX transaction */ + retval = s5p_dp_start_aux_transaction(dp); + if (retval == 0) + break; + else + debug("Aux Transaction fail!\n"); + } + + /* Read data buffer */ + if (!retval) { + reg = readl(&base->buf_data_0); + *data = (unsigned char)(reg & 0xff); + } + + return retval; +} + +void s5p_dp_init_video(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; + writel(reg, &base->common_int_sta_1); + + reg = 0x0; + writel(reg, &base->sys_ctl_1); + + reg = (4 & CHA_CRI_MASK) << CHA_CRI_SHIFT; + reg |= CHA_CTRL; + writel(reg, &base->sys_ctl_2); + + reg = 0x0; + writel(reg, &base->sys_ctl_3); +} + +void s5p_dp_set_video_color_format(struct s5p_dp_device *dp, + unsigned int color_depth, + unsigned int color_space, + unsigned int dynamic_range, + unsigned int coeff) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + /* Configure the input color depth, color space, dynamic range */ + reg = (dynamic_range << IN_D_RANGE_SHIFT) | + (color_depth << IN_BPC_SHIFT) | + (color_space << IN_COLOR_F_SHIFT); + writel(reg, &base->video_ctl_2); + + /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ + reg = readl(&base->video_ctl_3); + reg &= ~IN_YC_COEFFI_MASK; + if (coeff) + reg |= IN_YC_COEFFI_ITU709; + else + reg |= IN_YC_COEFFI_ITU601; + writel(reg, &base->video_ctl_3); +} + +int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->sys_ctl_1); + writel(reg, &base->sys_ctl_1); + + reg = readl(&base->sys_ctl_1); + + if (!(reg & DET_STA)) + return -1; + + reg = readl(&base->sys_ctl_2); + writel(reg, &base->sys_ctl_2); + + reg = readl(&base->sys_ctl_2); + + if (reg & CHA_STA) { + debug("Input stream clk is changing\n"); + return -1; + } + + return 0; +} + +void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, + enum clock_recovery_m_value_type type, + unsigned int m_value, + unsigned int n_value) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + if (type == REGISTER_M) { + setbits_le32(&base->sys_ctl_4, FIX_M_VID); + + reg = m_value >> M_VID_0_VALUE_SHIFT; + writel(reg, &base->m_vid_0); + + reg = (m_value >> M_VID_1_VALUE_SHIFT); + writel(reg, &base->m_vid_1); + + reg = (m_value >> M_VID_2_VALUE_SHIFT); + writel(reg, &base->m_vid_2); + + reg = n_value >> N_VID_0_VALUE_SHIFT; + writel(reg, &base->n_vid_0); + + reg = (n_value >> N_VID_1_VALUE_SHIFT); + writel(reg, &base->n_vid_1); + + reg = (n_value >> N_VID_2_VALUE_SHIFT); + writel(reg, &base->n_vid_2); + } else { + clrbits_le32(&base->sys_ctl_4, FIX_M_VID); + + writel(0x00, &base->n_vid_0); + writel(0x80, &base->n_vid_1); + writel(0x00, &base->n_vid_2); + } +} + +void s5p_dp_enable_video_master(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->soc_general_ctl); + reg &= ~VIDEO_MODE_MASK; + reg |= VIDEO_MODE_SLAVE_MODE; + writel(reg, &base->soc_general_ctl); +} + +int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp) +{ + u32 reg, i = 0; + u32 start; + struct exynos5_dp *base = dp->base; + + /* Wait for 4 VSYNC_DET interrupts */ + start = get_timer(0); + do { + reg = readl(&base->common_int_sta_1); + if (reg & VSYNC_DET) { + i++; + writel(reg | VSYNC_DET, &base->common_int_sta_1); + } + if (i == 4) + break; + } while (get_timer(start) <= STREAM_ON_TIMEOUT); + + if (i != 4) { + debug("s5p_dp_is_video_stream_on timeout\n"); + return -1; + } + + return 0; +} + +void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, + struct video_info *video_info) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->func_en_1); + reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); + reg |= MASTER_VID_FUNC_EN_N; + writel(reg, &base->func_en_1); + + reg = readl(&base->video_ctl_10); + reg &= ~INTERACE_SCAN_CFG; + reg |= (video_info->interlaced << 2); + writel(reg, &base->video_ctl_10); + + reg = readl(&base->video_ctl_10); + reg &= ~VSYNC_POLARITY_CFG; + reg |= (video_info->v_sync_polarity << 1); + writel(reg, &base->video_ctl_10); + + reg = readl(&base->video_ctl_10); + reg &= ~HSYNC_POLARITY_CFG; + reg |= (video_info->h_sync_polarity << 0); + writel(reg, &base->video_ctl_10); + + reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; + writel(reg, &base->soc_general_ctl); +} + +void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp) +{ + u32 reg; + struct exynos5_dp *base = dp->base; + + reg = readl(&base->dp_hw_link_training); + while (reg & HW_TRAINING_EN) + reg = readl(&base->dp_hw_link_training); +} diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index 6face94..85b90a5 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. +## Copyright 2013 Google Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DRIVER_MAXIM_MAX77686 # select HAVE_ACPI_TABLES # select MMCONF_SUPPORT + select EXYNOS_DISPLAYPORT select CHROMEOS config MAINBOARD_DIR diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index 4c88ea8..cc24cf7 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -28,5 +28,19 @@ device domain 0 on device i2c 6 on end # ? device i2c 9 on end # ? end + chip cpu/samsung/exynos5-common/displayport/ + register "xres" = "1366" + register "yres" = "768" + register "bpp" = "16" + # complex magic timing! + register "clkval_f" = "2" + register "upper_margin" = "14" + register "lower_margin" = "3" + register "vsync" = "5" + register "left_margin" = "80" + register "right_margin" = "48" + register "hsync" = "32" + register "lcdbase" = "0x10000000" + end end end diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 5970357..72434fc 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -19,6 +19,8 @@ #include <console/console.h> #include <cbmem.h> +#include <cpu/samsung/exynos5250/fimd.h> +#include <cpu/samsung/exynos5-common/s5p-dp-core.h> void hardwaremain(int boot_complete); void main(void) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7e1cd57..639c2ef 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -31,7 +31,6 @@ #include <cpu/samsung/exynos5250/setup.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/clock_init.h> - #include <console/console.h> #include <arch/stages.h> @@ -70,6 +69,11 @@ static void initialize_s5p_mshc(void) { exynos_pinmux_config(PERIPH_ID_SDMMC2, 0); } +static void graphics(void) +{ + + exynos_pinmux_config(PERIPH_ID_DPHPD, 0); +} void main(void) { struct mem_timings *mem; @@ -108,6 +112,8 @@ void main(void) initialize_s5p_mshc(); + graphics(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);

1 0

Patch set updated for coreboot: d89337c AMD Hudson-E1: document Broadcom BCM57xx secret sauce Selfboot Patch format
by Jens Rottmann 04 Mar '13

04 Mar '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2581 -gerrit commit d89337c8fce0d214dd487fd63693be844acf1734 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Fri Mar 1 19:41:41 2013 +0100 AMD Hudson-E1: document Broadcom BCM57xx secret sauce Selfboot Patch format The Broadcom BCM5785 integrated in the AMD Hudson-E1 requires a proprietary firmware blob to work. As Broadcom wasn't willing to send us any documentation (or a firmware adapted to our Micrel PHY) I had to figure out everything by myself in weeks of hard detective work. In the end we had to settle for a different solution, this file is now only needed for Ethernet support on our early FrontRunner-AF prototypes. However the information contained here may be very useful for others, for example it can easily be used in place of the usual firmware blob to get Ethernet on AMD Inagua. The fun thing is: as Broadcom refused to do any business with us at all, or send us any documentation, we never had to sign an NDA with them. This leaves me free to publish everything I have found out. :-) Change-Id: Ifa628751d14143f277b27cfd34b1d2771ca1302f Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/mainboard/lippert/frontrunner-af/broadcom.c | 321 ++++++++++++++++++++++++ 1 file changed, 321 insertions(+) diff --git a/src/mainboard/lippert/frontrunner-af/broadcom.c b/src/mainboard/lippert/frontrunner-af/broadcom.c new file mode 100644 index 0000000..48f1a42 --- /dev/null +++ b/src/mainboard/lippert/frontrunner-af/broadcom.c @@ -0,0 +1,321 @@ +/* + * Initialize Broadcom 5785 GbE MAC embedded in AMD A55E (Hudson-E1) Southbridge + * by uploading a Selfboot Patch to the A55E's shadow ROM area. + * The patch itself supports the Micrel KSZ9021 PHY that was used on LiPPERT + * FrontRunner-AF (CFR-AF) revision 0v0, the first prototype. The board is + * history and this code now serves only to document Broadcom's proprietary + * Selfboot Patch format. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2012 LiPPERT ADLINK Technology GmbH + * (Written by Jens Rottmann <JRottmann(a)LiPPERTembedded.de>) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <arch/byteorder.h> +#include <console/console.h> +#include <device/device.h> //Coreboot device access +#include <device/pci.h> +#include <delay.h> + +#define be16(x) cpu_to_be16(x) //a little easier to type +#define be(x) cpu_to_be32(x) //this is used a lot! + +/* C forces us to specify these before defining struct selfboot_patch :-( */ +#define INIT1_LENGTH 13 +#define INIT2_LENGTH 6 +#define INIT3_LENGTH 3 +#define INIT4_LENGTH 11 //this one may be 0 +#define PWRDN_LENGTH 4 + + +/* The AMD A55E (Hudson-E1) Southbridge contains an integrated Gigabit Ethernet + * MAC, however AMD's documentation merely defines the related balls (without + * fully describing their function) and states that only Broadcom 50610(M) PHYs + * will be supported, that's all. The Hudson register reference skips all MAC + * registers entirely, even AMD support doesn't seem to know more about it. + * + * As Broadcom refused to sell us any 50610 chips or provide any docs (or indeed + * even a price list) below $100K expected sales we had to figure out everything + * by ourselves. *Everything* below is the result of months of detective work, + * documented here lest it get lost: + * + * The AMD A55E's GbE MAC is a Broadcom 5785, which AMD obviously licensed as IP + * core. It uses a standard RGMII/MII interface and the Broadcom drivers will + * recognize it by its unchanged PCI ID 14E4:1699, however there are some + * specialties. + * + * The 5785 MAC can detect the link with 4 additional inputs, "phy_status[3:0]", + * 'snooping' on the PHY's LED outputs. Interpretation of the LEDs' patterns is + * programmed with register 0x5A4 of the MAC. AMD renamed them to "GBE_STAT" and + * won't say anything about their purpose. Appearently hardware designers are + * expected to blindly copy the Inagua reference schematic: GBE_STAT2: + * 0=activity; GBE_STAT[1:0]: 11=no link, 10=10Mbit, 01=100Mbit, 00=1Gbit. + * + * For package processing the 5785 also features a MIPS-based RISC CPU, booting + * from an internal ROM. The firmware loads config data and supplements (e.g. to + * support specific PHYs), named "Selfboot Patches", via the "NVRAM Interface", + * usually from an external EEPROM. The A55E doesn't have any balls for an ext. + * EEPROM, instead AMD added a small internal RAM. The BIOS is expected to copy + * the correct contents into this RAM (which only supports byte access!) upon + * each powerup. The A55E can trigger an SMI upon writes, enabling the BIOS to + * forward any changes to an actually 'NV' location, e.g. the BIOS's SPI flash, + * behind the scenes. AMD calls it "GEC shadow ROM", not describing what it's + * for nor mentioning the term "NVRAM". broadcom_init() below documents a + * procedure how to upload the patch. No SMI magic is installed, therefore + * 'NV'RAM writes won't be persistent. + * + * The "Selfboot Patch" can execute simple commands at various points during + * main firmware execution. This can be used to change config registers, + * initialize a specific PHY or work around firmware bugs. Broadcom provides + * suitable Patches only for their AC131 and 50610 PHYs (as binary blobs). I + * found them in DOS\sb_patch\5785\*\sb5785*.* in Driver_14_6_4_2.zip. (Note + * that every 32bit-word of these files must be byte-swapped before uploading + * them to the A55E.) + * + * Below is a derived Patch supporting the Micrel KSZ9021 PHY used on the + * LiPPERT CFR-AF PC/104 SBC instead, with detailled description of the format. + * (Here in correct order for upload.) + * + * This Patch made Ethernet work with Linux 3.3 - without having to modify the + * tg3.ko driver. Broadcom's Windows-Drivers still fail with "Code 10" however; + * disassembly showed they check the PHY ID and abort, because the Micrel PHY is + * not supported. + */ + +static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! + + struct { /* Global header */ + u8 signature; //0xA5 + u8 format; //bits 7-3: patch format; 2-0: revision + u8 mac_addr[6]; + u16 subsys_device; //IDs will be loaded into PCI config space + u16 subsys_vendor; + u16 pci_device; //PCI device ID; vendor is always Broadcom (0x14E4) + u8 unknown1[8]; //?, noticed no effect + u16 basic_config; //?, see below + u8 checksum; //byte sum of header == 0 + u8 unknown2; //?, patch rejected if changed + u16 patch_version; //10-8: major; 7-0: minor; 15-11: variant (1=a, 2=b, ...) + } header; + + struct { /* Init code */ + u8 checksum; //byte sum of init == 0 + u8 unknown; //?, looks unused + u8 num_hunks; //0x60 = 3 hunks, 0x80 = 4 hunks, other values not supported + u8 size; //total size of all hunk#_code[] in bytes + u8 hunk1_when; //mark when hunk1_code gets executed + u8 hunk1_size; //sizeof(hunk1_code) + u8 hunk2_when; + u8 hunk2_size; + u8 hunk3_when; + u8 hunk3_size; + u8 hunk4_when; //0x00 (padding) if only 3 hunks + u8 hunk4_size; //dito + u32 hunk1_code[INIT1_LENGTH]; //actual commands, see below + u32 hunk2_code[INIT2_LENGTH]; + u32 hunk3_code[INIT3_LENGTH]; + u32 hunk4_code[INIT4_LENGTH]; //missing (zero length) if only 3 hunks + } init; + + struct { /* Power down code */ + u8 checksum; //byte sum of powerdown == 0 + u8 unknown; //?, looks unused + u8 num_hunks; //0x20 = 1 hunk, other values not supported + u8 size; //total size of all hunk#_code[] in bytes + u8 hunk1_when; //mark when hunk1_code gets executed + u8 hunk1_size; //sizeof(hunk1_code) + u16 padding; //0x0000, hunk2 is not supported + u32 hunk1_code[PWRDN_LENGTH]; //commands, see below + } powerdown; + +} selfboot_patch = { + +/* Keep the following invariant for valid Selfboot patches */ + .header.signature = 0xA5, + .header.format = 0x23, //format 1 revision 3 + .header.unknown1 = { 0x61, 0xB1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + .header.checksum = 0, //calculated later + .header.unknown2 = 0x30, + .init.checksum = 0, //calculated later + .init.unknown = 0x00, + .init.num_hunks = sizeof(selfboot_patch.init.hunk4_code) ? 0x80 : 0x60, + .init.size = sizeof(selfboot_patch.init.hunk1_code) + + sizeof(selfboot_patch.init.hunk2_code) + + sizeof(selfboot_patch.init.hunk3_code) + + sizeof(selfboot_patch.init.hunk4_code), + .init.hunk1_size = sizeof(selfboot_patch.init.hunk1_code), + .init.hunk2_size = sizeof(selfboot_patch.init.hunk2_code), + .init.hunk3_size = sizeof(selfboot_patch.init.hunk3_code), + .init.hunk4_size = sizeof(selfboot_patch.init.hunk4_code), + .powerdown.checksum = 0, //calculated later + .powerdown.unknown = 0x00, + .powerdown.num_hunks = 0x20, + .powerdown.size = sizeof(selfboot_patch.powerdown.hunk1_code), + .powerdown.hunk1_size = sizeof(selfboot_patch.powerdown.hunk1_code), + .powerdown.padding = be16(0x0000), + +/* Only the lines below may be adapted to your needs ... */ + .header.mac_addr = { 0x00, 0x20, 0x9D, 0x00, 0x00, 0x00 }, //LiPPERT + .header.subsys_device = be16(0x1699), //simply kept this + .header.subsys_vendor = be16(0x121D), //LiPPERT + .header.pci_device = be16(0x1699), //Broadcom 5785 with GbE PHY + .header.patch_version = be16(0x110B), //1.11b, as this was based on Broadcom's sb5785m1.11 patch + /* Bitfield enabling general features/codepaths in the firmware or + * selecting support for one of several supported PHYs? + * Bits not listed had no appearent effect: + * 14-11: any bit 1=firmware execution seemed delayed + * 10: 0=firmware execution seemed delayed + * 9,2,0: select PHY type, affects these registers, probably more + * 9 2 0 | reg 0x05A4 PHY reg 31 PHY 23,24,28 Notes + * -------+---------------------------------------------------------- + * 0 0 0 | 0x331C71C1 - changed Inband Status enabled + * 0 1 0 | 0x3210C500 - changed - + * 0 X 1 | 0x33FF66C0 changed - 10/100 Mbit only + * 1 X 0 | 0x330C5180 - - - + * 1 X 1 | 0x391C6140 - - - + */ + .header.basic_config = be16(0x0604), //bit 9 set so not to mess up PHY regs, kept other bits unchanged + + /* Tag that defines when / on what occasion the commands are interpreted. + * Bits 2-0 = 0 i.e. possible values are 0x00, 08, 10, ..., F8. + * On a RISC CPU reset every tag except 0x38, A0, F0, F8 is used. 0x38 + * seems to be run before a reset is performed(?), the other 3 I have + * never seen used. Generally, lower values appear to be run earlier. + * An "ifconfig up" with Linux' "tg3" driver causes the tags 0x50, 60, + * 68, 20, 70, 80 to be interpreted in this order. + * All tests were performed with .basic_config=0x0604. + */ + .init.hunk1_when = 0x10, //only once at RISC CPU reset? + /* Instructions are obviously a specialized bytecode interpreted by the + * main firmware, rather than MIPS machine code. Commands consist of 1-3 + * 32-bit words. In the following, 0-9,A-F = hex literals, a-z,_ = variable + * parts, each character = 4 bits. + * 0610offs newvalue: write (32-bit) <newvalue> to 5785-internal shared mem at <offs> + * 08rgvalu: write <valu> to PHY register, <rg> = 0x20 + register number + * C610rgnr newvalue: write <newvalue> to MAC register <rgnr> + * C1F0rgnr andvalue or_value: modify MAC register <rgnr> by ANDing with <andvalue> and then ORing with <or_value> + * C4btrgnr: clear bit in 32-bit MAC register <rgnr>, <bt> = bit number << 3 + * C3btrgnr: set bit, see C4...; example: command 0xC3200454 sets bit 4 of 32-bit register 0x0454 + * CBbtrgnr: run next command only if bit (see C4...) == 1 (so far only seen before F7F0...) + * F7F0skip: unconditional jump i.e. skip next <skip> code bytes (only seen small positive <skip>) + * F7Fxaddr: call function at <addr> in main firmware? <x> = 3 or 4, bool parameter?? Wild guess! + * F7FFFadr somvalue: also call func. at <adr>, but with <somvalue> as parameter?? More guessing! + * More commands probably exist, but all code I've ever seen was kept + * included below, commented out if not suitable for the CFR-AF. v1.xx + * is Broadcom's Selfboot patch version sb5785m1.xx where the command + * was added, for reference see Broadcom's changelog. + */ + .init.hunk1_code = { + be(0x082B8104), //CFR-AF: PHY0B: KSZ9021 select PHY104 + be(0x082CF0F0), //CFR-AF: PHY0C: KSZ9021 clk/ctl skew (advised by Micrel) + be(0x082B8105), //CFR-AF: PHY0B: KSZ9021 select PHY105 + be(0x082C3333), //CFR-AF: PHY0C: KSZ9021 RX data skew (empirical) + be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), //v1.05 : 5A0.24,12=1: auto-clock-switch + be(0x06100D34), be(0x00000000), //v1.03 : MemD34: clear config vars + be(0x06100D38), be(0x00000000), //v1.03 : - | + be(0x06100D3C), be(0x00000000), //v1.03 : MemD3F| + }, //-->INIT1_LENGTH! + + .init.hunk2_when = 0x30, //after global reset, PHY reset + .init.hunk2_code = { + //be(0x08370F08), //v1.06 : PHY17: B50610 select reg. 08 + //be(0x08350001), //v1.06 : PHY15: B50610 slow link fix + //be(0x08370F00), //v1.06 : PHY17: B50610 disable reg. 08 + //be(0x083C2C00), //v1.11 : PHY1C: B50610 Shadow 0B + be(0xF7F301E6), //v1.09+: ?: subroutine calls to + be(0xF7FFF0B6), be(0x0000FFE7), //v1.09+: ?| restore Port Mode ??? + be(0xF7FFF0F6), be(0x00008000), //v1.09+: ?| + be(0xF7F401E6), //v1.09+: ?| + }, //-->INIT2_LENGTH! + + .init.hunk3_when = 0xA8, //?, I'd guess quite late + .init.hunk3_code = { + be(0xC1F03604), be(0xFFE0FFFF), be(0x00110000), //v1.08 : 3604.20-16: 10Mb clock = 12.5MHz + }, //-->INIT3_LENGTH! + + //.init.hunk4_when = 0xD8, //was used in B50610 GPHY Selfboot patch v1.11 this is based on + .init.hunk4_when = 0x80, //run last, after Linux' "ifconfig up" + .init.hunk4_code = { + be(0x083F4300), //CFR-AF: PHY1F: IRQ active high + be(0x083C0000), //CFR-AF: PHY1C: revert driver writes + be(0x08380000), //CFR-AF: PHY18| + be(0x083C0000), //CFR-AF: PHY1C| + be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0==1 -->skip next 12 bytes + //be(0xC61005A4), be(0x3210C500), //v1.01 : 5A4: PHY LED mode + be(0xC61005A4), be(0x331C71CE), //CFR-AF: 5A4: fake LED mode + be(0xF7F00008), //v1.01 : -->skip next 8 bytes + be(0xC61005A4), be(0x331C71C1), //v1.01 : 5A4: inband LED mode + //be(0xC3200454), //CFR-AF: 454.4: auto link polling + }, //-->INIT4_LENGTH! + + .powerdown.hunk1_when = 0x50, //prior to IDDQ MAC + .powerdown.hunk1_code = { + //be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY + be(0xF7F30116), // IDDQ PHY + be(0xC40005A0), //v1.09 : 5A0.0=0: Port Mode = MII + be(0xC4180400), //v1.09 : 400.3=0| + be(0xC3100400), //v1.09 : 400.2=1| + }, //-->PWRDN_LENGTH! + +}; + +/* Upload 'NV'RAM contents for BCM5785 GbE MAC integrated in A55E. + * Call this from mainboard.c. + */ +void broadcom_init(void) +{ + volatile u32 *gec_base; //Gigabit Ethernet Controller base addr + u8 *gec_shadow; //base addr of shadow 'NV'RAM for GbE MAC in A55E + u8 sum; + int i; + + gec_base = (u32*)(long)dev_find_slot(0, PCI_DEVFN(0x14, 6))->resource_list->base; + gec_shadow = (u8*)(pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x14, 3)), 0x9C) & 0xFFFFFC00); + printk(BIOS_DEBUG, "Upload GbE 'NV'RAM contents @ 0x%08lx\n", (unsigned long)gec_shadow); + + /* Halt RISC CPU before uploading the firmware patch */ + for (i=10000; i > 0; i--) { + gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state + gec_base[0x5000/4] |= (1<<10); //issue RISC halt + if (gec_base[0x5000/4] | (1<<10)) + break; + udelay(10); + } + if (!i) + printk(BIOS_ERR, "Failed to halt RISC CPU!\n"); + + /* Calculate checksums (standard byte sum) */ + for (sum = 0, i = 0; i < sizeof(selfboot_patch.header); i++) + sum -= ((u8*)&selfboot_patch.header)[i]; + selfboot_patch.header.checksum = sum; + for (sum = 0, i = 0; i < sizeof(selfboot_patch.init); i++) + sum -= ((u8*)&selfboot_patch.init)[i]; + selfboot_patch.init.checksum = sum; + for (sum = 0, i = 0; i < sizeof(selfboot_patch.powerdown); i++) + sum -= ((u8*)&selfboot_patch.powerdown)[i]; + selfboot_patch.powerdown.checksum = sum; + + /* Upload firmware patch to shadow 'NV'RAM */ + for (i = 0; i < sizeof(selfboot_patch); i++) + gec_shadow[i] = ((u8*)&selfboot_patch)[i]; //access byte-wise! + + /* Restart BCM5785's CPU */ + gec_base[0x5004/4] = 0xFFFFFFFF; //clear CPU state + gec_base[0x5000/4] = 0x00000001; //reset RISC processor + //usually we'd have to wait for the reset bit to clear again ... +}

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Trac reminder: list of new ticket(s)
by coreboot tracker 04 Mar '13

04 Mar '13

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coreboot March 2013