Patch set updated for coreboot: 0fd9295 Google Link: Add remaining code to support native graphics

[Paul Menzel]

Paul Menzel ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2531

-gerrit

commit 0fd9295968ec5ec619923fa39239fd6f92f657a5
Author: Ronald G. Minnich 
Date:   Tue Feb 26 10:07:40 2013 -0800

Google Link: Add remaining code to support native graphics

The Link native graphics commit 49428d84 [1]

Add support for Google's Chromebook Pixel

was missing some of the higher level bits, and hence could not be
    used.  This is not new code -- it has been working since last
    August -- so the effort now is to get it into the tree and structure
    it in a way compatible with upstream coreboot.

1. Add options to src/device/Kconfig to enable native graphics.
    2. Export the MTRR function for setting variable MTRRs.
    3. Clean up some of the comments and white space.

While I realize that the product name is Pixel, the mainboard in the
    coreboot tree is called Link, and that name is what we will use
    in our commits.

[1] http://review.coreboot.org/2482

Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8
    Signed-off-by: Ronald G. Minnich 
---
 src/arch/x86/boot/coreboot_table.c      |  2 +-
 src/cpu/x86/mtrr/mtrr.c                 |  2 +-
 src/device/Kconfig                      | 26 ++++++++++++++-----
 src/device/oprom/realmode/x86.c         |  4 +--
 src/include/cpu/x86/mtrr.h              |  7 ++++++
 src/northbridge/intel/sandybridge/gma.c | 44 +++++++++++++++++++++++++++------
 6 files changed, 67 insertions(+), 18 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index e456e1e..d6d579f 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -172,7 +172,7 @@ static void lb_console(struct lb_header *header)

static void lb_framebuffer(struct lb_header *header)
 {
-#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE
+#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE || defined(CONFIG_MAINBOARD_DO_NATIVE_INIT)
    void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
    int vbe_mode_info_valid(void);

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index a061b54..5051904 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -83,7 +83,7 @@ static void enable_var_mtrr(void)
 }

/* setting variable mtrr, comes from linux kernel source */
-static void set_var_mtrr(
+void set_var_mtrr(
    unsigned int reg, unsigned long basek, unsigned long sizek,
    unsigned char type, unsigned address_bits)
 {
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 8e1265f..f7eac8d 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -19,12 +19,26 @@
 ##

menu "Devices"
+
+# Only set this in the mainboard
+config MAINBOARD_HAS_NATIVE_VGA_INIT
+	bool
+	default n
+
+config MAINBOARD_DO_NATIVE_VGA_INIT
+	bool "use Native graphics setup code"
+	depends on MAINBOARD_HAS_NATIVE_VGA_INIT
+	default n
+	help
+	  Enable mainboard code to turn on graphics, but without needing a video BIOS.
+	  This mode is only supported on some mainboards, such as the Google Link.
+
 # TODO: Explain differences (if any) for onboard cards.
 config VGA_ROM_RUN
    bool "Run VGA Option ROMs"
    default n if PAYLOAD_SEABIOS
    default y if !PAYLOAD_SEABIOS
-	depends on PCI && !PAYLOAD_SEABIOS || EXPERT
+	depends on (!MAINBOARD_DO_NATIVE_VGA_INIT) && PCI && !PAYLOAD_SEABIOS || EXPERT
    help
      Execute VGA Option ROMs in coreboot if found. This is required
      to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
@@ -94,7 +108,7 @@ choice
 config PCI_OPTION_ROM_RUN_REALMODE
    prompt "Native mode"
    bool
-	depends on ARCH_X86
+	depends on ARCH_X86 && !MAINBOARD_DO_NATIVE_VGA_INIT
    help
      If you select this option, PCI Option ROMs will be executed
      natively on the CPU in real mode. No CPU emulation is involved,
@@ -104,7 +118,7 @@ config PCI_OPTION_ROM_RUN_REALMODE
 config PCI_OPTION_ROM_RUN_YABEL
    prompt "Secure mode"
    bool
-	depends on !GEODE_VSA
+	depends on !GEODE_VSA && !MAINBOARD_DO_NATIVE_VGA_INIT
    help
      If you select this option, the x86emu CPU emulator will be used to
      execute PCI Option ROMs.
@@ -282,12 +296,12 @@ config MBI_FILE
 endmenu

menu "Display"
-	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
+	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT

config FRAMEBUFFER_SET_VESA_MODE
    prompt "Set VESA framebuffer mode"
    bool
-	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
+	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT
    help
      Set VESA framebuffer mode (needed for bootsplash)

@@ -425,7 +439,7 @@ config FRAMEBUFFER_VESA_MODE
 config FRAMEBUFFER_KEEP_VESA_MODE
    prompt "Keep VESA framebuffer"
    bool
-	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
+	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT
    help
      This option keeps the framebuffer mode set after coreboot finishes
      execution. If this option is enabled, coreboot will pass a
diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c
index 5fd11b5..6a8bdfc 100644
--- a/src/device/oprom/realmode/x86.c
+++ b/src/device/oprom/realmode/x86.c
@@ -191,7 +191,7 @@ static void setup_realmode_idt(void)
    write_idt_stub((void *)0xffe6e, 0x1a);
 }

-#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
 vbe_mode_info_t mode_info;
 static int mode_info_valid;

@@ -322,7 +322,7 @@ void run_bios(struct device *dev, unsigned long addr)
    realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, 0x0);
    printk(BIOS_DEBUG, "... Option ROM returned.\n");

-#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
    if ((dev->class >> 8)== PCI_CLASS_DISPLAY_VGA)
    	vbe_set_graphics();
 #endif
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 58bee04..dcb7075 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -40,6 +40,13 @@

#if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__)
 #include <device/device.h>
+/* You should almost NEVER use this function.
+ * N.B. We worked on a lot of ways to make this continue as static,
+ * but just making it available ended up being the simplest solution.
+ */
+void set_var_mtrr(
+	unsigned int reg, unsigned long basek, unsigned long sizek,
+	unsigned char type, unsigned address_bits);
 void enable_fixed_mtrr(void);
 void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);
 void x86_setup_mtrrs(void);
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index f35299e..1770710 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -23,6 +23,9 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>

#include "chip.h"
 #include "sandybridge.h"
@@ -619,20 +622,44 @@ static void gma_pm_init_post_vbios(struct device *dev)
 static void gma_func0_init(struct device *dev)
 {
    u32 reg32;
+	u32 graphics_base, graphics_size;

/* IGD needs to be Bus Master */
    reg32 = pci_read_config32(dev, PCI_COMMAND);
    reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
    pci_write_config32(dev, PCI_COMMAND, reg32);

+	/* Set up an MTRR to make anything the VBIOS does run fast. */
+	/* We have agreed on MTRR #8. */
+	graphics_base = dev->resource_list[1].base;
+	graphics_size = dev->resource_list[1].size;
+	printk(BIOS_DEBUG, "Set graphics %p size 0x%x\n",
+				(void *)graphics_base, graphics_size);
+	set_var_mtrr(8, graphics_base>>10, graphics_size>>10, MTRR_TYPE_WRCOMB, 0x24);
+
    /* Init graphics power management */
    gma_pm_init_pre_vbios(dev);

/* PCI Init, will run VBIOS */
+#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+	printk(BIOS_SPEW, "Run the VBIOS init\n");
    pci_dev_init(dev);
+#endif

/* Post VBIOS init */
    gma_pm_init_post_vbios(dev);
+
+#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+	printk(BIOS_SPEW, "NATIVE graphics, run native enable\n");
+	u32 iobase, mmiobase, physbase;
+	iobase = dev->resource_list[2].base;
+	mmiobase = dev->resource_list[0].base;
+	physbase = pci_read_config32(dev, 0x5c) & ~0xf;
+
+	int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx);
+	i915lightup(physbase, iobase, mmiobase, graphics_base);
+#endif
+
 }

static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
@@ -660,12 +687,13 @@ static struct device_operations gma_func0_ops = {
    .ops_pci		= &gma_pci_ops,
 };

-static const unsigned short gma_ids[] = {
-	0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, 0x0156, 0x166,
-	0,
-};
-static const struct pci_driver gma_gt1_desktop __pci_driver = {
-	.ops	= &gma_func0_ops,
-	.vendor	= PCI_VENDOR_ID_INTEL,
-	.devices= gma_ids,
+static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112,
+						 0x0116, 0x0122, 0x0126, 0x0156,
+						 0x0166,
+						 0 };
+
+static const struct pci_driver pch_lpc __pci_driver = {
+	.ops	 = &gma_func0_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
+	.devices = pci_device_ids,
 };