coreboot March 2013

coreboot@coreboot.org

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782 discussions

Re: [coreboot] Unifying AMD SB700/SB800/SB900 code base
by Bruce Griffith 08 Mar '13

08 Mar '13

> This is awesome news. Was it intentional that you did not reply to the > list > too? It was intentional but probably poor judgment. This reply is to the list. > As can be seen from the latest responses this seems to be considered > quite controversial. The focus is on AMD-designed boards, but may impact other boards with AMD processors and chipsets. Marc and Martin are watching over the effort and the patches will be pushed to Gerrit where they will go through the normal review process. > My message was also about code outside `src/mainboard`. But let’s take one > step at a time. Replicated code in the wrappers for CIM-X, AGESA, and pre-AGESA is less of a concern. That would be at a lower priority than src/mainboards. > -----Original Message----- > From: Paul Menzel [mailto:paulepanter@users.sourceforge.net] > Sent: 07 March 2013 4:35 AM > To: Bruce Griffith > Subject: Re: [coreboot] Unifying AMD SB700/SB800/SB900 code base > > Dear Bruce, > > thank you very much for your response and sorry for my late reply. > > Am Montag, den 04.03.2013, 18:40 -0600 schrieb Bruce Griffith: > > > You're right. There's a lot of replicated code in the AMD-specific > > parts of the coreboot tree. In the past, the focus has been to get > > new parts and development boards released as early as possible. And > > that has been at the expense of keeping the codebase clean. > > > > There is an effort starting up to clean up the codebase to [get] as much > > code as possible out of the mainboards directories for AMD boards. As > > a consequence, we expect that some amount of code will get refactored > > into common files. Using standard file names, function names, and > > variable names when similar code needs to be differentiated by > > processor or chipset is a good suggestion. > > > > I expect that we will start to have patches into gerrit within a week > > or two. > > This is awesome news. Was it intentional that you did not reply to the > list > too? As can be seen from the latest responses this seems to be considered > quite controversial. > > My message was also about code outside `src/mainboard`. But let’s take one > step at a time. > > Thanks, > Paul

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Patch merged into coreboot/master: 00d673d FrontRunner/Toucan-AF: lower SPI speed to 22 MHz
by gerrit＠coreboot.org 08 Mar '13

08 Mar '13

the following patch was just integrated into master: commit 00d673d165006b28bbbe5b2d84ef80d8665d8f34 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Thu Mar 7 19:02:15 2013 +0100 FrontRunner/Toucan-AF: lower SPI speed to 22 MHz The Hudson-E1's default SPI speed for normal i.e. non-fast reads is 66 MHz, but the SST 25VF032B datasheet allows max. 25. Lower the speed to 22 MHz, otherwise BIOS flashing fails. Change-Id: I22e87d833a3ebd316b6e873595a2480831533ab1 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2605 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Build-Tested: build bot (Jenkins) at Thu Mar 7 19:29:33 2013, giving +1 See http://review.coreboot.org/2605 for details. -gerrit

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Patch set updated for coreboot: b02c5e6 Persimmon DSDT: Add secondary bus range to PCI0
by Mike Loptien 08 Mar '13

08 Mar '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2592 -gerrit commit b02c5e684fc5ec0aeafb0b23a3e0ffa3c1689d6f Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Tue Mar 5 14:21:28 2013 -0700 Persimmon DSDT: Add secondary bus range to PCI0 Adding the 'WordBusNumber' macro to the PCI0 CRES ResourceTemplate in the Persimmon DSDT. This sets up the bus number for the PCI0 device and the secondary bus number in the CRS method. This change came in response to a 'dmesg' error which states: '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS' By adding the 'WordBusNumber' macro, ACPI can set up a valid range for the PCIe downstream busses, thereby relieving the Linux kernel from "guessing" the valid range based off _BBN or assuming [0-0xFF]. The Linux kernel code that checks this bus range is in `drivers/acpi/pci_root.c`. PCI busses can have up to 256 secondary busses connected to them via a PCI-PCI bridge. However, these busses do not have to be sequentially numbered, so leaving out a section of the range (eg. allowing [0-0x7F]) will unnecessarily restrict the downstream busses. This change will apply to other AMD mainboards and will be in a different commit. Change-Id: I44f22bc03a0dcbcd2594d4291508826cc2146860 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/amd/persimmon/dsdt.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index 582ab7f..148d7b0 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -1477,6 +1477,22 @@ DefinitionBlock ( } /* end Ac97modem */ Name(CRES, ResourceTemplate() { + /* Set the Bus number and Secondary Bus number for the PCI0 device + * The Secondary bus range for PCI0 lets the system + * know what bus values are allowed on the downstream + * side of this PCI bus if there is a PCI-PCI bridge. + * PCI busses can have 256 secondary busses which + * range from [0-0xFF] but they do not need to be + * sequential. + */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x00FF, /* range maximum */ + 0x0000, /* translation */ + 0x0100, /* length */ + ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,

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New patch to review for coreboot: c71730d src/device/root_device.c: Spew out when mainboard
by Paul Menzel 08 Mar '13

08 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2612 -gerrit commit c71730d79f9e989ca3c898acb522b8d6f96917df Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Mar 7 15:19:25 2013 +0100 src/device/root_device.c: Spew out when mainboard For example change for ASRock E350M1 […] Mainboard E350M1 Enable. → Enable mainboard ASROCK E350M1 scan_static_bus for Root Device […] Peter’s suggestion [1]: Not sure how this looks like, when dev is printed out. printk(BIOS_INFO "%s " CONFIG_MAINBOARD_DIR ". dev=0x%p\n", __func__, dev); TODO 0. Decide on level: `BIOS_INFO` or `BIOS_SPEW`? 1. Decide on wording. 2. Decide if `CONFIG_MAINBOARD_DIR` or `mainboard_name` should be used. 3. Adapt all boards. 4. Add test. [1] http://www.coreboot.org/pipermail/coreboot/2013-February/074621.html Change-Id: Ie22cfac202f6dd8060860d9600312fe5af499612 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/device/root_device.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/device/root_device.c b/src/device/root_device.c index 49fa711..f285283 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -136,6 +136,8 @@ static void root_dev_enable_resources(device_t dev) */ static unsigned int root_dev_scan_bus(device_t root, unsigned int max) { + printk(BIOS_SPEW, "Enable mainboard %s\n", mainboard_name); + return scan_static_bus(root, max); }

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New patch to review for coreboot: b8ccab2 AMD Persimmon: mainboard.c: Make comment generic to reduce difference
by Paul Menzel 07 Mar '13

07 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2611 -gerrit commit b8ccab29d3619b9d7cfb3e0907c1df2835e478d8 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Mar 7 22:41:25 2013 +0100 AMD Persimmon: mainboard.c: Make comment generic to reduce difference Replace »persimmon« by »board« in comment to keep `diff` output between boards small. Change-Id: Ieae2a63782c488ae35f22eb30f5b1049200d12c8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/persimmon/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 6cba175..b17bc6a 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -77,7 +77,7 @@ static void mainboard_enable(device_t dev) /* * Initialize ASF registers to an arbitrary address because someone * long ago set things up this way inside the SPD read code. The - * SPD read code has been made generic and moved out of the persimmon + * SPD read code has been made generic and moved out of the board * directory, so the ASF init is being done here. */ pm_iowrite(0x29, 0x80);

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New patch to review for coreboot: 5d9bbe7 ASRock E350M1: platform_cfg.h: Hook up Kconfig SATA Mode choice
by Paul Menzel 07 Mar '13

07 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2610 -gerrit commit 5d9bbe7ec6b88276947fd15e8a54edeaf50ed038 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 3 10:56:15 2013 +0100 ASRock E350M1: platform_cfg.h: Hook up Kconfig SATA Mode choice Currently despite what is chosen in Kconfig »Chipset« menu item, $ more .config […] # CONFIG_ENABLE_IDE_COMBINED_MODE is not set CONFIG_IDE_COMBINED_MODE=0x1 # CONFIG_SB800_SATA_IDE is not set CONFIG_SB800_SATA_AHCI=y # CONFIG_SB800_SATA_RAID is not set CONFIG_SB800_SATA_MODE=0x2 […] the SATA controller is put into IDE mode. $ lspci -nn | grep SATA 00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [IDE mode] [1002:4390] (rev 40) Commit »sb800: Add sata ahci/raid mode kconfig option« (d4a0e7d0) [1] added the options above to configure the mode using Kconfig and the other SB800 boards were adapted already. For example commit »persimmon: sb800 sata mode configure update« (1386fa74) [2] did so for AMD Persimmon. Doing the same by assigning the Kconfig variable to the value in `platform_cfg.h` hooks this up to the ASRock E350M1 too as was successfully tested. $ lspci -nn | grep SATA 00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] (rev 40) [1] http://review.coreboot.org/225 [2] http://review.coreboot.org/227 Change-Id: I227257e2c8f04f18c27ff00fe62d42e372de67e4 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/platform_cfg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 389e7db..24a66dd 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -103,7 +103,7 @@ * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ -#define SATA_MODE NATIVE_IDE_MODE +#define SATA_MODE CONFIG_SB800_SATA_MODE /** * @brief INCHIP Sata IDE Controller Mode

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Patch set updated for coreboot: 52cabd5 AMD Union Station: Use SPD read code from F14 wrapper
by Kimarie Hoot 07 Mar '13

07 Mar '13

Kimarie Hoot (kimarie.hoot(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2609 -gerrit commit 52cabd5e231e2ab709566cac091dc3cc76a915b2 Author: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Date: Thu Mar 7 09:10:29 2013 -0700 AMD Union Station: Use SPD read code from F14 wrapper Changes: - Get rid of the union_station mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I19d6b0d674b67294519383f80928471b37da1e14 Signed-off-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> --- src/mainboard/amd/union_station/BiosCallOuts.c | 8 +- src/mainboard/amd/union_station/Makefile.inc | 2 - src/mainboard/amd/union_station/devicetree.cb | 7 ++ src/mainboard/amd/union_station/dimmSpd.c | 167 ------------------------- src/mainboard/amd/union_station/dimmSpd.h | 63 ---------- src/mainboard/amd/union_station/mainboard.c | 12 +- 6 files changed, 24 insertions(+), 235 deletions(-) diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 6059549..2aca184 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -19,10 +19,10 @@ #include "agesawrapper.h" #include "amdlib.h" -#include "dimmSpd.h" #include "BiosCallOuts.h" #include "heapManager.h" #include "SB800.h" +#include <northbridge/amd/agesa/family14/dimmSpd.h> STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -424,7 +424,11 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); +#ifdef __PRE_RAM__ + Status = agesa_ReadSPD (Func, Data, ConfigPtr); +#else + Status = AGESA_UNSUPPORTED; +#endif return Status; } diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc index 50f9447..59c6cd0 100644 --- a/src/mainboard/amd/union_station/Makefile.inc +++ b/src/mainboard/amd/union_station/Makefile.inc @@ -19,13 +19,11 @@ romstage-y += buildOpts.c romstage-y += agesawrapper.c -romstage-y += dimmSpd.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c -ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb index 7f06e64..2289126 100644 --- a/src/mainboard/amd/union_station/devicetree.cb +++ b/src/mainboard/amd/union_station/devicetree.cb @@ -75,6 +75,13 @@ chip northbridge/amd/agesa/family14/root_complex device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/union_station/dimmSpd.c b/src/mainboard/amd/union_station/dimmSpd.c deleted file mode 100644 index e1586b0..0000000 --- a/src/mainboard/amd/union_station/dimmSpd.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); -#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) - -/*#pragma optimize ("", off) // for source level debug -*--------------------------------------------------------------------------- -* -* SPD address table - porting required -*/ - -static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm - { - // socket 0 - { - {0xA0, 0xA2}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, - // socket 1 - { - {0x00, 0x00}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, - }; - -/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) - { - unsigned int status; - UINT64 limit; - - address |= 1; // set read bit - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; - } - -/*----------------------------------------------------------------------------- - * - * readSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData - */ - -static int readSmbusByte (int iobase, int address, char *buffer) - { - unsigned int status; - UINT64 limit; - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command - - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; - } - -/*--------------------------------------------------------------------------- - * - * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. - */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) - { - int index, error; - - /* read the first byte using offset zero */ - error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); - if (error) return error; - - /* read the remaining bytes using auto-increment for speed */ - for (index = 1; index < count; index++) - { - error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); - if (error) return error; - } - - return 0; - } - -static void writePmReg (int reg, int data) - { - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); - } - -static void setupFch (int ioBase) - { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); - writePmReg (0x29, 0x80); - writePmReg (0x28, 0x61); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz - } - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) - { - int spdAddress, ioBase; - - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; - if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; - if (spdAddress == 0) return AGESA_ERROR; - ioBase = SMBUS0_BASE_ADDRESS; - setupFch (ioBase); - return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); - } diff --git a/src/mainboard/amd/union_station/dimmSpd.h b/src/mainboard/amd/union_station/dimmSpd.h deleted file mode 100644 index 81ab02e..0000000 --- a/src/mainboard/amd/union_station/dimmSpd.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#ifndef _DIMMSPD_H_ -#define _DIMMSPD_H_ - -#include "Porting.h" -#include "AGESA.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -AmdMemoryReadSPD ( - IN UINT32 Func, - IN UINT32 Data, - IN OUT AGESA_READ_SPD_PARAMS *SpdData - ); - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -#endif diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 916b62e..8f9b26c 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -22,8 +22,9 @@ #include <device/pci.h> #include <arch/io.h> #include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> +#include <southbridge/amd/sb800/sb800.h> +#include <cpu/amd/mtrr.h> #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ void set_pcie_reset(void); @@ -52,6 +53,15 @@ void set_pcie_dereset(void) static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* + * Initialize ASF registers to an arbitrary address because someone + * long ago set things up this way inside the SPD read code. The + * SPD read code has been made generic and moved out of the + * union_station directory, so the ASF init is being done here. + */ + pm_iowrite(0x29, 0x80); + pm_iowrite(0x28, 0x61); } struct chip_operations mainboard_ops = {

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Patch set updated for coreboot: 190de1b AMD South Station: Use SPD read code from F14 wrapper
by Kimarie Hoot 07 Mar '13

07 Mar '13

Kimarie Hoot (kimarie.hoot(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2608 -gerrit commit 190de1bc97854d1dd5a5c6a178ac9978c1ecac9a Author: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Date: Thu Mar 7 08:54:36 2013 -0700 AMD South Station: Use SPD read code from F14 wrapper Changes: - Get rid of the south_station mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: If4291d25ea81bf375f55b64c07c223a847a211d0 Signed-off-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> --- src/mainboard/amd/south_station/BiosCallOuts.c | 8 +- src/mainboard/amd/south_station/Makefile.inc | 2 - src/mainboard/amd/south_station/devicetree.cb | 7 ++ src/mainboard/amd/south_station/dimmSpd.c | 167 ------------------------- src/mainboard/amd/south_station/dimmSpd.h | 63 ---------- src/mainboard/amd/south_station/mainboard.c | 10 ++ 6 files changed, 23 insertions(+), 234 deletions(-) diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 6059549..2aca184 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -19,10 +19,10 @@ #include "agesawrapper.h" #include "amdlib.h" -#include "dimmSpd.h" #include "BiosCallOuts.h" #include "heapManager.h" #include "SB800.h" +#include <northbridge/amd/agesa/family14/dimmSpd.h> STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -424,7 +424,11 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); +#ifdef __PRE_RAM__ + Status = agesa_ReadSPD (Func, Data, ConfigPtr); +#else + Status = AGESA_UNSUPPORTED; +#endif return Status; } diff --git a/src/mainboard/amd/south_station/Makefile.inc b/src/mainboard/amd/south_station/Makefile.inc index 50f9447..59c6cd0 100644 --- a/src/mainboard/amd/south_station/Makefile.inc +++ b/src/mainboard/amd/south_station/Makefile.inc @@ -19,13 +19,11 @@ romstage-y += buildOpts.c romstage-y += agesawrapper.c -romstage-y += dimmSpd.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c -ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb index 883166c..60335d7 100644 --- a/src/mainboard/amd/south_station/devicetree.cb +++ b/src/mainboard/amd/south_station/devicetree.cb @@ -99,6 +99,13 @@ chip northbridge/amd/agesa/family14/root_complex device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/south_station/dimmSpd.c b/src/mainboard/amd/south_station/dimmSpd.c deleted file mode 100644 index e1586b0..0000000 --- a/src/mainboard/amd/south_station/dimmSpd.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); -#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) - -/*#pragma optimize ("", off) // for source level debug -*--------------------------------------------------------------------------- -* -* SPD address table - porting required -*/ - -static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm - { - // socket 0 - { - {0xA0, 0xA2}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, - // socket 1 - { - {0x00, 0x00}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, - }; - -/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) - { - unsigned int status; - UINT64 limit; - - address |= 1; // set read bit - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; - } - -/*----------------------------------------------------------------------------- - * - * readSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData - */ - -static int readSmbusByte (int iobase, int address, char *buffer) - { - unsigned int status; - UINT64 limit; - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command - - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; - } - -/*--------------------------------------------------------------------------- - * - * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. - */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) - { - int index, error; - - /* read the first byte using offset zero */ - error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); - if (error) return error; - - /* read the remaining bytes using auto-increment for speed */ - for (index = 1; index < count; index++) - { - error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); - if (error) return error; - } - - return 0; - } - -static void writePmReg (int reg, int data) - { - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); - } - -static void setupFch (int ioBase) - { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); - writePmReg (0x29, 0x80); - writePmReg (0x28, 0x61); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz - } - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) - { - int spdAddress, ioBase; - - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; - if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; - if (spdAddress == 0) return AGESA_ERROR; - ioBase = SMBUS0_BASE_ADDRESS; - setupFch (ioBase); - return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); - } diff --git a/src/mainboard/amd/south_station/dimmSpd.h b/src/mainboard/amd/south_station/dimmSpd.h deleted file mode 100644 index 81ab02e..0000000 --- a/src/mainboard/amd/south_station/dimmSpd.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#ifndef _DIMMSPD_H_ -#define _DIMMSPD_H_ - -#include "Porting.h" -#include "AGESA.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -AmdMemoryReadSPD ( - IN UINT32 Func, - IN UINT32 Data, - IN OUT AGESA_READ_SPD_PARAMS *SpdData - ); - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -#endif diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index 83b4b38..5d08b67 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <arch/io.h> #include <cpu/x86/msr.h> +#include <southbridge/amd/sb800/sb800.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <delay.h> @@ -80,6 +81,15 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); southstation_led_init(); + + /* + * Initialize ASF registers to an arbitrary address because someone + * long ago set things up this way inside the SPD read code. The + * SPD read code has been made generic and moved out of the + * south_station directory, so the ASF init is being done here. + */ + pm_iowrite(0x29, 0x80); + pm_iowrite(0x28, 0x61); } struct chip_operations mainboard_ops = {

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Patch set updated for coreboot: a2b39a5 AMD SouthStation: Use SPD read code from F14 wrapper
by Kimarie Hoot 07 Mar '13

07 Mar '13

Kimarie Hoot (kimarie.hoot(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2608 -gerrit commit a2b39a5fcc33fbf9ba9e2373f465e1028767155a Author: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Date: Thu Mar 7 08:54:36 2013 -0700 AMD SouthStation: Use SPD read code from F14 wrapper Changes: - Get rid of the south_station mainboard specific code and uses the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: If4291d25ea81bf375f55b64c07c223a847a211d0 Signed-off-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> --- src/mainboard/amd/south_station/BiosCallOuts.c | 8 +- src/mainboard/amd/south_station/Makefile.inc | 2 - src/mainboard/amd/south_station/devicetree.cb | 7 ++ src/mainboard/amd/south_station/dimmSpd.c | 167 ------------------------- src/mainboard/amd/south_station/dimmSpd.h | 63 ---------- src/mainboard/amd/south_station/mainboard.c | 10 ++ 6 files changed, 23 insertions(+), 234 deletions(-) diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 6059549..2aca184 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -19,10 +19,10 @@ #include "agesawrapper.h" #include "amdlib.h" -#include "dimmSpd.h" #include "BiosCallOuts.h" #include "heapManager.h" #include "SB800.h" +#include <northbridge/amd/agesa/family14/dimmSpd.h> STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -424,7 +424,11 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); +#ifdef __PRE_RAM__ + Status = agesa_ReadSPD (Func, Data, ConfigPtr); +#else + Status = AGESA_UNSUPPORTED; +#endif return Status; } diff --git a/src/mainboard/amd/south_station/Makefile.inc b/src/mainboard/amd/south_station/Makefile.inc index 50f9447..59c6cd0 100644 --- a/src/mainboard/amd/south_station/Makefile.inc +++ b/src/mainboard/amd/south_station/Makefile.inc @@ -19,13 +19,11 @@ romstage-y += buildOpts.c romstage-y += agesawrapper.c -romstage-y += dimmSpd.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c -ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb index 883166c..60335d7 100644 --- a/src/mainboard/amd/south_station/devicetree.cb +++ b/src/mainboard/amd/south_station/devicetree.cb @@ -99,6 +99,13 @@ chip northbridge/amd/agesa/family14/root_complex device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/south_station/dimmSpd.c b/src/mainboard/amd/south_station/dimmSpd.c deleted file mode 100644 index e1586b0..0000000 --- a/src/mainboard/amd/south_station/dimmSpd.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); -#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) - -/*#pragma optimize ("", off) // for source level debug -*--------------------------------------------------------------------------- -* -* SPD address table - porting required -*/ - -static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm - { - // socket 0 - { - {0xA0, 0xA2}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, - // socket 1 - { - {0x00, 0x00}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, - }; - -/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) - { - unsigned int status; - UINT64 limit; - - address |= 1; // set read bit - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; - } - -/*----------------------------------------------------------------------------- - * - * readSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData - */ - -static int readSmbusByte (int iobase, int address, char *buffer) - { - unsigned int status; - UINT64 limit; - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command - - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; - } - -/*--------------------------------------------------------------------------- - * - * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. - */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) - { - int index, error; - - /* read the first byte using offset zero */ - error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); - if (error) return error; - - /* read the remaining bytes using auto-increment for speed */ - for (index = 1; index < count; index++) - { - error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); - if (error) return error; - } - - return 0; - } - -static void writePmReg (int reg, int data) - { - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); - } - -static void setupFch (int ioBase) - { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); - writePmReg (0x29, 0x80); - writePmReg (0x28, 0x61); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz - } - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) - { - int spdAddress, ioBase; - - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; - if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; - if (spdAddress == 0) return AGESA_ERROR; - ioBase = SMBUS0_BASE_ADDRESS; - setupFch (ioBase); - return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); - } diff --git a/src/mainboard/amd/south_station/dimmSpd.h b/src/mainboard/amd/south_station/dimmSpd.h deleted file mode 100644 index 81ab02e..0000000 --- a/src/mainboard/amd/south_station/dimmSpd.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#ifndef _DIMMSPD_H_ -#define _DIMMSPD_H_ - -#include "Porting.h" -#include "AGESA.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -AmdMemoryReadSPD ( - IN UINT32 Func, - IN UINT32 Data, - IN OUT AGESA_READ_SPD_PARAMS *SpdData - ); - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -#endif diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index 83b4b38..104492e 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <arch/io.h> #include <cpu/x86/msr.h> +#include <southbridge/amd/sb800/sb800.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <delay.h> @@ -80,6 +81,15 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); southstation_led_init(); + + /* + * Initialize ASF registers to an arbitrary address because someone + * long ago set things up this way inside the SPD read code. The + * SPD read code has been made generic and moved out of the persimmon + * directory, so the ASF init is being done here. + */ + pm_iowrite(0x29, 0x80); + pm_iowrite(0x28, 0x61); } struct chip_operations mainboard_ops = {

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Patch set updated for coreboot: 14fe011 AMD UnionStation: Use SPD read code from F14 wrapper
by Kimarie Hoot 07 Mar '13

07 Mar '13

Kimarie Hoot (kimarie.hoot(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2609 -gerrit commit 14fe0115d13ad78ca35a9151aaaa81091dff222e Author: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Date: Thu Mar 7 09:10:29 2013 -0700 AMD UnionStation: Use SPD read code from F14 wrapper Changes: - Get rid of the union_station mainboard specific code and uses the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I19d6b0d674b67294519383f80928471b37da1e14 Signed-off-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> --- src/mainboard/amd/union_station/BiosCallOuts.c | 8 +- src/mainboard/amd/union_station/Makefile.inc | 2 - src/mainboard/amd/union_station/devicetree.cb | 7 ++ src/mainboard/amd/union_station/dimmSpd.c | 167 ------------------------- src/mainboard/amd/union_station/dimmSpd.h | 63 ---------- src/mainboard/amd/union_station/mainboard.c | 12 +- 6 files changed, 24 insertions(+), 235 deletions(-) diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 6059549..2aca184 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -19,10 +19,10 @@ #include "agesawrapper.h" #include "amdlib.h" -#include "dimmSpd.h" #include "BiosCallOuts.h" #include "heapManager.h" #include "SB800.h" +#include <northbridge/amd/agesa/family14/dimmSpd.h> STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -424,7 +424,11 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); +#ifdef __PRE_RAM__ + Status = agesa_ReadSPD (Func, Data, ConfigPtr); +#else + Status = AGESA_UNSUPPORTED; +#endif return Status; } diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc index 50f9447..59c6cd0 100644 --- a/src/mainboard/amd/union_station/Makefile.inc +++ b/src/mainboard/amd/union_station/Makefile.inc @@ -19,13 +19,11 @@ romstage-y += buildOpts.c romstage-y += agesawrapper.c -romstage-y += dimmSpd.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c -ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb index 7f06e64..2289126 100644 --- a/src/mainboard/amd/union_station/devicetree.cb +++ b/src/mainboard/amd/union_station/devicetree.cb @@ -75,6 +75,13 @@ chip northbridge/amd/agesa/family14/root_complex device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/union_station/dimmSpd.c b/src/mainboard/amd/union_station/dimmSpd.c deleted file mode 100644 index e1586b0..0000000 --- a/src/mainboard/amd/union_station/dimmSpd.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); -#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) - -/*#pragma optimize ("", off) // for source level debug -*--------------------------------------------------------------------------- -* -* SPD address table - porting required -*/ - -static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm - { - // socket 0 - { - {0xA0, 0xA2}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, - // socket 1 - { - {0x00, 0x00}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, - }; - -/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) - { - unsigned int status; - UINT64 limit; - - address |= 1; // set read bit - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; - } - -/*----------------------------------------------------------------------------- - * - * readSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData - */ - -static int readSmbusByte (int iobase, int address, char *buffer) - { - unsigned int status; - UINT64 limit; - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command - - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; - } - -/*--------------------------------------------------------------------------- - * - * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. - */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) - { - int index, error; - - /* read the first byte using offset zero */ - error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); - if (error) return error; - - /* read the remaining bytes using auto-increment for speed */ - for (index = 1; index < count; index++) - { - error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); - if (error) return error; - } - - return 0; - } - -static void writePmReg (int reg, int data) - { - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); - } - -static void setupFch (int ioBase) - { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); - writePmReg (0x29, 0x80); - writePmReg (0x28, 0x61); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz - } - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) - { - int spdAddress, ioBase; - - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; - if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; - if (spdAddress == 0) return AGESA_ERROR; - ioBase = SMBUS0_BASE_ADDRESS; - setupFch (ioBase); - return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); - } diff --git a/src/mainboard/amd/union_station/dimmSpd.h b/src/mainboard/amd/union_station/dimmSpd.h deleted file mode 100644 index 81ab02e..0000000 --- a/src/mainboard/amd/union_station/dimmSpd.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#ifndef _DIMMSPD_H_ -#define _DIMMSPD_H_ - -#include "Porting.h" -#include "AGESA.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -AmdMemoryReadSPD ( - IN UINT32 Func, - IN UINT32 Data, - IN OUT AGESA_READ_SPD_PARAMS *SpdData - ); - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -#endif diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 916b62e..76e5ae3 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -22,8 +22,9 @@ #include <device/pci.h> #include <arch/io.h> #include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> +#include <southbridge/amd/sb800/sb800.h> +#include <cpu/amd/mtrr.h> #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ void set_pcie_reset(void); @@ -52,6 +53,15 @@ void set_pcie_dereset(void) static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* + * Initialize ASF registers to an arbitrary address because someone + * long ago set things up this way inside the SPD read code. The + * SPD read code has been made generic and moved out of the persimmon + * directory, so the ASF init is being done here. + */ + pm_iowrite(0x29, 0x80); + pm_iowrite(0x28, 0x61); } struct chip_operations mainboard_ops = {

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coreboot March 2013