coreboot March 2013

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Patch merged into coreboot/master: d9b16f3 snow: add real values for GPIOs in fill_lb_gpios()
by gerrit＠coreboot.org 07 Mar '13

07 Mar '13

the following patch was just integrated into master: commit d9b16f3b048243fd7d4c4513875f7f241261ce50 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Mar 6 19:16:10 2013 -0800 snow: add real values for GPIOs in fill_lb_gpios() This adds some real GPIO mappings where virtual GPIOs were used before. Change-Id: I25d4be45f986c8d622b97151f8bdae2651baf3e6 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2603 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Mar 7 05:47:54 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 7 06:42:16 2013, giving +2 See http://review.coreboot.org/2603 for details. -gerrit

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Patch merged into coreboot/master: 1d290ee exynos5: add GPIO port enums
by gerrit＠coreboot.org 07 Mar '13

07 Mar '13

the following patch was just integrated into master: commit 1d290eeb1c72a31b5d49a1fca57f99b081fe24d4 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Mar 6 20:11:20 2013 -0800 exynos5: add GPIO port enums This adds an enum for GPIO ports on the Exynos5. To make them useful, they are assigned the absolute MMIO address where a s5p_gpio_bank struct can point to. Change-Id: Ia539ba52d7393501d434ba8fecde01da37b0d8aa Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2602 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Mar 7 05:37:40 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 7 06:41:36 2013, giving +2 See http://review.coreboot.org/2602 for details. -gerrit

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[RFC] Keep all Jenkins build logs
by Paul Menzel 07 Mar '13

07 Mar '13

Dear coreboot folks, Jenkins seems to be configured to delete build logs after a certain amount of time. For example #4000 is not there anymore [1]. I am aware that Jenkins has to build a lot of commits (and their iterations). For archival purposes, I’d vote for keeping the logs, if possible. For example to find out if certain warnings have existed already without having to rebuild locally. With big hard drives and compression that should be doable, right? Thanks, Paul [1] http://qa.coreboot.org/job/coreboot-gerrit/4000/

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New patch to review for coreboot: 5a33377 snow: add real values for GPIOs in fill_lb_gpios()
by David Hendricks 07 Mar '13

07 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2603 -gerrit commit 5a33377f33c6a8d38287fa9b2795f8909f28da00 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Mar 6 19:16:10 2013 -0800 snow: add real values for GPIOs in fill_lb_gpios() This adds some real GPIO mappings where virtual GPIOs were used before. Change-Id: I25d4be45f986c8d622b97151f8bdae2651baf3e6 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/chromeos.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index fd2006c..14da49c 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -22,6 +22,10 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> +#include <cpu/samsung/exynos5250/cpu.h> +#include <cpu/samsung/exynos5250/gpio.h> +#include <cpu/samsung/exynos5-common/gpio.h> + #include <device/device.h> #define ACTIVE_LOW 0 @@ -30,6 +34,8 @@ #define DEVMODE_GPIO 54 #define FORCE_RECOVERY_MODE 0 #define FORCE_DEVELOPER_MODE 0 +#define LID_OPEN 3 +#define POWER_BUTTON 3 #include <boot/coreboot_tables.h> #include <arch/coreboot_tables.h> @@ -38,33 +44,38 @@ void fill_lb_gpios(struct lb_gpios *gpios) { + struct exynos5_gpio_part1 *gpio_pt1; + struct exynos5_gpio_part2 *gpio_pt2; gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); gpios->count = GPIO_COUNT; - /* Write Protect: virtual GPIO active Low */ - gpios->gpios[0].port = -1; + gpio_pt1 = (struct exynos5_gpio_part1 *)EXYNOS5_GPIO_PART1_BASE; + gpio_pt2 = (struct exynos5_gpio_part2 *)EXYNOS5_GPIO_PART2_BASE; + + /* Write Protect: active Low */ + gpios->gpios[0].port = EXYNOS5_GPD1; gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = 1; + gpios->gpios[0].value = s5p_gpio_get_value(&gpio_pt1->d1, WP_GPIO); strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); - /* Recovery: virtual GPIO active high */ - gpios->gpios[1].port = -1; + /* Recovery: active high */ + gpios->gpios[1].port = EXYNOS5_GPY1; gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = 0; + gpios->gpios[2].value = s5p_gpio_get_value(&gpio_pt1->y1, FORCE_RECOVERY_MODE); strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); /* Lid: the "switch" comes from the EC */ - gpios->gpios[2].port = -1; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = 0; + gpios->gpios[2].port = EXYNOS5_GPX3; + gpios->gpios[2].polarity = ACTIVE_LOW; + gpios->gpios[2].value = s5p_gpio_get_value(&gpio_pt2->x3, LID_OPEN); strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); - /* Power: hardcoded as not pressed */ + /* Power: virtual GPIO active low */ gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = 0; + gpios->gpios[3].polarity = ACTIVE_LOW; + gpios->gpios[3].value = 1; strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); /* Developer: virtual GPIO active high */

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New patch to review for coreboot: 0ab3fec exynos5: add GPIO port enums
by David Hendricks 07 Mar '13

07 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2602 -gerrit commit 0ab3fec064562b446c232d37de158a69d646182c Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Mar 6 20:11:20 2013 -0800 exynos5: add GPIO port enums This adds an enum for GPIO ports on the Exynos5. To make them useful, they are assigned the absolute MMIO address where a s5p_gpio_bank struct can point to. Change-Id: Ia539ba52d7393501d434ba8fecde01da37b0d8aa Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/gpio.h | 68 +++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/src/cpu/samsung/exynos5-common/gpio.h b/src/cpu/samsung/exynos5-common/gpio.h index 0de53f6..0e4afc5 100644 --- a/src/cpu/samsung/exynos5-common/gpio.h +++ b/src/cpu/samsung/exynos5-common/gpio.h @@ -214,4 +214,72 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); #define EXYNOS_GPIO_DRV_4X 0x3 #define EXYNOS_GPIO_DRV_FAST 0x0 #define EXYNOS_GPIO_DRV_SLOW 0x1 + +#define EXYNOS5_GPIO_BASE0 0x11400000 +#define EXYNOS5_GPIO_BASE1 0x13400000 +#define EXYNOS5_GPIO_BASE2 0x10d10000 +#define EXYNOS5_GPIO_BASE3 0x03860000 + +enum exynos5_gpio_port { + /* + * Ordered by base address + offset. + * ETC registers are special, thus not included. + */ + + /* base == EXYNOS_GPIO_BASE0 */ + EXYNOS5_GPA0 = EXYNOS5_GPIO_BASE0 + 0x0000, + EXYNOS5_GPA1 = EXYNOS5_GPIO_BASE0 + 0x0020, + EXYNOS5_GPA2 = EXYNOS5_GPIO_BASE0 + 0x0040, + + EXYNOS5_GPB0 = EXYNOS5_GPIO_BASE0 + 0x0060, + EXYNOS5_GPB1 = EXYNOS5_GPIO_BASE0 + 0x0080, + EXYNOS5_GPB2 = EXYNOS5_GPIO_BASE0 + 0x00a0, + EXYNOS5_GPB3 = EXYNOS5_GPIO_BASE0 + 0x00c0, + + EXYNOS5_GPC0 = EXYNOS5_GPIO_BASE0 + 0x00e0, + EXYNOS5_GPC1 = EXYNOS5_GPIO_BASE0 + 0x0100, + EXYNOS5_GPC2 = EXYNOS5_GPIO_BASE0 + 0x0120, + EXYNOS5_GPC3 = EXYNOS5_GPIO_BASE0 + 0x0140, + + EXYNOS5_GPD0 = EXYNOS5_GPIO_BASE0 + 0x0160, + EXYNOS5_GPD1 = EXYNOS5_GPIO_BASE0 + 0x0180, + + EXYNOS5_GPY0 = EXYNOS5_GPIO_BASE0 + 0x01a0, + EXYNOS5_GPY1 = EXYNOS5_GPIO_BASE0 + 0x01c0, + EXYNOS5_GPY2 = EXYNOS5_GPIO_BASE0 + 0x01e0, + EXYNOS5_GPY3 = EXYNOS5_GPIO_BASE0 + 0x0200, + EXYNOS5_GPY4 = EXYNOS5_GPIO_BASE0 + 0x0220, + EXYNOS5_GPY5 = EXYNOS5_GPIO_BASE0 + 0x0240, + EXYNOS5_GPY6 = EXYNOS5_GPIO_BASE0 + 0x0260, + + EXYNOS5_GPX0 = EXYNOS5_GPIO_BASE0 + 0x0c00, + EXYNOS5_GPX1 = EXYNOS5_GPIO_BASE0 + 0x0c20, + EXYNOS5_GPX2 = EXYNOS5_GPIO_BASE0 + 0x0c40, + EXYNOS5_GPX3 = EXYNOS5_GPIO_BASE0 + 0x0c60, + + /* base == EXYNOS_GPIO_BASE1 */ + EXYNOS5_GPE0 = EXYNOS5_GPIO_BASE1 + 0x0000, + EXYNOS5_GPE1 = EXYNOS5_GPIO_BASE1 + 0x0020, + + EXYNOS5_GPF0 = EXYNOS5_GPIO_BASE1 + 0x0040, + EXYNOS5_GPF1 = EXYNOS5_GPIO_BASE1 + 0x0060, + + EXYNOS5_GPG0 = EXYNOS5_GPIO_BASE1 + 0x0080, + EXYNOS5_GPG1 = EXYNOS5_GPIO_BASE1 + 0x00a0, + EXYNOS5_GPG2 = EXYNOS5_GPIO_BASE1 + 0x00c0, + + EXYNOS5_GPH0 = EXYNOS5_GPIO_BASE1 + 0x00e0, + EXYNOS5_GPH1 = EXYNOS5_GPIO_BASE1 + 0x0100, + + /* base == EXYNOS_GPIO_BASE2 */ + EXYNOS5_GPV0 = EXYNOS5_GPIO_BASE2 + 0x0000, + EXYNOS5_GPV1 = EXYNOS5_GPIO_BASE2 + 0x0020, + EXYNOS5_GPV2 = EXYNOS5_GPIO_BASE2 + 0x0060, + EXYNOS5_GPV3 = EXYNOS5_GPIO_BASE2 + 0x0080, + EXYNOS5_GPV4 = EXYNOS5_GPIO_BASE2 + 0x00c0, + + /* base == EXYNOS_GPIO_BASE3 */ + EXYNOS5_GPZ = EXYNOS5_GPIO_BASE3 + 0x0000, +}; + #endif

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Patch merged into coreboot/master: 2323f35 google/snow: fix coding style
by gerrit＠coreboot.org 07 Mar '13

07 Mar '13

the following patch was just integrated into master: commit 2323f3551fe630e33f7ef59f1309db56956af5d4 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Mar 6 15:56:14 2013 -0800 google/snow: fix coding style cosmetics Change-Id: Iea33768d901641861aa7b2c76af8753a848f584d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2601 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Build-Tested: build bot (Jenkins) at Thu Mar 7 01:20:01 2013, giving +1 See http://review.coreboot.org/2601 for details. -gerrit

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Patch merged into coreboot/master: 0f4c0e2 src/arch/x86/boot/acpigen.c: Small coding style and comment fixes
by gerrit＠coreboot.org 07 Mar '13

07 Mar '13

the following patch was just integrated into master: commit 0f4c0e2669f76bf1081bf13019bc664b4f0e6b38 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Feb 22 12:33:08 2013 +0100 src/arch/x86/boot/acpigen.c: Small coding style and comment fixes While reading through the file fix some spotted errors like indentation, locution(?), capitalization and missing full stops. Change-Id: Id435b4750e329b06a9b36c1df2c39d2038a09b18 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2484 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Sat Feb 23 09:42:39 2013, giving +1 Reviewed-By: Marc Jones <marc.jones(a)se-eng.com> at Thu Mar 7 01:07:43 2013, giving +2 See http://review.coreboot.org/2484 for details. -gerrit

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New patch to review for coreboot: 99e484f google/snow: fix coding style
by Stefan Reinauer 07 Mar '13

07 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2601 -gerrit commit 99e484f98420d39d5a9b8f20e2d0de01dd00fa1e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Mar 6 15:56:14 2013 -0800 google/snow: fix coding style cosmetics Change-Id: Iea33768d901641861aa7b2c76af8753a848f584d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/google/snow/romstage.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 8de4381..83d5105 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -51,7 +51,8 @@ static int board_wakeup_permitted(void) } #endif -static void initialize_s5p_mshc(void) { +static void initialize_s5p_mshc(void) +{ /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ if (clock_set_mshci(PERIPH_ID_SDMMC0)) printk(BIOS_CRIT, "Failed to set clock for SDMMC0.\n"); @@ -69,9 +70,9 @@ static void initialize_s5p_mshc(void) { static void graphics(void) { - exynos_pinmux_config(PERIPH_ID_DPHPD, 0); } + void main(void) { struct mem_timings *mem;

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New patch to review for coreboot: ca10347 Revert "ARMv7: Simplify div64"
by David Hendricks 06 Mar '13

06 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2600 -gerrit commit ca10347d23dc11e0873279cba6dfcd194930fef3 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 7 00:58:10 2013 +0100 Revert "ARMv7: Simplify div64" This reverts commit 1cd616082100f47dc2d6d73669c6aa2e5eb039ad Division bites us again. I don't know how or why, but printk() seems to break (again) with this patch. I'm surprised we didn't encounter problems earlier on... Change-Id: I81cb9f20879f5eb73a76e1af47b96a68d1e81dc8 TODO: Find a better solution for div64. This one is too painful, but seems necessary for now (and sort-of works with our vtxprintf hack). --- src/arch/armv7/include/div64.h | 186 +++++++++++++++++++++++++++++++++++++++- src/arch/armv7/lib/Makefile.inc | 2 - src/arch/armv7/lib/div64.S | 9 +- 3 files changed, 190 insertions(+), 7 deletions(-) diff --git a/src/arch/armv7/include/div64.h b/src/arch/armv7/include/div64.h index 9c3c29a..5baed2b 100644 --- a/src/arch/armv7/include/div64.h +++ b/src/arch/armv7/include/div64.h @@ -3,7 +3,12 @@ #ifndef __ASM_ARM_DIV64 #define __ASM_ARM_DIV64 +//#include <asm/system.h> +//#include <linux/types.h> +// FIXME + #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" +#define __LINUX_ARM_ARCH__ 7 /* * The semantics of do_div() are: @@ -29,7 +34,7 @@ #define __xh "r1" #endif -#define do_div(n, base) \ +#define __do_div_asm(n, base) \ ({ \ register unsigned int __base asm("r4") = base; \ register unsigned long long __n asm("r0") = n; \ @@ -46,4 +51,183 @@ n = __res; \ __rem; \ }) + +#if __GNUC__ < 4 + +/* + * gcc versions earlier than 4.0 are simply too problematic for the + * optimized implementation below. First there is gcc PR 15089 that + * tend to trig on more complex constructs, spurious .global __udivsi3 + * are inserted even if none of those symbols are referenced in the + * generated code, and those gcc versions are not able to do constant + * propagation on long long values anyway. + */ +#define do_div(n, base) __do_div_asm(n, base) + +#elif __GNUC__ >= 4 + +//#include <asm/bug.h> + +/* + * If the divisor happens to be constant, we determine the appropriate + * inverse at compile time to turn the division into a few inline + * multiplications instead which is much faster. And yet only if compiling + * for ARMv4 or higher (we need umull/umlal) and if the gcc version is + * sufficiently recent to perform proper long long constant propagation. + * (It is unfortunate that gcc doesn't perform all this internally.) + */ +#define do_div(n, base) \ +({ \ + unsigned int __r, __b = (base); \ + if (!__builtin_constant_p(__b) || __b == 0 || \ + (__LINUX_ARM_ARCH__ < 4 && (__b & (__b - 1)) != 0)) { \ + /* non-constant divisor (or zero): slow path */ \ + __r = __do_div_asm(n, __b); \ + } else if ((__b & (__b - 1)) == 0) { \ + /* Trivial: __b is constant and a power of 2 */ \ + /* gcc does the right thing with this code. */ \ + __r = n; \ + __r &= (__b - 1); \ + n /= __b; \ + } else { \ + /* Multiply by inverse of __b: n/b = n*(p/b)/p */ \ + /* We rely on the fact that most of this code gets */ \ + /* optimized away at compile time due to constant */ \ + /* propagation and only a couple inline assembly */ \ + /* instructions should remain. Better avoid any */ \ + /* code construct that might prevent that. */ \ + unsigned long long __res, __x, __t, __m, __n = n; \ + unsigned int __c, __p, __z = 0; \ + /* preserve low part of n for reminder computation */ \ + __r = __n; \ + /* determine number of bits to represent __b */ \ + __p = 1 << __div64_fls(__b); \ + /* compute __m = ((__p << 64) + __b - 1) / __b */ \ + __m = (~0ULL / __b) * __p; \ + __m += (((~0ULL % __b + 1) * __p) + __b - 1) / __b; \ + /* compute __res = __m*(~0ULL/__b*__b-1)/(__p << 64) */ \ + __x = ~0ULL / __b * __b - 1; \ + __res = (__m & 0xffffffff) * (__x & 0xffffffff); \ + __res >>= 32; \ + __res += (__m & 0xffffffff) * (__x >> 32); \ + __t = __res; \ + __res += (__x & 0xffffffff) * (__m >> 32); \ + __t = (__res < __t) ? (1ULL << 32) : 0; \ + __res = (__res >> 32) + __t; \ + __res += (__m >> 32) * (__x >> 32); \ + __res /= __p; \ + /* Now sanitize and optimize what we've got. */ \ + if (~0ULL % (__b / (__b & -__b)) == 0) { \ + /* those cases can be simplified with: */ \ + __n /= (__b & -__b); \ + __m = ~0ULL / (__b / (__b & -__b)); \ + __p = 1; \ + __c = 1; \ + } else if (__res != __x / __b) { \ + /* We can't get away without a correction */ \ + /* to compensate for bit truncation errors. */ \ + /* To avoid it we'd need an additional bit */ \ + /* to represent __m which would overflow it. */ \ + /* Instead we do m=p/b and n/b=(n*m+m)/p. */ \ + __c = 1; \ + /* Compute __m = (__p << 64) / __b */ \ + __m = (~0ULL / __b) * __p; \ + __m += ((~0ULL % __b + 1) * __p) / __b; \ + } else { \ + /* Reduce __m/__p, and try to clear bit 31 */ \ + /* of __m when possible otherwise that'll */ \ + /* need extra overflow handling later. */ \ + unsigned int __bits = -(__m & -__m); \ + __bits |= __m >> 32; \ + __bits = (~__bits) << 1; \ + /* If __bits == 0 then setting bit 31 is */ \ + /* unavoidable. Simply apply the maximum */ \ + /* possible reduction in that case. */ \ + /* Otherwise the MSB of __bits indicates the */ \ + /* best reduction we should apply. */ \ + if (!__bits) { \ + __p /= (__m & -__m); \ + __m /= (__m & -__m); \ + } else { \ + __p >>= __div64_fls(__bits); \ + __m >>= __div64_fls(__bits); \ + } \ + /* No correction needed. */ \ + __c = 0; \ + } \ + /* Now we have a combination of 2 conditions: */ \ + /* 1) whether or not we need a correction (__c), and */ \ + /* 2) whether or not there might be an overflow in */ \ + /* the cross product (__m & ((1<<63) | (1<<31))) */ \ + /* Select the best insn combination to perform the */ \ + /* actual __m * __n / (__p << 64) operation. */ \ + if (!__c) { \ + asm ( "umull %Q0, %R0, %1, %Q2\n\t" \ + "mov %Q0, #0" \ + : "=&r" (__res) \ + : "r" (__m), "r" (__n) \ + : "cc" ); \ + } else if (!(__m & ((1ULL << 63) | (1ULL << 31)))) { \ + __res = __m; \ + asm ( "umlal %Q0, %R0, %Q1, %Q2\n\t" \ + "mov %Q0, #0" \ + : "+&r" (__res) \ + : "r" (__m), "r" (__n) \ + : "cc" ); \ + } else { \ + asm ( "umull %Q0, %R0, %Q1, %Q2\n\t" \ + "cmn %Q0, %Q1\n\t" \ + "adcs %R0, %R0, %R1\n\t" \ + "adc %Q0, %3, #0" \ + : "=&r" (__res) \ + : "r" (__m), "r" (__n), "r" (__z) \ + : "cc" ); \ + } \ + if (!(__m & ((1ULL << 63) | (1ULL << 31)))) { \ + asm ( "umlal %R0, %Q0, %R1, %Q2\n\t" \ + "umlal %R0, %Q0, %Q1, %R2\n\t" \ + "mov %R0, #0\n\t" \ + "umlal %Q0, %R0, %R1, %R2" \ + : "+&r" (__res) \ + : "r" (__m), "r" (__n) \ + : "cc" ); \ + } else { \ + asm ( "umlal %R0, %Q0, %R2, %Q3\n\t" \ + "umlal %R0, %1, %Q2, %R3\n\t" \ + "mov %R0, #0\n\t" \ + "adds %Q0, %1, %Q0\n\t" \ + "adc %R0, %R0, #0\n\t" \ + "umlal %Q0, %R0, %R2, %R3" \ + : "+&r" (__res), "+&r" (__z) \ + : "r" (__m), "r" (__n) \ + : "cc" ); \ + } \ + __res /= __p; \ + /* The reminder can be computed with 32-bit regs */ \ + /* only, and gcc is good at that. */ \ + { \ + unsigned int __res0 = __res; \ + unsigned int __b0 = __b; \ + __r -= __res0 * __b0; \ + } \ + /* BUG_ON(__r >= __b || __res * __b + __r != n); */ \ + n = __res; \ + } \ + __r; \ +}) + +/* our own fls implementation to make sure constant propagation is fine */ +#define __div64_fls(bits) \ +({ \ + unsigned int __left = (bits), __nr = 0; \ + if (__left & 0xffff0000) __nr += 16, __left >>= 16; \ + if (__left & 0x0000ff00) __nr += 8, __left >>= 8; \ + if (__left & 0x000000f0) __nr += 4, __left >>= 4; \ + if (__left & 0x0000000c) __nr += 2, __left >>= 2; \ + if (__left & 0x00000002) __nr += 1; \ + __nr; \ +}) + +#endif + #endif diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 0e81c99..388864a 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -2,8 +2,6 @@ bootblock-y += syslib.c bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c bootblock-y += cache_v7.c bootblock-y += cache-cp15.c -bootblock-y += div0.c -bootblock-y += div64.S romstage-y += cache_v7.c romstage-y += cache-cp15.c diff --git a/src/arch/armv7/lib/div64.S b/src/arch/armv7/lib/div64.S index 41a0949..44edf48 100644 --- a/src/arch/armv7/lib/div64.S +++ b/src/arch/armv7/lib/div64.S @@ -13,7 +13,8 @@ */ // FIXME -#define __ARM_ARCH__ 7 +//#include <linux/linkage.h> +#define __LINUX_ARM_ARCH__ 7 #ifdef __ARMEB__ #define xh r0 @@ -64,7 +65,7 @@ __do_div64: @ The aligned divisor is stored in yl preserving the original. @ The bit position is stored in ip. -#if __ARM_ARCH__ >= 5 +#if __LINUX_ARM_ARCH__ >= 5 clz yl, r4 clz ip, xh @@ -124,7 +125,7 @@ __do_div64: @ We still have remainer bits in the low part. Bring them up. -#if __ARM_ARCH__ >= 5 +#if __LINUX_ARM_ARCH__ >= 5 clz xh, xl @ we know xh is zero here so... add xh, xh, #1 @@ -151,7 +152,7 @@ __do_div64: 8: @ Division by a power of 2: determine what that divisor order is @ then simply shift values around -#if __ARM_ARCH__ >= 5 +#if __LINUX_ARM_ARCH__ >= 5 clz ip, r4 rsb ip, ip, #31

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Patch merged into coreboot/master: d59fc53 Fix build by adding `cbmem.c` to `COLLECT_TIMESTAMPS`
by gerrit＠coreboot.org 06 Mar '13

06 Mar '13

the following patch was just integrated into master: commit d59fc5340ea2fc12f6cf98a2e2166435869f0d3c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 28 00:32:25 2013 +0200 Fix build by adding `cbmem.c` to `COLLECT_TIMESTAMPS` A board without HAVE_ACPI_RESUME did not build with COLLECT_TIMESTAMPS enabled as `cbmem.c` was not built. Change-Id: I9c8b575d445ac566a2ec533d73080bcccc3dfbca Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/2549 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Thu Feb 28 10:36:33 2013, giving +1 Reviewed-By: Marc Jones <marc.jones(a)se-eng.com> at Thu Mar 7 00:48:58 2013, giving +2 See http://review.coreboot.org/2549 for details. -gerrit

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coreboot March 2013