coreboot March 2013

coreboot@coreboot.org

46 participants
782 discussions

ASRock E350M1: `PCI: Static device PCI: 00:04.0 not found, disabling it.` despite vendor BIOS showing it
by Paul Menzel 08 Mar '13

08 Mar '13

Dear coreboot folks, the ASRock E350M1 [1] still has some issues and with the changes committed since May 2012 new ones have been introduced too and I am going to report them to the list one by one starting from the first issues reported in the coreboot log. The following is reported with the vendor BIOS [2]. -[0000:00]-+-00.0 1022:1510 +-01.0 1002:9802 +-01.1 1002:1314 +-04.0-[01]-- +-11.0 1002:4391 +-12.0 1002:4397 +-12.2 1002:4396 +-13.0 1002:4397 +-13.2 1002:4396 +-14.0 1002:4385 +-14.1 1002:439c +-14.2 1002:4383 +-14.3 1002:439d +-14.4-[02]-- +-14.5 1002:4399 +-15.0-[03]-- +-15.1-[04]----00.0 10ec:8168 +-16.0 1002:4397 +-16.2 1002:4396 +-18.0 1022:1700 +-18.1 1022:1701 +-18.2 1022:1702 +-18.3 1022:1703 +-18.4 1022:1704 +-18.5 1022:1718 +-18.6 1022:1716 \-18.7 1022:1719 Running the board with coreboot (based on fdfd89f2 with [4] applied and debug messages) [3] PCI device 0:04.0 is not detected. $ lspci -tnvv -[0000:00]-+-00.0 1022:1510 +-01.0 1002:9802 +-01.1 1002:1314 +-11.0 1002:4390 +-12.0 1002:4397 +-12.2 1002:4396 +-13.0 1002:4397 +-13.2 1002:4396 +-14.0 1002:4385 +-14.2 1002:4383 +-14.3 1002:439d +-14.4-[01]-- +-14.5 1002:4399 +-18.0 1022:1700 +-18.1 1022:1701 +-18.2 1022:1702 +-18.3 1022:1703 +-18.4 1022:1704 +-18.5 1022:1718 +-18.6 1022:1716 \-18.7 1022:1719 This problem has been present since the beginning (at least confirmed with an image built from commit bdca153. $ git show bdca153 commit bdca15337bc9337f399b43290dc74cb598c5ec4d Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon May 21 14:01:52 2012 +0200 libpayload: Remove orphaned delay from USB mass storage The coreboot log (attached) contains the following. […] Mainboard E350M1 Enable. scan_static_bus for Root Device setup_bsp_ramtop, TOP MEM: msr.lo = 0xe0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x1f000000, msr.hi = 0x00000002 setup_uma_memory: uma size 0x18000000, memory start 0xc8000000 CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled CPU_CLUSTER: 0 scanning... AP siblings=1 CPU: APIC: 00 enabled CPU: APIC: 01 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [1022/1510] ops PCI: 00:00.0 [1022/1510] enabled PCI: 00:01.0 [1002/9802] enabled PCI: 00:01.1 [1002/1314] enabled PCI: Static device PCI: 00:04.0 not found, disabling it. sb800_enable SB800 - Smbus.c - alink_ab_indx - Start. SB800 - Smbus.c - alink_ab_indx - End. PCI: 00:11.0 [1002/4390] enabled sb800_enable PCI: 00:12.0 [1002/4397] ops PCI: 00:12.0 [1002/4397] enabled sb800_enable PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled sb800_enable PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb800_enable PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled […] Any idea what might be wrong. The vendor BIOS says it is the following device. 00:04.0 PCI bridge: Advanced Micro Devices [AMD] Family 14h Processor Root Port (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 00001000-00001fff Memory behind bridge: d0100000-d02fffff Prefetchable memory behind bridge: 00000000d0300000-00000000d04fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #247, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed unknown, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise- Slot #4, PowerLimit 75.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd- DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device 1234 Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Kernel driver in use: pcieport 00: 22 10 12 15 07 00 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 11 11 00 00 20: 10 d0 20 d0 31 d0 41 d0 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 10 00 Any ideas are appreciated. Thanks, Paul [1] http://www.coreboot.org/ASRock_E350M1 [2] http://www.coreboot.org/File:ASRock_E350M1_info_dump.tar.bz2 [3] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=fdfd89f21326f13… [4] http://review.coreboot.org/#/c/2536/

3 4

Re: [coreboot] Git
by Peter Stuge 08 Mar '13

08 Mar '13

Hi Wolfgang, Wolfgang Kamp - datakamp wrote: > I'm struggling with git to send a commit. The Git show command > shows what I really want to commit. That's good, it means that you have created a commit locally with what the desired changes. Before pushing the only thing to check is that there are no other commits on the same branch. > The Git log origin/master command shows a lot of commit messages > for every patch ever done. That's correct. git log shows the history going *back* in time starting from the point that you specify. When you specify origin/master you get all commits leading up to your current origin/master, which is a so-called remote tracking branch, within your repository. This branch should be left read-only, except when running git fetch or git pull to make it up-to-date with what is in the public repository. Please run instead: git log origin/master..HEAD Or shorter: git log origin/master.. You can leave out HEAD if you like, but you must include the two dots. Instead of specifying a single point like before, these commands specify a range of commits. When you specify this range you'll be shown only the commits in HEAD which are based on origin/master. HEAD means "the last commit on the current branch" > I think the git push origin command will send all the commit > history and not only my commit. No, git only sends new commits. So if the above log origin/master.. command only shows the same commit as git show, then that is the only thing that will be sent. A brief explanation of the git data model, maybe it's already known: Files are called blobs, directories are called trees. Trees contain blobs and other trees. There is a top-level tree corresponding to the root directory of the repo. Blobs and trees are identified solely by their hash, which is calculated from their contents. A commit consists of only: The top-level tree hash Zero or more parent commit hashes Author name, email and timestamp Committer name, email and timestamp The commit message [optional PGP signature] Commits are also identified by a hash calculated from their contents. If any of the data in the commit (a blob, which bubbles up to the root tree, or the commit timestamp, or the commit message) changes, then the commit id also changes. Commits can be said to be immutable, it's not really possible to change a commit. It is however possible to *replace* it. Commits are organized into branches. A branch is just a nickname for some particular commit, but with special semantics: Whenever a new commit is created, the current branch is changed to refer to the new commit. A tag is also a nickname for a commit, but tags must and do never change. If a commit has zero parents it is generally the very first commit in the repository. It's theoretically possible to have multiple commits like that on different branches, but that's a rare occurance. If a commit has more than one parent it is called a merge commit, because it joins together multiple branches. Most commits have just one parent. Try the command: git show --pretty=raw Or maybe even better: git log --pretty=raw ..in your own repo. Compare parent lines with the following commit lines. You should see how the commits chain together, forming a DAG, direct acyclic graph, similar to a linked list going back in time. Note that the diff, ie. the changes in all files, isn't stored anywhere by git. The diff is generated each time by comparing which blobs changed between two root trees. Creating a branch is cheap, fast, fun and easy. git branch $name $startingpoint $startingpoint is anything that identifies a commit; a branch name, a tag name, or a commit hash. The new branch is strictly local, like almost everything that you do with git. The command: git branch -a -v Shows -a(ll) branches in your repository -v(erbosely), meaning that you will see both your local branches and your "remote" or "remote tracking" branches. The remote branches are the for-reading-only ones like origin/master. You literally have a local copy of every commit in every branch that existed on the remote when you cloned or fetched/pulled last time. Verbose means that you are shown the abbreviated commit hash and the commit message summary for the commit that is HEAD of each branch. git fetch downloads new commits into your remote tracking branches but makes no changes to your local branches. git pull is by default: git fetch && git merge pull thus performs a merge of your current branch with the updated remote branch that it is based on. If you have created a new commit locally, and at the same time there are also new commits from the server, then your current branch and the remote branch are said to have diverged. git merge will in that case create a merge commit with two parents, namely your last commit and the last commit on the remote. We generally avoid merge commits in coreboot, so it's good to run: git pull --rebase instead of simply git pull. This amounts to: git fetch && git rebase So rebase, instead of merge. Rebasing is a lot of fun, it takes your local commits which you created based on the old origin/master and instead of merging it simply tries to re-apply (re-base) them on top of the latest state of origin/master. If something changed on the remote where you have made changes, you get a conflict which you will have to resolve somehow. (Merging can have conflicts too of course.) I hope that helps some.. Feel free to ask if you have other questions. I can recommend #git on irc.freenode.org as well as the book Pro Git available at http://git-scm.com/book and the lighter weight Git reference site at http://gitref.org/ //Peter

1 2

New patch to review for coreboot: 8a1bfcf ASUS M5A88-V: Kconfig: Fix mainboard model name
by Paul Menzel 08 Mar '13

08 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2613 -gerrit commit 8a1bfcf3fca7fec02d4026b6ee4c960c673dc128 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 8 12:10:16 2013 +0100 ASUS M5A88-V: Kconfig: Fix mainboard model name Despite everywhere the model name M5A88-V is used, in Kconfig the string M5A88PM-V is used. Searching for that model string on the WWW does not return anything which is unrelated to coreboot, so change that string to M5A88-V. Change-Id: I25cf9d4a5fc3f9b9356e8616452066ebf873f44c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asus/m5a88-v/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index 3ac4f77..5318977 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -37,7 +37,7 @@ config APIC_ID_OFFSET config MAINBOARD_PART_NUMBER string - default "M5A88PM-V" + default "M5A88-V" config HW_MEM_HOLE_SIZEK hex

1 0

Patch set updated for coreboot: a5e76f5 AMD CIMx SB800 boards: platform_cfg.h: Hook up Kconfig SATA Mode choice
by Paul Menzel 08 Mar '13

08 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2610 -gerrit commit a5e76f5789ca8efbf01010d2071cd49570ec7130 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 3 10:56:15 2013 +0100 AMD CIMx SB800 boards: platform_cfg.h: Hook up Kconfig SATA Mode choice Currently for Advansus A785E-I, ASRock E350M1 and ASUS M5A88-V despite what is chosen in Kconfig »Chipset« menu item, $ more .config […] # CONFIG_ENABLE_IDE_COMBINED_MODE is not set CONFIG_IDE_COMBINED_MODE=0x1 # CONFIG_SB800_SATA_IDE is not set CONFIG_SB800_SATA_AHCI=y # CONFIG_SB800_SATA_RAID is not set CONFIG_SB800_SATA_MODE=0x2 […] the SATA controller is put into IDE mode. $ lspci -nn | grep SATA 00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [IDE mode] [1002:4390] (rev 40) Commit »sb800: Add sata ahci/raid mode kconfig option« (d4a0e7d0) [1] added the options above to configure the mode using Kconfig and the some SB800 boards were adapted already. For example commit »persimmon: sb800 sata mode configure update« (1386fa74) [2] did so for AMD Persimmon. Doing the same by assigning the Kconfig variable to the value in `platform_cfg.h` hooks this up to the three remaining boards listed above. The patch is successfully tested with the ASRock E350M1. $ lspci -nn | grep SATA 00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] (rev 40) [1] http://review.coreboot.org/225 [2] http://review.coreboot.org/227 Change-Id: I227257e2c8f04f18c27ff00fe62d42e372de67e4 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/advansus/a785e-i/platform_cfg.h | 2 +- src/mainboard/asrock/e350m1/platform_cfg.h | 2 +- src/mainboard/asus/m5a88-v/platform_cfg.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h index 9f70dcc..f1eb9f5 100644 --- a/src/mainboard/advansus/a785e-i/platform_cfg.h +++ b/src/mainboard/advansus/a785e-i/platform_cfg.h @@ -101,7 +101,7 @@ * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ -#define SATA_MODE NATIVE_IDE_MODE +#define SATA_MODE CONFIG_SB800_SATA_MODE /** * @brief INCHIP Sata IDE Controller Mode diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 389e7db..24a66dd 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -103,7 +103,7 @@ * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ -#define SATA_MODE NATIVE_IDE_MODE +#define SATA_MODE CONFIG_SB800_SATA_MODE /** * @brief INCHIP Sata IDE Controller Mode diff --git a/src/mainboard/asus/m5a88-v/platform_cfg.h b/src/mainboard/asus/m5a88-v/platform_cfg.h index 9f70dcc..f1eb9f5 100644 --- a/src/mainboard/asus/m5a88-v/platform_cfg.h +++ b/src/mainboard/asus/m5a88-v/platform_cfg.h @@ -101,7 +101,7 @@ * @brief INCHIP Sata Controller Mode * NOTE: DO NOT ALLOW SATA & IDE use same mode */ -#define SATA_MODE NATIVE_IDE_MODE +#define SATA_MODE CONFIG_SB800_SATA_MODE /** * @brief INCHIP Sata IDE Controller Mode

1 0

Git
by Wolfgang Kamp - datakamp 08 Mar '13

08 Mar '13

Hi, I'm struggling with git to send a commit. The Git show command shows what I really want to commit. The Git log origin/master command shows a lot of commit messages for every patch ever done. But I think the git push origin command will send all the commit history and not only my commit. What is the solution for that behavior? Thanks, Wolfgang

1 0

Patch set updated for coreboot: 523405b Intel Panther Point USB3 initalization
by Marc Jones 08 Mar '13

08 Mar '13

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2519 -gerrit commit 523405bb98f3ea267c2b2c80505aee1c27b4c146 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Nov 13 15:07:45 2012 -0700 Intel Panther Point USB3 initalization Add PEI updates and ACPI updates for supporting EHCI to XHCI USB port support. Change-Id: I9ace68a1b3950771aefb96c1319b8899291edd9a Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/northbridge/intel/sandybridge/pei_data.h | 12 ++++- src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 14 +++++ src/southbridge/intel/bd82x6x/acpi/pch.asl | 23 ++++---- src/southbridge/intel/bd82x6x/acpi/usb.asl | 69 ++++++++++++++++++++++++ src/southbridge/intel/bd82x6x/early_usb.c | 9 ++++ src/southbridge/intel/bd82x6x/nvs.h | 4 +- src/southbridge/intel/bd82x6x/pch.h | 7 ++- src/southbridge/intel/bd82x6x/smihandler.c | 14 +++++ 8 files changed, 140 insertions(+), 12 deletions(-) diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 8c907c1..396dc8a 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -30,8 +30,16 @@ #ifndef PEI_DATA_H #define PEI_DATA_H +typedef struct { + uint16_t mode; // 0: Disable; 1: Enable, 2: Auto, 3: Smart Auto + uint16_t hs_port_switch_mask; // 4 bit mask, 1: switchable, 0: not switchable + uint16_t preboot_support; // 0: No xHCI preOS driver; 1: xHCI preOS driver + uint16_t xhci_streams; // 0: Disable; 1: Enable +} pch_usb3_controller_settings; + typedef void (*tx_byte_func)(unsigned char byte); -#define PEI_VERSION 4 +#define PEI_VERSION 5 + struct pei_data { uint32_t pei_version; @@ -92,6 +100,8 @@ struct pei_data * < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude) */ uint16_t usb_port_config[16][3]; + /* See the usb3 struct above for details */ + pch_usb3_controller_settings usb3; /* SPD data array for onboard RAM. Specify address 0xf0, * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in * spd_address for a given "DIMM". diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 2fe092d..99edc31 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -136,6 +136,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) GTF2, 56, // 0xa4 - GTF task file buffer for port 2 IDEM, 8, // 0xab - IDE mode (compatible / enhanced) IDET, 8, // 0xac - IDE + /* XHCI */ + Offset (0xb2), + XHCI, 8, /* IGD OpRegion */ Offset (0xb4), ASLB, 32, // 0xb4 - IGD OpRegion Base Address @@ -223,6 +226,17 @@ Method (S3GD) Store (Zero, \S33G) } +/* Set XHCI Mode enable */ +Method (XHCE) +{ + Store (One, \XHCI) +} + +/* Set XHCI Mode disable */ +Method (XHCD) +{ + Store (Zero, \XHCI) +} External (\_TZ.THRM) External (\_TZ.SKIN) diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 8632ad8..2f75fdc 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -245,7 +245,7 @@ Scope(\) // PCI Express Ports 0:1c.x #include "pcie.asl" -// USB 0:1d.0 and 0:1a.0 +// USB EHCI 0:1d.0 and 0:1a.0, XHCI 0:14.0 #include "usb.asl" // LPC Bridge 0:1f.0 @@ -259,17 +259,22 @@ Scope(\) Method (_OSC, 4) { - /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + /* Check for XHCI */ + If (LEqual (Arg0, ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) { - /* Let OS control everything */ - Return (Arg3) + Return (^XHC.POSC(Arg1, Arg2, Arg3)) } - Else + + /* Check for PCIe */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - /* Unrecognized UUID */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + /* Let OS control everything */ Return (Arg3) } + + /* Else Return Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } diff --git a/src/southbridge/intel/bd82x6x/acpi/usb.asl b/src/southbridge/intel/bd82x6x/acpi/usb.asl index cf3e6a0..f19d368 100644 --- a/src/southbridge/intel/bd82x6x/acpi/usb.asl +++ b/src/southbridge/intel/bd82x6x/acpi/usb.asl @@ -89,3 +89,72 @@ Device (EHC2) } } +Device (XHC) +{ + Name(_ADR, 0x00140000) + OperationRegion(XDEV, PCI_Config, 0, 256) + Field(XDEV, DWordAcc, NoLock, Preserve) + { + Offset(0xD0), + X2PR, 32, // XUSB2PR + PRM2, 32, // XUSB2PRM + SSEN, 32, // USB3_PSSEN + RPM3, 32, // USB3PRM + XPRT, 32, // XHCI Ports + } + + Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + + Method(POSC,3,Serialized) + { + // Create DWord field from the Capabilities Buffer + CreateDWordField(Arg2,0,CDW1) + + // Check revision + If(LNotEqual(Arg1,One)) { + // Set unknown revision bit + Or(CDW1,0x8,CDW1) + } + + // Set failure if xHCI is disabled by coreboot + If(LEqual(XHCI, 0)) { + Or(CDW1,0x2,CDW1) + } + + // Query flag clear and xHCI in auto mode + If(LAnd(LNot(And(CDW1,0x1)),LOr(LEqual(XHCI ,2), LEqual(XHCI ,3)))) { + Store ("XHCI Switch", Debug) + Store(Zero, Local0) + And(XPRT, 0x3, Local0) + If(LOr(LEqual(Local0, 0), LEqual(Local0, 1))) { + Store(0xF, Local1) + } + ElseIf(LEqual(Local0, 2)) { + Store(0x3, Local1) + } + ElseIf(LEqual(Local0, 3)) { + Store(Zero, Local1) + } + And(RPM3, 0xFFFFFFF0, Local0) + Or(Local0, Local1, RPM3) + And(PRM2, 0xFFFFFFF0, Local0) + Or(Local0, Local1, PRM2) + And(SSEN, 0xFFFFFFF0, Local0) + Or(Local0, Local1, SSEN) + And(X2PR, 0xFFFFFFF0, Local0) + Or(Local0, Local1, X2PR) + } + Return(Arg2) + } + + // Leave USB ports on for to allow Wake from USB + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } +} diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 95906e3..66970f1 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -27,6 +27,7 @@ #define PCH_EHCI1_TEMP_BAR0 0xe8000000 #define PCH_EHCI2_TEMP_BAR0 0xe8000400 +#define PCH_XHCI_TEMP_BAR0 0xe8001000 /* * Setup USB controller MMIO BAR to prevent the @@ -39,6 +40,7 @@ void enable_usb_bar(void) { device_t usb0 = PCH_EHCI1_DEV; device_t usb1 = PCH_EHCI2_DEV; + device_t usb3 = PCH_XHCI_DEV; u32 cmd; /* USB Controller 1 */ @@ -54,4 +56,11 @@ void enable_usb_bar(void) cmd = pci_read_config32(usb1, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb1, PCI_COMMAND, cmd); + + /* USB3 Controller */ + pci_write_config32(usb3, PCI_BASE_ADDRESS_0, + PCH_XHCI_TEMP_BAR0); + cmd = pci_read_config32(usb3, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(usb3, PCI_COMMAND, cmd); } diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index b8506d4..7b8b6c9 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -113,7 +113,9 @@ typedef struct { u8 gtf2[7]; u8 idem; u8 idet; - u8 rsvd11[7]; + u8 rsvd11[6]; + /* XHCI */ + u8 xhci; /* IGD OpRegion (not implemented yet) */ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ u8 ibtt; /* 0xb8 - IGD boot type */ diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 1211671..f0f6c1b 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -95,6 +95,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) +#define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) #define PCH_PCIE_DEV_SLOT 28 @@ -365,6 +366,8 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define D22IP_IDERIP 8 /* IDE-R Pin */ #define D22IP_MEI2IP 4 /* MEI #2 Pin */ #define D22IP_MEI1IP 0 /* MEI #1 Pin */ +#define D20IP 0x3128 /* 32bit */ +#define D20IP_XHCIIP 0 #define D31IR 0x3140 /* 16bit */ #define D30IR 0x3142 /* 16bit */ #define D29IR 0x3144 /* 16bit */ @@ -373,6 +376,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define D26IR 0x314c /* 16bit */ #define D25IR 0x3150 /* 16bit */ #define D22IR 0x315c /* 16bit */ +#define D20IR 0x3160 /* 16bit */ #define OIC 0x31fe /* 16bit */ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 @@ -392,7 +396,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define CG 0x341c /* 32bit */ /* Function Disable 1 RCBA 0x3418 */ -#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)|(1 << 27)) +#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) #define PCH_DISABLE_P2P (1 << 1) #define PCH_DISABLE_SATA1 (1 << 2) #define PCH_DISABLE_SMBUS (1 << 3) @@ -403,6 +407,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) #define PCH_DISABLE_THERMAL (1 << 24) #define PCH_DISABLE_SATA2 (1 << 25) +#define PCH_DISABLE_XHCI (1 << 27) /* Function Disable 2 RCBA 0x3428 */ #define PCH_DISABLE_KT (1 << 4) diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 420c5db..a1248d6 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -326,6 +326,17 @@ static void southbridge_gate_memory_reset(void) outl(reg32, gpiobase + GP_LVL2); } +static void xhci_sleep(u8 slp_typ) +{ + u32 reg32; + + if (slp_typ == SLP_TYP_S5) { + reg32 = pcie_read_config32(PCH_XHCI_DEV, 0x74); + reg32 |= (1 << 8 | 0x03 ); + pcie_write_config32(PCH_XHCI_DEV, 0x74, reg32); + } +} + static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) { u8 reg8; @@ -353,6 +364,9 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = (reg32 >> 10) & 7; + if(smm_get_gnvs()->xhci) + xhci_sleep(slp_typ); + /* Do any mainboard sleep handling */ tseg_relocate((void **)&mainboard_sleep); if (mainboard_sleep)

1 0

Patch merged into coreboot/master: c2f2bd0 AGESA: Fix CR0_PE bit define
by gerrit＠coreboot.org 08 Mar '13

08 Mar '13

the following patch was just integrated into master: commit c2f2bd0a6d00a7f8df4005f148f67373db6d26d6 Author: Konstantin Aladyshev <aladyshev(a)nicevt.ru> Date: Wed Mar 6 22:13:42 2013 +0400 AGESA: Fix CR0_PE bit define AGESA code has wrong definition of CR0_PE bit (1 instead of 0). PE [Protected Mode Enable] is 0 bit in CR0 register (If PE=1, system is in protected mode, else system is in real mode) Bit 1 is MP [Monitor co-processor] (Controls interaction of WAIT/FWAIT instructions with TS flag in CR0) System uses CR0_PE define, but I didn't expect any consequences because of this bug. Change-Id: I54d9a8c0ee3af0a2e0267777036f227a9e05f3e1 Signed-off-by: Konstantin Aladyshev <aladyshev(a)nicevt.ru> Reviewed-on: http://review.coreboot.org/2591 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Wed Mar 6 19:38:43 2013, giving +1 Reviewed-By: Marc Jones <marc.jones(a)se-eng.com> at Wed Mar 6 19:53:01 2013, giving +2 See http://review.coreboot.org/2591 for details. -gerrit

1 0

Patch merged into coreboot/master: 4c1e906 Supermicro H8QGI: set up right frequency limits for memory controller
by gerrit＠coreboot.org 08 Mar '13

08 Mar '13

the following patch was just integrated into master: commit 4c1e906e36252db3361d7df4c3764b352f53e2f3 Author: Konstantin Aladyshev <aladyshev(a)nicevt.ru> Date: Wed Mar 6 21:39:40 2013 +0400 Supermicro H8QGI: set up right frequency limits for memory controller According to BKDG: "Memory controller (MCT) and DRAM controllers (DCTs) additions: • Support for 933 MHz (1866 MT/s) MEMCLK frequency." Change-Id: I6f307ce3fcb355d5445f1ea86def73a41b928a57 Signed-off-by: Konstantin Aladyshev <aladyshev(a)nicevt.ru> Reviewed-on: http://review.coreboot.org/2589 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Wed Mar 6 18:54:15 2013, giving +1 Reviewed-By: Marc Jones <marc.jones(a)se-eng.com> at Wed Mar 6 19:41:13 2013, giving +2 See http://review.coreboot.org/2589 for details. -gerrit

1 0

Patch merged into coreboot/master: 7fcbbb0 AGESA: Fix bug in AMD_DISABLE_STACK_FAMILY_HOOK_F15
by gerrit＠coreboot.org 08 Mar '13

08 Mar '13

the following patch was just integrated into master: commit 7fcbbb09fd788a9a1791c2abab96359ce960a2cc Author: Konstantin Aladyshev <aladyshev(a)nicevt.ru> Date: Wed Mar 6 19:58:38 2013 +0400 AGESA: Fix bug in AMD_DISABLE_STACK_FAMILY_HOOK_F15 _RDMSR instruction loads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX. The EDX register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. EDX:EAX = MSR[ECX] So bit 49 will be contained in EDX register. Buggy code instead of bit 49 (CombineCr0Cd) sets bit [49-32=17] (PfcStrideDis). PfcStrideDis bit disables stride prefetch generation. This leads to memory bandwidth loss. _________ Supermicro H8QGI board After applying this change i observed huge memory bandwidth increase in tests that runs on small amount of cores. But unfortunately it doesn't affect overall bandwidth results on 4P system with 48 cores. So i think that in this system leading limiting factor is AMD HT-ASSIST feature (Probe filter). But right now it is not working. System stucks in Linux boot. I have done some experiments and figured out that stuck happens when system have cores in compute unit (CU) other than CU with BSC (boot strap core). CU is two cores (primary and seconary) that shares some things (L2 cache, FPU ...) So with probe filter i can boot Linux with one (BSC) or two (BSC + secondary core in its CU) cores. And with this configuration i can see memory bandwidth on 1 core (or two cores) close to original bios. Change-Id: I5a95f5b753d600c70d3c93d36fecc687610c61cd Signed-off-by: Konstantin Aladyshev <aladyshev(a)nicevt.ru> Reviewed-on: http://review.coreboot.org/2588 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Wed Mar 6 18:21:11 2013, giving +1 Reviewed-By: Marc Jones <marc.jones(a)se-eng.com> at Wed Mar 6 19:38:50 2013, giving +2 See http://review.coreboot.org/2588 for details. -gerrit

1 0

Re: [coreboot] [SeaBIOS] [SimNow] PORT_IRQ_STAT register is 0 in ahci_port_setup
by Kevin O'Connor 08 Mar '13

08 Mar '13

On Thu, Mar 07, 2013 at 04:59:43PM +0800, WANG Siyuan wrote: > Hi, > I am trying to boot a hard disk image using coreboot and seabios on > SimNow Simulator. > The system stops at seabios stage. > > PORT_CMD_START fails in function ahci_port_setup (seabios/src/ahci.c), > Then I traced into function ahci_command (seabios/src/ahci.c), I found > the value of register ORT_IRQ_STAT is always 0: > intbits = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT); > intbits returns 0 all the time, so system stops here until time out. > > Any comments would be appreciated. There is a 32 second timeout in that code (which may be a longer wall time if run under a simulator) - are you sure it didn't eventually time out. As to why it is taking so long - could be an error in the simulator or in the seabios driver. You could try disabling the ahci code in seabios via kconfig. -Kevin

2 2

← Newer
1
...
61
62
63
64
65
66
67
...
79
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2013