coreboot March 2013

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Patch set updated for coreboot: af97ac3 AMD Fam14 DSDT: Remove INI method from AZHD device
by Mike Loptien 15 Mar '13

15 Mar '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2741 -gerrit commit af97ac3d5964115595e0922f372207a80b0c6750 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Mar 15 13:31:20 2013 -0600 AMD Fam14 DSDT: Remove INI method from AZHD device I am removing the _INI method from the AZHD device because it does not seem to do anything and causes errors in the FWTS[1] (Firmware Test Suite) test 'method'. The INI method performs device specific initialization and is run when OSPM loads a description table. It must only access OperationRegions that have been indicated as available by the _REG (Region) method. We do not have a _REG method and during my testing, I added a REG method but it did not seem to make a difference in the PCI register space. The bit fields defined as NSDI (Disable No Snoop), NSDO (Disable No Snoop Override), and NSEN (Enable No Snoop Request) do not ever get written from their default values. And writing to these bit fields does not seem to be necessary because I did not notice any change in audio functionality. In an effort to clean up as many FWTS errors as possible, I propose removing this method altogether. I have seen no change in operation (audio works with and without this method) and there does not seem to be any change in lspci or dmesg. FWTS information can be found here: [1]: https://wiki.ubuntu.com/Kernel/Reference/fwts This is the same chagne as made to Persimmon in Change-ID If8d86f: http://review.coreboot.org/#/c/2726/ Change-Id: Id560ea85a38f73aaba2c35447bbce46bd9c0d0dd Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/amd/inagua/dsdt.asl | 8 -------- src/mainboard/amd/south_station/dsdt.asl | 8 -------- src/mainboard/amd/union_station/dsdt.asl | 8 -------- 3 files changed, 24 deletions(-) diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 148d7b0..68cce17 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -1373,14 +1373,6 @@ DefinitionBlock ( offset (0x6C), MMDT, 16, } - - Method(_INI) { - If(LEqual(OSTP,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } } /* end AZHD */ Device(LIBR) { diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 148d7b0..68cce17 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -1373,14 +1373,6 @@ DefinitionBlock ( offset (0x6C), MMDT, 16, } - - Method(_INI) { - If(LEqual(OSTP,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } } /* end AZHD */ Device(LIBR) { diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index 1d2435c..e3381e9 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -1374,14 +1374,6 @@ DefinitionBlock ( offset (0x6C), MMDT, 16, } - - Method(_INI) { - If(LEqual(OSTP,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } } /* end AZHD */ Device(LIBR) {

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New patch to review for coreboot: aa04070 AMD Fam14 DSDT: Remove INI method from AZHD device
by Mike Loptien 15 Mar '13

15 Mar '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2741 -gerrit commit aa0407070d182b70924c059bd2a4b1dc75796a0b Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Mar 15 13:31:20 2013 -0600 AMD Fam14 DSDT: Remove INI method from AZHD device I am removing the _INI method from the AZHD device because it does not seem to do anything and causes errors in the FWTS[1] (Firmware Test Suite) test 'method'. The INI method performs device specific initialization and is run when OSPM loads a description table. It must only access OperationRegions that have been indicated as available by the _REG (Region) method. We do not have a _REG method and during my testing, I added a REG method but it did not seem to make a difference in the PCI register space. The bit fields defined as NSDI (Disable No Snoop), NSDO (Disable No Snoop Override), and NSEN (Enable No Snoop Request) do not ever get written from their default values. And writing to these bit fields does not seem to be necessary because I did not notice any change in audio functionality. In an effort to clean up as many FWTS errors as possible, I propose removing this method altogether. I have seen no change in operation (audio works with and without this method) and there does not seem to be any change in lspci or dmesg. FWTS information can be found here: [1]: https://wiki.ubuntu.com/Kernel/Reference/fwts This is the same chagne as made to Persimmon in Change-ID If8d86f: http://review.coreboot.org/#/c/2726/ Change-Id: Id560ea85a38f73aaba2c35447bbce46bd9c0d0dd Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/amd/inagua/dsdt.asl | 8 -------- src/mainboard/amd/south_station/dsdt.asl | 8 -------- src/mainboard/amd/union_station/dsdt.asl | 8 -------- 3 files changed, 24 deletions(-) diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 582ab7f..557e40c 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -1373,14 +1373,6 @@ DefinitionBlock ( offset (0x6C), MMDT, 16, } - - Method(_INI) { - If(LEqual(OSTP,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } } /* end AZHD */ Device(LIBR) { diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 582ab7f..557e40c 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -1373,14 +1373,6 @@ DefinitionBlock ( offset (0x6C), MMDT, 16, } - - Method(_INI) { - If(LEqual(OSTP,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } } /* end AZHD */ Device(LIBR) { diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index da6f266..5d5b128 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -1374,14 +1374,6 @@ DefinitionBlock ( offset (0x6C), MMDT, 16, } - - Method(_INI) { - If(LEqual(OSTP,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } } /* end AZHD */ Device(LIBR) {

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Patch set updated for coreboot: 5e364fb lib: add rmodule support
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2692 -gerrit commit 5e364fb1f80538ba0b589df3b2cf96acd9cb14b1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Dec 24 14:28:37 2012 -0600 lib: add rmodule support A rmodule is short for relocation module. Relocaiton modules are standalone programs. These programs are linked at address 0 as a shared object with a special linker script that maintains the relocation entries for the object. These modules can then be embedded as a raw binary (objcopy -O binary) to be loaded at any location desired. Initially, the only arch support is for x86. All comments below apply to x86 specific properties. The intial user of this support would be for SMM handlers since those handlers sometimes need to be located at a dynamic address (e.g. TSEG region). The relocation entries are currently Elf32_Rel. They are 8 bytes large, and the entries are not necessarily in sorted order. An future optimization would be to have a tool convert the unsorted relocations into just sorted offsets. This would reduce the size of the blob produced after being processed. Essentialy, 8 bytes per relocation meta entry would reduce to 4 bytes. Change-Id: I2236dcb66e9d2b494ce2d1ae40777c62429057ef Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/Kconfig | 8 ++ src/include/rmodule.h | 126 ++++++++++++++++++++++++++ src/lib/Makefile.inc | 18 ++++ src/lib/rmodule.c | 245 ++++++++++++++++++++++++++++++++++++++++++++++++++ src/lib/rmodule.ld | 115 ++++++++++++++++++++++++ 5 files changed, 512 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 3e24967..7206878 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -357,6 +357,14 @@ config GFXUMA help Enable Unified Memory Architecture for graphics. +config RELOCATABLE_MODULES + bool "Relocatable Modules" + default n + help + If RELOCATABLE_MODULES is selected then support is enabled for + building relocatable modules in the ram stage. Those modules can be + loaded anywhere and all the relocations are handled automatically. + config HAVE_ACPI_TABLES bool help diff --git a/src/include/rmodule.h b/src/include/rmodule.h new file mode 100644 index 0000000..b51700c --- /dev/null +++ b/src/include/rmodule.h @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 ChromeOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef RMODULE_H +#define RMODULE_H + +#include <stdint.h> + +#define RMODULE_MAGIC 0xf8fe +#define RMODULE_VERSION_1 1 + +enum { + RMODULE_TYPE_SMM, +}; + +struct rmodule; + +/* Public API for loading rmdoules. */ +int rmodule_parse(void *ptr, struct rmodule *m); +void *rmodule_parameters(const struct rmodule *m); +void *rmodule_entry(const struct rmodule *m); +int rmodule_entry_offset(const struct rmodule *m); +int rmodule_memory_size(const struct rmodule *m); +int rmodule_load(void *loc, struct rmodule *m); +int rmodule_load_alignment(const struct rmodule *m); + +#define FIELD_ENTRY(x_) ((u32)&x_) +#define RMODULE_HEADER(entry_, type_) \ +{ \ + .magic = RMODULE_MAGIC, \ + .version = RMODULE_VERSION_1, \ + .type = type_, \ + .payload_begin_offset = FIELD_ENTRY(_payload_begin_offset), \ + .payload_end_offset = FIELD_ENTRY(_payload_end_offset), \ + .relocations_begin_offset = \ + FIELD_ENTRY(_relocations_begin_offset), \ + .relocations_end_offset = \ + FIELD_ENTRY(_relocations_end_offset), \ + .module_link_start_address = \ + FIELD_ENTRY(_module_link_start_addr), \ + .module_program_size = FIELD_ENTRY(_module_program_size), \ + .module_entry_point = FIELD_ENTRY(entry_), \ + .parameters_begin = FIELD_ENTRY(_module_params_begin), \ + .parameters_end = FIELD_ENTRY(_module_params_end), \ + .bss_begin = FIELD_ENTRY(_bss_begin), \ + .bss_end = FIELD_ENTRY(_bss_end), \ +} + +#define DEFINE_RMODULE_HEADER(name_, entry_, type_) \ + struct rmodule_header name_ \ + __attribute__ ((section (".module_header"))) = \ + RMODULE_HEADER(entry_, type_) + + +/* Private data structures below should not be used directly. */ + +/* All fields with '_offset' in the name are byte offsets into the flat blob. + * The linker and the linker script takes are of assigning the values. */ +struct rmodule_header { + u16 magic; + u8 version; + u8 type; + /* The payload represents the program's loadable code and data. */ + u32 payload_begin_offset; + u32 payload_end_offset; + /* Begin and of relocation information about the program module. */ + u32 relocations_begin_offset; + u32 relocations_end_offset; + /* The starting address of the linked program. This address is vital + * for determining relocation offsets as the reloction info and other + * symbols (bss, entry point) need this value as a basis to calculate + * the offsets. + */ + u32 module_link_start_address; + /* The module_program_size is the size of memory used while running + * the program. The program is assumed to consume a contiguos amount + * of memory. */ + u32 module_program_size; + /* This is program's execution entry point. */ + u32 module_entry_point; + /* Optional paramter structure that can be used to pass data into + * the module. */ + u32 parameters_begin; + u32 parameters_end; + /* BSS section information so the loader can clear the bss. */ + u32 bss_begin; + u32 bss_end; +} __attribute__ ((packed)); + +struct rmodule { + void *location; + struct rmodule_header *header; + const void *payload; + int payload_size; + void *relocations; +}; + +/* These are the symbols assumed that every module contains. The linker script + * provides these symbols. */ +extern char _relocations_begin_offset[]; +extern char _relocations_end_offset[]; +extern char _payload_end_offset[]; +extern char _payload_begin_offset[]; +extern char _bss_begin[]; +extern char _bss_end[]; +extern char _module_program_size[]; +extern char _module_link_start_addr[]; +extern char _module_params_begin[]; +extern char _module_params_end[]; + +#endif /* RMODULE_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index be57f29..160fce6 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -107,3 +107,21 @@ endif $(obj)/lib/uart8250mem.smm.o : $(OPTION_TABLE_H) $(obj)/lib/uart8250.smm.o : $(OPTION_TABLE_H) +ifeq ($(CONFIG_RELOCATABLE_MODULES),y) +ramstage-y += rmodule.c + +RMODULE_LDSCRIPT := $(src)/lib/rmodule.ld +RMODULE_LDFLAGS := -nostartfiles -shared -z defs -nostdlib -Bsymbolic -T $(RMODULE_LDSCRIPT) + +# rmodule_link_rules is a function that should be called with: +# (1) the object name to link +# (2) the dependencies +# (3) heap size of the relocatable module +# It will create the necessary Make rules. +define rmodule_link +$(strip $(1)): $(strip $(2)) $$(RMODULE_LDSCRIPT) $$(obj)/ldoptions + $$(LD) $$(RMODULE_LDFLAGS) --defsym=__heap_size=$(strip $(3)) -o $$@ $(strip $(2)) + $$(NM) -n $$@ > $$(basename $$(a)).map +endef + +endif diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c new file mode 100644 index 0000000..56d7c6d --- /dev/null +++ b/src/lib/rmodule.c @@ -0,0 +1,245 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 ChromeOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <stdint.h> +#include <string.h> +#include <console/console.h> +#include <rmodule.h> + +/* Change this define to get more verbose debugging for module loading. */ +#define PK_ADJ_LEVEL BIOS_NEVER + +#if CONFIG_ARCH_X86 +/* + * On X86, the only relocations currently allowed are R_386_RELATIVE which + * have '0' for the symbol info in the relocation metadata (in r_info). + * The reason is that the module is fully linked and just has the relocations' + * locations. + */ +typedef struct { + u32 r_offset; + u32 r_info; +} Elf32_Rel; + +#define R_386_RELATIVE 8 + +#define RELOCTION_ENTRY_SIZE sizeof(Elf32_Rel) +static inline int rmodule_reloc_offset(const void *reloc) +{ + const Elf32_Rel *rel = reloc; + return rel->r_offset; +} + +static inline int rmodule_reloc_valid(const void *reloc) +{ + const Elf32_Rel *rel = reloc; + return (rel->r_info == R_386_RELATIVE); +} + +static inline void *remodule_next_reloc(const void *reloc) +{ + const Elf32_Rel *rel = reloc; + rel++; + return (void *)rel; +} + +#else +#error Arch needs to add relocation information support for RMODULE +#endif + +static inline int rmodule_is_loaded(const struct rmodule *module) +{ + return module->location != NULL; +} + +/* Calculate a loaded program address based on the blob address. */ +static inline void *rmodule_load_addr(const struct rmodule *module, + u32 blob_addr) +{ + char *loc = module->location; + return &loc[blob_addr - module->header->module_link_start_address]; +} + +/* Initialize a rmodule structure based on raw data. */ +int rmodule_parse(void *ptr, struct rmodule *module) +{ + char *base; + struct rmodule_header *rhdr; + + base = ptr; + rhdr = ptr; + + if (rhdr == NULL) + return -1; + + /* Sanity check the raw data. */ + if (rhdr->magic != RMODULE_MAGIC) + return -1; + if (rhdr->version != RMODULE_VERSION_1) + return -1; + + /* Indicate the module hasn't been loaded yet. */ + module->location = NULL; + + /* The rmodule only needs a reference to the reloc_header. */ + module->header = rhdr; + + /* The payload lives after the header. */ + module->payload = &base[rhdr->payload_begin_offset]; + module->payload_size = rhdr->payload_end_offset - + rhdr->payload_begin_offset; + module->relocations = &base[rhdr->relocations_begin_offset]; + + return 0; +} + +int rmodule_memory_size(const struct rmodule *module) +{ + return module->header->module_program_size; +} + +void *rmodule_parameters(const struct rmodule *module) +{ + if (!rmodule_is_loaded(module)) + return NULL; + + /* Indicate if there are no parameters. */ + if (module->header->parameters_begin == module->header->parameters_end) + return NULL; + + return rmodule_load_addr(module, module->header->parameters_begin); +} + +int rmodule_entry_offset(const struct rmodule *module) +{ + return module->header->module_entry_point - + module->header->module_link_start_address; +} + +void *rmodule_entry(const struct rmodule *module) +{ + if (!rmodule_is_loaded(module)) + return NULL; + + return rmodule_load_addr(module, module->header->module_entry_point); +} + +static void rmodule_clear_bss(struct rmodule *module) +{ + char *begin; + int size; + + begin = rmodule_load_addr(module, module->header->bss_begin); + size = module->header->bss_end - module->header->bss_begin; + memset(begin, 0, size); +} + +static inline int rmodule_number_relocations(const struct rmodule *module) +{ + int r; + + r = module->header->relocations_end_offset; + r -= module->header->relocations_begin_offset; + r /= RELOCTION_ENTRY_SIZE; + return r; +} + +static void rmodule_copy_payload(const struct rmodule *module) +{ + printk(BIOS_DEBUG, "Loading module at %p with entry %p. " + "filesize: 0x%x memsize: 0x%x\n", + module->location, rmodule_entry(module), + module->payload_size, rmodule_memory_size(module)); + memcpy(module->location, module->payload, module->payload_size); +} + +static inline u32 *rmodule_adjustment_location(const struct rmodule *module, + const void *reloc) +{ + int reloc_offset; + + /* Don't relocate header field entries -- only program relocations. */ + reloc_offset = rmodule_reloc_offset(reloc); + if (reloc_offset < module->header->module_link_start_address) + return NULL; + + return rmodule_load_addr(module, reloc_offset); +} + +static int rmodule_relocate(const struct rmodule *module) +{ + int num_relocations; + const void *reloc; + u32 adjustment; + + /* Each relocation needs to be adjusted relative to the beginning of + * the loaded program. */ + adjustment = (u32)rmodule_load_addr(module, 0); + + reloc = module->relocations; + num_relocations = rmodule_number_relocations(module); + + printk(BIOS_DEBUG, "Processing %d relocs with adjust value of 0x%08x\n", + num_relocations, adjustment); + + while (num_relocations > 0) { + u32 *adjust_loc; + + if (!rmodule_reloc_valid(reloc)) + return -1; + + /* If the adjustment location is non-NULL adjust it. */ + adjust_loc = rmodule_adjustment_location(module, reloc); + if (adjust_loc != NULL) { + printk(PK_ADJ_LEVEL, "Adjusting %p: 0x%08x -> 0x%08x\n", + adjust_loc, *adjust_loc, + *adjust_loc + adjustment); + *adjust_loc += adjustment; + } + + reloc = remodule_next_reloc(reloc); + num_relocations--; + } + + return 0; +} + +int rmodule_load_alignment(const struct rmodule *module) +{ + /* The load alignment is the start of the program's linked address. + * The base address where the program is loaded needs to be a multiple + * of the program's starting link address. That way all data alignment + * in the program is presered. */ + return module->header->module_link_start_address; +} + +int rmodule_load(void *base, struct rmodule *module) +{ + /* + * In order to load the module at a given address, the following steps + * take place: + * 1. Copy payload to base address. + * 2. Clear the bss segment. + * 3. Adjust relocations within the module to new base address. + */ + module->location = base; + rmodule_copy_payload(module); + rmodule_clear_bss(module); + return rmodule_relocate(module); +} + diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld new file mode 100644 index 0000000..4c13c84 --- /dev/null +++ b/src/lib/rmodule.ld @@ -0,0 +1,115 @@ +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) + +/* + * This linker script is used to link rmodules (relocatable modules). It + * links at zero so that relocation fixups are easy when placing the binaries + * anywhere in the address space. + * + * NOTE: The program's loadable sections (text, module_params, and data) are + * packed into the flat blob using the AT directive. The rmodule loader assumes + * the entire program resides in one contiguous address space. Therefore, + * alignment for a given section (if required) needs to be done at the end of + * the preceeding section. e.g. if the data section should be aligned to an 8 + * byte address the text section should have ALIGN(8) at the end of its section. + * Otherwise there won't be a consistent mapping between the flat blob and the + * loaded program. + */ + +BASE_ADDRESS = 0x00000; + +SECTIONS +{ + . = BASE_ADDRESS; + + .header : AT (0) { + *(.module_header); + . = ALIGN(8); + } + + /* Align the start of the module program to a large enough alignment + * so that any data in the program with an alignement property is met. + * Essentially, this alignment is the maximum possible data alignment + * property a program can have. */ + . = ALIGN(4096); + _module_link_start_addr = .; + _payload_begin_offset = LOADADDR(.header) + SIZEOF(.header); + + .text : AT (_payload_begin_offset) { + /* C code of the module. */ + *(.text); + *(.text.*); + /* C read-only data. */ + . = ALIGN(16); + *(.rodata); + *(.rodata.*); + . = ALIGN(4); + } + + .module_params : AT (LOADADDR(.text) + SIZEOF(.text)) { + /* The parameters section can be used to pass parameters + * to a module, however there has to be an prior agreement + * on how to interpret the parameters. */ + _module_params_begin = .; + *(.module_parameters); + _module_params_end = .; + . = ALIGN(4); + } + + .data : AT (LOADADDR(.module_params) + SIZEOF(.module_params)) { + _sdata = .; + *(.data); + . = ALIGN(4); + _edata = .; + } + + /* _payload_end marks the end of the module's code and data. */ + _payload_end_offset = LOADADDR(.data) + SIZEOF(.data); + + .bss (NOLOAD) : { + /* C uninitialized data of the SMM handler */ + _bss_begin = .; + *(.bss); + *(.sbss); + *(COMMON); + . = ALIGN(8); + _bss_end = .; + } + + .heap (NOLOAD) : { + /* + * Place the heap after BSS. The heap size is passed in by + * by way of ld --defsym=__heap_size=<> + */ + _heap = .; + . = . + __heap_size; + _eheap = .; + } + + /* _module_program_size is the total memory used by the program. */ + _module_program_size = _eheap - _module_link_start_addr; + + /* The relocation information is linked on top of the BSS section + * because the BSS section takes no space on disk. The relocation data + * resides directly after the data section in the flat binary. */ + .relocations ADDR(.bss) : AT (_payload_end_offset) { + *(.rel.*); + } + _relocations_begin_offset = LOADADDR(.relocations); + _relocations_end_offset = _relocations_begin_offset + + SIZEOF(.relocations); + + /DISCARD/ : { + /* Drop unnecessary sections. Since these modules are linked + * as shared objects there are dynamic sections. These sections + * aren't needed so drop them. */ + *(.comment); + *(.note); + *(.note.*); + *(.dynamic); + *(.dynsym); + *(.dynstr); + *(.gnu.hash); + *(.eh_frame); + } +}

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Patch set updated for coreboot: 9b69e39 SMM: link against libgcc
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2727 -gerrit commit 9b69e39d197345c063c84581da217edf2f39b0e6 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Mar 14 17:53:19 2013 -0700 SMM: link against libgcc The non-relocatable SMM code was changed to link against libgcc a while back so that printk could use built-in division instead of a hand crafted div() function. However, the relocatable SMM code was not adapted by mistake. This patch links the relocatable SMM against libgcc, too, so we can enable it for Haswell. Change-Id: Ia64a78e2e62348d115ae4ded52d1a02c74c5cea4 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/smm/Makefile.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index ee4dbea..b595a36 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -18,7 +18,6 @@ ## ifeq ($(CONFIG_SMM_MODULES),y) - smmstub-y += smm_stub.S smmstub-y += smm_module_header.c @@ -48,8 +47,9 @@ $(obj)/cpu/x86/smm/smmstub.ramstage.o: $(obj)/cpu/x86/smm/smmstub # C-based SMM handler. -$(obj)/cpu/x86/smm/smm.o: $$(smm-objs) - $(CC) $(LDFLAGS) -nostdlib -r -o $@ $^ +$(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(LIBGCC_FILE_NAME) + $(CC) $(LDFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(smm-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smm.elf, $(obj)/cpu/x86/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE)))

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Patch set updated for coreboot: b64d4b2 haswell: Use SMM Modules
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2728 -gerrit commit b64d4b22c5a305045fddd0875d35ee975a4500bf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Dec 21 21:21:48 2012 -0600 haswell: Use SMM Modules This commit adds support for using the SMM modules for haswell-based boards. The SMI handling was also refactored to put the relocation handler and permanent SMM handler loading in the cpu directory. All tseg adjustment support is dropped by relying on the SMM module support to perform the necessary relocations. Change-Id: I8dd23610772fc4408567d9f4adf339596eac7b1f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/Kconfig | 1 + src/cpu/intel/haswell/Makefile.inc | 1 + src/cpu/intel/haswell/smmrelocate.c | 332 +++++++++++++++++++++++++++ src/cpu/x86/smm/smmrelocate.S | 5 - src/southbridge/intel/lynxpoint/lpc.c | 52 +---- src/southbridge/intel/lynxpoint/pch.h | 5 + src/southbridge/intel/lynxpoint/smi.c | 96 ++------ src/southbridge/intel/lynxpoint/smihandler.c | 82 ++----- 8 files changed, 378 insertions(+), 196 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 460b497..bf0abbc 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -10,6 +10,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG + select SMM_MODULES select CPU_MICROCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 467c948..67b0954 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -2,6 +2,7 @@ ramstage-y += haswell_init.c subdirs-y += ../../x86/name ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c new file mode 100644 index 0000000..e2a6482 --- /dev/null +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -0,0 +1,332 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 ChromeOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> +#include <console/console.h> +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include "haswell.h" + +#define EMRRphysBase_MSR 0x1f4 +#define EMRRphysMask_MSR 0x1f5 +#define UNCORE_EMRRphysBase_MSR 0x2f4 +#define UNCORE_EMRRphysMask_MSR 0x2f5 + +#define CORE_THREAD_COUNT_MSR 0x35 + +#define SMRR_SUPPORTED (1<<11) +#define EMRR_SUPPORTED (1<<12) + +struct smm_relocation_params { + u32 smram_base; + u32 smram_size; + u32 ied_base; + u32 ied_size; + msr_t smrr_base; + msr_t smrr_mask; + msr_t emrr_base; + msr_t emrr_mask; + msr_t uncore_emrr_base; + msr_t uncore_emrr_mask; +}; + +/* This gets filled in and used during relocation. */ +static struct smm_relocation_params smm_reloc_params; + +static inline void write_smrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + wrmsr(SMRRphysBase_MSR, relo_params->smrr_base); + wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask); +} + +static inline void write_emrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->emrr_base.lo, relo_params->emrr_mask.lo); + wrmsr(EMRRphysBase_MSR, relo_params->emrr_base); + wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask); +} + +static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) +{ + printk(BIOS_DEBUG, + "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_emrr_base.lo, + relo_params->uncore_emrr_mask.lo); + wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base); + wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask); +} + +/* The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. */ +static void cpu_smm_do_relocation(void *arg, int cpu, + const struct smm_runtime *runtime) +{ + em64t101_smm_state_save_area_t *save_state; + msr_t mtrr_cap; + struct smm_relocation_params *relo_params = arg; + + if (cpu >= CONFIG_MAX_CPUS) { + printk(BIOS_CRIT, + "Invalid CPU number assigned in SMM stub: %d\n", cpu); + return; + } + + printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); + + /* All threads need to set IEDBASE and SMBASE in the save state area. + * Since one thread runs at a time during the relocation the save state + * is the same for all cpus. */ + save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE - + runtime->save_state_size); + + /* The relocated handler runs with all CPUs concurrently. Therefore + * stagger the entry points adjusting SMBASE downwards by save state + * size * CPU num. */ + save_state->smbase = relo_params->smram_base - + cpu * runtime->save_state_size; + save_state->iedbase = relo_params->ied_base; + + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n", + save_state->smbase, save_state->iedbase, save_state); + + /* Write EMRR and SMRR MSRs based on indicated support. */ + mtrr_cap = rdmsr(MTRRcap_MSR); + if (mtrr_cap.lo & SMRR_SUPPORTED) + write_smrr(relo_params); + + if (mtrr_cap.lo & EMRR_SUPPORTED) { + write_emrr(relo_params); + /* UNCORE_EMRR msrs are package level. Therefore, only + * configure these MSRs on the BSP. */ + if (cpu == 0) + write_uncore_emrr(relo_params); + } + + southbridge_clear_smi_status(); +} + +static u32 northbridge_get_base_reg(device_t dev, int reg) +{ + u32 value; + + value = pci_read_config32(dev, reg); + /* Base registers are at 1MiB granularity. */ + value &= ~((1 << 20) - 1); + return value; +} + +static void fill_in_relocation_params(device_t dev, + struct smm_relocation_params *params) +{ + u32 tseg_size; + u32 tsegmb; + u32 bgsm; + u32 emrr_base; + u32 emrr_size; + int phys_bits; + /* All range registers are aligned to 4KiB */ + const u32 rmask = ~((1 << 12) - 1); + + /* Some of the range registers are dependent on the number of physical + * address bits supported. */ + phys_bits = cpuid_eax(0x80000008) & 0xff; + + /* The range bounded by the TSEGMB and BGSM registers encompasses the + * SMRAM range as well as the IED range. However, the SMRAM available + * to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB. + */ + tsegmb = northbridge_get_base_reg(dev, TSEG); + bgsm = northbridge_get_base_reg(dev, BGSM); + tseg_size = bgsm - tsegmb; + + params->smram_base = tsegmb; + params->smram_size = 4 << 20; + params->ied_base = tsegmb + params->smram_size; + params->ied_size = tseg_size - params->smram_size; + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid; + params->smrr_mask.hi = 0; + + /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ + emrr_base = (params->ied_base + (2 << 20)) & rmask; + emrr_size = params->ied_size - (2 << 20); + + /* EMRR has 46 bits of valid address aligned to 4KiB. It's dependent + * on the number of physical address bits supported. */ + params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK; + params->emrr_base.hi = 0; + params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRRphysMaskValid; + params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1; + + /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */ + params->uncore_emrr_base.lo = emrr_base; + params->uncore_emrr_base.hi = 0; + params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | + MTRRphysMaskValid; + params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; +} + +static int install_relocation_handler(int num_cpus, + struct smm_relocation_params *relo_params) +{ + /* The default SMM entry happens serially at the default location. + * Therefore, there is only 1 concurrent save state area. Set the + * stack size to the save state size, and call into the + * do_relocation handler. */ + int save_state_size = sizeof(em64t101_smm_state_save_area_t); + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = 1, + .handler = &cpu_smm_do_relocation, + .handler_arg = (void *)relo_params, + }; + + return smm_setup_relocation_handler(&smm_params); +} + +static void setup_ied_area(struct smm_relocation_params *params) +{ + char *ied_base; + + struct ied_header ied = { + .signature = "INTEL RSVD", + .size = params->ied_size, + .reserved = {0}, + }; + + ied_base = (void *)params->ied_base; + + /* Place IED header at IEDBASE. */ + memcpy(ied_base, &ied, sizeof(ied)); + + /* Zero out 32KiB at IEDBASE + 1MiB */ + memset(ied_base + (1 << 20), 0, (32 << 10)); + + /* According to the BWG MP init section 2MiB of memory at IEDBASE + + * 2MiB should be zeroed as well. However, I suspect what is inteneded + * is to clear the memory covered by EMRR. TODO(adurbin): figure out if * this is really required. */ + //memset(ied_base + (2 << 20), 0, (2 << 20)); +} + +static int install_permanent_handler(int num_cpus, + struct smm_relocation_params *relo_params) +{ + /* There are num_cpus concurrent stacks and num_cpus concurrent save + * state areas. Lastly, set the stack size to the save state size. */ + int save_state_size = sizeof(em64t101_smm_state_save_area_t); + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = num_cpus, + }; + + printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", + relo_params->smram_base); + return smm_load_module((void *)relo_params->smram_base, + relo_params->smram_size, &smm_params); +} + +static int cpu_smm_setup(void) +{ + device_t dev; + int num_cpus; + msr_t msr; + + printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + + fill_in_relocation_params(dev, &smm_reloc_params); + + setup_ied_area(&smm_reloc_params); + + msr = rdmsr(CORE_THREAD_COUNT_MSR); + num_cpus = msr.lo & 0xffff; + if (num_cpus > CONFIG_MAX_CPUS) { + printk(BIOS_CRIT, + "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n", + num_cpus, CONFIG_MAX_CPUS); + } + + if (install_relocation_handler(num_cpus, &smm_reloc_params)) { + printk(BIOS_CRIT, "SMM Relocation handler install failed.\n"); + return -1; + } + + if (install_permanent_handler(num_cpus, &smm_reloc_params)) { + printk(BIOS_CRIT, "SMM Permanent handler install failed.\n"); + return -1; + } + + /* Ensure the SMM handlers hit DRAM before performing first SMI. */ + /* TODO(adurbin): Is this really needed? */ + wbinvd(); + + return 0; +} + +void smm_init(void) +{ + /* Return early if CPU SMM setup failed. */ + if (cpu_smm_setup()) + return; + + southbridge_smm_init(); + + /* Initiate first SMI to kick off SMM-context relocation. Note: this + * SMI being triggered here queues up an SMI in the APs which are in + * wait-for-SIPI state. Once an AP gets an SIPI it will service the SMI + * at the SMM_DEFAULT_BASE before jumping to startup vector. */ + southbridge_trigger_smi(); + + printk(BIOS_DEBUG, "Relocation complete.\n"); + + /* Lock down the SMRAM space. */ + smm_lock(); +} + +void smm_lock(void) +{ + /* LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + D_LCK | G_SMRAME | C_BASE_SEG); +} + diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index a6379cc..16d4b9f 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -39,8 +39,6 @@ #include "../../../southbridge/intel/bd82x6x/pch.h" #elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX #include "../../../southbridge/intel/i82801ix/i82801ix.h" -#elif CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT -#include "../../../southbridge/intel/lynxpoint/pch.h" #else #error "Southbridge needs SMM handler support." #endif @@ -50,9 +48,6 @@ #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE #include <northbridge/intel/sandybridge/sandybridge.h> #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) -#elif CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT -#include <northbridge/intel/haswell/haswell.h> -#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) #else #error "Northbridge must define TSEG_BAR." #endif diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index facea7c..eaf926c 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -29,13 +29,13 @@ #include <arch/ioapic.h> #include <arch/acpi.h> #include <cpu/cpu.h> +#include <cpu/x86/smm.h> #include <elog.h> #include "pch.h" #define NMI_OFF 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 typedef struct southbridge_intel_lynxpoint_config config_t; @@ -428,58 +428,22 @@ static void enable_clock_gating(device_t dev) #endif } -#if CONFIG_HAVE_SMI_HANDLER -static void pch_lock_smm(struct device *dev) +static void pch_set_acpi_mode(void) { -#if TEST_SMM_FLASH_LOCKDOWN - u8 reg8; -#endif - +#if CONFIG_HAVE_SMI_HANDLER if (acpi_slp_type != 3) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); - outb(0xe1, 0xb2); // Enable ACPI mode + outb(APM_CNT_ACPI_ENABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); #else printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(0x1e, 0xb2); // Disable ACPI mode + outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); #endif } - - /* Don't allow evil boot loaders, kernels, or - * userspace applications to deceive us: - */ - smm_lock(); - -#if TEST_SMM_FLASH_LOCKDOWN - /* Now try this: */ - printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); - printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - - printk(BIOS_DEBUG, "Writing:\n"); - *(volatile u8 *)0xfff00000 = 0x00; - printk(BIOS_DEBUG, "Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - printk(BIOS_DEBUG, "Done.\n"); -#endif +#endif /* CONFIG_HAVE_SMI_HANDLER */ } -#endif static void pch_disable_smm_only_flashing(struct device *dev) { @@ -567,9 +531,7 @@ static void lpc_init(struct device *dev) pch_disable_smm_only_flashing(dev); -#if CONFIG_HAVE_SMI_HANDLER - pch_lock_smm(dev); -#endif + pch_set_acpi_mode(); pch_fixups(dev); } diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index f27ae90..6f17d38 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -97,6 +97,11 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void pch_log_state(void); #endif void acpi_create_intel_hpet(acpi_hpet_t * hpet); + +/* These helpers are for performing SMM relocation. */ +void southbridge_smm_init(void); +void southbridge_trigger_smi(void); +void southbridge_clear_smi_status(void); #else void enable_smbus(void); void enable_usb_bar(void); diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 0bb9881..80dea2c 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -30,13 +30,6 @@ #include <string.h> #include "pch.h" -#if CONFIG_NORTHBRIDGE_INTEL_HASWELL -#include "northbridge/intel/haswell/haswell.h" -#endif - -extern unsigned char _binary_smm_start; -extern unsigned char _binary_smm_size; - /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ @@ -232,15 +225,17 @@ static void smi_set_eos(void) outb(reg8, pmbase + SMI_EN); } -extern uint8_t smm_relocation_start, smm_relocation_end; - -static void smm_relocate(void) +void southbridge_smm_init(void) { u32 smi_en; u16 pm1_en; u32 gpe0_en; - printk(BIOS_DEBUG, "Initializing SMM handler..."); +#if CONFIG_ELOG + /* Log events from chipset before clearing */ + pch_log_state(); +#endif + printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), PMBASE) & 0xff80; @@ -253,10 +248,6 @@ static void smm_relocate(void) return; } - /* copy the SMM relocation code */ - memcpy((void *)0x38000, &smm_relocation_start, - &smm_relocation_end - &smm_relocation_start); - printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status()); dump_pm1_status(reset_pm1_status()); @@ -305,7 +296,10 @@ static void smm_relocate(void) smi_en |= EOS | GBL_SMI_EN; outl(smi_en, pmbase + SMI_EN); +} +void southbridge_trigger_smi(void) +{ /** * There are several methods of raising a controlled SMI# via * software, among them: @@ -324,78 +318,18 @@ static void smm_relocate(void) outb(0x00, 0xb2); } -static int smm_handler_copied = 0; - -static void smm_install(void) -{ - device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - u32 smm_base = 0xa0000; - struct ied_header ied = { - .signature = "INTEL RSVD", - .size = IED_SIZE, - .reserved = {0}, - }; - - /* The first CPU running this gets to copy the SMM handler. But not all - * of them. - */ - if (smm_handler_copied) - return; - smm_handler_copied = 1; - - /* enable the SMM memory window */ - pci_write_config8(dev, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); - -#if CONFIG_SMM_TSEG - smm_base = pci_read_config32(dev, TSEG) & ~1; -#endif - - /* copy the real SMM handler */ - printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base); - memcpy((void *)smm_base, &_binary_smm_start, (size_t)&_binary_smm_size); - - /* copy the IED header into place */ - if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) { - /* Top of TSEG region */ - smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE; - printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n", - smm_base); - memcpy((void *)smm_base, &ied, sizeof(ied)); - } - wbinvd(); - - /* close the SMM memory window and enable normal SMM */ - pci_write_config8(dev, SMRAM, G_SMRAME | C_BASE_SEG); -} - -void smm_init(void) +void southbridge_clear_smi_status(void) { -#if CONFIG_ELOG - /* Log events from chipset before clearing */ - pch_log_state(); -#endif - - /* Put SMM code to 0xa0000 */ - smm_install(); + /* Clear SMI status */ + reset_smi_status(); - /* Put relocation code to 0x38000 and relocate SMBASE */ - smm_relocate(); + /* Clear PM1 status */ + reset_pm1_status(); - /* We're done. Make sure SMIs can happen! */ + /* Set EOS bit so other SMIs can occur. */ smi_set_eos(); } -void smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); -} - void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { /* diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 7c982d1..48dca2c 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -33,12 +33,6 @@ #include "nvs.h" -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -#include <northbridge/intel/haswell/haswell.h> - /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ @@ -53,28 +47,12 @@ static u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -static global_nvs_t *gnvs = (global_nvs_t *)0x0; +static global_nvs_t *gnvs; global_nvs_t *smm_get_gnvs(void) { return gnvs; } -#if CONFIG_SMM_TSEG -static u32 tseg_base = 0; -u32 smi_get_tseg_base(void) -{ - if (!tseg_base) - tseg_base = pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; - return tseg_base; -} -void tseg_relocate(void **ptr) -{ - /* Adjust pointer with TSEG base */ - if (*ptr && *ptr < (void*)smi_get_tseg_base()) - *ptr = (void *)(((u8*)*ptr) + smi_get_tseg_base()); -} -#endif - /** * @brief read and clear PM1_STS * @return PM1_STS register @@ -290,7 +268,7 @@ static void busmaster_disable_on_bus(int bus) } } -static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_sleep(void) { u8 reg8; u32 reg32; @@ -305,8 +283,6 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat outb(tmp70, 0x70); outb(tmp72, 0x72); - void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep; - /* First, disable further SMIs */ reg8 = inb(pmbase + SMI_EN); reg8 &= ~SLP_SMI_EN; @@ -318,9 +294,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat slp_typ = (reg32 >> 10) & 7; /* Do any mainboard sleep handling */ - tseg_relocate((void **)&mainboard_sleep); - if (mainboard_sleep) - mainboard_sleep(slp_typ-2); + mainboard_smi_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -390,17 +364,14 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat * core in case we are not running on the same core that * initiated the IO transaction. */ -/* FIXME: Confirm Haswell's SMM save state area structure. */ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) { em64t101_smm_state_save_area_t *state; - u32 base = smi_get_tseg_base() + 0x8000 + 0x7d00; int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = (em64t101_smm_state_save_area_t *) - (base - (node * 0x400)); + state = smm_get_save_state(node); /* Check for Synchronous IO (bit0==1) */ if (!(state->io_misc_info & (1 << 0))) @@ -447,11 +418,10 @@ static void southbridge_smi_gsmi(void) } #endif -static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_apmc(void) { u32 pmctrl; u8 reg8; - int (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc; em64t101_smm_state_save_area_t *state; /* Emulate B2 register as the FADT / Linux expects it */ @@ -504,12 +474,10 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state #endif } - tseg_relocate((void **)&mainboard_apmc); - if (mainboard_apmc) - mainboard_apmc(reg8); + mainboard_smi_apmc(reg8); } -static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_pm1(void) { u16 pm1_sts; @@ -530,7 +498,7 @@ static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_ } } -static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_gpe0(void) { u32 gpe0_sts; @@ -538,27 +506,20 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state dump_gpe0_status(gpe0_sts); } -static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_gpi(void) { - void (*mainboard_gpi)(u16 gpi_sts) = mainboard_smi_gpi; u16 reg16; reg16 = inw(pmbase + ALT_GP_SMI_STS); outw(reg16, pmbase + ALT_GP_SMI_STS); reg16 &= inw(pmbase + ALT_GP_SMI_EN); - tseg_relocate((void **)&mainboard_gpi); - if (mainboard_gpi) { - mainboard_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_smi_gpi(reg16); outw(reg16, pmbase + ALT_GP_SMI_STS); } -static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_mc(void) { u32 reg32; @@ -573,7 +534,7 @@ static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_s -static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_tco(void) { u32 tco_sts; @@ -610,7 +571,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ } } -static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_periodic(void) { u32 reg32; @@ -623,7 +584,7 @@ static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *s printk(BIOS_DEBUG, "Periodic SMI.\n"); } -static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save) +static void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_sts, trap_cycle; @@ -677,8 +638,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st #undef IOTRAP } -typedef void (*smi_handler_t)(unsigned int node, - smm_state_save_area_t *state_save); +typedef void (*smi_handler_t)(void); static smi_handler_t southbridge_smi[32] = { NULL, // [0] reserved @@ -721,7 +681,7 @@ static smi_handler_t southbridge_smi[32] = { * @param smm_revision revision of the smm state save map */ -void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) +void southbridge_smi_handler(void) { int i, dump = 0; u32 smi_sts; @@ -738,15 +698,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav for (i = 0; i < 31; i++) { if (smi_sts & (1 << i)) { if (southbridge_smi[i]) { -#if CONFIG_SMM_TSEG - smi_handler_t handler = (smi_handler_t) - ((u8*)southbridge_smi[i] + - smi_get_tseg_base()); - if (handler) - handler(node, state_save); -#else - southbridge_smi[i](node, state_save); -#endif + southbridge_smi[i](); } else { printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no " "handler available.\n", i);

1 0

New patch to review for coreboot: 2f3b077 Lippert Fam14 DSDT: Add OSC method
by Mike Loptien 15 Mar '13

15 Mar '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2740 -gerrit commit 2f3b07738c1fd63db8c65e6b5efbe5defced1040 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Mar 15 13:24:53 2013 -0600 Lippert Fam14 DSDT: Add OSC method The _OSC method is used to tell the OS what capabilities it can take control over from the firmware. This method is described in chapter 6.2.9 of the ACPI spec v3.0. The method takes 4 inputs (UUID, Rev ID, Input Count, and Capabilities Buffer) and returns a Capabilites Buffer the same size as the input Buffer. This Buffer is generally 3 Dwords long consisting of an Errors Dword, a Supported Capabilities Dword, and a Control Dword. The OS will request control of certain capabilities and the firmware must grant or deny control of those features. We do not want to have control over anything so let the OS control as much as it can. The _OSC method is required for PCIe devices and dmesg checks for its existence and issues an error if it is not found. This is the same change made to Persimmon with Change-ID I149428: http://review.coreboot.org/#/c/2684/ Change-Id: Iaf7b8153cec4d730efbceae3e6957d2904b8fae4 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/lippert/frontrunner-af/dsdt.asl | 14 +++++++++++++- src/mainboard/lippert/toucan-af/dsdt.asl | 14 +++++++++++++- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index d3b88f7..b9345de 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -1157,8 +1157,20 @@ DefinitionBlock ( Device(PCI0) { External (TOM1) External (TOM2) - Name(_HID, EISAID("PNP0A03")) + Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ + Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + + /* Operating System Capabilities Method */ + Method(_OSC,4) + { /* Check for proper PCI/PCIe UUID */ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + } + Method(_BBN, 0) { /* Bus number = 0 */ Return(0) } diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index cde41b4..9c0faac 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -1157,8 +1157,20 @@ DefinitionBlock ( Device(PCI0) { External (TOM1) External (TOM2) - Name(_HID, EISAID("PNP0A03")) + Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ + Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + + /* Operating System Capabilities Method */ + Method(_OSC,4) + { /* Check for proper PCI/PCIe UUID */ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + } + Method(_BBN, 0) { /* Bus number = 0 */ Return(0) }

1 0

Patch set updated for coreboot: 29d9d6c armv7/exynos/snow: set up caches properly
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2729 -gerrit commit 29d9d6c682d651b470a67f8d04dc3948c0f5d955 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 14 15:24:57 2013 -0700 armv7/exynos/snow: set up caches properly ** do not submit ** This (hopefully) sets up caches more carefully than we were doing before. This patch needs a bit more testing before going in. TODO: Code placement needs to be tidied up. Right now the code is scattered about in a less-than-ideal manner due to the differences between handling L1 cache (generic for ARMv7) and L2 (SoC-dependent). I suspect we'll disable and invalidate L1 in the CPU bootblock, then do try to consolidate everything else in a helper function called from the board's romstage (since we need board DRAM info for MMU setup). Change-Id: I7390981190e3213f4e1431f8e56746545c5cc7c9 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/bootblock_simple.c | 57 +++++++++++++++++++++++++++++++ src/arch/armv7/include/system.h | 16 +++++++++ src/arch/armv7/lib/Makefile.inc | 1 + src/arch/armv7/lib/cache-cp15.c | 3 +- src/arch/armv7/lib/cache_v7.c | 2 +- src/cpu/samsung/exynos5250/Makefile.inc | 1 - src/cpu/samsung/exynos5250/bootblock.c | 6 ++++ src/cpu/samsung/exynos5250/exynos_cache.c | 8 ++--- src/mainboard/google/snow/romstage.c | 45 ++++++++++++------------ 9 files changed, 105 insertions(+), 34 deletions(-) diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index 0132b87..0b2d884 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -24,9 +24,57 @@ #include <arch/stages.h> #include <cbfs.h> #include <console/console.h> +#include <system.h> #include "stages.c" +/* + * Set/clear program flow prediction and return the previous state. + */ +static int config_branch_prediction(int set_cr_z) +{ + unsigned int cr; + + /* System Control Register: 11th bit Z Branch prediction enable */ + cr = get_cr(); + set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z); + + return cr & CR_Z; +} + +/* Cache and MMU init */ +static void armv7_invalidate_caches(void) +{ + unsigned int cr; + + /* + * From Cortex-A Series Programmers guide (Example 15-3): + * 1. Disable MMU + * 2. Disable L1 caches (example disables i-cache then d-cache) + * 3. Invalidate L1 caches (same order) + * 4. Invalidate TLB + * + * L2 cache setup will be done by SoC-specific code. MMU setup + * needs to be done after DRAM init in board-specific code. + */ + + /* Disable MMU */ + cr = get_cr(); + cr &= ~CR_M; + set_cr(cr); + + /* Disable L1 caches */ + icache_disable(); + dcache_disable(); + + /* Invalidate caches */ + invalidate_icache_all(); + invalidate_dcache_all(); + + /* Invalidate TLB */ + v7_inval_tlb(); +} + static int boot_cpu(void) { /* @@ -42,6 +90,15 @@ void main(void) const char *stage_name = "fallback/romstage"; void *entry; + armv7_invalidate_caches(); + + /* + * Branch prediction enable. + * Note: If booting from USB, we need to disable branch prediction + * before copying from USB into RAM (FIXME: why?) + */ + config_branch_prediction(1); + if (boot_cpu()) { bootblock_cpu_init(); bootblock_mainboard_init(); diff --git a/src/arch/armv7/include/system.h b/src/arch/armv7/include/system.h index 053df8d..9a694ba 100644 --- a/src/arch/armv7/include/system.h +++ b/src/arch/armv7/include/system.h @@ -64,6 +64,20 @@ static inline void set_cr(unsigned int val) isb(); } +static inline unsigned int get_acr(void) +{ + unsigned int val; + asm("mrc p15, 0, %0, c1, c0, 1 @ get ACR" : "=r" (val) : : "cc"); + return val; +} + +static inline void set_acr(unsigned int val) +{ + asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set ACR" + : : "r" (val) : "cc"); + isb(); +} + /* options available for data cache on each page */ enum dcache_option { DCACHE_OFF, @@ -97,6 +111,8 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop); void mmu_setup(unsigned long start, unsigned long size); +void v7_inval_tlb(void); + void arm_init_before_mmu(void); /* diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 508f776..75e6752 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -14,6 +14,7 @@ ramstage-y += div0.c #ramstage-y += memcpy.S #ramstage-y += memset.S ramstage-y += syslib.c +ramstage-y += cache-cp15.c ramstage-y += cache_v7.c #FIXME(dhendrix): should this be a config option? diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c index e08ea57..32f3c79 100644 --- a/src/arch/armv7/lib/cache-cp15.c +++ b/src/arch/armv7/lib/cache-cp15.c @@ -123,8 +123,7 @@ inline void mmu_setup(unsigned long start, unsigned long size_mb) int i; u32 reg; - arm_init_before_mmu(); - +// arm_init_before_mmu(); /* Set up an identity-mapping for all 4GB, rw for everyone */ for (i = 0; i < 4096; i++) set_section_dcache(i, DCACHE_OFF); diff --git a/src/arch/armv7/lib/cache_v7.c b/src/arch/armv7/lib/cache_v7.c index 31072c7..1764351 100644 --- a/src/arch/armv7/lib/cache_v7.c +++ b/src/arch/armv7/lib/cache_v7.c @@ -226,7 +226,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) } /* Invalidate TLB */ -static void v7_inval_tlb(void) +void v7_inval_tlb(void) { /* Invalidate entire unified TLB */ asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 2774b12..961b719 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -30,7 +30,6 @@ ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c -ramstage-y += exynos_cache.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/bootblock.c b/src/cpu/samsung/exynos5250/bootblock.c index 949468f..48f390a 100644 --- a/src/cpu/samsung/exynos5250/bootblock.c +++ b/src/cpu/samsung/exynos5250/bootblock.c @@ -17,7 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <armv7.h> + void bootblock_cpu_init(void); void bootblock_cpu_init(void) { + /* Enable L2 cache */ + /* FIXME: maybe do this in romstage along with the other cache + * init functions? */ + v7_outer_cache_enable(); } diff --git a/src/cpu/samsung/exynos5250/exynos_cache.c b/src/cpu/samsung/exynos5250/exynos_cache.c index 7f4effe..87eded5 100644 --- a/src/cpu/samsung/exynos5250/exynos_cache.c +++ b/src/cpu/samsung/exynos5250/exynos_cache.c @@ -34,15 +34,11 @@ enum l2_cache_params { }; -/* FIXME(dhendrix): maybe move this to a romstage-specific file? */ -#ifdef __PRE_RAM__ void enable_caches(void) { - /* Enable D-cache. I-cache is already enabled in start.S */ - /* can't use it anyway -- it has dependencies we have to fix. */ - //dcache_enable(); + icache_enable(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); + dcache_enable(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); } -#endif /* * Set L2 cache parameters diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index ea2feec..3b14d91 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -20,6 +20,7 @@ #include <types.h> #include <system.h> +#include <armv7.h> #include <cache.h> #include <cbfs.h> #include <common.h> @@ -52,20 +53,6 @@ static int board_wakeup_permitted(void) } #endif -/* - * Set/clear program flow prediction and return the previous state. - */ -static int config_branch_prediction(int set_cr_z) -{ - unsigned int cr; - - /* System Control Register: 11th bit Z Branch prediction enable */ - cr = get_cr(); - set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z); - - return cr & CR_Z; -} - static void initialize_s5p_mshc(void) { /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ @@ -94,13 +81,16 @@ void main(void) struct arm_clk_ratios *arm_ratios; int ret; void *entry; - - /* FIXME: if we boot from USB, we need to disable branch prediction - * before copying from USB into RAM */ - config_branch_prediction(1); + unsigned int cr; clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ + /* + * FIXME: Do necessary I2C init so low-level PMIC code doesn't need to. + * Also, we should only call power_init() on cold boot. + */ + power_init(); + /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ mem = get_mem_timings(); @@ -109,12 +99,6 @@ void main(void) console_init(); - /* - * FIXME: Do necessary I2C init so low-level PMIC code doesn't need to. - * Also, we should only call power_init() on cold boot. - */ - power_init(); - if (!mem) { printk(BIOS_CRIT, "Unable to auto-detect memory timings\n"); while(1); @@ -132,8 +116,21 @@ void main(void) while(1); } + /* Set up MMU and caches */ mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); + /* Enable D-side prefetch */ + cr = get_acr(); + cr |= (1 << 2); + set_acr(cr); + CP15DSB; + CP15ISB; + + /* FIXME: these functions take because the "generic" cache_enable() + * tries to call mmu_setup if mmu has not already been enabled */ + icache_enable(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); + dcache_enable(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); + initialize_s5p_mshc(); graphics();

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New patch to review for coreboot: c3d086e ASROCK Fam14 DSDT: Add OSC method
by Mike Loptien 15 Mar '13

15 Mar '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2739 -gerrit commit c3d086e49f33ce939a4366fdb5d3be8dd937152c Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Mar 15 13:22:32 2013 -0600 ASROCK Fam14 DSDT: Add OSC method The _OSC method is used to tell the OS what capabilities it can take control over from the firmware. This method is described in chapter 6.2.9 of the ACPI spec v3.0. The method takes 4 inputs (UUID, Rev ID, Input Count, and Capabilities Buffer) and returns a Capabilites Buffer the same size as the input Buffer. This Buffer is generally 3 Dwords long consisting of an Errors Dword, a Supported Capabilities Dword, and a Control Dword. The OS will request control of certain capabilities and the firmware must grant or deny control of those features. We do not want to have control over anything so let the OS control as much as it can. The _OSC method is required for PCIe devices and dmesg checks for its existence and issues an error if it is not found. This is the same change made to Persimmon with Change-ID I149428: http://review.coreboot.org/#/c/2684/ Change-Id: I2701d915338294bdade2ad334b22a51db980892e Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/asrock/e350m1/dsdt.asl | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index bc45435..feec7c9 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -1157,8 +1157,20 @@ DefinitionBlock ( Device(PCI0) { External (TOM1) External (TOM2) - Name(_HID, EISAID("PNP0A03")) + Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ + Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + + /* Operating System Capabilities Method */ + Method(_OSC,4) + { /* Check for proper PCI/PCIe UUID */ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + } + Method(_BBN, 0) { /* Bus number = 0 */ Return(0) }

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Patch merged into coreboot/master: 69efaa0 Google Link: Add remaining code to support native graphics
by gerrit＠coreboot.org 15 Mar '13

15 Mar '13

the following patch was just integrated into master: commit 69efaa0388c2989cd224821adb07715d64623953 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Feb 26 10:07:40 2013 -0800 Google Link: Add remaining code to support native graphics The Link native graphics commit 49428d84 [1] Add support for Google's Chromebook Pixel was missing some of the higher level bits, and hence could not be used. This is not new code -- it has been working since last August -- so the effort now is to get it into the tree and structure it in a way compatible with upstream coreboot. 1. Add options to src/device/Kconfig to enable native graphics. 2. Export the MTRR function for setting variable MTRRs. 3. Clean up some of the comments and white space. While I realize that the product name is Pixel, the mainboard in the coreboot tree is called Link, and that name is what we will use in our commits. [1] http://review.coreboot.org/2482 Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2531 Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Mar 15 19:55:36 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Mar 15 19:52:24 2013, giving +2 See http://review.coreboot.org/2531 for details. -gerrit

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New patch to review for coreboot: e4e6c14 AMD Fam14 DSDT: Add OSC method
by Mike Loptien 15 Mar '13

15 Mar '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2738 -gerrit commit e4e6c145e36e37ae2e0e83f1edbd532e79635acb Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Mar 15 13:17:52 2013 -0600 AMD Fam14 DSDT: Add OSC method The _OSC method is used to tell the OS what capabilities it can take control over from the firmware. This method is described in chapter 6.2.9 of the ACPI spec v3.0. The method takes 4 inputs (UUID, Rev ID, Input Count, and Capabilities Buffer) and returns a Capabilites Buffer the same size as the input Buffer. This Buffer is generally 3 Dwords long consisting of an Errors Dword, a Supported Capabilities Dword, and a Control Dword. The OS will request control of certain capabilities and the firmware must grant or deny control of those features. We do not want to have control over anything so let the OS control as much as it can. The _OSC method is required for PCIe devices and dmesg checks for its existence and issues an error if it is not found. This is the same change made to Persimmon with Change-ID I149428: http://review.coreboot.org/#/c/2684/ Change-Id: If6dd1a558d9c319d9a41ce63588550c8e81e595f Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/amd/inagua/dsdt.asl | 14 +++++++++++++- src/mainboard/amd/south_station/dsdt.asl | 14 +++++++++++++- src/mainboard/amd/union_station/dsdt.asl | 14 +++++++++++++- 3 files changed, 39 insertions(+), 3 deletions(-) diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 148d7b0..dff5917 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -1157,8 +1157,20 @@ DefinitionBlock ( Device(PCI0) { External (TOM1) External (TOM2) - Name(_HID, EISAID("PNP0A03")) + Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ + Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + + /* Operating System Capabilities Method */ + Method(_OSC,4) + { /* Check for proper PCI/PCIe UUID */ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + } + Method(_BBN, 0) { /* Bus number = 0 */ Return(0) } diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 148d7b0..dff5917 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -1157,8 +1157,20 @@ DefinitionBlock ( Device(PCI0) { External (TOM1) External (TOM2) - Name(_HID, EISAID("PNP0A03")) + Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ + Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + + /* Operating System Capabilities Method */ + Method(_OSC,4) + { /* Check for proper PCI/PCIe UUID */ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + } + Method(_BBN, 0) { /* Bus number = 0 */ Return(0) } diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index 1d2435c..b59ea7b 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -1157,8 +1157,20 @@ DefinitionBlock ( Device(PCI0) { External (TOM1) External (TOM2) - Name(_HID, EISAID("PNP0A03")) + Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ + Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + + /* Operating System Capabilities Method */ + Method(_OSC,4) + { /* Check for proper PCI/PCIe UUID */ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + } + Method(_BBN, 0) { /* Bus number = 0 */ Return(0) }

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coreboot March 2013