coreboot March 2013

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New patch to review for coreboot: 5455e38 Add bd82x6x XHCI(USB3) S3/S4 workaround
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2759 -gerrit commit 5455e38d72a5d4e5b9a62f1f419d9bdebdbd8637 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon Feb 11 14:39:28 2013 -0700 Add bd82x6x XHCI(USB3) S3/S4 workaround The bd82x6x requires some additional setting on S3/S4 entry. Change-Id: I24489ab94dd7cd5a4a64044f25153f5b01a45b77 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/southbridge/intel/bd82x6x/smihandler.c | 45 ++++++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 5 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 093da5c..5d5dad1 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -328,15 +328,50 @@ static void southbridge_gate_memory_reset(void) static void xhci_sleep(u8 slp_typ) { - u32 reg32; + u32 reg32, xhci_bar; + u16 reg16; - if (slp_typ == SLP_TYP_S5) { - reg32 = pcie_read_config32(PCH_XHCI_DEV, 0x74); - reg32 |= (1 << 8 | 0x03 ); - pcie_write_config32(PCH_XHCI_DEV, 0x74, reg32); + switch (slp_typ) { + case SLP_TYP_S3: + case SLP_TYP_S4: + reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74); + reg16 &= ~0x03UL; + pcie_write_config32(PCH_XHCI_DEV, 0x74, reg16); + + reg32 = pcie_read_config32(PCH_XHCI_DEV, PCI_COMMAND); + reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pcie_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); + + xhci_bar = pcie_read_config32(PCH_XHCI_DEV, + PCI_BASE_ADDRESS_0) & ~0xFUL; + + if ((xhci_bar + 0x4C0) & 1) + pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); + if ((xhci_bar + 0x4D0) & 1) + pch_iobp_update(0xEC000182, ~0UL, (3 << 2)); + if ((xhci_bar + 0x4E0) & 1) + pch_iobp_update(0xEC000282, ~0UL, (3 << 2)); + if ((xhci_bar + 0x4F0) & 1) + pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); + + reg32 = pcie_read_config32(PCH_XHCI_DEV, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pcie_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); + + reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74); + reg16 |= 0x03; + pcie_write_config16(PCH_XHCI_DEV, 0x74, reg16); + break; + + case SLP_TYP_S5: + reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74); + reg16 |= ((1 << 8) | 0x03); + pcie_write_config16(PCH_XHCI_DEV, 0x74, reg16); + break; } } + static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) { u8 reg8;

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New patch to review for coreboot: 019d64c Add bd82x6x PCH functions to SMM
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2758 -gerrit commit 019d64c446855d621d2a875e96f78469800f5721 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon Feb 11 14:36:35 2013 -0700 Add bd82x6x PCH functions to SMM Add the PCH function to SMM for follow-on SMM patches that require these functions. Change-Id: I7f3a512c5e98446e835b59934d63a99e8af15280 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/southbridge/intel/bd82x6x/Makefile.inc | 2 +- src/southbridge/intel/bd82x6x/pch.c | 150 ++++++++++++++++------------- src/southbridge/intel/bd82x6x/pch.h | 8 +- 3 files changed, 91 insertions(+), 69 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 99dd409..0b0385b 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -42,7 +42,7 @@ ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 9782f1f..f2c7dc1 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -21,8 +21,14 @@ #include <console/console.h> #include <delay.h> +#ifdef __SMM__ +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#else /* !__SMM__ */ #include <device/device.h> #include <device/pci.h> +#endif #include "pch.h" static int pch_revision_id = -1; @@ -30,19 +36,31 @@ static int pch_type = -1; int pch_silicon_revision(void) { + device_t dev; + +#ifdef __SMM__ + dev = PCI_DEV(0, 0x1f, 0); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); +#endif + if (pch_revision_id < 0) - pch_revision_id = pci_read_config8( - dev_find_slot(0, PCI_DEVFN(0x1f, 0)), - PCI_REVISION_ID); + pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID); return pch_revision_id; } int pch_silicon_type(void) { + device_t dev; + +#ifdef __SMM__ + dev = PCI_DEV(0, 0x1f, 0); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); +#endif + if (pch_type < 0) - pch_type = pci_read_config8( - dev_find_slot(0, PCI_DEVFN(0x1f, 0)), - PCI_DEVICE_ID + 1); + pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1); return pch_type; } @@ -71,65 +89,6 @@ int pch_silicon_supported(int type, int rev) return 0; } -/* Set bit in Function Disble register to hide this device */ -static void pch_hide_devfn(unsigned devfn) -{ - switch (devfn) { - case PCI_DEVFN(22, 0): /* MEI #1 */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); - break; - case PCI_DEVFN(22, 1): /* MEI #2 */ - RCBA32_OR(FD2, PCH_DISABLE_MEI2); - break; - case PCI_DEVFN(22, 2): /* IDE-R */ - RCBA32_OR(FD2, PCH_DISABLE_IDER); - break; - case PCI_DEVFN(22, 3): /* KT */ - RCBA32_OR(FD2, PCH_DISABLE_KT); - break; - case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ - RCBA32_OR(BUC, PCH_DISABLE_GBE); - break; - case PCI_DEVFN(26, 0): /* EHCI #2 */ - RCBA32_OR(FD, PCH_DISABLE_EHCI2); - break; - case PCI_DEVFN(27, 0): /* HD Audio Controller */ - RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); - break; - case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ - case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ - case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ - case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ - case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ - case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ - case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ - case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ - RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn))); - break; - case PCI_DEVFN(29, 0): /* EHCI #1 */ - RCBA32_OR(FD, PCH_DISABLE_EHCI1); - break; - case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */ - RCBA32_OR(FD, PCH_DISABLE_P2P); - break; - case PCI_DEVFN(31, 0): /* LPC */ - RCBA32_OR(FD, PCH_DISABLE_LPC); - break; - case PCI_DEVFN(31, 2): /* SATA #1 */ - RCBA32_OR(FD, PCH_DISABLE_SATA1); - break; - case PCI_DEVFN(31, 3): /* SMBUS */ - RCBA32_OR(FD, PCH_DISABLE_SMBUS); - break; - case PCI_DEVFN(31, 5): /* SATA #22 */ - RCBA32_OR(FD, PCH_DISABLE_SATA2); - break; - case PCI_DEVFN(31, 6): /* Thermal Subsystem */ - RCBA32_OR(FD, PCH_DISABLE_THERMAL); - break; - } -} - #define IOBP_RETRY 1000 static inline int iobp_poll(void) { @@ -191,6 +150,66 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) return; } +#ifndef __SMM__ +/* Set bit in Function Disble register to hide this device */ +static void pch_hide_devfn(unsigned devfn) +{ + switch (devfn) { + case PCI_DEVFN(22, 0): /* MEI #1 */ + RCBA32_OR(FD2, PCH_DISABLE_MEI1); + break; + case PCI_DEVFN(22, 1): /* MEI #2 */ + RCBA32_OR(FD2, PCH_DISABLE_MEI2); + break; + case PCI_DEVFN(22, 2): /* IDE-R */ + RCBA32_OR(FD2, PCH_DISABLE_IDER); + break; + case PCI_DEVFN(22, 3): /* KT */ + RCBA32_OR(FD2, PCH_DISABLE_KT); + break; + case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ + RCBA32_OR(BUC, PCH_DISABLE_GBE); + break; + case PCI_DEVFN(26, 0): /* EHCI #2 */ + RCBA32_OR(FD, PCH_DISABLE_EHCI2); + break; + case PCI_DEVFN(27, 0): /* HD Audio Controller */ + RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); + break; + case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ + case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ + case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ + case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ + case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ + case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ + case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ + case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ + RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn))); + break; + case PCI_DEVFN(29, 0): /* EHCI #1 */ + RCBA32_OR(FD, PCH_DISABLE_EHCI1); + break; + case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */ + RCBA32_OR(FD, PCH_DISABLE_P2P); + break; + case PCI_DEVFN(31, 0): /* LPC */ + RCBA32_OR(FD, PCH_DISABLE_LPC); + break; + case PCI_DEVFN(31, 2): /* SATA #1 */ + RCBA32_OR(FD, PCH_DISABLE_SATA1); + break; + case PCI_DEVFN(31, 3): /* SMBUS */ + RCBA32_OR(FD, PCH_DISABLE_SMBUS); + break; + case PCI_DEVFN(31, 5): /* SATA #22 */ + RCBA32_OR(FD, PCH_DISABLE_SATA2); + break; + case PCI_DEVFN(31, 6): /* Thermal Subsystem */ + RCBA32_OR(FD, PCH_DISABLE_THERMAL); + break; + } +} + /* Check if any port in set X to X+3 is enabled */ static int pch_pcie_check_set_enabled(device_t dev) { @@ -408,3 +427,4 @@ struct chip_operations southbridge_intel_bd82x6x_ops = { CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge") .enable_dev = pch_enable, }; +#endif diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index ca54418..7f64571 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -57,17 +57,19 @@ void intel_pch_finalize_smm(void); #endif #if !defined(__ASSEMBLER__) && !defined(__ROMCC__) -#if !defined(__PRE_RAM__) && !defined(__SMM__) +#if !defined(__PRE_RAM__) +#if !defined(__SMM__) #include "chip.h" +void pch_enable(device_t dev); +#endif int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); -void pch_enable(device_t dev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #if CONFIG_ELOG void pch_log_state(void); #endif -#else +#else /* __PRE_RAM__ */ void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address);

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New patch to review for coreboot: ac80aac haswell: add romstage_after_car() function
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2757 -gerrit commit ac80aacaeced2eaa0fac2077facb091600508840 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Feb 8 22:18:04 2013 -0600 haswell: add romstage_after_car() function There are changes coming to perform more complex tasks after cache-as-ram has been torn down but before ramstage is loaded. Therefore, add the romstage_after_car() function to call after cache-as-ram is torn down. Its responsibility is for loading the ramstage and any other complex tasks. For example, the saving of OS-controlled memory in the resume path has now been moved into C instead of assembly. Change-Id: Ie0c229cf83a9271c8995b31c534c8e5a696b164e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/cache_as_ram.inc | 30 +----------------------------- src/cpu/intel/haswell/haswell.h | 3 +++ src/cpu/intel/haswell/romstage.c | 21 +++++++++++++++++++++ 3 files changed, 25 insertions(+), 29 deletions(-) diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 5fb5712..8601f46 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -305,38 +305,10 @@ before_romstage: post_code(0x3c) -#if CONFIG_HAVE_ACPI_RESUME - movl CBMEM_BOOT_MODE, %eax - cmpl $0x2, %eax // Resume? - jne __acpi_resume_backup_done - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high - * tables memory completely, but that's a wonderful clean up task for - * another day. - */ - cld - movl $CONFIG_RAMBASE, %esi - movl CBMEM_RESUME_BACKUP, %edi - movl $HIGH_MEMORY_SAVE / 4, %ecx - rep movsl - -__acpi_resume_backup_done: -#endif - - post_code(0x3d) - - /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - - movl %ebp, %esi - - movl %esp, %ebp - pushl %esi - call copy_and_run + call romstage_after_car .Lhlt: post_code(POST_DEAD_CODE) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 7a55ef7..733ddd3 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -129,6 +129,9 @@ void romstage_common(const struct romstage_params *params); * ... */ void * __attribute__((regparm(0))) romstage_main(unsigned long bist); +/* romstage_after_car() is the C function called after cache-as-ram has + * been torn down. It is responsible for loading the ramstage. */ +void romstage_after_car(void); #endif #ifdef __SMM__ diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 3ce04e2..d62377e 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -18,6 +18,7 @@ */ #include <stdint.h> +#include <string.h> #include <cbmem.h> #include <console/console.h> #include <arch/cpu.h> @@ -28,6 +29,7 @@ #include <lib.h> #include <timestamp.h> #include <arch/io.h> +#include <arch/stages.h> #include <arch/romcc_io.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> @@ -272,3 +274,22 @@ void romstage_common(const struct romstage_params *params) timestamp_add_now(TS_END_ROMSTAGE); #endif } + +static inline void prepare_for_resume(void) +{ +#if CONFIG_HAVE_ACPI_RESUME + /* Back up the OS-controlled memory where ramstage will be loaded. */ + if (*(u32 *)CBMEM_BOOT_MODE == 2) { + void *src = (void *)CONFIG_RAMBASE; + void *dest = *(void **)CBMEM_RESUME_BACKUP; + memcpy(dest, src, HIGH_MEMORY_SAVE); + } +#endif +} + +void romstage_after_car(void) +{ + prepare_for_resume(); + /* Load the ramstage. */ + copy_and_run(0); +}

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New patch to review for coreboot: e0ba95f haswell: move call site of save_mrc_data()
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2756 -gerrit commit e0ba95f5f99992cb6d80075c09844f629c921466 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Feb 7 00:51:18 2013 -0600 haswell: move call site of save_mrc_data() The save_mrc_data() was previously called conditionally in the raminit code. The save_mrc_data() function was called in the non-S3 wake paths. However, the common romstage_common() code was checking cbmem initialization things on s3 wake. Between the two callers cbmem_initialize() was being called twice in the non-s3 wake paths. Moreover, saving of the mrc data was not allowed when CONFIG_EARLY_CBMEM_INIT wasn't enabled. Therefore, move the save_mrc_data() to romstage_common. It already has the knowledge of the wake path. Also remove the CONFIG_EARLY_CBMEM_INIT requirement from save_mrc_data() as well as the call to cbmem_initialize(). Change-Id: I7f0e4d752c92d9d5eedb8fa56133ec190caf77da Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/romstage.c | 4 ++++ src/northbridge/intel/haswell/raminit.c | 9 +-------- src/northbridge/intel/haswell/raminit.h | 2 ++ 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 8b0e2cc..3ce04e2 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -230,6 +230,10 @@ void romstage_common(const struct romstage_params *params) - HIGH_MEMORY_SIZE)); #endif + /* Save data returned from MRC on non-S3 resumes. */ + if (boot_mode != 2) + save_mrc_data(params->pei_data); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 8a38e76..1439200 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -38,14 +38,12 @@ #define recovery_mode_enabled(x) 0 #endif -static void save_mrc_data(struct pei_data *pei_data) +void save_mrc_data(struct pei_data *pei_data) { -#if CONFIG_EARLY_CBMEM_INIT struct mrc_data_container *mrcdata; int output_len = ALIGN(pei_data->mrc_output_len, 16); /* Save the MRC S3 restore data to cbmem */ - cbmem_initialize(); mrcdata = cbmem_add (CBMEM_ID_MRCDATA, output_len + sizeof(struct mrc_data_container)); @@ -66,7 +64,6 @@ static void save_mrc_data(struct pei_data *pei_data) mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, mrcdata->mrc_data_size); -#endif } static void prepare_mrc_cache(struct pei_data *pei_data) @@ -204,10 +201,6 @@ void sdram_initialize(struct pei_data *pei_data) (version >> 8) & 0xff, version & 0xff); report_memory_config(); - - /* S3 resume: don't save scrambler seed or MRC data */ - if (pei_data->boot_mode != 2) - save_mrc_data(pei_data); } struct cbmem_entry *get_cbmem_toc(void) diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index f94dea8..46be570 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -25,5 +25,7 @@ void sdram_initialize(struct pei_data *pei_data); unsigned long get_top_of_ram(void); int fixup_haswell_errata(void); +/* save_mrc_data() must be called after cbmem has been initialized. */ +void save_mrc_data(struct pei_data *pei_data); #endif /* RAMINIT_H */

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New patch to review for coreboot: 0e64b4a haswell: romstage: pass stack pointer and MTRRs
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2755 -gerrit commit 0e64b4a773edefeb528395636043f1d5f79ac362 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Feb 7 00:03:33 2013 -0600 haswell: romstage: pass stack pointer and MTRRs Instead of hard coding the policy for the stack and MTRR values after the cache-as-ram is torn down, allow for the C code to pass those policies back to the cache-as-ram assembly file. That way, ramstage relocation can use a different stack as well as different MTRR policies. Change-Id: Ied024d933f96a12ed0703c51c506586f4b50bd14 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/cache_as_ram.inc | 51 ++++++++++-------- src/cpu/intel/haswell/haswell.h | 16 ++++++ src/cpu/intel/haswell/romstage.c | 95 +++++++++++++++++++++++++++++++--- 3 files changed, 133 insertions(+), 29 deletions(-) diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 72b4958..5fb5712 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -182,7 +182,11 @@ clear_mtrrs: before_romstage: post_code(0x29) /* Call romstage.c main function. */ - call main + call romstage_main + /* Save return value from romstage_main. It contains the stack to use + * after cache-as-ram is torn down. It also contains the information + * for setting up MTTRs. */ + movl %eax, %ebx post_code(0x2f) @@ -251,30 +255,34 @@ before_romstage: post_code(0x38) - /* Enable Write Back and Speculative Reads for the first MB - * and coreboot_ram. - */ - movl $MTRRphysBase_MSR(0), %ecx - movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx // 36bit address space - wrmsr + /* Setup stack as indicated by return value from ramstage_main(). */ + movl %ebx, %esp - /* Enable Caching and speculative Reads for the - * complete ROM now that we actually have RAM. - */ - movl $MTRRphysBase_MSR(1), %ecx - movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx + /* Get number of MTTRs. */ + popl %ebx + movl $MTRRphysBase_MSR(0), %ecx +1: + testl %ebx, %ebx + jz 1f + + /* Low 32 bits of MTTR base. */ + popl %eax + /* Upper 32 bits of MTTR base. */ + popl %edx + /* Write MTRR base. */ wrmsr - movl $MTRRphysMask_MSR(1), %ecx - movl $(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx + inc %ecx + /* Low 32 bits of MTTR mask. */ + popl %eax + /* Upper 32 bits of MTTR mask. */ + popl %edx + /* Write MTRR mask. */ wrmsr + inc %ecx + dec %ebx + jmp 1b +1: post_code(0x39) /* And enable cache again after setting MTRRs. */ @@ -326,7 +334,6 @@ __main: movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp movl %esp, %ebp pushl %esi call copy_and_run diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 3ced0c0..7a55ef7 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -113,6 +113,22 @@ struct romstage_params { }; void mainboard_romstage_entry(unsigned long bist); void romstage_common(const struct romstage_params *params); +/* romstage_main is called from the cache-as-ram assembly file. The return + * value is the stack value to be used for romstage once cache-as-ram is + * torn down. The following values are pushed onto the stack to setup the + * MTRRs: + * +0: Number of MTRRs + * +4: MTTR base 0 31:0 + * +8: MTTR base 0 63:32 + * +12: MTTR mask 0 31:0 + * +16: MTTR mask 0 63:32 + * +20: MTTR base 1 31:0 + * +24: MTTR base 1 63:32 + * +28: MTTR mask 1 31:0 + * +32: MTTR mask 1 63:32 + * ... + */ +void * __attribute__((regparm(0))) romstage_main(unsigned long bist); #endif #ifdef __SMM__ diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 1d00af1..8b0e2cc 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -23,6 +23,8 @@ #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/stack.h> #include <lib.h> #include <timestamp.h> #include <arch/io.h> @@ -40,16 +42,90 @@ #include "southbridge/intel/lynxpoint/me.h" -/* The cache-as-ram assembly file calls main() after setting up cache-as-ram. - * main() will then call the mainboards's mainboard_romstage_entry() function. - * That function then calls romstage_common() below. The reason for the back - * and forth is to provide common entry point from cache-as-ram while still - * allowing for code sharing. Because we can't use global variables the stack - * is used for allocations -- thus the need to call back and forth. */ +/* The cache-as-ram assembly file calls romstage_main() after setting up + * cache-as-ram. romstage_main() will then call the mainboards's + * mainboard_romstage_entry() function. That function then calls + * romstage_common() below. The reason for the back and forth is to provide + * common entry point from cache-as-ram while still allowing for code sharing. + * Because we can't use global variables the stack is used for allocations -- + * thus the need to call back and forth. */ -void main(unsigned long bist) + +static inline u32 *stack_push(u32 *stack, u32 value) +{ + stack = &stack[-1]; + *stack = value; + return stack; +} + +/* setup_romstage_stack_after_car() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ +static void *setup_romstage_stack_after_car(void) +{ + unsigned long top_of_stack; + int num_mtrrs; + u32 *slot; + u32 mtrr_mask_upper; + + /* Top of stack needs to be aligned to a 4-byte boundary. */ + top_of_stack = ROMSTAGE_STACK & ~3; + slot = (void *)top_of_stack; + num_mtrrs = 0; + + /* The upper bits of the MTRR mask need to set according to the number + * of physical address bits. */ + mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; + + /* The order for each MTTR is value then base with upper 32-bits of + * each value coming before the lower 32-bits. The reasoning for + * this ordering is to create a stack layout like the following: + * +0: Number of MTRRs + * +4: MTTR base 0 31:0 + * +8: MTTR base 0 63:32 + * +12: MTTR mask 0 31:0 + * +16: MTTR mask 0 63:32 + * +20: MTTR base 1 31:0 + * +24: MTTR base 1 63:32 + * +28: MTTR mask 1 31:0 + * +32: MTTR mask 1 63:32 + */ + + /* Cache the ROM as WP just below 4GiB. */ + slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); + slot = stack_push(slot, 0); /* upper base */ + slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); + num_mtrrs++; + + /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ + slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); + slot = stack_push(slot, 0); /* upper base */ + slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); + num_mtrrs++; + + /* Cache 8MiB below the top of ram. On haswell systems the top of + * ram under 4GiB is the start of the TSEG region. It is required to + * be 8MiB aligned. Set this area as cacheable so it can be used later + * for ramstage before setting up the entire RAM as cacheable. */ + slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); + slot = stack_push(slot, 0); /* upper base */ + slot = stack_push(slot, + (get_top_of_ram() - (8 << 20)) | MTRR_TYPE_WRBACK); + num_mtrrs++; + + /* Save the number of MTTRs to setup. Return the stack location + * pointing to the number of MTRRs. */ + slot = stack_push(slot, num_mtrrs); + + return slot; +} + +void * __attribute__((regparm(0))) romstage_main(unsigned long bist) { int i; + void *romstage_stack_after_car; const int num_guards = 4; const u32 stack_guard = 0xdeadbeef; u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE + @@ -69,10 +145,15 @@ void main(unsigned long bist) printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); } + /* Get the stack to use after cache-as-ram is torn down. */ + romstage_stack_after_car = setup_romstage_stack_after_car(); + #if CONFIG_CONSOLE_CBMEM /* Keep this the last thing this function does. */ cbmemc_reinit(); #endif + + return romstage_stack_after_car; } void romstage_common(const struct romstage_params *params)

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New patch to review for coreboot: 0c9bc70 haswell: unify romstage logic
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2754 -gerrit commit 0c9bc70c993ef45577984e8f2fd038056dbce5fc Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 6 21:41:01 2013 -0600 haswell: unify romstage logic This commit pulls in all the common logic for romstage into the Haswell cpu directory. The bits specific to the mainboard still reside under their respective directories. The calling sequence bounces from the cpu directory to mainboard then back to the cpu directory. The reasoning is that Haswell systems use cache-as-ram for backing memory in romstage. The stack is used to allocate structures. However, now changes can be made to the romstage for Haswell and apply to all boards. Change-Id: I2bf08013c46a99235ffe4bde88a935c3378eb341 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/haswell.h | 11 ++- src/cpu/intel/haswell/romstage.c | 142 +++++++++++++++++++++++++++- src/mainboard/intel/baskingridge/romstage.c | 136 ++------------------------ src/mainboard/intel/wtm1/romstage.c | 135 ++------------------------ src/mainboard/intel/wtm2/romstage.c | 135 ++------------------------ 5 files changed, 176 insertions(+), 383 deletions(-) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 8d91dba..3ced0c0 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -103,7 +103,16 @@ #ifndef __ROMCC__ #if defined(__PRE_RAM__) -void romstage_main(unsigned long bist); +struct pei_data; +struct rcba_config_instruction; +struct romstage_params { + struct pei_data *pei_data; + const void *gpio_map; + const struct rcba_config_instruction *rcba_config; + unsigned long bist; +}; +void mainboard_romstage_entry(unsigned long bist); +void romstage_common(const struct romstage_params *params); #endif #ifdef __SMM__ diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index f954b91..1d00af1 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -20,9 +20,32 @@ #include <stdint.h> #include <cbmem.h> #include <console/console.h> +#include <arch/cpu.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <cpu/x86/lapic.h> +#include <cbmem.h> +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/chromeos.h> +#endif +#include "haswell.h" +#include "northbridge/intel/haswell/haswell.h" +#include "northbridge/intel/haswell/raminit.h" +#include "southbridge/intel/lynxpoint/pch.h" +#include "southbridge/intel/lynxpoint/me.h" + -/* Mainboard needs to supply this symbol. */ -extern void romstage_main(unsigned long bist); +/* The cache-as-ram assembly file calls main() after setting up cache-as-ram. + * main() will then call the mainboards's mainboard_romstage_entry() function. + * That function then calls romstage_common() below. The reason for the back + * and forth is to provide common entry point from cache-as-ram while still + * allowing for code sharing. Because we can't use global variables the stack + * is used for allocations -- thus the need to call back and forth. */ void main(unsigned long bist) { @@ -37,7 +60,7 @@ void main(unsigned long bist) for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; - romstage_main(bist); + mainboard_romstage_entry(bist); /* Check the stack. */ for (i = 0; i < num_guards; i++) { @@ -51,3 +74,116 @@ void main(unsigned long bist) cbmemc_reinit(); #endif } + +void romstage_common(const struct romstage_params *params) +{ + int boot_mode = 0; + int wake_from_s3; + int cbmem_was_initted; + +#if CONFIG_COLLECT_TIMESTAMPS + tsc_t start_romstage_time; + tsc_t before_dram_time; + tsc_t after_dram_time; + tsc_t base_time = { + .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), + .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) + }; +#endif + +#if CONFIG_COLLECT_TIMESTAMPS + start_romstage_time = rdtsc(); +#endif + + if (params->bist == 0) + enable_lapic(); + + wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); + + /* Halt if there was a built in self test failure */ + report_bist_failure(params->bist); + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + haswell_early_initialization(HASWELL_MOBILE); + printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); + + if (wake_from_s3) { +#if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; +#else + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); +#endif + } + + /* Prepare USB controller early in S3 resume */ + if (boot_mode == 2) + enable_usb_bar(); + + post_code(0x3a); + params->pei_data->boot_mode = boot_mode; +#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = rdtsc(); +#endif + + report_platform_info(); + + sdram_initialize(params->pei_data); + +#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = rdtsc(); +#endif + post_code(0x3b); + + intel_early_me_status(); + + quick_ram_check(); + post_code(0x3e); + +#if CONFIG_EARLY_CBMEM_INIT + cbmem_was_initted = !cbmem_initialize(); +#else + cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() + - HIGH_MEMORY_SIZE)); +#endif + +#if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + + *(u32 *)CBMEM_BOOT_MODE = 0; + *(u32 *)CBMEM_RESUME_BACKUP = 0; + + if ((boot_mode == 2) && cbmem_was_initted) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (resume_backup_memory) { + *(u32 *)CBMEM_BOOT_MODE = boot_mode; + *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; + } + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } else if (boot_mode == 2) { + /* Failed S3 resume, reset to come up cleanly */ + outb(0x6, 0xcf9); + while (1) { + hlt(); + } + } else { + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + } +#endif + post_code(0x3f); +#if CONFIG_CHROMEOS + init_chromeos(boot_mode); +#endif +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); + timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); + timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); + timestamp_add(TS_AFTER_INITRAM, after_dram_time ); + timestamp_add_now(TS_END_ROMSTAGE); +#endif +} diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 45316f6..3659254 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -19,29 +19,12 @@ */ #include <stdint.h> -#include <string.h> -#include <lib.h> -#include <timestamp.h> -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_def.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <cbmem.h> #include <console/console.h> #include "cpu/intel/haswell/haswell.h" #include "northbridge/intel/haswell/haswell.h" #include "northbridge/intel/haswell/raminit.h" #include "southbridge/intel/lynxpoint/pch.h" -#include "southbridge/intel/lynxpoint/me.h" -#include <arch/cpu.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/msr.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif const struct rcba_config_instruction rcba_config[] = { /* @@ -83,21 +66,8 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void romstage_main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { - int boot_mode = 0; - int wake_from_s3; - int cbmem_was_initted; - -#if CONFIG_COLLECT_TIMESTAMPS - tsc_t start_romstage_time; - tsc_t before_dram_time; - tsc_t after_dram_time; - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; -#endif struct pei_data pei_data = { pei_version: PEI_VERSION, mchbar: DEFAULT_MCHBAR, @@ -141,101 +111,13 @@ void romstage_main(unsigned long bist) }, }; -#if CONFIG_COLLECT_TIMESTAMPS - start_romstage_time = rdtsc(); -#endif - - if (bist == 0) - enable_lapic(); - - wake_from_s3 = early_pch_init(&mainboard_gpio_map, &rcba_config[0]); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - haswell_early_initialization(HASWELL_MOBILE); - printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); - - if (wake_from_s3) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif - } - - /* Prepare USB controller early in S3 resume */ - if (boot_mode == 2) - enable_usb_bar(); - - post_code(0x3a); - pei_data.boot_mode = boot_mode; -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = rdtsc(); -#endif - - report_platform_info(); - - sdram_initialize(&pei_data); - -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = rdtsc(); -#endif - post_code(0x3b); - - intel_early_me_status(); - - quick_ram_check(); - post_code(0x3e); - - MCHBAR16(SSKPD) = 0xCAFE; -#if CONFIG_EARLY_CBMEM_INIT - cbmem_was_initted = !cbmem_initialize(); -#else - cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() - - HIGH_MEMORY_SIZE)); -#endif - -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + .bist = bist, + }; - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - while (1) { - hlt(); - } - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); - } -#endif - post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); - timestamp_add(TS_AFTER_INITRAM, after_dram_time ); - timestamp_add_now(TS_END_ROMSTAGE); -#endif + /* Call into the real romstage main with this board's attributes. */ + romstage_common(&romstage_params); } - diff --git a/src/mainboard/intel/wtm1/romstage.c b/src/mainboard/intel/wtm1/romstage.c index c80c721..525bd6f 100644 --- a/src/mainboard/intel/wtm1/romstage.c +++ b/src/mainboard/intel/wtm1/romstage.c @@ -19,30 +19,13 @@ */ #include <stdint.h> -#include <string.h> -#include <lib.h> -#include <timestamp.h> -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_def.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <cbmem.h> #include <console/console.h> #include "cpu/intel/haswell/haswell.h" #include "northbridge/intel/haswell/haswell.h" #include "northbridge/intel/haswell/raminit.h" -#include "southbridge/intel/lynxpoint/me.h" #include "southbridge/intel/lynxpoint/pch.h" #include "southbridge/intel/lynxpoint/lp_gpio.h" -#include <arch/cpu.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/msr.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif const struct rcba_config_instruction rcba_config[] = { @@ -88,21 +71,8 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void romstage_main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { - int boot_mode = 0; - int wake_from_s3; - int cbmem_was_initted; - -#if CONFIG_COLLECT_TIMESTAMPS - tsc_t start_romstage_time; - tsc_t before_dram_time; - tsc_t after_dram_time; - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; -#endif struct pei_data pei_data = { pei_version: PEI_VERSION, mchbar: DEFAULT_MCHBAR, @@ -146,100 +116,13 @@ void romstage_main(unsigned long bist) }, }; -#if CONFIG_COLLECT_TIMESTAMPS - start_romstage_time = rdtsc(); -#endif - - if (bist == 0) - enable_lapic(); - - wake_from_s3 = early_pch_init(&mainboard_gpio_map, &rcba_config[0]); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - haswell_early_initialization(HASWELL_MOBILE); - printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); - - if (wake_from_s3) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif - } - - /* Prepare USB controller early in S3 resume */ - if (boot_mode == 2) - enable_usb_bar(); - - post_code(0x3a); - pei_data.boot_mode = boot_mode; -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = rdtsc(); -#endif - - report_platform_info(); - - sdram_initialize(&pei_data); - -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = rdtsc(); -#endif - post_code(0x3b); - - intel_early_me_status(); - - quick_ram_check(); - post_code(0x3e); - - MCHBAR16(SSKPD) = 0xCAFE; -#if CONFIG_EARLY_CBMEM_INIT - cbmem_was_initted = !cbmem_initialize(); -#else - cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() - - HIGH_MEMORY_SIZE)); -#endif - -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + .bist = bist, + }; - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - while (1) { - hlt(); - } - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); - } -#endif - post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); - timestamp_add(TS_AFTER_INITRAM, after_dram_time ); - timestamp_add_now(TS_END_ROMSTAGE); -#endif + /* Call into the real romstage main with this board's attributes. */ + romstage_common(&romstage_params); } diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 4737073..b0232ec 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -19,30 +19,13 @@ */ #include <stdint.h> -#include <string.h> -#include <lib.h> -#include <timestamp.h> -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_def.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <cbmem.h> #include <console/console.h> #include "cpu/intel/haswell/haswell.h" #include "northbridge/intel/haswell/haswell.h" #include "northbridge/intel/haswell/raminit.h" -#include "southbridge/intel/lynxpoint/me.h" #include "southbridge/intel/lynxpoint/pch.h" #include "southbridge/intel/lynxpoint/lp_gpio.h" -#include <arch/cpu.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/msr.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif const struct rcba_config_instruction rcba_config[] = { @@ -88,21 +71,8 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void romstage_main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { - int boot_mode = 0; - int wake_from_s3; - int cbmem_was_initted; - -#if CONFIG_COLLECT_TIMESTAMPS - tsc_t start_romstage_time; - tsc_t before_dram_time; - tsc_t after_dram_time; - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; -#endif struct pei_data pei_data = { pei_version: PEI_VERSION, mchbar: DEFAULT_MCHBAR, @@ -146,100 +116,13 @@ void romstage_main(unsigned long bist) }, }; -#if CONFIG_COLLECT_TIMESTAMPS - start_romstage_time = rdtsc(); -#endif - - if (bist == 0) - enable_lapic(); - - wake_from_s3 = early_pch_init(&mainboard_gpio_map, &rcba_config[0]); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - haswell_early_initialization(HASWELL_MOBILE); - printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); - - if (wake_from_s3) { -#if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif - } - - /* Prepare USB controller early in S3 resume */ - if (boot_mode == 2) - enable_usb_bar(); - - post_code(0x3a); - pei_data.boot_mode = boot_mode; -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = rdtsc(); -#endif - - report_platform_info(); - - sdram_initialize(&pei_data); - -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = rdtsc(); -#endif - post_code(0x3b); - - intel_early_me_status(); - - quick_ram_check(); - post_code(0x3e); - - MCHBAR16(SSKPD) = 0xCAFE; -#if CONFIG_EARLY_CBMEM_INIT - cbmem_was_initted = !cbmem_initialize(); -#else - cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() - - HIGH_MEMORY_SIZE)); -#endif - -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + .bist = bist, + }; - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - while (1) { - hlt(); - } - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); - } -#endif - post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); - timestamp_add(TS_AFTER_INITRAM, after_dram_time ); - timestamp_add_now(TS_END_ROMSTAGE); -#endif + /* Call into the real romstage main with this board's attributes. */ + romstage_common(&romstage_params); }

1 0

New patch to review for coreboot: 2ae7c27 haswell: remove unused sys_info structure
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2753 -gerrit commit 2ae7c276a18a7e598bfef0355065ddb4182b2ce0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Feb 7 00:09:59 2013 -0600 haswell: remove unused sys_info structure This structure is not used nor the variable being instantiated on the stack. Remove them. Change-Id: If3abe2dd77104eff49665dd33570b07179bf34f5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/northbridge/intel/haswell/raminit.c | 5 ----- src/northbridge/intel/haswell/raminit.h | 7 ------- 2 files changed, 12 deletions(-) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index e2b085b..8a38e76 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -147,15 +147,10 @@ static void report_memory_config(void) */ void sdram_initialize(struct pei_data *pei_data) { - struct sys_info sysinfo; unsigned long entry; printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); - memset(&sysinfo, 0, sizeof(sysinfo)); - - sysinfo.boot_path = pei_data->boot_mode; - /* * Do not pass MRC data in for recovery mode boot, * Always pass it in for S3 resume. diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index 958e983..f94dea8 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -22,13 +22,6 @@ #include "pei_data.h" -struct sys_info { - u8 boot_path; -#define BOOT_PATH_NORMAL 0 -#define BOOT_PATH_RESET 1 -#define BOOT_PATH_RESUME 2 -} __attribute__ ((packed)); - void sdram_initialize(struct pei_data *pei_data); unsigned long get_top_of_ram(void); int fixup_haswell_errata(void);

1 0

New patch to review for coreboot: c7aaf88 haswell: adjust CAR usage
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2752 -gerrit commit c7aaf889cdeba2454c2d56abe86b7f5bec46def5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 18 14:32:50 2013 -0600 haswell: adjust CAR usage It was found that the Haswell reference code was smashing through the stack into the reference code's heap implementation. The reason for this is because our current CAR allocation is too small. Moreover there are quite a few things to coordinate between 2 code bases to get correct. This commit separates the CAR into 2 parts: 1. MRC CAR usage. 2. Coreboot CAR usage. Pointers from one region can be passed between the 2 modules, but one should not be able to affect the others as checking has been put into place in both modules. The CAR size has effectively been doubled from 0x20000 (128 KiB) to 0x40000 (256KiB). Not all of that increase was needed, but enforcing a power of 2 size only utilizes 1 MTRR. Old CAR layout with a single contiguous stack with the region starting at CONFIG_DCACHE_RAM_BASE: +---------------------------------------+ Offset CONFIG_DCACHE_RAM_SIZE | MRC global variables | | CONFIG_DCACHE_RAM_MRC_VAR_SIZE bytes | +---------------------------------------+ | ROM stage stack | | | | | +---------------------------------------+ | MRC Heap 30000 bytes | +---------------------------------------+ | ROM stage console | | CONFIG_CONSOLE_CAR_BUFFER_SIZE bytes | +---------------------------------------+ | ROM stage CAR_GLOBAL variables | +---------------------------------------+ Offset 0 There was some hard coded offsets in the reference code wrapper to start the heap past the console buffer. Even with this commit the console can smash into the following region depending on what size CONFIG_CONSOLE_CAR_BUFFER_SIZE is. As noted above This change splits the CAR region into 2 parts starting at CONFIG_DCACHE_RAM_BASE: +---------------------------------------+ | MRC Region | | CONFIG_DCACHE_RAM_MRC_VAR_SIZE bytes | +---------------------------------------+ Offset CONFIG_DCACHE_RAM_SIZE | ROM stage stack | | | | | +---------------------------------------+ | ROM stage console | | CONFIG_CONSOLE_CAR_BUFFER_SIZE bytes | +---------------------------------------+ | ROM stage CAR_GLOBAL variables | +---------------------------------------+ Offset 0 Another variable was add, CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE, which represents the expected stack usage for the romstage. A marker is checked at the base of the stack to determine if either the stack was smashed or the console encroached on the stack. Change-Id: Id76f2fe4a5cf1c776c8f0019f406593f68e443a7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/Makefile.inc | 1 + src/cpu/intel/haswell/cache_as_ram.inc | 11 +++--- src/cpu/intel/haswell/haswell.h | 5 +++ src/cpu/intel/haswell/romstage.c | 53 +++++++++++++++++++++++++++++ src/mainboard/intel/baskingridge/romstage.c | 8 ++--- src/mainboard/intel/wtm1/romstage.c | 7 ++-- src/mainboard/intel/wtm2/romstage.c | 7 ++-- src/northbridge/intel/haswell/Kconfig | 19 +++++++++-- 8 files changed, 89 insertions(+), 22 deletions(-) diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 67b0954..b2116f2 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += haswell_init.c subdirs-y += ../../x86/name +romstage-y += romstage.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index f5ee82e..72b4958 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -24,7 +24,11 @@ #include <cpu/x86/post_code.h> #include <cbmem.h> -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +/* The full cache-as-ram size includes the cache-as-ram portion from coreboot + * and the space used by the reference code. These 2 values combined should + * be a power of 2 because the MTRR setup assumes that. */ +#define CACHE_AS_RAM_SIZE \ + (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE /* Cache 4GB - MRC_SIZE_KB for MRC */ @@ -166,9 +170,8 @@ clear_mtrrs: andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 - /* Set up the stack pointer below MRC variable space. */ - movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \ - CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4), %eax + /* Setup the stack. */ + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax movl %eax, %esp /* Restore the BIST result. */ diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index cb85078..8d91dba 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -101,6 +101,11 @@ #define PSS_LATENCY_BUSMASTER 10 #ifndef __ROMCC__ + +#if defined(__PRE_RAM__) +void romstage_main(unsigned long bist); +#endif + #ifdef __SMM__ /* Lock MSRs */ void intel_cpu_haswell_finalize_smm(void); diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c new file mode 100644 index 0000000..f954b91 --- /dev/null +++ b/src/cpu/intel/haswell/romstage.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 ChromeOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cbmem.h> +#include <console/console.h> + +/* Mainboard needs to supply this symbol. */ +extern void romstage_main(unsigned long bist); + +void main(unsigned long bist) +{ + int i; + const int num_guards = 4; + const u32 stack_guard = 0xdeadbeef; + u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - + CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE); + + printk(BIOS_DEBUG, "Setting up stack guards.\n"); + for (i = 0; i < num_guards; i++) + stack_base[i] = stack_guard; + + romstage_main(bist); + + /* Check the stack. */ + for (i = 0; i < num_guards; i++) { + if (stack_base[i] == stack_guard) + continue; + printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); + } + +#if CONFIG_CONSOLE_CBMEM + /* Keep this the last thing this function does. */ + cbmemc_reinit(); +#endif +} diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index d47fbf1..45316f6 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -30,6 +30,7 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> +#include "cpu/intel/haswell/haswell.h" #include "northbridge/intel/haswell/haswell.h" #include "northbridge/intel/haswell/raminit.h" #include "southbridge/intel/lynxpoint/pch.h" @@ -82,7 +83,7 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void main(unsigned long bist) +void romstage_main(unsigned long bist) { int boot_mode = 0; int wake_from_s3; @@ -236,8 +237,5 @@ void main(unsigned long bist) timestamp_add(TS_AFTER_INITRAM, after_dram_time ); timestamp_add_now(TS_END_ROMSTAGE); #endif -#if CONFIG_CONSOLE_CBMEM - /* Keep this the last thing this function does. */ - cbmemc_reinit(); -#endif } + diff --git a/src/mainboard/intel/wtm1/romstage.c b/src/mainboard/intel/wtm1/romstage.c index 0190964..c80c721 100644 --- a/src/mainboard/intel/wtm1/romstage.c +++ b/src/mainboard/intel/wtm1/romstage.c @@ -30,6 +30,7 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> +#include "cpu/intel/haswell/haswell.h" #include "northbridge/intel/haswell/haswell.h" #include "northbridge/intel/haswell/raminit.h" #include "southbridge/intel/lynxpoint/me.h" @@ -87,7 +88,7 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void main(unsigned long bist) +void romstage_main(unsigned long bist) { int boot_mode = 0; int wake_from_s3; @@ -241,8 +242,4 @@ void main(unsigned long bist) timestamp_add(TS_AFTER_INITRAM, after_dram_time ); timestamp_add_now(TS_END_ROMSTAGE); #endif -#if CONFIG_CONSOLE_CBMEM - /* Keep this the last thing this function does. */ - cbmemc_reinit(); -#endif } diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 75a4e99..4737073 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -30,6 +30,7 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> +#include "cpu/intel/haswell/haswell.h" #include "northbridge/intel/haswell/haswell.h" #include "northbridge/intel/haswell/raminit.h" #include "southbridge/intel/lynxpoint/me.h" @@ -87,7 +88,7 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void main(unsigned long bist) +void romstage_main(unsigned long bist) { int boot_mode = 0; int wake_from_s3; @@ -241,8 +242,4 @@ void main(unsigned long bist) timestamp_add(TS_AFTER_INITRAM, after_dram_time ); timestamp_add_now(TS_END_ROMSTAGE); #endif -#if CONFIG_CONSOLE_CBMEM - /* Keep this the last thing this function does. */ - cbmemc_reinit(); -#endif } diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index a7f1f9b..f689780 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -59,15 +59,28 @@ config MRC_CACHE_SIZE config DCACHE_RAM_BASE hex - default 0xff7e0000 + default 0xff7c0000 config DCACHE_RAM_SIZE hex - default 0x20000 + default 0x10000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE + must add up to a power of 2. config DCACHE_RAM_MRC_VAR_SIZE hex - default 0x4000 + default 0x30000 + help + The amount of cache-as-ram region required by the reference code. + +config DCACHE_RAM_ROMSTAGE_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage from the data cache + during pre-ram rom stage execution. config HAVE_MRC bool "Add a System Agent binary"

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New patch to review for coreboot: e980d34 rmodule: add rmodules class and new type
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2751 -gerrit commit e980d34f26874dbef51f948c77a4a09982ff21a3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Jan 12 00:41:44 2013 -0600 rmodule: add rmodules class and new type Add an rmodules class so that there are default rules for compiling files that will be linked by the rmodule linker. Also, add a new type for SIPI vectors. Change-Id: Ided9e15577b34aff34dc23e5e16791c607caf399 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- Makefile.inc | 2 +- src/include/rmodule.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 3fb74e7..da350d1 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -60,7 +60,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage bootblock smm smmstub cpu_microcode +classes-y := ramstage romstage bootblock smm smmstub cpu_microcode rmodules ####################################################################### # Helper functions for ramstage postprocess diff --git a/src/include/rmodule.h b/src/include/rmodule.h index c81ec17..30eee0e 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -26,6 +26,7 @@ enum { RMODULE_TYPE_SMM, + RMODULE_TYPE_SIPI_VECTOR, }; struct rmodule;

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New patch to review for coreboot: 2c9b877 rmodule: include heap in bss section
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2750 -gerrit commit 2c9b877bc3c935a3ec4e7e392405f29d088a76b4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Feb 5 11:09:49 2013 -0600 rmodule: include heap in bss section By including the heap in the bss output section the size is accounted for in a elf PT_LOAD segment. Without this change the heap wasn't being put into a PT_LOAD segment. The result is a nop w.r.t. functionality, but readelf and company will have proper MemSiz fields. Change-Id: Ibfe9bb87603dcd4c5ff1c57c6af910bbba96b02b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/rmodule.ld | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index 4c13c84..fdee279 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -74,9 +74,7 @@ SECTIONS *(COMMON); . = ALIGN(8); _bss_end = .; - } - .heap (NOLOAD) : { /* * Place the heap after BSS. The heap size is passed in by * by way of ld --defsym=__heap_size=<>

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coreboot March 2013