coreboot March 2013

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New patch to review for coreboot: 13e1b9f rmodule: add 16 bytes of padding
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2749 -gerrit commit 13e1b9f5219d48978c19372a63ef0da8b8321df0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 6 12:47:26 2013 -0600 rmodule: add 16 bytes of padding There is a plan to utlize rmodules for loading ramstage as a relocatable module. However, the rmodule header may change. In order to provide some wiggle room for changing the contents of the rmodule header add some padding. This won't stop the need for coordinating properly between the romstage loader that may be in readonly flash and rmodule header fields. But it will provide for a way to make certain assumptions about alignment of the rmodule's program when the rmodule is compressed in the flash. Change-Id: I9ac5cf495c0bce494e7eaa3bd2f2bd39889b4c52 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/rmodule.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/include/rmodule.h b/src/include/rmodule.h index b51700c..c81ec17 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -100,6 +100,8 @@ struct rmodule_header { /* BSS section information so the loader can clear the bss. */ u32 bss_begin; u32 bss_end; + /* Add some room for growth. */ + u32 padding[4]; } __attribute__ ((packed)); struct rmodule {

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New patch to review for coreboot: 75684e1 haswell: fix ACPI MCFG table
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2748 -gerrit commit 75684e139163afce7bf268a49417dad749df2091 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 17 09:39:39 2013 -0600 haswell: fix ACPI MCFG table The acpi_fill_mcfg() was still using ivy/sandy PCI device ids which Hawell obviously doesn't have. This resulted in an empty MCFG table. Instead of relying on PCI device ids use dev/fn 0/0 since that is where the host bridge always resides. Additionally remove the defines for the IB and SB pci device ids. Replace them with mobile and ult Haswel device ids and use those in the pci driver tables for the northbridge code. Booted to Linux and noted that MCFG was properly parsed. Change-Id: Ieaab2dfef0e9daf3edbd8a27efe0825d2beb9443 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/northbridge/intel/haswell/acpi.c | 4 +--- src/northbridge/intel/haswell/haswell.h | 4 ++-- src/northbridge/intel/haswell/northbridge.c | 4 ++-- 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index c616699..e4d86be 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -38,9 +38,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar_reg; int max_buses; - dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SB, 0); - if (!dev) - dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_IB, 0); + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return current; diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index bbb51aa..3a18038 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -204,8 +204,8 @@ struct ied_header { u8 reserved[34]; } __attribute__ ((packed)); -#define PCI_DEVICE_ID_SB 0x0104 -#define PCI_DEVICE_ID_IB 0x0154 +#define PCI_DEVICE_ID_HSW_MOBILE 0x0c04 +#define PCI_DEVICE_ID_HSW_ULT 0x0a04 #ifdef __SMM__ void intel_northbridge_haswell_finalize_smm(void); diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index d20a40b..c8c1704 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -583,13 +583,13 @@ static struct device_operations mc_ops = { static const struct pci_driver mc_driver_hsw_mobile __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0c04, /* Mobile Haswell */ + .device = PCI_DEVICE_ID_HSW_MOBILE, }; static const struct pci_driver mc_driver_hsw_ult __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0a04, /* ULT Haswell */ + .device = PCI_DEVICE_ID_HSW_ULT, }; static void cpu_bus_init(device_t dev)

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New patch to review for coreboot: 47a75d1 haswell: lapic timer support
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2747 -gerrit commit 47a75d1a734d5dc67dc5bd196cd6ce40795bd942 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jan 15 15:34:08 2013 -0600 haswell: lapic timer support Haswell's BCLK is fised at 100MHz like Sandy/Ivy. Add Haswell's model to the switch statement. Change-Id: Ib9e2afc04eba940bfcee92a6ee5402759b21cc45 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/lapic/apic_timer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index cd6e472..b60da27 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -62,6 +62,8 @@ static int set_timer_fsb(void) break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ + case 0x3c: /* Haswell BCLK fixed at 100MHz */ + case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ timer_fsb = 100; break; default:

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New patch to review for coreboot: 86eb663 haswell: enable caching before SMM initialization
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2746 -gerrit commit 86eb663528f3aae1057c0dc3289b4f8d2d028e86 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 14 14:54:41 2013 -0600 haswell: enable caching before SMM initialization The SMM handler resides in the TSEG region which is far above CONFIG_RAM_TOP (which is the highest cacheable address) before MTRRs are setup. This means that calling initialize_cpus() before performing MTRR setup on the BSP means the SMM handler is copied using uncacheable accesses. Improve the SMM handler setup path by enabling performing MTRR setup on for the BSP before the call to initialize_cpus(). In order to do this the haswell_init() function was split into 2 paths: BSP & AP paths. There is a cpu_common_init() that both call to perform similar functionality. The BSP path in haswell_init() then starts the APs using intel_cores_init(). The AP path in haswell_init() loads microcode and sets up MTRRs. This split will be leveraged for future support of bringing up APs in parallel as well as adhering to the Haswell MP initialization requirements. Change-Id: Id8e17af149e68d708f3d4765e38b1c61f7ebb470 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/haswell.h | 2 + src/cpu/intel/haswell/haswell_init.c | 72 +++++++++++++++++++++-------- src/northbridge/intel/haswell/northbridge.c | 11 +---- 3 files changed, 57 insertions(+), 28 deletions(-) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 7ce868d..cb85078 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -108,6 +108,8 @@ void intel_cpu_haswell_finalize_smm(void); /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); +struct bus; +void bsp_init_and_start_aps(struct bus *cpu_bus); #endif #endif diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 45c1a25..9e62b31 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -499,18 +499,9 @@ static void intel_cores_init(device_t cpu) } } -static void haswell_init(device_t cpu) +static void bsp_init_before_ap_bringup(void) { char processor_name[49]; - struct cpuid_result cpuid_regs; - - intel_update_microcode_from_cbfs(); - - /* Turn on caching if we haven't already */ - x86_enable_cache(); - - /* Clear out pending MCEs */ - configure_mca(); /* Print processor name */ fill_processor_name(processor_name); @@ -523,19 +514,36 @@ static void haswell_init(device_t cpu) set_ehci_debug(0); #endif - /* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); + /* Setup MTRRs based on physical address size. */ x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); x86_mtrr_check(); - /* Setup Page Attribute Tables (PAT) */ - // TODO set up PAT - #if CONFIG_USBDEBUG set_ehci_debug(ehci_debug_addr); #endif + enable_lapic(); +} + +static void ap_init(device_t cpu) +{ + /* Microcode needs to be loaded before caching is enabled. */ + intel_update_microcode_from_cbfs(); + + /* Turn on caching if we haven't already */ + x86_enable_cache(); + x86_setup_fixed_mtrrs(); + x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + + enable_lapic(); +} + +static void cpu_common_init(device_t cpu) +{ + /* Clear out pending MCEs */ + configure_mca(); + /* Enable the local cpu apics */ enable_lapic_tpr(); setup_lapic(); @@ -560,9 +568,37 @@ static void haswell_init(device_t cpu) /* Enable Turbo */ enable_turbo(); +} + +void bsp_init_and_start_aps(struct bus *cpu_bus) +{ + /* Perform any necesarry BSP initialization before APs are brought up. + * This call alos allows the BSP to prepare for any secondary effects + * from calling cpu_initialize() such as smm_init(). */ + bsp_init_before_ap_bringup(); + + /* + * This calls into the gerneic initialize_cpus() which attempts to + * start APs on the APIC bus in the devicetree. No APs get started + * because there is only the BSP and a placeholder (disabled) in the + * devicetree. initialize_cpus() also does SMM initialization by way + * of smm_init(). It will eventually call cpu_initialize(0) which calls + * dev_ops->init(). For Haswell the dev_ops->init() starts up the APs + * by way of intel_cores_init(). + */ + initialize_cpus(cpu_bus); +} - /* Start up extra cores */ - intel_cores_init(cpu); +static void haswell_init(device_t cpu) +{ + if (cpu->path.apic.apic_id == 0) { + cpu_common_init(cpu); + /* Start up extra cores */ + intel_cores_init(cpu); + } else { + ap_init(cpu); + cpu_common_init(cpu); + } } static struct device_operations cpu_dev_ops = { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 90c47a7..d20a40b 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -594,16 +594,7 @@ static const struct pci_driver mc_driver_hsw_ult __pci_driver = { static void cpu_bus_init(device_t dev) { - /* - * This calls into the gerneic initialize_cpus() which attempts to - * start APs on the APIC bus in the devicetree. No APs get started - * because there is only the BSP and placeholder (disabled) in the - * devicetree. initialize_cpus() also does SMM initialization by way - * of smm_init(). It will eventually call cpu_initialize(0) which calls - * dev_ops->init(). For Haswell the dev_ops->init() starts up the APs - * by way of intel_cores_init(). - */ - initialize_cpus(dev->link_list); + bsp_init_and_start_aps(dev->link_list); } static void cpu_bus_noop(device_t dev)

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New patch to review for coreboot: 2359210 haswell: Clear correct number of MCA banks
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2745 -gerrit commit 2359210f1aa72b0597c4e9492767f3b39143a0df Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Jan 12 01:07:28 2013 -0600 haswell: Clear correct number of MCA banks The configure_mca() function was hard coding the number of banks the cpu supported. Query this dynamically so that it no longer clears only 7 banks. Change-Id: I33fce8fadc0facd1016b3295faaf3ae90e490a71 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/haswell_init.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 762b7e8..45c1a25 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -424,11 +424,17 @@ static void set_energy_perf_bias(u8 policy) static void configure_mca(void) { msr_t msr; + const unsigned int mcg_cap_msr = 0x179; int i; + int num_banks; + msr = rdmsr(mcg_cap_msr); + num_banks = msr.lo & 0xff; msr.lo = msr.hi = 0; - /* This should only be done on a cold boot */ - for (i = 0; i < 7; i++) + /* TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank. */ + for (i = 0; i < num_banks; i++) wrmsr(IA32_MC0_STATUS + (i * 4), msr); }

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New patch to review for coreboot: 1d3497c haswell: move definition of CORE_THREAD_COUNT_MSR
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2744 -gerrit commit 1d3497c6aa024143088b622e13f5e471b574aba6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Jan 12 00:45:10 2013 -0600 haswell: move definition of CORE_THREAD_COUNT_MSR This just moves the definiton of CORE_THREAD_COUNT_MSR so that future code can utilize it. Change-Id: I15a381090f21ff758288f55dc964b6694feb6064 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/haswell.h | 1 + src/cpu/intel/haswell/smmrelocate.c | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index f5c580e..7ce868d 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -25,6 +25,7 @@ /* Haswell bus clock is fixed at 100MHz */ #define HASWELL_BCLK 100 +#define CORE_THREAD_COUNT_MSR 0x35 #define IA32_FEATURE_CONTROL 0x3a #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index e2a6482..1ccc9bb 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -36,8 +36,6 @@ #define UNCORE_EMRRphysBase_MSR 0x2f4 #define UNCORE_EMRRphysMask_MSR 0x2f5 -#define CORE_THREAD_COUNT_MSR 0x35 - #define SMRR_SUPPORTED (1<<11) #define EMRR_SUPPORTED (1<<12)

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New patch to review for coreboot: a1ec073 Lippert Fam14 DSDT: Remove INI method from AZHD device
by Mike Loptien 15 Mar '13

15 Mar '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2743 -gerrit commit a1ec07344a580eeb24949f88b2e88ce087c8527b Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Mar 15 13:40:13 2013 -0600 Lippert Fam14 DSDT: Remove INI method from AZHD device I am removing the _INI method from the AZHD device because it does not seem to do anything and causes errors in the FWTS[1] (Firmware Test Suite) test 'method'. The INI method performs device specific initialization and is run when OSPM loads a description table. It must only access OperationRegions that have been indicated as available by the _REG (Region) method. We do not have a _REG method and during my testing, I added a REG method but it did not seem to make a difference in the PCI register space. The bit fields defined as NSDI (Disable No Snoop), NSDO (Disable No Snoop Override), and NSEN (Enable No Snoop Request) do not ever get written from their default values. And writing to these bit fields does not seem to be necessary because I did not notice any change in audio functionality. In an effort to clean up as many FWTS errors as possible, I propose removing this method altogether. I have seen no change in operation (audio works with and without this method) and there does not seem to be any change in lspci or dmesg. FWTS information can be found here: [1]: https://wiki.ubuntu.com/Kernel/Reference/fwts This is the same change as made to Persimmon in Change-ID If8d86f: http://review.coreboot.org/#/c/2726/ Change-Id: Iff594d4a3493531561eb25d1cceeb97bcefde424 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/lippert/frontrunner-af/dsdt.asl | 8 -------- src/mainboard/lippert/toucan-af/dsdt.asl | 8 -------- 2 files changed, 16 deletions(-) diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index d3b88f7..1e8c09e 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -1373,14 +1373,6 @@ DefinitionBlock ( offset (0x6C), MMDT, 16, } - - Method(_INI) { - If(LEqual(OSTP,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } } /* end AZHD */ Device(LIBR) { diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index cde41b4..cdde01a 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -1373,14 +1373,6 @@ DefinitionBlock ( offset (0x6C), MMDT, 16, } - - Method(_INI) { - If(LEqual(OSTP,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } } /* end AZHD */ Device(LIBR) {

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Patch set updated for coreboot: 273a54e ASROCK Fam14 DSDT: Remove INI method from AZHD device
by Mike Loptien 15 Mar '13

15 Mar '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2742 -gerrit commit 273a54ec2b9f6baf11c0d18edb80655c6713acb5 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Mar 15 13:36:25 2013 -0600 ASROCK Fam14 DSDT: Remove INI method from AZHD device I am removing the _INI method from the AZHD device because it does not seem to do anything and causes errors in the FWTS[1] (Firmware Test Suite) test 'method'. The INI method performs device specific initialization and is run when OSPM loads a description table. It must only access OperationRegions that have been indicated as available by the _REG (Region) method. We do not have a _REG method and during my testing, I added a REG method but it did not seem to make a difference in the PCI register space. The bit fields defined as NSDI (Disable No Snoop), NSDO (Disable No Snoop Override), and NSEN (Enable No Snoop Request) do not ever get written from their default values. And writing to these bit fields does not seem to be necessary because I did not notice any change in audio functionality. In an effort to clean up as many FWTS errors as possible, I propose removing this method altogether. I have seen no change in operation (audio works with and without this method) and there does not seem to be any change in lspci or dmesg. FWTS information can be found here: [1]: https://wiki.ubuntu.com/Kernel/Reference/fwts This is the same change as made to Persimmon in Change-ID If8d86f: http://review.coreboot.org/#/c/2726/ Change-Id: Iae70c3d0af1cdaca31b206ad6daba4d38ee6b780 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/asrock/e350m1/dsdt.asl | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index bc45435..1e60661 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -1373,14 +1373,6 @@ DefinitionBlock ( offset (0x6C), MMDT, 16, } - - Method(_INI) { - If(LEqual(OSTP,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } } /* end AZHD */ Device(LIBR) {

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Patch set updated for coreboot: 2054f24 ASROCK Fam14 DSDT: Remove INI method from AZHD device
by Mike Loptien 15 Mar '13

15 Mar '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2742 -gerrit commit 2054f24350532720727f891a647f215fb42fcd4f Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Mar 15 13:36:25 2013 -0600 ASROCK Fam14 DSDT: Remove INI method from AZHD device I am removing the _INI method from the AZHD device because it does not seem to do anything and causes errors in the FWTS[1] (Firmware Test Suite) test 'method'. The INI method performs device specific initialization and is run when OSPM loads a description table. It must only access OperationRegions that have been indicated as available by the _REG (Region) method. We do not have a _REG method and during my testing, I added a REG method but it did not seem to make a difference in the PCI register space. The bit fields defined as NSDI (Disable No Snoop), NSDO (Disable No Snoop Override), and NSEN (Enable No Snoop Request) do not ever get written from their default values. And writing to these bit fields does not seem to be necessary because I did not notice any change in audio functionality. In an effort to clean up as many FWTS errors as possible, I propose removing this method altogether. I have seen no change in operation (audio works with and without this method) and there does not seem to be any change in lspci or dmesg. FWTS information can be found here: [1]: https://wiki.ubuntu.com/Kernel/Reference/fwts This is the same chagne as made to Persimmon in Change-ID If8d86f: http://review.coreboot.org/#/c/2726/ Change-Id: Iae70c3d0af1cdaca31b206ad6daba4d38ee6b780 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/asrock/e350m1/dsdt.asl | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index bc45435..1e60661 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -1373,14 +1373,6 @@ DefinitionBlock ( offset (0x6C), MMDT, 16, } - - Method(_INI) { - If(LEqual(OSTP,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } } /* end AZHD */ Device(LIBR) {

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New patch to review for coreboot: 7fb9e1d ASROCK Fam14 DSDT: Remove INI method from AZHD device
by Mike Loptien 15 Mar '13

15 Mar '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2742 -gerrit commit 7fb9e1de25b1dc1b9548d77dad5ad7edceae9897 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Mar 15 13:36:25 2013 -0600 ASROCK Fam14 DSDT: Remove INI method from AZHD device I am removing the _INI method from the AZHD device because it does not seem to do anything and causes errors in the FWTS[1] (Firmware Test Suite) test 'method'. The INI method performs device specific initialization and is run when OSPM loads a description table. It must only access OperationRegions that have been indicated as available by the _REG (Region) method. We do not have a _REG method and during my testing, I added a REG method but it did not seem to make a difference in the PCI register space. The bit fields defined as NSDI (Disable No Snoop), NSDO (Disable No Snoop Override), and NSEN (Enable No Snoop Request) do not ever get written from their default values. And writing to these bit fields does not seem to be necessary because I did not notice any change in audio functionality. In an effort to clean up as many FWTS errors as possible, I propose removing this method altogether. I have seen no change in operation (audio works with and without this method) and there does not seem to be any change in lspci or dmesg. FWTS information can be found here: [1]: https://wiki.ubuntu.com/Kernel/Reference/fwts This is the same chagne as made to Persimmon in Change-ID If8d86f: http://review.coreboot.org/#/c/2726/ Change-Id: Iae70c3d0af1cdaca31b206ad6daba4d38ee6b780 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/asrock/e350m1/dsdt.asl | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index bc45435..1e60661 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -1373,14 +1373,6 @@ DefinitionBlock ( offset (0x6C), MMDT, 16, } - - Method(_INI) { - If(LEqual(OSTP,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } } /* end AZHD */ Device(LIBR) {

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coreboot March 2013