coreboot March 2013

coreboot@coreboot.org

46 participants
782 discussions

Patch set updated for coreboot: bf84c0e AMD DSDT: Add secondary bus range to PCI0
by Mike Loptien 15 Mar '13

15 Mar '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2735 -gerrit commit bf84c0ea2f375c5704fc76f70e9ffe59762d5a8a Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Mar 15 10:53:40 2013 -0600 AMD DSDT: Add secondary bus range to PCI0 Adding the 'WordBusNumber' macro to the PCI0 CRES ResourceTemplate in the Persimmon DSDT. This sets up the bus number for the PCI0 device and the secondary bus number in the CRS method. This change came in response to a 'dmesg' error which states: '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS' By adding the 'WordBusNumber' macro, ACPI can set up a valid range for the PCIe downstream busses, thereby relieving the Linux kernel from "guessing" the valid range based off _BBN or assuming [0-0xFF]. The Linux kernel code that checks this bus range is in `drivers/acpi/pci_root.c`. PCI busses can have up to 256 secondary busses connected to them via a PCI-PCI bridge. However, these busses do not have to be sequentially numbered, so leaving out a section of the range (eg. allowing [0-0x7F]) will unnecessarily restrict the downstream busses. This is the same change as made to Persimmon with change-id I44f22: http://review.coreboot.org/#/c/2592/ Change-Id: I9017a7619b3b17e0e95ad0fe46d0652499289b00 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/amd/inagua/dsdt.asl | 16 ++++++++++++++++ src/mainboard/amd/south_station/dsdt.asl | 16 ++++++++++++++++ src/mainboard/amd/union_station/dsdt.asl | 16 ++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 582ab7f..148d7b0 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -1477,6 +1477,22 @@ DefinitionBlock ( } /* end Ac97modem */ Name(CRES, ResourceTemplate() { + /* Set the Bus number and Secondary Bus number for the PCI0 device + * The Secondary bus range for PCI0 lets the system + * know what bus values are allowed on the downstream + * side of this PCI bus if there is a PCI-PCI bridge. + * PCI busses can have 256 secondary busses which + * range from [0-0xFF] but they do not need to be + * sequential. + */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x00FF, /* range maximum */ + 0x0000, /* translation */ + 0x0100, /* length */ + ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 582ab7f..148d7b0 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -1477,6 +1477,22 @@ DefinitionBlock ( } /* end Ac97modem */ Name(CRES, ResourceTemplate() { + /* Set the Bus number and Secondary Bus number for the PCI0 device + * The Secondary bus range for PCI0 lets the system + * know what bus values are allowed on the downstream + * side of this PCI bus if there is a PCI-PCI bridge. + * PCI busses can have 256 secondary busses which + * range from [0-0xFF] but they do not need to be + * sequential. + */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x00FF, /* range maximum */ + 0x0000, /* translation */ + 0x0100, /* length */ + ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index da6f266..1d2435c 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -1478,6 +1478,22 @@ DefinitionBlock ( } /* end Ac97modem */ Name(CRES, ResourceTemplate() { + /* Set the Bus number and Secondary Bus number for the PCI0 device + * The Secondary bus range for PCI0 lets the system + * know what bus values are allowed on the downstream + * side of this PCI bus if there is a PCI-PCI bridge. + * PCI busses can have 256 secondary busses which + * range from [0-0xFF] but they do not need to be + * sequential. + */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x00FF, /* range maximum */ + 0x0000, /* translation */ + 0x0100, /* length */ + ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,

1 0

New patch to review for coreboot: 3e8a7bb AMD DSDT: Add secondary bus range to PCI0
by Mike Loptien 15 Mar '13

15 Mar '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2735 -gerrit commit 3e8a7bb57eb8a3096a35a46dcceded75bb61a853 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Mar 15 10:53:40 2013 -0600 AMD DSDT: Add secondary bus range to PCI0 Adding the 'WordBusNumber' macro to the PCI0 CRES ResourceTemplate in the Persimmon DSDT. This sets up the bus number for the PCI0 device and the secondary bus number in the CRS method. This change came in response to a 'dmesg' error which states: '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS' By adding the 'WordBusNumber' macro, ACPI can set up a valid range for the PCIe downstream busses, thereby relieving the Linux kernel from "guessing" the valid range based off _BBN or assuming [0-0xFF]. The Linux kernel code that checks this bus range is in `drivers/acpi/pci_root.c`. PCI busses can have up to 256 secondary busses connected to them via a PCI-PCI bridge. However, these busses do not have to be sequentially numbered, so leaving out a section of the range (eg. allowing [0-0x7F]) will unnecessarily restrict the downstream busses. This is the same change as made to Persimmon with change-id I44f22: http://review.coreboot.org/#/c/2592/ Change-Id: I9017a7619b3b17e0e95ad0fe46d0652499289b00 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/mainboard/amd/inagua/dsdt.asl | 16 ++++++++++++++++ src/mainboard/amd/south_station/dsdt.asl | 16 ++++++++++++++++ src/mainboard/amd/union_station/dsdt.asl | 16 ++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 582ab7f..148d7b0 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -1477,6 +1477,22 @@ DefinitionBlock ( } /* end Ac97modem */ Name(CRES, ResourceTemplate() { + /* Set the Bus number and Secondary Bus number for the PCI0 device + * The Secondary bus range for PCI0 lets the system + * know what bus values are allowed on the downstream + * side of this PCI bus if there is a PCI-PCI bridge. + * PCI busses can have 256 secondary busses which + * range from [0-0xFF] but they do not need to be + * sequential. + */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x00FF, /* range maximum */ + 0x0000, /* translation */ + 0x0100, /* length */ + ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 582ab7f..148d7b0 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -1477,6 +1477,22 @@ DefinitionBlock ( } /* end Ac97modem */ Name(CRES, ResourceTemplate() { + /* Set the Bus number and Secondary Bus number for the PCI0 device + * The Secondary bus range for PCI0 lets the system + * know what bus values are allowed on the downstream + * side of this PCI bus if there is a PCI-PCI bridge. + * PCI busses can have 256 secondary busses which + * range from [0-0xFF] but they do not need to be + * sequential. + */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x00FF, /* range maximum */ + 0x0000, /* translation */ + 0x0100, /* length */ + ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index da6f266..1d2435c 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -1478,6 +1478,22 @@ DefinitionBlock ( } /* end Ac97modem */ Name(CRES, ResourceTemplate() { + /* Set the Bus number and Secondary Bus number for the PCI0 device + * The Secondary bus range for PCI0 lets the system + * know what bus values are allowed on the downstream + * side of this PCI bus if there is a PCI-PCI bridge. + * PCI busses can have 256 secondary busses which + * range from [0-0xFF] but they do not need to be + * sequential. + */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x00FF, /* range maximum */ + 0x0000, /* translation */ + 0x0100, /* length */ + ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,

1 0

New patch to review for coreboot: a4092a7 Update 3rdparty mark to latest repository
by Stefan Reinauer 15 Mar '13

15 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2734 -gerrit commit a4092a7904f2fe298e9f8df09e5a7853033bcd4e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 15 10:04:20 2013 -0700 Update 3rdparty mark to latest repository For google/stout binaries Apparently the actual marker got lost in the rebase / change of the commit message. Change-Id: I4f18b9ddba326988b58f2595c0025a113feb0d68 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- 3rdparty | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty b/3rdparty index dac1a18..ba8caa3 160000 --- a/3rdparty +++ b/3rdparty @@ -1 +1 @@ -Subproject commit dac1a18d184976e4447b98479f0b7a172054b98f +Subproject commit ba8caa30bd5ed6d89dbfd40e17c75c94d43804c6

1 0

Patch merged into coreboot/master: 9ae1eb6 Super I/O W83627DHG: Enable UART B by redirecting pins
by gerrit＠coreboot.org 15 Mar '13

15 Mar '13

the following patch was just integrated into master: commit 9ae1eb6961b483c9905423fb113100a8038b4507 Author: Wolfgang Kamp <wmkamp(a)datakamp.de> Date: Mon Mar 11 16:35:42 2013 +0100 Super I/O W83627DHG: Enable UART B by redirecting pins Pins 78-85 are set to GPIO after power on or reset. To enable UART B the pins must be redirected to it. Look at W83627DHG databook version 1.4 page 185 Chip (global) Control Register CR2C. Change-Id: I12b094a60d9c5cb2447a553be4679a4605e19845 Signed-off-by: Wolfgang Kamp <wmkamp(a)datakamp.de> Reviewed-on: http://review.coreboot.org/2626 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Mar 15 17:50:04 2013, giving +1 See http://review.coreboot.org/2626 for details. -gerrit

1 0

Patch set updated for coreboot: 7684c57 i945: Replace some magic values by defined names
by Patrick Georgi 15 Mar '13

15 Mar '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2733 -gerrit commit 7684c5704fae4af6606beda9b37bc0b8b48a6344 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Mar 15 14:11:37 2013 +0100 i945: Replace some magic values by defined names Cleanup. Change-Id: I4e4c617dcd3ede81a0abbe16f9916562d24fa8ce Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/northbridge/intel/i945/raminit.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 758a97e..bbd6528 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -295,18 +295,18 @@ static void sdram_detect_errors(struct sys_info *sysinfo) pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); /* clear self refresh status if check is disabled or not a resume */ - if (!CONFIG_CHECK_SLFRCS_ON_RESUME || sysinfo->boot_path != 2) { - MCHBAR8(0xf14) |= 3; + if (!CONFIG_CHECK_SLFRCS_ON_RESUME || sysinfo->boot_path != BOOT_PATH_RESUME) { + MCHBAR8(SLFRCS) |= 3; } else { /* Validate self refresh config */ if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) || (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) && - !(MCHBAR8(0xf14) & (1<<0))) { + !(MCHBAR8(SLFRCS) & (1<<0))) { do_reset = 1; } if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) || (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) && - !(MCHBAR8(0xf14) & (1<<1))) { + !(MCHBAR8(SLFRCS) & (1<<1))) { do_reset = 1; } }

1 0

Patch set updated for coreboot: 89194fb cbfstool: Fix initial empty space in image creation.
by Hung-Te Lin 15 Mar '13

15 Mar '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2731 -gerrit commit 89194fbca009d34535bdd46a1bf3bda11e11f95f Author: Hung-Te Lin <hungte(a)chromium.org> Date: Fri Mar 15 17:40:08 2013 +0800 cbfstool: Fix initial empty space in image creation. When calculating initial CBFS empty entry space, the size of header itself must be not included (with the reserved space for entry name). This is a regression of the old cbfstool size bug. Before this fix, in build process we see: OBJCOPY cbfs/fallback/romstage_null.bin W: CBFS image was created with old cbfstool with size bug. Fixing size in last entry... And checking the output binary: cbfstool build/coreboot.pre1 print -v -v DEBUG: read_cbfs_image: build/coreboot.pre1 (262144 bytes) DEBUG: x86sig: 0xfffffd30, offset: 0x3fd30 W: CBFS image was created with old cbfstool with size bug. Fixing size in last entry... DEBUG: Last entry has been changed from 0x3fd40 to 0x3fd00. coreboot.pre1: 256 kB, bootblksz 688, romsize 262144, offset 0x0 align: 64 Name Offset Type Size (empty) 0x0 null 261296 DEBUG: cbfs_file=0x0, offset=0x28, content_address=0x28+0x3fcb0 After this fix, no more alerts in build process. Verified to build successfully on x86/qemu and arm/snow configurations. Change-Id: I35c96f4c10a41bae671148a0e08988fa3bf6b7d3 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- util/cbfstool/cbfs_image.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 2cdbf23..19362f1 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -142,6 +142,7 @@ int cbfs_image_create(struct cbfs_image *image, struct cbfs_header *header; struct cbfs_file *entry; uint32_t cbfs_len; + size_t entry_header_len; DEBUG("cbfs_image_create: bootblock=0x%x+0x%zx, " "header=0x%x+0x%zx, entries_offset=0x%x\n", @@ -205,9 +206,10 @@ int cbfs_image_create(struct cbfs_image *image, entries_offset, align); return -1; } - if (entries_offset + sizeof(*entry) > size) { + entry_header_len = cbfs_calculate_file_header_size(""); + if (entries_offset + entry_header_len > size) { ERROR("Offset (0x%x+0x%zx) exceed ROM size(0x%zx)\n", - entries_offset, sizeof(*entry), size); + entries_offset, entry_header_len, size); return -1; } entry = (struct cbfs_file *)(image->buffer.data + entries_offset); @@ -218,7 +220,7 @@ int cbfs_image_create(struct cbfs_image *image, cbfs_len = bootblock_offset; if (header_offset > entries_offset && header_offset < cbfs_len) cbfs_len = header_offset; - cbfs_len -= entries_offset + align; + cbfs_len -= entries_offset + align + entry_header_len; cbfs_create_empty_entry(image, entry, cbfs_len, ""); LOG("Created CBFS image (capacity = %d bytes)\n", cbfs_len); return 0;

1 0

Patch set updated for coreboot: f834cf0 Super I/O W83627DHG: Enable UART B by redirecting pins
by Paul Menzel 15 Mar '13

15 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2626 -gerrit commit f834cf0defcb4e7dd64eb3978322aa74e0f2965c Author: Wolfgang Kamp <wmkamp(a)datakamp.de> Date: Mon Mar 11 16:35:42 2013 +0100 Super I/O W83627DHG: Enable UART B by redirecting pins Pins 78-85 are set to GPIO after power on or reset. To enable UART B the pins must be redirected to it. Look at W83627DHG databook version 1.4 page 185 Chip (global) Control Register CR2C. Change-Id: I12b094a60d9c5cb2447a553be4679a4605e19845 Signed-off-by: Wolfgang Kamp <wmkamp(a)datakamp.de> --- src/superio/winbond/w83627dhg/superio.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 26f2921..bbde26a 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -37,6 +37,17 @@ void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, dev->path.pnp.port); } +static void w83627dhg_enable_UR2(device_t dev) +{ + u8 reg8; + + pnp_enter_ext_func_mode(dev); + reg8 = pnp_read_config(dev, 0x2c); + reg8 |= (0x3); + pnp_write_config(dev, 0x2c, reg8); // Set pins 78-85-> UART B + pnp_exit_ext_func_mode(dev); +} + static void w83627dhg_init(device_t dev) { struct superio_winbond_w83627dhg_config *conf = dev->chip_info; @@ -45,6 +56,9 @@ static void w83627dhg_init(device_t dev) return; switch(dev->path.pnp.device) { + case W83627DHG_SP2: + w83627dhg_enable_UR2(dev); + break; case W83627DHG_KBC: pc_keyboard_init(&conf->keyboard); break;

1 0

Patch merged into coreboot/master: 8d629c1 Persimmon DSDT: Remove INI method from AZHD device
by gerrit＠coreboot.org 15 Mar '13

15 Mar '13

the following patch was just integrated into master: commit 8d629c14eb776ce6e243218bb554a335dc0f3672 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Thu Mar 14 16:07:09 2013 -0600 Persimmon DSDT: Remove INI method from AZHD device I am removing the _INI method from the AZHD device because it does not seem to do anything and causes errors in the FWTS[1] (Firmware Test Suite) test 'method'. The INI method performs device specific initialization and is run when OSPM loads a description table. It must only access OperationRegions that have been indicated as available by the _REG (Region) method. We do not have a _REG method and during my testing, I added a REG method but it did not seem to make a difference in the PCI register space. The bit fields defined as NSDI (Disable No Snoop), NSDO (Disable No Snoop Override), and NSEN (Enable No Snoop Request) do not ever get written from their default values. And writing to these bit fields does not seem to be necessary because I did not notice any change in audio functionality. In an effort to clean up as many FWTS errors as possible, I propose removing this method altogether. I have seen no change in operation (audio works with and without this method) and there does not seem to be any change in lspci or dmesg. FWTS information can be found here: [1]: https://wiki.ubuntu.com/Kernel/Reference/fwts Change-Id: If8d86f959822d528c44ab011a851659d486289b5 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2726 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 15 01:31:47 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 15 17:07:01 2013, giving +2 See http://review.coreboot.org/2726 for details. -gerrit

1 0

Patch merged into coreboot/master: e31c0ed Persimmon DSDT: Add OSC method
by gerrit＠coreboot.org 15 Mar '13

15 Mar '13

the following patch was just integrated into master: commit e31c0ed9b5f789cb0207740c588c769f7eda5f0e Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Tue Mar 12 10:21:24 2013 -0600 Persimmon DSDT: Add OSC method The _OSC method is used to tell the OS what capabilities it can take control over from the firmware. This method is described in chapter 6.2.9 of the ACPI spec v3.0. The method takes 4 inputs (UUID, Rev ID, Input Count, and Capabilities Buffer) and returns a Capabilites Buffer the same size as the input Buffer. This Buffer is generally 3 Dwords long consisting of an Errors Dword, a Supported Capabilities Dword, and a Control Dword. The OS will request control of certain capabilities and the firmware must grant or deny control of those features. We do not want to have control over anything so let the OS control as much as it can. The _OSC method is required for PCIe devices and dmesg checks for its existence and issues an error if it is not found. Change-Id: I1494285def7440972f0549b7cb73eb94dafc72c2 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2684 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 15 01:01:24 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 15 17:06:23 2013, giving +2 See http://review.coreboot.org/2684 for details. -gerrit

1 0

Patch merged into coreboot/master: 35c2f4f Drop CHIP_NAME from intel/baskingridge
by gerrit＠coreboot.org 15 Mar '13

15 Mar '13

the following patch was just integrated into master: commit 35c2f4fd4aac8b14421ee73be490bde06dbcef56 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Mar 14 13:00:14 2013 -0700 Drop CHIP_NAME from intel/baskingridge It's no longer required. Change-Id: I621226a3bdfba9bc8edfd6e511a5337ae603ae19 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2723 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Thu Mar 14 23:43:57 2013, giving +1 See http://review.coreboot.org/2723 for details. -gerrit

1 0

← Newer
1
...
29
30
31
32
33
34
35
...
79
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2013