coreboot March 2013

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Patch merged into coreboot/master: b7ecf6d Add support for "Stout" Chromebook
by gerrit＠coreboot.org 18 Mar '13

18 Mar '13

the following patch was just integrated into master: commit b7ecf6d83047e70ed5846ac35833a04983318b9c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Mar 13 17:13:32 2013 -0700 Add support for "Stout" Chromebook We're happy to announce coreboot support for the "Stout" Chromebook, a.k.a Lenovo X131e Chromebook. Change-Id: I9b995f8d0dd48e41c788b7c3d35b4fac5840e425 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2636 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Mar 15 19:43:19 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Mar 18 17:07:01 2013, giving +2 See http://review.coreboot.org/2636 for details. -gerrit

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Trac reminder: list of new ticket(s)
by coreboot tracker 18 Mar '13

18 Mar '13

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Patch set updated for coreboot: 0273393 cbfstool: Extend "locate" command to support alignment and page-fitting.
by Hung-Te Lin 18 Mar '13

18 Mar '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2730 -gerrit commit 0273393fccaf7922473f8404f2a45bd2fe19e220 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Fri Mar 15 14:44:05 2013 +0800 cbfstool: Extend "locate" command to support alignment and page-fitting. cbfstool usage change: The "-a" parameter for "cbfstool locate" has changed to "-P/--page-size". "-a" for "cbfstool locate" is now for specifying base address alignment. The "locate" command was used to find a place to store ELF stage image in one memory page. Its argument "-a (alignment)" was actually specifying the page size instead of doing memory address alignment. This can be confusing when people are trying to put a blob in aligned location (ex, microcode needs to be aligned in 0x10), and see this: cbfstool coreboot.rom localte -f test.bin -n test -a 0x100 # output: 0x44, which does not look like aligned to 0x100. To support that and prevent confusion, we should rename the page-fitting argument to "-P/--page-size" and leave "-a/--alignment" for real alignment. Verified by manually testing a file (324 bytes) with alignment=0x10: cbfstool coreboot.rom locate -f test -n test -a 0x10 # output: 0x71fdd0 cbfstool coreboot.rom add -f test -n test -t raw -b 0x71fdd0 cbfstool coreboot.rom print -v -v # output: test 0x71fd80 raw 324 # output: cbfs_file=0x71fd80, offset=0x50, content_address=0x71fdd0+0x144 And verified to be compatible with old behavior by building i386/axus/tc320 (with page limitation 0x40000): cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000 # output: 0x44 cbfstool coreboot.rom locate -f x.bin -n romstage -P 0x40000 -a 0x30 # output: 0x60 Change-Id: I0893adde51ebf46da1c34913f9c35507ed8ff731 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/arch/armv7/Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 2 +- util/cbfstool/cbfs_image.c | 71 +++++++++++++++++++++++++++++++-------------- util/cbfstool/cbfs_image.h | 6 ++-- util/cbfstool/cbfstool.c | 15 ++++++---- 5 files changed, 65 insertions(+), 31 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 39c115e..8601112 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -282,7 +282,7 @@ $(objgenerated)/romstage_xip.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/bas $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin @printf " generating base_xip.txt\n" rm -f $@ - $(CBFSTOOL) $(obj)/coreboot.pre1 locate -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -a $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } mv $@.tmp $@ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index cc7bfc2..433b434 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -393,7 +393,7 @@ $(objgenerated)/romstage_xip.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/bas $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin rm -f $@ - $(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -a $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } mv $@.tmp $@ diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 2cdbf23..63d6f78 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -773,7 +773,7 @@ int cbfs_create_empty_entry(struct cbfs_image *image, struct cbfs_file *entry, return 0; } -/* Finds a place to hold whole stage data in same memory page. +/* Finds a place to hold whole data in same memory page. */ static int is_in_same_page(uint32_t start, uint32_t size, uint32_t page) { if (!page) @@ -781,24 +781,44 @@ static int is_in_same_page(uint32_t start, uint32_t size, uint32_t page) { return (start / page) == (start + size - 1) / page; } +/* Tests if data can fit in a range by given offset: + * start ->| header_len | offset (+ size) |<- end + */ +static int is_in_range(uint32_t start, uint32_t end, uint32_t header_len, + uint32_t offset, uint32_t size) { + return (offset >= start + header_len && offset + size <= end); +} + int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, - uint32_t size, uint32_t page_size) { + uint32_t size, uint32_t page_size, uint32_t align) { struct cbfs_file *entry; size_t need_len; - uint32_t addr, addr_next, addr2, addr3, header_len; - assert(size < page_size); + uint32_t addr, addr_next, addr2, addr3, offset, header_len; + + /* Default values: allow fitting anywhere in ROM. */ + if (!page_size) + page_size = ntohl(image->header->romsize); + if (!align) + align = 1; + + if (size > page_size) + ERROR("Input file size (%d) greater than page size (%d).\n", + size, page_size); if (page_size % ntohl(image->header->align)) - WARN("locate_entry: page does not align with CBFS image.\n"); + WARN("%s: Page size (%#x) not aligned with CBFS image (%#x).\n", + __func__, page_size, ntohl(image->header->align)); /* TODO Old cbfstool always assume input is a stage file (and adding * sizeof(cbfs_stage) for header. We should fix that by adding "-t" - * (type) param in future. For right now, follow old behavior. */ + * (type) param in future. For right now, we assume cbfs_stage is the + * largest structure and add it into header size. */ + assert(sizeof(struct cbfs_stage) >= sizeof(struct cbfs_payload)); header_len = (cbfs_calculate_file_header_size(name) + sizeof(struct cbfs_stage)); need_len = header_len + size; - // Merge empty entries to build get max available pages. + // Merge empty entries to build get max available space. cbfs_walk(image, cbfs_merge_empty_entry, NULL); /* Three cases of content location on memory page: @@ -812,14 +832,15 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, * shift-> | <header>|<content> | at starting of PAGE 2. * * case 3. (large content filling whole page) - * | PAGE 1 | PAGE 2 | PAGE 3| - * | <header>< content > | | Can't fit. If we shift content to - * | { free space . } PAGE 2, header can't fit in free - * | shift-> <header><content> space, so we must use PAGE 3. + * | PAGE 1 | PAGE 2 | PAGE 3 | + * | <header>< content > | Can't fit. If we shift content to + * |trial-> <header>< content > | PAGE 2, header can't fit in free + * | shift-> <header><content> space, so we must use PAGE 3. * - * The returned address will be used to re-link stage file, and then - * assigned to add-stage command (-b), which will be then re-calculated - * by ELF loader and positioned by cbfs_add_entry. + * The returned address can be then used as "base-address" (-b) in add-* + * commands (will be re-calculated and positioned by cbfs_add_entry_at). + * For stage targets, the address is also used to re-link stage before + * being added into CBFS. */ for (entry = cbfs_find_first_entry(image); entry && cbfs_is_valid_entry(image, entry); @@ -834,23 +855,29 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, image, entry)); if (addr_next - addr < need_len) continue; - if (is_in_same_page(addr + header_len, size, page_size)) { + + offset = align_up(addr + header_len, align); + if (is_in_same_page(offset, size, page_size) && + is_in_range(addr, addr_next, header_len, offset, size)) { DEBUG("cbfs_locate_entry: FIT (PAGE1)."); - return addr + header_len; + return offset; } addr2 = align_up(addr, page_size); - if (addr2 < addr_next && addr_next - addr2 >= size && - addr2 - addr >= header_len) { + offset = align_up(addr2, align); + if (is_in_range(addr, addr_next, header_len, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP (PAGE2)."); - return addr2; + return offset; } + /* Assume page_size >= header_len so adding one page will + * definitely provide the space for header. */ + assert(page_size >= header_len); addr3 = addr2 + page_size; - if (addr3 < addr_next && addr_next - addr3 >= size && - addr3 - addr >= header_len) { + offset = align_up(addr3, align); + if (is_in_range(addr, addr_next, header_len, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP+ (PAGE3)."); - return addr3; + return offset; } } return -1; diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 57bbfa1..7ad418a 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -76,10 +76,12 @@ int cbfs_remove_entry(struct cbfs_image *image, const char *name); int cbfs_create_empty_entry(struct cbfs_image *image, struct cbfs_file *entry, size_t len, const char *name); -/* Finds a location to put given content in same memory page. +/* Finds a location to put given content by specified criteria: + * "page_size" limits the content to fit on same memory page, and + * "align" specifies starting address alignment. * Returns a valid offset, or -1 on failure. */ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, - uint32_t size, uint32_t page_size); + uint32_t size, uint32_t page_size, uint32_t align); /* Callback function used by cbfs_walk. * Returns 0 on success, or non-zero to stop further iteration. */ diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 97fd88d..7eca01d 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -50,6 +50,7 @@ static struct param { uint32_t entrypoint; uint32_t size; uint32_t alignment; + uint32_t pagesize; uint32_t offset; uint32_t top_aligned; comp_algo algo; @@ -355,12 +356,12 @@ static int cbfs_locate(void) } address = cbfs_locate_entry(&image, param.name, buffer.size, - param.alignment); + param.pagesize, param.alignment); buffer_delete(&buffer); if (address == -1) { - ERROR("'%s' can't fit in CBFS for align 0x%x.\n", - param.name, param.alignment); + ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n", + param.name, param.pagesize, param.alignment); cbfs_image_delete(&image); return 1; } @@ -421,7 +422,7 @@ static const struct command commands[] = { {"add-flat-binary", "f:n:l:e:c:b:vh?", cbfs_add_flat_binary}, {"remove", "n:vh?", cbfs_remove}, {"create", "s:B:b:H:a:o:m:vh?", cbfs_create}, - {"locate", "f:n:a:Tvh?", cbfs_locate}, + {"locate", "f:n:a:P:Tvh?", cbfs_locate}, {"print", "vh?", cbfs_print}, {"extract", "n:f:vh?", cbfs_extract}, }; @@ -437,6 +438,7 @@ static struct option long_options[] = { {"size", required_argument, 0, 's' }, {"bootblock", required_argument, 0, 'B' }, {"alignment", required_argument, 0, 'a' }, + {"page-size", required_argument, 0, 'P' }, {"offset", required_argument, 0, 'o' }, {"file", required_argument, 0, 'f' }, {"arch", required_argument, 0, 'm' }, @@ -468,7 +470,7 @@ static void usage(char *name) "Remove a component\n" " create -s size -B bootblock -m ARCH [-a align] [-o offset] " "Create a ROM file\n" - " locate -f FILE -n NAME [-a align] [-T] " + " locate -f FILE -n NAME [-P page-size] [-a align] [-T] " "Find a place for a file of that size\n" " print " "Show the contents of the ROM\n" @@ -572,6 +574,9 @@ int main(int argc, char **argv) case 'a': param.alignment = strtoul(optarg, NULL, 0); break; + case 'P': + param.pagesize = strtoul(optarg, NULL, 0); + break; case 'o': param.offset = strtoul(optarg, NULL, 0); break;

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Patch set updated for coreboot: c5d61e5 cbfstool: Extend "locate" command to support alignment and page-fitting.
by Hung-Te Lin 18 Mar '13

18 Mar '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2730 -gerrit commit c5d61e5a06138f36a486d053e24b6fba1f9b87b5 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Fri Mar 15 14:44:05 2013 +0800 cbfstool: Extend "locate" command to support alignment and page-fitting. cbfstool usage change: The "-a" parameter for "cbfstool locate" has changed to "-P/--page-size". "-a" for "cbfstool locate" is now for specifying base address alignment. The "locate" command was used to find a place to store ELF stage image in one memory page. Its argument "-a (alignment)" was actually specifying the page size instead of doing memory address alignment. This can be confusing when people are trying to put a blob in aligned location (ex, microcode needs to be aligned in 0x10), and see this: cbfstool coreboot.rom localte -f test.bin -n test -a 0x100 # output: 0x44, which does not look like aligned to 0x100. To support that and prevent confusion, we should rename the page-fitting argument to "-P/--page-size" and leave "-a/--alignment" for real alignment. Verified by manually testing a file (324 bytes) with alignment=0x10: cbfstool coreboot.rom locate -f test -n test -a 0x10 # output: 0x71fdd0 cbfstool coreboot.rom add -f test -n test -t raw -b 0x71fdd0 cbfstool coreboot.rom print -v -v # output: test 0x71fd80 raw 324 # output: cbfs_file=0x71fd80, offset=0x50, content_address=0x71fdd0+0x144 And verified to be compatible with old behavior by building i386/axus/tc320 (with page limitation 0x40000): cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000 # output: 0x44 cbfstool coreboot.rom locate -f x.bin -n romstage -P 0x40000 -a 0x30 # output: 0x60 Change-Id: I0893adde51ebf46da1c34913f9c35507ed8ff731 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/arch/armv7/Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 2 +- util/cbfstool/cbfs_image.c | 71 +++++++++++++++++++++++++++++++-------------- util/cbfstool/cbfs_image.h | 6 ++-- util/cbfstool/cbfstool.c | 15 ++++++---- 5 files changed, 65 insertions(+), 31 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 39c115e..8601112 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -282,7 +282,7 @@ $(objgenerated)/romstage_xip.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/bas $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin @printf " generating base_xip.txt\n" rm -f $@ - $(CBFSTOOL) $(obj)/coreboot.pre1 locate -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -a $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } mv $@.tmp $@ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 0892efd..3c57701 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -387,7 +387,7 @@ $(objgenerated)/romstage_xip.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/bas $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin rm -f $@ - $(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -a $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } mv $@.tmp $@ diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 2cdbf23..63d6f78 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -773,7 +773,7 @@ int cbfs_create_empty_entry(struct cbfs_image *image, struct cbfs_file *entry, return 0; } -/* Finds a place to hold whole stage data in same memory page. +/* Finds a place to hold whole data in same memory page. */ static int is_in_same_page(uint32_t start, uint32_t size, uint32_t page) { if (!page) @@ -781,24 +781,44 @@ static int is_in_same_page(uint32_t start, uint32_t size, uint32_t page) { return (start / page) == (start + size - 1) / page; } +/* Tests if data can fit in a range by given offset: + * start ->| header_len | offset (+ size) |<- end + */ +static int is_in_range(uint32_t start, uint32_t end, uint32_t header_len, + uint32_t offset, uint32_t size) { + return (offset >= start + header_len && offset + size <= end); +} + int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, - uint32_t size, uint32_t page_size) { + uint32_t size, uint32_t page_size, uint32_t align) { struct cbfs_file *entry; size_t need_len; - uint32_t addr, addr_next, addr2, addr3, header_len; - assert(size < page_size); + uint32_t addr, addr_next, addr2, addr3, offset, header_len; + + /* Default values: allow fitting anywhere in ROM. */ + if (!page_size) + page_size = ntohl(image->header->romsize); + if (!align) + align = 1; + + if (size > page_size) + ERROR("Input file size (%d) greater than page size (%d).\n", + size, page_size); if (page_size % ntohl(image->header->align)) - WARN("locate_entry: page does not align with CBFS image.\n"); + WARN("%s: Page size (%#x) not aligned with CBFS image (%#x).\n", + __func__, page_size, ntohl(image->header->align)); /* TODO Old cbfstool always assume input is a stage file (and adding * sizeof(cbfs_stage) for header. We should fix that by adding "-t" - * (type) param in future. For right now, follow old behavior. */ + * (type) param in future. For right now, we assume cbfs_stage is the + * largest structure and add it into header size. */ + assert(sizeof(struct cbfs_stage) >= sizeof(struct cbfs_payload)); header_len = (cbfs_calculate_file_header_size(name) + sizeof(struct cbfs_stage)); need_len = header_len + size; - // Merge empty entries to build get max available pages. + // Merge empty entries to build get max available space. cbfs_walk(image, cbfs_merge_empty_entry, NULL); /* Three cases of content location on memory page: @@ -812,14 +832,15 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, * shift-> | <header>|<content> | at starting of PAGE 2. * * case 3. (large content filling whole page) - * | PAGE 1 | PAGE 2 | PAGE 3| - * | <header>< content > | | Can't fit. If we shift content to - * | { free space . } PAGE 2, header can't fit in free - * | shift-> <header><content> space, so we must use PAGE 3. + * | PAGE 1 | PAGE 2 | PAGE 3 | + * | <header>< content > | Can't fit. If we shift content to + * |trial-> <header>< content > | PAGE 2, header can't fit in free + * | shift-> <header><content> space, so we must use PAGE 3. * - * The returned address will be used to re-link stage file, and then - * assigned to add-stage command (-b), which will be then re-calculated - * by ELF loader and positioned by cbfs_add_entry. + * The returned address can be then used as "base-address" (-b) in add-* + * commands (will be re-calculated and positioned by cbfs_add_entry_at). + * For stage targets, the address is also used to re-link stage before + * being added into CBFS. */ for (entry = cbfs_find_first_entry(image); entry && cbfs_is_valid_entry(image, entry); @@ -834,23 +855,29 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, image, entry)); if (addr_next - addr < need_len) continue; - if (is_in_same_page(addr + header_len, size, page_size)) { + + offset = align_up(addr + header_len, align); + if (is_in_same_page(offset, size, page_size) && + is_in_range(addr, addr_next, header_len, offset, size)) { DEBUG("cbfs_locate_entry: FIT (PAGE1)."); - return addr + header_len; + return offset; } addr2 = align_up(addr, page_size); - if (addr2 < addr_next && addr_next - addr2 >= size && - addr2 - addr >= header_len) { + offset = align_up(addr2, align); + if (is_in_range(addr, addr_next, header_len, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP (PAGE2)."); - return addr2; + return offset; } + /* Assume page_size >= header_len so adding one page will + * definitely provide the space for header. */ + assert(page_size >= header_len); addr3 = addr2 + page_size; - if (addr3 < addr_next && addr_next - addr3 >= size && - addr3 - addr >= header_len) { + offset = align_up(addr3, align); + if (is_in_range(addr, addr_next, header_len, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP+ (PAGE3)."); - return addr3; + return offset; } } return -1; diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 57bbfa1..7ad418a 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -76,10 +76,12 @@ int cbfs_remove_entry(struct cbfs_image *image, const char *name); int cbfs_create_empty_entry(struct cbfs_image *image, struct cbfs_file *entry, size_t len, const char *name); -/* Finds a location to put given content in same memory page. +/* Finds a location to put given content by specified criteria: + * "page_size" limits the content to fit on same memory page, and + * "align" specifies starting address alignment. * Returns a valid offset, or -1 on failure. */ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, - uint32_t size, uint32_t page_size); + uint32_t size, uint32_t page_size, uint32_t align); /* Callback function used by cbfs_walk. * Returns 0 on success, or non-zero to stop further iteration. */ diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 97fd88d..7eca01d 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -50,6 +50,7 @@ static struct param { uint32_t entrypoint; uint32_t size; uint32_t alignment; + uint32_t pagesize; uint32_t offset; uint32_t top_aligned; comp_algo algo; @@ -355,12 +356,12 @@ static int cbfs_locate(void) } address = cbfs_locate_entry(&image, param.name, buffer.size, - param.alignment); + param.pagesize, param.alignment); buffer_delete(&buffer); if (address == -1) { - ERROR("'%s' can't fit in CBFS for align 0x%x.\n", - param.name, param.alignment); + ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n", + param.name, param.pagesize, param.alignment); cbfs_image_delete(&image); return 1; } @@ -421,7 +422,7 @@ static const struct command commands[] = { {"add-flat-binary", "f:n:l:e:c:b:vh?", cbfs_add_flat_binary}, {"remove", "n:vh?", cbfs_remove}, {"create", "s:B:b:H:a:o:m:vh?", cbfs_create}, - {"locate", "f:n:a:Tvh?", cbfs_locate}, + {"locate", "f:n:a:P:Tvh?", cbfs_locate}, {"print", "vh?", cbfs_print}, {"extract", "n:f:vh?", cbfs_extract}, }; @@ -437,6 +438,7 @@ static struct option long_options[] = { {"size", required_argument, 0, 's' }, {"bootblock", required_argument, 0, 'B' }, {"alignment", required_argument, 0, 'a' }, + {"page-size", required_argument, 0, 'P' }, {"offset", required_argument, 0, 'o' }, {"file", required_argument, 0, 'f' }, {"arch", required_argument, 0, 'm' }, @@ -468,7 +470,7 @@ static void usage(char *name) "Remove a component\n" " create -s size -B bootblock -m ARCH [-a align] [-o offset] " "Create a ROM file\n" - " locate -f FILE -n NAME [-a align] [-T] " + " locate -f FILE -n NAME [-P page-size] [-a align] [-T] " "Find a place for a file of that size\n" " print " "Show the contents of the ROM\n" @@ -572,6 +574,9 @@ int main(int argc, char **argv) case 'a': param.alignment = strtoul(optarg, NULL, 0); break; + case 'P': + param.pagesize = strtoul(optarg, NULL, 0); + break; case 'o': param.offset = strtoul(optarg, NULL, 0); break;

1 0

Patch set updated for coreboot: 133e5cb cbfstool: Extend "locate" command to support alignment and page-fitting.
by Hung-Te Lin 18 Mar '13

18 Mar '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2730 -gerrit commit 133e5cb1c3e149544a7f6e5e24018d70dec675ac Author: Hung-Te Lin <hungte(a)chromium.org> Date: Fri Mar 15 14:44:05 2013 +0800 cbfstool: Extend "locate" command to support alignment and page-fitting. cbfstool usage change: The "-a" parameter for "cbfstool locate" has changed to "-P/--page-size". "-a" for "cbfstool locate" is now for specifying base address alignment. The "locate" command was used to find a place to store ELF stage image in one memory page. Its argument "-a (alignment)" was actually specifying the page size instead of doing memory address alignment. This can be confusing when people are trying to put a blob in aligned location (ex, microcode needs to be aligned in 0x10), and see this: cbfstool coreboot.rom localte -f test.bin -n test -a 0x100 # output: 0x44, which does not look like aligned to 0x100. To support that and prevent confusion, we should rename the page-fitting argument to "-P/--page-size" and leave "-a/--alignment" for real alignment. Verified by manually testing a file (324 bytes) with alignment=0x10: cbfstool coreboot.rom locate -f test -n test -a 0x10 # output: 0x71fdd0 cbfstool coreboot.rom add -f test -n test -t raw -b 0x71fdd0 cbfstool coreboot.rom print -v -v # output: test 0x71fd80 raw 324 # output: cbfs_file=0x71fd80, offset=0x50, content_address=0x71fdd0+0x144 And verified to be compatible with old behavior by building i386/axus/tc320 (with page limitation 0x40000): cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000 # output: 0x44 cbfstool coreboot.rom locate -f x.bin -n romstage -P 0x40000 -a 0x30 # output: 0x60 Change-Id: I0893adde51ebf46da1c34913f9c35507ed8ff731 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/arch/armv7/Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 2 +- util/cbfstool/cbfs_image.c | 71 +++++++++++++++++++++++++++++++-------------- util/cbfstool/cbfs_image.h | 6 ++-- util/cbfstool/cbfstool.c | 15 ++++++---- 5 files changed, 65 insertions(+), 31 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 39c115e..8601112 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -282,7 +282,7 @@ $(objgenerated)/romstage_xip.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/bas $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin @printf " generating base_xip.txt\n" rm -f $@ - $(CBFSTOOL) $(obj)/coreboot.pre1 locate -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -a $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } mv $@.tmp $@ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 0892efd..3c57701 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -387,7 +387,7 @@ $(objgenerated)/romstage_xip.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/bas $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin rm -f $@ - $(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -a $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } mv $@.tmp $@ diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 2cdbf23..321779f 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -773,7 +773,7 @@ int cbfs_create_empty_entry(struct cbfs_image *image, struct cbfs_file *entry, return 0; } -/* Finds a place to hold whole stage data in same memory page. +/* Finds a place to hold whole data in same memory page. */ static int is_in_same_page(uint32_t start, uint32_t size, uint32_t page) { if (!page) @@ -781,24 +781,44 @@ static int is_in_same_page(uint32_t start, uint32_t size, uint32_t page) { return (start / page) == (start + size - 1) / page; } +/* Tests if data can fit in a range by given offset: + * start ->| header_len | offset (+ size) |<- end + */ +static int is_in_range(uint32_t start, uint32_t end, uint32_t header_len, + uint32_t offset, uint32_t size) { + return (offset >= start + header_len && offset + size <= end); +} + int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, - uint32_t size, uint32_t page_size) { + uint32_t size, uint32_t page_size, uint32_t align) { struct cbfs_file *entry; size_t need_len; - uint32_t addr, addr_next, addr2, addr3, header_len; - assert(size < page_size); + uint32_t addr, addr_next, addr2, addr3, offset, header_len; + + /* Default values: allow fitting anywhere in ROM. */ + if (!page_size) + page_size = ntohl(image->header->romsize); + if (!align) + align = 1; + + if (size > page_size) + ERROR("Input file size (%d) greater than page size (%d).\n", + size, page_size); if (page_size % ntohl(image->header->align)) - WARN("locate_entry: page does not align with CBFS image.\n"); + WARN("%s: Page size (%#x) not aligned with CBFS image (%#x).\n", + __func__, page_size, ntohl(image->header->align)); /* TODO Old cbfstool always assume input is a stage file (and adding * sizeof(cbfs_stage) for header. We should fix that by adding "-t" - * (type) param in future. For right now, follow old behavior. */ + * (type) param in future. For right now, we assume cbfs_stage is the + * largest structure and add it into header size. */ + assert(sizeof(struct cbfs_stage) >= sizeof(struct cbfs_payload)); header_len = (cbfs_calculate_file_header_size(name) + sizeof(struct cbfs_stage)); need_len = header_len + size; - // Merge empty entries to build get max available pages. + // Merge empty entries to build get max available space. cbfs_walk(image, cbfs_merge_empty_entry, NULL); /* Three cases of content location on memory page: @@ -812,14 +832,15 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, * shift-> | <header>|<content> | at starting of PAGE 2. * * case 3. (large content filling whole page) - * | PAGE 1 | PAGE 2 | PAGE 3| - * | <header>< content > | | Can't fit. If we shift content to - * | { free space . } PAGE 2, header can't fit in free - * | shift-> <header><content> space, so we must use PAGE 3. + * | PAGE 1 | PAGE 2 | PAGE 3 | + * | <header>< content > | Can't fit. If we shift content to + * |trial-> <header>< content > | PAGE 2, header can't fit in free + * | shift-> <header><content> space, so we must use PAGE 3. * - * The returned address will be used to re-link stage file, and then - * assigned to add-stage command (-b), which will be then re-calculated - * by ELF loader and positioned by cbfs_add_entry. + * The returned address can be then used as "base-address" (-b) in add-* + * commands (will be re-calulated and positioned by cbfs_add_entry_at). + * For stage targets, the address is also used to re-link stage before + * being added into CBFS. */ for (entry = cbfs_find_first_entry(image); entry && cbfs_is_valid_entry(image, entry); @@ -834,23 +855,29 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, image, entry)); if (addr_next - addr < need_len) continue; - if (is_in_same_page(addr + header_len, size, page_size)) { + + offset = align_up(addr + header_len, align); + if (is_in_same_page(offset, size, page_size) && + is_in_range(addr, addr_next, header_len, offset, size)) { DEBUG("cbfs_locate_entry: FIT (PAGE1)."); - return addr + header_len; + return offset; } addr2 = align_up(addr, page_size); - if (addr2 < addr_next && addr_next - addr2 >= size && - addr2 - addr >= header_len) { + offset = align_up(addr2, align); + if (is_in_range(addr, addr_next, header_len, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP (PAGE2)."); - return addr2; + return offset; } + /* Assume page_size >= header_len so adding one page will + * definitely provide the space for header. */ + assert(page_size >= header_len); addr3 = addr2 + page_size; - if (addr3 < addr_next && addr_next - addr3 >= size && - addr3 - addr >= header_len) { + offset = align_up(addr3, align); + if (is_in_range(addr, addr_next, header_len, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP+ (PAGE3)."); - return addr3; + return offset; } } return -1; diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 57bbfa1..e7a5d6b 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -76,10 +76,12 @@ int cbfs_remove_entry(struct cbfs_image *image, const char *name); int cbfs_create_empty_entry(struct cbfs_image *image, struct cbfs_file *entry, size_t len, const char *name); -/* Finds a location to put given content in same memory page. +/* Finds a location to put given content by specified criteria: + * "page_size" limits the content to fit on same memory page, and + * "align" specified starting address alignment. * Returns a valid offset, or -1 on failure. */ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, - uint32_t size, uint32_t page_size); + uint32_t size, uint32_t page_size, uint32_t align); /* Callback function used by cbfs_walk. * Returns 0 on success, or non-zero to stop further iteration. */ diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 97fd88d..7eca01d 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -50,6 +50,7 @@ static struct param { uint32_t entrypoint; uint32_t size; uint32_t alignment; + uint32_t pagesize; uint32_t offset; uint32_t top_aligned; comp_algo algo; @@ -355,12 +356,12 @@ static int cbfs_locate(void) } address = cbfs_locate_entry(&image, param.name, buffer.size, - param.alignment); + param.pagesize, param.alignment); buffer_delete(&buffer); if (address == -1) { - ERROR("'%s' can't fit in CBFS for align 0x%x.\n", - param.name, param.alignment); + ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n", + param.name, param.pagesize, param.alignment); cbfs_image_delete(&image); return 1; } @@ -421,7 +422,7 @@ static const struct command commands[] = { {"add-flat-binary", "f:n:l:e:c:b:vh?", cbfs_add_flat_binary}, {"remove", "n:vh?", cbfs_remove}, {"create", "s:B:b:H:a:o:m:vh?", cbfs_create}, - {"locate", "f:n:a:Tvh?", cbfs_locate}, + {"locate", "f:n:a:P:Tvh?", cbfs_locate}, {"print", "vh?", cbfs_print}, {"extract", "n:f:vh?", cbfs_extract}, }; @@ -437,6 +438,7 @@ static struct option long_options[] = { {"size", required_argument, 0, 's' }, {"bootblock", required_argument, 0, 'B' }, {"alignment", required_argument, 0, 'a' }, + {"page-size", required_argument, 0, 'P' }, {"offset", required_argument, 0, 'o' }, {"file", required_argument, 0, 'f' }, {"arch", required_argument, 0, 'm' }, @@ -468,7 +470,7 @@ static void usage(char *name) "Remove a component\n" " create -s size -B bootblock -m ARCH [-a align] [-o offset] " "Create a ROM file\n" - " locate -f FILE -n NAME [-a align] [-T] " + " locate -f FILE -n NAME [-P page-size] [-a align] [-T] " "Find a place for a file of that size\n" " print " "Show the contents of the ROM\n" @@ -572,6 +574,9 @@ int main(int argc, char **argv) case 'a': param.alignment = strtoul(optarg, NULL, 0); break; + case 'P': + param.pagesize = strtoul(optarg, NULL, 0); + break; case 'o': param.offset = strtoul(optarg, NULL, 0); break;

1 0

Patch set updated for coreboot: a1223c4 armv7/exynos/snow: set up caches properly
by David Hendricks 18 Mar '13

18 Mar '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2729 -gerrit commit a1223c4ea1ca094341e18ec1737e27b2ce22b2a7 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Mar 14 15:24:57 2013 -0700 armv7/exynos/snow: set up caches properly ** do not submit ** This (hopefully) sets up caches more carefully than we were doing before. This patch needs a bit more testing before going in. TODO: - Get rid of imported CP15ISB and isb() macros. They are wrong for ARMv7 -- it was assumed in u-boot that the code would be compiled with -march=armv5 (see comment in armv7.h). - Clean up. Most of this is now done in a generic manner in bootblock_simple, so a lot of earlier code can go away. - Set cache policy explicitly before re-enabling - Replace imported cache routines (and use BSD license to match libpayload?) Change-Id: I7390981190e3213f4e1431f8e56746545c5cc7c9 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/bootblock_simple.c | 242 ++++++++++++++++++++++++++++++ src/arch/armv7/include/system.h | 18 ++- src/arch/armv7/lib/Makefile.inc | 1 + src/arch/armv7/lib/cache-cp15.c | 3 +- src/arch/armv7/lib/cache_v7.c | 2 +- src/cpu/samsung/exynos5250/Makefile.inc | 1 - src/cpu/samsung/exynos5250/bootblock.c | 2 + src/cpu/samsung/exynos5250/exynos_cache.c | 8 +- src/mainboard/google/snow/ramstage.c | 15 -- src/mainboard/google/snow/romstage.c | 54 ++++--- 10 files changed, 296 insertions(+), 50 deletions(-) diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index 0132b87..c5d900d 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -24,9 +24,233 @@ #include <arch/stages.h> #include <cbfs.h> #include <console/console.h> +#include <system.h> #include "stages.c" +/* FIXME: gross hack to get around src/include/lib.h's romcc limitation. Note: + * returns 0 in the log2(0) case. */ +static unsigned long log2(unsigned long u) +{ + int i = 0; + + while (u >>= 1) + i++; + + return i; +} + +#if 0 +/* + * Set/clear program flow prediction and return the previous state. + */ +static int config_branch_prediction(int set_cr_z) +{ + unsigned int cr; + + /* System Control Register: 11th bit Z Branch prediction enable */ + cr = get_cr(); + set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z); + + return cr & CR_Z; +} +#endif + +static inline uint32_t read_clidr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (val)); + return val; +} + +static inline uint32_t read_ccsidr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); + return val; +} + +static inline uint32_t read_csselr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (val)); + return val; +} + +/* Write to Cache Size Selection Register (CSSELR) */ +static inline void write_csselr(uint32_t val) +{ + /* + * Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd) + * Bit 0 - 0 = data or unified cache, 1 = instruction cache + */ + asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (val)); + isb(); /* ISB to sync the change in case CCSIDR follows */ +} + +/* Branch predictor invalidate all */ +static inline void bpiall(void) +{ + asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); +} + +/* Invalidate entire unified TLB */ +static inline void tlbiall(void) +{ + asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); +} + +/* Instruction cache invalidate all by PoU */ +static inline void iciallu(void) +{ + asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); +} + +/* Data cache invalidate all by set/way */ +static inline void dcisw(uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val)); +} + +static inline void dsb(void) +{ + asm volatile ("dsb"); +} + +/* FIXME: replace isb() in system.h */ +static inline void myisb(void) +{ + asm volatile ("isb"); +} + +static void clear_icache(unsigned int level) +{ + uint32_t ccselr; + + ccselr = (level << 1) | 1; + write_csselr(ccselr); + + /* icache can be entirely invalidated with one operation. + * Note: If branch predictors are architecturally-visible, ICIALLU + * also performs a BPIALL operation (B2-1283 in arch manual) + */ + iciallu(); + isb(); +} + +#define bitmask(high, low) ((1UL << (high)) + \ + ((1UL << (high)) - 1) - ((1UL << (low)) - 1)) + +static void clear_dcache(unsigned int level) +{ + uint32_t ccsidr, ccselr; + unsigned int associativity, num_sets, linesize_bytes; + unsigned int set, way; + + ccselr = level << 1; + write_csselr(ccselr); + + /* + * dcache must be invalidated by set/way for portability since virtual + * memory mapping is system-defined. The number of sets and + * associativity is given by CCSIDR. We'll use DCISW to invalidate the + * dcache. + */ + ccsidr = read_ccsidr(); + + /* FIXME: rounding up required here? */ + num_sets = ((ccsidr & bitmask(27, 13)) >> 13) + 1; + associativity = ((ccsidr & bitmask(12, 3)) >> 3) + 1; + /* FIXME: do we need to use CTR.DminLine here? */ + linesize_bytes = (1 << ((ccsidr & 0x7) + 2)) * 4; + + /* + * Set/way operations require an interesting bit packing. See section + * B4-35 in the ARMv7 Architecture Reference Manual: + * + * A: Log2(associativity) + * B: L+S + * L: Log2(linesize) + * S: Log2(num_sets) + * + * The bits are packed as follows: + * 31 31-A B B-1 L L-1 4 3 1 0 + * |---|-------------|--------|-------|-----|-| + * |Way| zeros | Set | zeros |level|0| + * |---|-------------|--------|-------|-----|-| + */ + for (way = 0; way < associativity; way++) { + for (set = 0; set < num_sets; set++) { + uint32_t val = 0; + val |= way << (32 - log2(associativity)); + val |= set << log2(linesize_bytes); + val |= level << 1; + dcisw(val); + } + } + + dsb(); +} + +static void armv7_invalidate_caches(void) +{ + uint32_t clidr; + int level; + + /* + * From Cortex-A Series Programmers guide (Example 15-3): + * 1. Disable MMU + * 2. Disable L1 caches (example disables i-cache then d-cache) + * 3. Invalidate L1 caches (same order) + * 4. Invalidate TLB + * + * L2 cache setup will be done by SoC-specific code. MMU setup + * needs to be done after DRAM init in board-specific code. + */ + + /* Invalidate branch predictor */ + bpiall(); + + /* + * Iterate thru each cache identified in CLIDR and invalidate. + */ + clidr = read_clidr(); + for (level = 0; level < 7; level++) { + unsigned int ctype = (clidr >> (level * 3)) & 0x7; + switch(ctype) { + case 0x0: + /* no cache */ + break; + case 0x1: + /* icache only */ + clear_icache(level); + break; + case 0x2: + case 0x4: + /* dcache only or unified cache */ + clear_dcache(level); + break; + case 0x3: + /* separate icache and dcache */ + clear_icache(level); + clear_dcache(level); + break; + default: + /* reserved */ + break; + } + } + + /* Invalidate TLB */ + v7_inval_tlb(); + /* FIXME: ARMv7 Architecture Ref. Manual claims that the distinction + * instruction vs. data TLBs is deprecated in ARMv7. But that doesn't + * really seem true for Cortex-A15? */ +// itlbiall(); +// dtlbiall(); +// tlbiall(); +} + static int boot_cpu(void) { /* @@ -41,6 +265,24 @@ void main(void) { const char *stage_name = "fallback/romstage"; void *entry; + uint32_t sctlr; + + /* Globally disable MMU, caches, and branch prediction (these should + * be disabled by default on reset) */ + sctlr = get_cr(); + sctlr &= ~(CR_M | CR_C | CR_Z | CR_I); + set_cr(sctlr); + + armv7_invalidate_caches(); + + /* + * Re-enable caches and branch prediction. MMU will be set up later. + * Note: If booting from USB, we need to disable branch prediction + * before copying from USB into RAM (FIXME: why?) + */ + sctlr = get_cr(); + sctlr |= CR_C | CR_Z | CR_I; + set_cr(sctlr); if (boot_cpu()) { bootblock_cpu_init(); diff --git a/src/arch/armv7/include/system.h b/src/arch/armv7/include/system.h index 053df8d..fdafd15 100644 --- a/src/arch/armv7/include/system.h +++ b/src/arch/armv7/include/system.h @@ -61,7 +61,21 @@ static inline void set_cr(unsigned int val) { asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" : : "r" (val) : "cc"); - isb(); + isb(); /* ref: B3.10.2 of ARM Arch Ref. Manual for ARMv7 */ +} + +static inline unsigned int get_acr(void) +{ + unsigned int val; + asm("mrc p15, 0, %0, c1, c0, 1 @ get ACR" : "=r" (val) : : "cc"); + return val; +} + +static inline void set_acr(unsigned int val) +{ + asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set ACR" + : : "r" (val) : "cc"); + isb(); /* ref: B3.10.2 of ARM Arch Ref. Manual for ARMv7 */ } /* options available for data cache on each page */ @@ -97,6 +111,8 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop); void mmu_setup(unsigned long start, unsigned long size); +void v7_inval_tlb(void); + void arm_init_before_mmu(void); /* diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 508f776..75e6752 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -14,6 +14,7 @@ ramstage-y += div0.c #ramstage-y += memcpy.S #ramstage-y += memset.S ramstage-y += syslib.c +ramstage-y += cache-cp15.c ramstage-y += cache_v7.c #FIXME(dhendrix): should this be a config option? diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c index e08ea57..32f3c79 100644 --- a/src/arch/armv7/lib/cache-cp15.c +++ b/src/arch/armv7/lib/cache-cp15.c @@ -123,8 +123,7 @@ inline void mmu_setup(unsigned long start, unsigned long size_mb) int i; u32 reg; - arm_init_before_mmu(); - +// arm_init_before_mmu(); /* Set up an identity-mapping for all 4GB, rw for everyone */ for (i = 0; i < 4096; i++) set_section_dcache(i, DCACHE_OFF); diff --git a/src/arch/armv7/lib/cache_v7.c b/src/arch/armv7/lib/cache_v7.c index 31072c7..1764351 100644 --- a/src/arch/armv7/lib/cache_v7.c +++ b/src/arch/armv7/lib/cache_v7.c @@ -226,7 +226,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) } /* Invalidate TLB */ -static void v7_inval_tlb(void) +void v7_inval_tlb(void) { /* Invalidate entire unified TLB */ asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 2774b12..961b719 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -30,7 +30,6 @@ ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c -ramstage-y += exynos_cache.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/bootblock.c b/src/cpu/samsung/exynos5250/bootblock.c index 949468f..4995dc2 100644 --- a/src/cpu/samsung/exynos5250/bootblock.c +++ b/src/cpu/samsung/exynos5250/bootblock.c @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <armv7.h> + void bootblock_cpu_init(void); void bootblock_cpu_init(void) { diff --git a/src/cpu/samsung/exynos5250/exynos_cache.c b/src/cpu/samsung/exynos5250/exynos_cache.c index 7f4effe..87eded5 100644 --- a/src/cpu/samsung/exynos5250/exynos_cache.c +++ b/src/cpu/samsung/exynos5250/exynos_cache.c @@ -34,15 +34,11 @@ enum l2_cache_params { }; -/* FIXME(dhendrix): maybe move this to a romstage-specific file? */ -#ifdef __PRE_RAM__ void enable_caches(void) { - /* Enable D-cache. I-cache is already enabled in start.S */ - /* can't use it anyway -- it has dependencies we have to fix. */ - //dcache_enable(); + icache_enable(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); + dcache_enable(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); } -#endif /* * Set L2 cache parameters diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index e4d53cf..687f9b1 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -23,22 +23,10 @@ #include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/power.h> -#include <system.h> /* FIXME: for testing cache */ -static void cp_delay(void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++) - nop(); - asm volatile("" : : : "memory"); -} - static inline uint32_t read_clidr(void) { uint32_t val = 0; asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (val)); - isb(); return val; } @@ -46,7 +34,6 @@ static inline uint32_t read_ccsidr(void) { uint32_t val = 0; asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); - isb(); return val; } @@ -54,7 +41,6 @@ static inline uint32_t read_csselr(void) { uint32_t val = 0; asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (val)); - isb(); return val; } @@ -66,7 +52,6 @@ static inline void write_csselr(uint32_t val) * Bit 0 - 0 = data or unified cache, 1 = instruction cache */ asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (val)); - isb(); } #ifndef __mask diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index ea2feec..0a46f2d 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -20,6 +20,7 @@ #include <types.h> #include <system.h> +#include <armv7.h> #include <cache.h> #include <cbfs.h> #include <common.h> @@ -52,20 +53,6 @@ static int board_wakeup_permitted(void) } #endif -/* - * Set/clear program flow prediction and return the previous state. - */ -static int config_branch_prediction(int set_cr_z) -{ - unsigned int cr; - - /* System Control Register: 11th bit Z Branch prediction enable */ - cr = get_cr(); - set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z); - - return cr & CR_Z; -} - static void initialize_s5p_mshc(void) { /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ @@ -88,19 +75,33 @@ static void graphics(void) exynos_pinmux_config(PERIPH_ID_DPHPD, 0); } +static inline void dsb(void) +{ + asm volatile ("dsb"); +} + +/* FIXME: replace isb() from system.h */ +static inline void my_isb(void) +{ + asm volatile ("isb"); +} + void main(void) { struct mem_timings *mem; struct arm_clk_ratios *arm_ratios; int ret; void *entry; - - /* FIXME: if we boot from USB, we need to disable branch prediction - * before copying from USB into RAM */ - config_branch_prediction(1); + unsigned int cr; clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ + /* + * FIXME: Do necessary I2C init so low-level PMIC code doesn't need to. + * Also, we should only call power_init() on cold boot. + */ + power_init(); + /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ mem = get_mem_timings(); @@ -109,12 +110,6 @@ void main(void) console_init(); - /* - * FIXME: Do necessary I2C init so low-level PMIC code doesn't need to. - * Also, we should only call power_init() on cold boot. - */ - power_init(); - if (!mem) { printk(BIOS_CRIT, "Unable to auto-detect memory timings\n"); while(1); @@ -132,7 +127,18 @@ void main(void) while(1); } + /* Set up MMU and caches */ mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); +// cr = get_cr(); +// cr |= CR_C | CR_I; +// set_cr(cr); + + /* Enable D-side prefetch */ + cr = get_acr(); + cr |= (1 << 2); + set_acr(cr); + dsb(); + my_isb(); initialize_s5p_mshc();

1 0

Patch merged into coreboot/master: afad056 Add Intel Whitetip Mountain 2 mainboard
by gerrit＠coreboot.org 18 Mar '13

18 Mar '13

the following patch was just integrated into master: commit afad056c2298824caeb2c58d1541576c73bfef5d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 14 08:50:03 2013 -0800 Add Intel Whitetip Mountain 2 mainboard This is mostly a copy of Whitetip Mountain 1 with specific GPIO map for this Customer Reference Board (CRB). This mainboard currently has basic funcionality and is able to boot a Linux Kernel but many of the new Haswell ULT specific devices are not yet enabled. Change-Id: I999452d86f00a2c245fa39b1b76080f6a3b1e352 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2725 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Mar 18 00:15:26 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Mar 18 00:18:48 2013, giving +2 See http://review.coreboot.org/2725 for details. -gerrit

1 0

Patch set updated for coreboot: c3a79fc Add Intel Whitetip Mountain 2 mainboard
by Duncan Laurie 18 Mar '13

18 Mar '13

Duncan Laurie (dlaurie(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2725 -gerrit commit c3a79fc374d58104e90fd441c9ee3706c3e33d3b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 14 08:50:03 2013 -0800 Add Intel Whitetip Mountain 2 mainboard This is mostly a copy of Whitetip Mountain 1 with specific GPIO map for this Customer Reference Board (CRB). This mainboard currently has basic funcionality and is able to boot a Linux Kernel but many of the new Haswell ULT specific devices are not yet enabled. Change-Id: I999452d86f00a2c245fa39b1b76080f6a3b1e352 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/intel/Kconfig | 3 + src/mainboard/intel/wtm2/Kconfig | 44 +++ src/mainboard/intel/wtm2/Makefile.inc | 23 ++ src/mainboard/intel/wtm2/acpi/chromeos.asl | 23 ++ src/mainboard/intel/wtm2/acpi/ec.asl | 37 +++ src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl | 76 +++++ src/mainboard/intel/wtm2/acpi/mainboard.asl | 28 ++ src/mainboard/intel/wtm2/acpi/platform.asl | 73 ++++ src/mainboard/intel/wtm2/acpi/superio.asl | 20 ++ src/mainboard/intel/wtm2/acpi/thermal.asl | 246 ++++++++++++++ src/mainboard/intel/wtm2/acpi/video.asl | 43 +++ src/mainboard/intel/wtm2/acpi_tables.c | 282 ++++++++++++++++ src/mainboard/intel/wtm2/chromeos.c | 77 +++++ src/mainboard/intel/wtm2/cmos.layout | 139 ++++++++ src/mainboard/intel/wtm2/devicetree.cb | 85 +++++ src/mainboard/intel/wtm2/dsdt.asl | 56 ++++ src/mainboard/intel/wtm2/fadt.c | 156 +++++++++ src/mainboard/intel/wtm2/gpio.h | 369 +++++++++++++++++++++ src/mainboard/intel/wtm2/hda_verb.h | 99 ++++++ src/mainboard/intel/wtm2/mainboard.c | 243 ++++++++++++++ src/mainboard/intel/wtm2/mainboard_smi.c | 73 ++++ src/mainboard/intel/wtm2/romstage.c | 248 ++++++++++++++ src/mainboard/intel/wtm2/thermal.h | 57 ++++ 23 files changed, 2500 insertions(+) diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig index 0000957..3594a30 100644 --- a/src/mainboard/intel/Kconfig +++ b/src/mainboard/intel/Kconfig @@ -23,6 +23,8 @@ config BOARD_INTEL_BASKING_RIDGE bool "Basking Ridge CRB" config BOARD_INTEL_WTM1 bool "Whitetip Mountain 1 CRB" +config BOARD_INTEL_WTM2 + bool "Whitetip Mountain 2 CRB" endchoice @@ -36,6 +38,7 @@ source "src/mainboard/intel/mtarvon/Kconfig" source "src/mainboard/intel/truxton/Kconfig" source "src/mainboard/intel/xe7501devkit/Kconfig" source "src/mainboard/intel/wtm1/Kconfig" +source "src/mainboard/intel/wtm2/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig new file mode 100644 index 0000000..8942591 --- /dev/null +++ b/src/mainboard/intel/wtm2/Kconfig @@ -0,0 +1,44 @@ +if BOARD_INTEL_WTM2 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_HASWELL + select SOUTHBRIDGE_INTEL_LYNXPOINT + select INTEL_LYNXPOINT_LP + select BOARD_ROMSIZE_KB_8192 + select BOARD_HAS_FADT + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select MMCONF_SUPPORT + select HAVE_SMI_HANDLER + select CHROMEOS + select EXTERNAL_MRC_BLOB + +config MAINBOARD_DIR + string + default intel/wtm2 + +config MAINBOARD_PART_NUMBER + string + default "WHITETIP MOUNTAIN 2" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 16 + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +endif # BOARD_INTEL_WTM2 diff --git a/src/mainboard/intel/wtm2/Makefile.inc b/src/mainboard/intel/wtm2/Makefile.inc new file mode 100644 index 0000000..658c96c --- /dev/null +++ b/src/mainboard/intel/wtm2/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/intel/wtm2/acpi/chromeos.asl b/src/mainboard/intel/wtm2/acpi/chromeos.asl new file mode 100644 index 0000000..c6b258b --- /dev/null +++ b/src/mainboard/intel/wtm2/acpi/chromeos.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name(OIPG, Package() { + // This GPIO is not available but the package cannot be empty + Package () { 0x0001, 0, 0, "LynxPoint" }, // recovery +}) diff --git a/src/mainboard/intel/wtm2/acpi/ec.asl b/src/mainboard/intel/wtm2/acpi/ec.asl new file mode 100644 index 0000000..9ae5951 --- /dev/null +++ b/src/mainboard/intel/wtm2/acpi/ec.asl @@ -0,0 +1,37 @@ +Device (EC0) +{ + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 1) + Name (_GPE, 10) // GPIO 10 is SMC_RUNTIME_SCI_N + + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, Lock, Preserve) + { + Offset (0x03), + ACPR, 1, // AC Power (1=present) + , 2, + CFAN, 1, // CPU Fan (1=on) + , 2, + LIDS, 1, // Lid State (1=open) + , 1, + SPTR, 8, // SMBUS Protocol Register + SSTS, 8, // SMBUS Status Register + SADR, 8, // SMBUS Address Register + SCMD, 8, // SMBUS Command Register + SBFR, 256, // SMBUS Block Buffer + SCNT, 8, // SMBUS Block Count + + Offset (0x3a), + ECMD, 8, // EC Command Register + + Offset (0x82), + PECL, 8, // PECI fractional (1/64 Celsius) + PECH, 8, // PECI integer (Celsius) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) +} diff --git a/src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl b/src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl new file mode 100644 index 0000000..a8b6b5f --- /dev/null +++ b/src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for IvyBridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 }, + Package() { 0x001cffff, 1, 0, 18 }, + Package() { 0x001cffff, 2, 0, 19 }, + Package() { 0x001cffff, 3, 0, 20 }, + // EHCI 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, 0, 16 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 21 }, + Package() { 0x001fffff, 1, 0, 22 }, + Package() { 0x001fffff, 2, 0, 23 }, + Package() { 0x001fffff, 3, 0, 16 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, 0, 16 }, + Package() { 0x0015ffff, 1, 0, 17 }, + Package() { 0x0015ffff, 2, 0, 18 }, + Package() { 0x0015ffff, 3, 0, 19 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, 0, 16 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} + diff --git a/src/mainboard/intel/wtm2/acpi/mainboard.asl b/src/mainboard/intel/wtm2/acpi/mainboard.asl new file mode 100644 index 0000000..3e0eb33 --- /dev/null +++ b/src/mainboard/intel/wtm2/acpi/mainboard.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake from deep sleep via GPIO27 + Name(_PRW, Package(){27, 4}) +} diff --git a/src/mainboard/intel/wtm2/acpi/platform.asl b/src/mainboard/intel/wtm2/acpi/platform.asl new file mode 100644 index 0000000..e069392 --- /dev/null +++ b/src/mainboard/intel/wtm2/acpi/platform.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + diff --git a/src/mainboard/intel/wtm2/acpi/superio.asl b/src/mainboard/intel/wtm2/acpi/superio.asl new file mode 100644 index 0000000..9092a6c --- /dev/null +++ b/src/mainboard/intel/wtm2/acpi/superio.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Values should match those defined in devicetree.cb */ diff --git a/src/mainboard/intel/wtm2/acpi/thermal.asl b/src/mainboard/intel/wtm2/acpi/thermal.asl new file mode 100644 index 0000000..00a8750 --- /dev/null +++ b/src/mainboard/intel/wtm2/acpi/thermal.asl @@ -0,0 +1,246 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 0 seconds + Name (_TZP, 0) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (_TMP, 0, Serialized) + { + Return (CTOK (30)) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (\F0OF)) + } Else { + Return (CTOK (\F0ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (\F1OF)) + } Else { + Return (CTOK (\F1ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (\F2OF)) + } Else { + Return (CTOK (\F2ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (\F3OF)) + } Else { + Return (CTOK (\F3ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (\F4OF)) + } Else { + Return (CTOK (\F4ON)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (0, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (1, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (1, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (2, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (2, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (3, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (3, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (4, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (4, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (4, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} + diff --git a/src/mainboard/intel/wtm2/acpi/video.asl b/src/mainboard/intel/wtm2/acpi/video.asl new file mode 100644 index 0000000..3ececa9 --- /dev/null +++ b/src/mainboard/intel/wtm2/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c new file mode 100644 index 0000000..18c9bb2 --- /dev/null +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -0,0 +1,282 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <vendorcode/google/chromeos/gnvs.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->f4of = FAN4_THRESHOLD_OFF; + gnvs->f4on = FAN4_THRESHOLD_ON; + gnvs->f4pw = FAN4_PWM; + + gnvs->f3of = FAN3_THRESHOLD_OFF; + gnvs->f3on = FAN3_THRESHOLD_ON; + gnvs->f3pw = FAN3_PWM; + + gnvs->f2of = FAN2_THRESHOLD_OFF; + gnvs->f2on = FAN2_THRESHOLD_ON; + gnvs->f2pw = FAN2_PWM; + + gnvs->f1of = FAN1_THRESHOLD_OFF; + gnvs->f1on = FAN1_THRESHOLD_ON; + gnvs->f1pw = FAN1_PWM; + + gnvs->f0of = FAN0_THRESHOLD_OFF; + gnvs->f0on = FAN0_THRESHOLD_ON; + gnvs->f0pw = FAN0_PWM; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; +} + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* CBMEM TOC */ + gnvs->cmem = (u32)get_cbmem_toc(); + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + +#if CONFIG_CHROMEOS + // TODO(reinauer) this could move elsewhere? + chromeos_init_vboot(&(gnvs->chromeos)); + /* Emerald Lake has no EC (?) */ + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; +#endif + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " + "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + acpi_save_gnvs(current); + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + /* And tell SMI about it */ + smm_setup_structures((void *)current, NULL, NULL); + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c new file mode 100644 index 0000000..1864754 --- /dev/null +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <arch/io.h> +#ifdef __PRE_RAM__ +#include <arch/romcc_io.h> +#else +#include <device/device.h> +#include <device/pci.h> +#endif +#include <southbridge/intel/lynxpoint/pch.h> + +#ifndef __PRE_RAM__ +#include <boot/coreboot_tables.h> +#include <arch/coreboot_tables.h> + +#define GPIO_COUNT 6 +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +static void fill_lb_gpio(struct lb_gpio *gpio, int num, + int polarity, const char *name, int force) +{ + memset(gpio, 0, sizeof(*gpio)); + gpio->port = num; + gpio->polarity = polarity; + if (force >= 0) + gpio->value = force; + else if (num >= 0) + gpio->value = get_gpio(num); + strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", 0); // force off + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", 1); // force on + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); // force open + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); +} +#endif + +int get_developer_mode_switch(void) +{ + return 1; // force on +} + +int get_recovery_mode_switch(void) +{ + return 0; // force off +} diff --git a/src/mainboard/intel/wtm2/cmos.layout b/src/mainboard/intel/wtm2/cmos.layout new file mode 100644 index 0000000..afdd3c6 --- /dev/null +++ b/src/mainboard/intel/wtm2/cmos.layout @@ -0,0 +1,139 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb new file mode 100644 index 0000000..db7c998 --- /dev/null +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -0,0 +1,85 @@ +chip northbridge/intel/haswell + + # Enable DisplayPort 1 Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable DisplayPort 0 Hotplug with 6ms pulse + register "gpu_dp_c_hotplug" = "0x06" + + # Enable DVI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + device cpu_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/haswell + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) + register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) + register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en" = "0x0000" + + register "ide_legacy_combined" = "0x0" + register "sata_ahci" = "0x1" + register "sata_port_map" = "0x2" + + device pci 13.0 on end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 on end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl new file mode 100644 index 0000000..ed953c4 --- /dev/null +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + #include "acpi/thermal.asl" + + #include "../../../cpu/intel/haswell/acpi/cpu.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } + } + + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> +} diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c new file mode 100644 index 0000000..510b765 --- /dev/null +++ b/src/mainboard/intel/wtm2/fadt.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), + 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/intel/wtm2/gpio.h b/src/mainboard/intel/wtm2/gpio.h new file mode 100644 index 0000000..179259c --- /dev/null +++ b/src/mainboard/intel/wtm2/gpio.h @@ -0,0 +1,369 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef INTEL_WTM2_GPIO_H +#define INTEL_WTM2_GPIO_H + +#include "southbridge/intel/lynxpoint/lp_gpio.h" + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + /* LPSS_UART1_RXD */ + { .gpio = 0, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_UART1_TXD */ + { .gpio = 1, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_UART1_RTS_N_R */ + { .gpio = 2, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_UART1_CTS_N */ + { .gpio = 3, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_I2C0_SDA_R */ + { .gpio = 4, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_I2C0_SCL */ + { .gpio = 5, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_I2C1_SDA */ + { .gpio = 6, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_I2C1_SCL */ + { .gpio = 7, + .conf0 = GPIO_MODE_NATIVE }, + /* NGFF_SLTA_WIFI_WAKE_N */ + { .gpio = 8, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .conf1 = GPIO_SENSE_DISABLE }, + /* ACCEL_INT2_MCP (NGFF_SLTA_UART_WAKE_N) */ + { .gpio = 9, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .conf1 = GPIO_SENSE_DISABLE }, + /* SMC_RUNTIME_SCI_N */ + { .gpio = 10, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, + .conf1 = GPIO_SENSE_ENABLE, + .owner = GPIO_OWNER_ACPI, + .route = GPIO_ROUTE_SCI }, + /* AMB_THRM_R_N */ + { .gpio = 11, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .conf1 = GPIO_SENSE_DISABLE }, + /* PM_LANPHY_ENABLE */ + { .gpio = 12, + .conf0 = GPIO_MODE_NATIVE }, + /* USB32_P0_PWREN */ + { .gpio = 13, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, + .conf1 = GPIO_SENSE_DISABLE }, + /* SH_INT_ACCEL_DRDY_USB_INT_N */ + { .gpio = 14, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, + .conf1 = GPIO_SENSE_ENABLE, + .owner = GPIO_OWNER_GPIO, + .irqen = GPIO_IRQ_ENABLE }, + /* LAN_PWREN_N */ + { .gpio = 15, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, + .conf1 = GPIO_SENSE_DISABLE }, + /* LAN_RST_N */ + { .gpio = 16, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, + .conf1 = GPIO_SENSE_DISABLE }, + /* CRIT_TEMP_REP_R_N (NGFF_SLTB_CARD_PRESENT_SSD_N) */ + { .gpio = 17, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW }, + /* TBT_FORCE_PWR */ + { .gpio = 18, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT, + .conf1 = GPIO_SENSE_DISABLE }, + /* EC_IN_RW */ + { .gpio = 19, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .conf1 = GPIO_SENSE_DISABLE, + .owner = GPIO_OWNER_GPIO }, + /* CK_REQ_P2_NGFFSLTA_N_R */ + { .gpio = 20, + .conf0 = GPIO_MODE_NATIVE }, + /* CK_PCIE_LAN_REQ_N */ + { .gpio = 21, + .conf0 = GPIO_MODE_NATIVE }, + /* CK_REQ_P4_TBT_N */ + { .gpio = 22, + .conf0 = GPIO_MODE_NATIVE }, + /* CK_REQ_P5_N */ + { .gpio = 23, + .conf0 = GPIO_MODE_NATIVE }, + /* ME_PG_LED (NGFF_SLTB_WWN_CRD_PRSNT) */ + { .gpio = 24, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, + .conf1 = GPIO_SENSE_DISABLE }, + /* USB_WAKEOUT_N */ + { .gpio = 25, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .conf1 = GPIO_SENSE_ENABLE }, + /* NFC_IRQ_MGP5 */ + { .gpio = 26, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, + .conf1 = GPIO_SENSE_ENABLE, + .owner = GPIO_OWNER_GPIO, + .irqen = GPIO_IRQ_ENABLE }, + /* SMC_WAKE_SCI_N */ + { .gpio = 27, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .conf1 = GPIO_SENSE_ENABLE }, + /* PCH_NFC_RESET */ + { .gpio = 28, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, + .conf1 = GPIO_SENSE_DISABLE }, + /* PCH_SLP_WLAN_N */ + { .gpio = 29, + .conf0 = GPIO_MODE_NATIVE }, + /* SUS_PWR_ACK_R */ + { .gpio = 30, + .conf0 = GPIO_MODE_NATIVE }, + /* AC_PRESENT_R */ + { .gpio = 31, + .conf0 = GPIO_MODE_NATIVE }, + /* PM_CKRUN_N */ + { .gpio = 32, + .conf0 = GPIO_MODE_NATIVE }, + /* SATA0_PHYSLP */ + { .gpio = 33, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, + .conf1 = GPIO_SENSE_DISABLE }, + /* ESATA_DET_N */ + { .gpio = 34, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + /* SATA_DIRECT_PRSNT_R_N */ + { .gpio = 35, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + /* NGFF_SSD_SATA2_PCIE1_DET_N */ + { .gpio = 36, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + /* NGFF_SSD_SATA3_PCIE0_DET_N */ + { .gpio = 37, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + /* SATA1_PHYSLP_DIRECT */ + { .gpio = 38, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, + .conf1 = GPIO_SENSE_DISABLE }, + /* SMC_EXTSMI_N_R */ + { .gpio = 39, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .conf1 = GPIO_SENSE_ENABLE, + .owner = GPIO_OWNER_ACPI, + .route = GPIO_ROUTE_SMI }, + /* USB_OC_0_1_R_N */ + { .gpio = 40, + .conf0 = GPIO_MODE_NATIVE }, + /* USB_OC_2_6_R_N */ + { .gpio = 41, + .conf0 = GPIO_MODE_NATIVE }, + /* TBT_CIO_PLUG_SMI_N_R */ + { .gpio = 42, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .conf1 = GPIO_SENSE_DISABLE }, + /* USB32_P1_PWREN */ + { .gpio = 43, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, + .conf1 = GPIO_SENSE_DISABLE }, + /* SENSOR_HUB_RST_N */ + { .gpio = 44, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + /* GYRO_INT2_MCP_R (TBT_WAKE_Q_N) */ + { .gpio = 45, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + /* SNSR_HUB_PWREN */ + { .gpio = 46, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, + .conf1 = GPIO_SENSE_DISABLE }, + /* SPI_TPM_HDR_IRQ_N */ + { .gpio = 47, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .conf1 = GPIO_SENSE_ENABLE, + .owner = GPIO_OWNER_GPIO, + .irqen = GPIO_IRQ_ENABLE }, + /* PCIE_TBT_RST_N */ + { .gpio = 48, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, + .conf1 = GPIO_SENSE_DISABLE }, + /* COMBO_JD */ + { .gpio = 49, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + /* TOUCH_PANEL_INTR_N */ + { .gpio = 50, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .conf1 = GPIO_SENSE_ENABLE, + .owner = GPIO_OWNER_GPIO, + .irqen = GPIO_IRQ_ENABLE }, + /* PCH_WIFI_RF_KILL_N */ + { .gpio = 51, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, + .conf1 = GPIO_SENSE_DISABLE }, + /* TOUCH_PNL_RST_N_R */ + { .gpio = 52, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, + .conf1 = GPIO_SENSE_DISABLE }, + /* SNSR_HUB_I2C_WAKE / ALS_INT_MCP (NGFF_SLTB_WWAN_SSD_DET2) */ + { .gpio = 53, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .conf1 = GPIO_SENSE_ENABLE, + .owner = GPIO_OWNER_GPIO }, + /* NGFF_SLTB_SSD_MC_WAKE_N */ + { .gpio = 54, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .conf1 = GPIO_SENSE_ENABLE, + .owner = GPIO_OWNER_GPIO }, + /* TOUCHPAD_INTR_N */ + { .gpio = 55, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .conf1 = GPIO_SENSE_ENABLE, + .owner = GPIO_OWNER_GPIO, + .irqen = GPIO_IRQ_ENABLE }, + /* NGFF_SLTB_WWAN_SSD_DET1 */ + { .gpio = 56, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + /* NGFF_SLTB_WWAN_PWREN */ + { .gpio = 57, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, + .conf1 = GPIO_SENSE_DISABLE }, + /* SLATEMODE_HALLOUT_R */ + { .gpio = 58, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, + .conf1 = GPIO_SENSE_DISABLE }, + /* USB2_CAM_PWREN */ + { .gpio = 59, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, + .conf1 = GPIO_SENSE_DISABLE }, + /* USB_CR_PWREN_N */ + { .gpio = 60, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, + .conf1 = GPIO_SENSE_DISABLE }, + /* PM_SUS_STAT_N */ + { .gpio = 61, + .conf0 = GPIO_MODE_NATIVE }, + /* SUS_CK */ + { .gpio = 62, + .conf0 = GPIO_MODE_NATIVE }, + /* SLP_S5_R_N */ + { .gpio = 63, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_SDIO_CLK_CMNHDR_R */ + { .gpio = 64, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_SDIO_CMD_CMNHDR_R */ + { .gpio = 65, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_SDIO_D0_CMNHDR_R */ + { .gpio = 66, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_SDIO_D1_CMNHDR_R */ + { .gpio = 67, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_SDIO_D2_CMNHDR_R */ + { .gpio = 68, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_SDIO_D3_CMNHDR_R1 */ + { .gpio = 69, + .conf0 = GPIO_MODE_NATIVE }, + /* NGFF_SLTA_WIFI_PWREN_N_R (SDIO_POWER_EN) */ + { .gpio = 70, + .conf0 = GPIO_MODE_NATIVE }, + /* MPHY_PWREN */ + { .gpio = 71, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, + .conf1 = GPIO_SENSE_DISABLE }, + /* PM_BATLOW_R_N */ + { .gpio = 72, + .conf0 = GPIO_MODE_NATIVE }, + /* PCH_NOT_N */ + { .gpio = 73, + .conf0 = GPIO_MODE_NATIVE }, + /* SML1_DATA */ + { .gpio = 74, + .conf0 = GPIO_MODE_NATIVE }, + /* SML1_CK */ + { .gpio = 75, + .conf0 = GPIO_MODE_NATIVE }, + /* PCH_AUDIO_PWR_R */ + { .gpio = 76, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, + .conf1 = GPIO_SENSE_DISABLE }, + /* PC_SLTB_SSD_RST_N_R */ + { .gpio = 77, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, + .conf1 = GPIO_SENSE_DISABLE }, + /* PM_EXTTS0_EC_N */ + { .gpio = 78, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + /* SIO1007_IRQ_N */ + { .gpio = 79, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + /* PM_EXTTS1_R_N */ + { .gpio = 80, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + /* PCH_HDA_SPKR */ + { .gpio = 81, + .conf0 = GPIO_MODE_NATIVE }, + /* H_RCIN_N */ + { .gpio = 82, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_GSPI0_CS_R_N */ + { .gpio = 83, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_GSPI0_CLK_R */ + { .gpio = 84, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_GSPI0_MISO_R */ + { .gpio = 85, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_GSPI0_MOSI_BBS0_R */ + { .gpio = 86, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_GSPI1_CS_R_N */ + { .gpio = 87, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_GSPI1_CLK_R */ + { .gpio = 88, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_GSPI1_MISO_R */ + { .gpio = 89, + .conf0 = GPIO_MODE_NATIVE }, + /* NGFF_SLTA_WIFI_RST_N */ + { .gpio = 90, + .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, + .conf1 = GPIO_SENSE_DISABLE }, + /* LPSS_UART0_RXD */ + { .gpio = 91, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_UART0_TXD */ + { .gpio = 92, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_UART0_RTS_N */ + { .gpio = 93, + .conf0 = GPIO_MODE_NATIVE }, + /* LPSS_UART0_CTS_N */ + { .gpio = 94, + .conf0 = GPIO_MODE_NATIVE }, + /* END */ + { .gpio = GPIO_LIST_END } +}; + +#endif diff --git a/src/mainboard/intel/wtm2/hda_verb.h b/src/mainboard/intel/wtm2/hda_verb.h new file mode 100644 index 0000000..c34d0f5 --- /dev/null +++ b/src/mainboard/intel/wtm2/hda_verb.h @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210 + 0x10134210, // Subsystem ID + 0x00000007, // Number of jacks + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10134210 */ + 0x00172010, + 0x00172142, + 0x00172213, + 0x00172310, + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x05) 1/8 Gray HP Out at Ext Front */ + 0x00571cf0, + 0x00571d20, + 0x00571e21, + 0x00571f02, + + /* Pin Complex (NID 0x06) Analog Unknown Speaker at Int N/A */ + 0x00671c10, + 0x00671d00, + 0x00671e17, + 0x00671f90, + + /* Pin Complex (NID 0x07) 1/8 Grey Line In at Ext Front */ + 0x00771cf0, + 0x00771d20, + 0x00771ea1, + 0x00771f02, + + /* Pin Complex (NID 0x08) Analog Unknown Mic at Oth Mobile-In */ + 0x00871c37, + 0x00871d00, + 0x00871ea7, + 0x00871f77, + + /* Pin Complex (NID 0x09) Digital Unknown Mic at Oth Mobile-In */ + 0x00971c3e, + 0x00971d00, + 0x00971ea6, + 0x00971f77, + + /* Pin Complex (NID 0x0a) Optical Black SPDIF Out at Ext N/A */ + 0x00a71cf0, + 0x00a71d10, + 0x00a71e45, + 0x00a71f43, + + /* coreboot specific header */ + 0x80862805, // Codec Vendor / Device ID: Intel CougarPoint HDMI + 0x80860101, // Subsystem ID + 0x00000004, // Number of jacks + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + 0x00172001, + 0x00172101, + 0x00172286, + 0x00172380, + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + 0x30571c10, + 0x30571d00, + 0x30571e56, + 0x30571f18, + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + 0x30671c20, + 0x30671d00, + 0x30671e56, + 0x30671f18, + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + 0x30771c30, + 0x30771d00, + 0x30771e56, + 0x30771f18 +}; + diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c new file mode 100644 index 0000000..e84b16e --- /dev/null +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -0,0 +1,243 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <arch/coreboot_tables.h> +#include "hda_verb.h" +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE +static int int15_handler(struct eregs *regs) +{ + int res=-1; + + printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", + __func__, regs->eax & 0xffff); + + switch(regs->eax & 0xffff) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffffff00; + regs->ecx |= 0x01; + res = 0; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) * + * bit 2 = EFP * + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) * + * bit 6 = EFP2 * + * bit 7 = LFP2 + */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffff0000; + regs->ecx |= 0x0000; + res = 0; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffff0000; + regs->ecx |= 0x0003; + res = 0; + break; + case 0x5f70: + switch ((regs->ecx >> 8) & 0xff) { + case 0: + /* Get Mux */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffff0000; + regs->ecx |= 0x0000; + res = 0; + break; + case 1: + /* Set Mux */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffff0000; + regs->ecx |= 0x0000; + res = 0; + break; + case 2: + /* Get SG/Non-SG mode */ + regs->eax &= 0xffff0000; + regs->eax |= 0x005f; + regs->ecx &= 0xffff0000; + regs->ecx |= 0x0000; + res = 0; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", + ((regs->ecx >> 8) & 0xff)); + return 0; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + regs->eax & 0xffff); + break; + } + return res; +} +#endif + +#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +static int int15_handler(void) +{ + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); + + switch (M.x86.R_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0001; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) * + * bit 2 = EFP * + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) * + * bit 6 = EFP2 * + * bit 7 = LFP2 + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 3; + break; + case 0x5f70: + /* Unknown */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n", + M.x86.R_AX); + return 0; + } + + /* Interrupt handled */ + return 1; +} +#endif + +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +static void int15_install(void) +{ +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL + typedef int (* yabel_handleIntFunc)(void); + extern yabel_handleIntFunc yabel_intFuncArray[256]; + yabel_intFuncArray[0x15] = int15_handler; +#endif +#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} +#endif + +/* Audio Setup */ + +extern const u32 * cim_verb_data; +extern u32 cim_verb_data_size; + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE + /* Install custom int15 handler for VGA OPROM */ + int15_install(); +#endif + verb_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/intel/wtm2/mainboard_smi.c b/src/mainboard/intel/wtm2/mainboard_smi.c new file mode 100644 index 0000000..281e061 --- /dev/null +++ b/src/mainboard/intel/wtm2/mainboard_smi.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/lynxpoint/nvs.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/me.h> +#include <northbridge/intel/haswell/haswell.h> +#include <cpu/intel/haswell/haswell.h> + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +#define APMC_FINALIZE 0xcb + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APMC_FINALIZE: + if (mainboard_finalized) { + printk(BIOS_DEBUG, "SMI#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_northbridge_haswell_finalize_smm(); + intel_cpu_haswell_finalize_smm(); + + mainboard_finalized = 1; + break; + } + return 0; +} diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c new file mode 100644 index 0000000..75a4e99 --- /dev/null +++ b/src/mainboard/intel/wtm2/romstage.c @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <cbmem.h> +#include <console/console.h> +#include "northbridge/intel/haswell/haswell.h" +#include "northbridge/intel/haswell/raminit.h" +#include "southbridge/intel/lynxpoint/me.h" +#include "southbridge/intel/lynxpoint/pch.h" +#include "southbridge/intel/lynxpoint/lp_gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include "gpio.h" +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/chromeos.h> +#endif + +const struct rcba_config_instruction rcba_config[] = { + + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P4IP ETH0 INTB -> PIRQC + * D29IP_E1P EHCI1 INTA -> PIRQD + * D20IP_XHCI XHCI INTA -> PIRQA + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQH + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + */ + + /* Device interrupt pin register (board specific) */ + RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), + RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), + RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP)), + RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), + RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), + RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), + RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), + RCBA_SET_REG_32(D20IR, (INTA << D20IP_XHCI)), + + /* Device interrupt route registers */ + RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)), + RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)), + RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)), + RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)), + RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQA, 0, 0, 0)), + + /* Disable unused devices (board specific) */ + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void main(unsigned long bist) +{ + int boot_mode = 0; + int wake_from_s3; + int cbmem_was_initted; + +#if CONFIG_COLLECT_TIMESTAMPS + tsc_t start_romstage_time; + tsc_t before_dram_time; + tsc_t after_dram_time; + tsc_t base_time = { + .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), + .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) + }; +#endif + struct pei_data pei_data = { + pei_version: PEI_VERSION, + mchbar: DEFAULT_MCHBAR, + dmibar: DEFAULT_DMIBAR, + epbar: DEFAULT_EPBAR, + pciexbar: DEFAULT_PCIEXBAR, + smbusbar: SMBUS_IO_BASE, + wdbbar: 0x4000000, + wdbsize: 0x1000, + hpet_address: HPET_ADDR, + rcba: DEFAULT_RCBA, + pmbase: DEFAULT_PMBASE, + gpiobase: DEFAULT_GPIOBASE, + temp_mmio_base: 0xfed08000, + system_type: 5, /* ULT */ + tseg_size: CONFIG_SMM_TSEG_SIZE, + spd_addresses: { 0xa2, 0x00, 0xa2, 0x00 }, + ec_present: 1, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + dimm_channel0_disabled: 2, + dimm_channel1_disabled: 2, + max_ddr3_freq: 1600, + usb_port_config: { + { 1, 0, 0x0040 }, /* P0: */ + { 1, 0, 0x0040 }, /* P1: */ + { 1, 0, 0x0040 }, /* P2: */ + { 1, 0, 0x0040 }, /* P3: */ + { 1, 0, 0x0040 }, /* P4: */ + { 1, 0, 0x0040 }, /* P5: */ + { 1, 0, 0x0040 }, /* P6: */ + { 1, 0, 0x0040 }, /* P7: */ + { 1, 0, 0x0040 }, /* P8: */ + { 1, 0, 0x0040 }, /* P9: */ + { 1, 0, 0x0040 }, /* P10: */ + { 1, 0, 0x0000 }, /* P11: */ + { 1, 0, 0x0040 }, /* P12: */ + { 1, 0, 0x0040 }, /* P13: */ + }, + }; + +#if CONFIG_COLLECT_TIMESTAMPS + start_romstage_time = rdtsc(); +#endif + + if (bist == 0) + enable_lapic(); + + wake_from_s3 = early_pch_init(&mainboard_gpio_map, &rcba_config[0]); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + haswell_early_initialization(HASWELL_MOBILE); + printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); + + if (wake_from_s3) { +#if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; +#else + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); +#endif + } + + /* Prepare USB controller early in S3 resume */ + if (boot_mode == 2) + enable_usb_bar(); + + post_code(0x3a); + pei_data.boot_mode = boot_mode; +#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = rdtsc(); +#endif + + report_platform_info(); + + sdram_initialize(&pei_data); + +#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = rdtsc(); +#endif + post_code(0x3b); + + intel_early_me_status(); + + quick_ram_check(); + post_code(0x3e); + + MCHBAR16(SSKPD) = 0xCAFE; +#if CONFIG_EARLY_CBMEM_INIT + cbmem_was_initted = !cbmem_initialize(); +#else + cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() + - HIGH_MEMORY_SIZE)); +#endif + +#if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + + *(u32 *)CBMEM_BOOT_MODE = 0; + *(u32 *)CBMEM_RESUME_BACKUP = 0; + + if ((boot_mode == 2) && cbmem_was_initted) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (resume_backup_memory) { + *(u32 *)CBMEM_BOOT_MODE = boot_mode; + *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; + } + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } else if (boot_mode == 2) { + /* Failed S3 resume, reset to come up cleanly */ + outb(0x6, 0xcf9); + while (1) { + hlt(); + } + } else { + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + } +#endif + post_code(0x3f); +#if CONFIG_CHROMEOS + init_chromeos(boot_mode); +#endif +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); + timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); + timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); + timestamp_add(TS_AFTER_INITRAM, after_dram_time ); + timestamp_add_now(TS_END_ROMSTAGE); +#endif +#if CONFIG_CONSOLE_CBMEM + /* Keep this the last thing this function does. */ + cbmemc_reinit(); +#endif +} diff --git a/src/mainboard/intel/wtm2/thermal.h b/src/mainboard/intel/wtm2/thermal.h new file mode 100644 index 0000000..e6116b6 --- /dev/null +++ b/src/mainboard/intel/wtm2/thermal.h @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef WTM2_THERMAL_H +#define WTM2_THERMAL_H + +/* Fan is OFF */ +#define FAN4_THRESHOLD_OFF 0 +#define FAN4_THRESHOLD_ON 0 +#define FAN4_PWM 0x00 + +/* Fan is at LOW speed */ +#define FAN3_THRESHOLD_OFF 48 +#define FAN3_THRESHOLD_ON 55 +#define FAN3_PWM 0x40 + +/* Fan is at MEDIUM speed */ +#define FAN2_THRESHOLD_OFF 52 +#define FAN2_THRESHOLD_ON 64 +#define FAN2_PWM 0x80 + +/* Fan is at HIGH speed */ +#define FAN1_THRESHOLD_OFF 60 +#define FAN1_THRESHOLD_ON 68 +#define FAN1_PWM 0xb0 + +/* Fan is at FULL speed */ +#define FAN0_THRESHOLD_OFF 66 +#define FAN0_THRESHOLD_ON 78 +#define FAN0_PWM 0xff + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 100 + +#endif

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Patch merged into coreboot/master: ab9b71d superiotool: Add support for the IT8728F Super I/O
by gerrit＠coreboot.org 17 Mar '13

17 Mar '13

the following patch was just integrated into master: commit ab9b71d54c0638f051e93b0109e04f7da39ee6ab Author: Андрей Павлов <7134956(a)gmail.com> Date: Sun Mar 17 19:11:05 2013 +0300 superiotool: Add support for the IT8728F Super I/O $ superiotool -d superiotool r4.0-3712-gd549279 Found ITE IT8728F (id=0x8728, rev=0x1) at 0x2e Register dump: idx 02 07 20 21 22 23 24 2b 2e 2f val 00 0a 87 28 01 00 00 40 00 00 def NA NA 87 28 01 00 00 MM 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 00 03 f0 06 02 00 00 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 val 01 03 f8 04 00 50 def 00 03 f8 04 00 50 LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 val 00 02 f8 03 00 50 def 00 02 f8 03 00 50 LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 01 03 78 00 00 07 04 08 def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 f9 fa fb val 01 0a 30 0a 20 09 00 80 00 00 20 00 f0 48 00 00 def 00 02 90 02 30 09 00 00 00 00 00 MM MM MM MM MM LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 08 def 01 00 60 00 64 01 02 48 LDN 0x06 (Mouse) idx 30 70 71 f0 val 01 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 2d 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc cd ce cf e0 e1 e2 e3 e4 e9 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb val 00 f3 10 00 00 00 80 00 00 00 0a 00 00 00 00 00 20 00 00 00 00 00 00 00 20 00 00 00 00 00 01 00 00 40 00 01 00 00 00 00 00 00 00 00 00 00 00 00 21 10 42 00 00 00 00 1c 00 00 00 00 00 def 00 f3 00 00 00 00 03 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 20 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 MM 00 00 00 00 00 00 00 00 00 00 00 00 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 06 Change-Id: Ifb45d28005d78b2a99d8552b59154d11bdf44f6f Signed-off-by: Андрей Павлов <7134956(a)gmail.com> Reviewed-on: http://review.coreboot.org/2775 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Build-Tested: build bot (Jenkins) at Sun Mar 17 22:45:07 2013, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Sun Mar 17 23:20:37 2013, giving +2 See http://review.coreboot.org/2775 for details. -gerrit

1 0

Patch merged into coreboot/master: 15ba2bc Intel HD Audio: clean up initialization code
by gerrit＠coreboot.org 17 Mar '13

17 Mar '13

the following patch was just integrated into master: commit 15ba2bcf2d78181de1047f46b6ae28e44fbd3f86 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Nov 14 12:25:15 2012 -0800 Intel HD Audio: clean up initialization code - Some initialization steps were done twice - One step was missing for Panther Point HDA - Added a 1ms delay after reset - Increased timeout to 1ms for all codec operations Change-Id: Ib751f1a16ccd88ea2fbbb2a10737f76277574026 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2518 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 26 02:11:56 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sun Mar 17 22:54:55 2013, giving +2 See http://review.coreboot.org/2518 for details. -gerrit

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coreboot March 2013