coreboot March 2013

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Patch merged into coreboot/master: 2ad1dba haswell: move call site of save_mrc_data()
by gerrit＠coreboot.org 18 Mar '13

18 Mar '13

the following patch was just integrated into master: commit 2ad1dbaf2a2dfe373ff89927202acc01e36c7cd4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Feb 7 00:51:18 2013 -0600 haswell: move call site of save_mrc_data() The save_mrc_data() was previously called conditionally in the raminit code. The save_mrc_data() function was called in the non-S3 wake paths. However, the common romstage_common() code was checking cbmem initialization things on s3 wake. Between the two callers cbmem_initialize() was being called twice in the non-s3 wake paths. Moreover, saving of the mrc data was not allowed when CONFIG_EARLY_CBMEM_INIT wasn't enabled. Therefore, move the save_mrc_data() to romstage_common. It already has the knowledge of the wake path. Also remove the CONFIG_EARLY_CBMEM_INIT requirement from save_mrc_data() as well as the call to cbmem_initialize(). Change-Id: I7f0e4d752c92d9d5eedb8fa56133ec190caf77da Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2756 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 16 01:02:43 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Mar 18 20:50:14 2013, giving +2 See http://review.coreboot.org/2756 for details. -gerrit

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Patch merged into coreboot/master: 38d9423 haswell: romstage: pass stack pointer and MTRRs
by gerrit＠coreboot.org 18 Mar '13

18 Mar '13

the following patch was just integrated into master: commit 38d9423dbe300514e1ba7224a962650980a96217 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Feb 7 00:03:33 2013 -0600 haswell: romstage: pass stack pointer and MTRRs Instead of hard coding the policy for the stack and MTRR values after the cache-as-ram is torn down, allow for the C code to pass those policies back to the cache-as-ram assembly file. That way, ramstage relocation can use a different stack as well as different MTRR policies. Change-Id: Ied024d933f96a12ed0703c51c506586f4b50bd14 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2755 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 16 00:51:53 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Mar 18 20:49:46 2013, giving +2 See http://review.coreboot.org/2755 for details. -gerrit

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Patch merged into coreboot/master: a267161 haswell: unify romstage logic
by gerrit＠coreboot.org 18 Mar '13

18 Mar '13

the following patch was just integrated into master: commit a267161362f23b94f2e7677a8ea55f729578a049 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 6 21:41:01 2013 -0600 haswell: unify romstage logic This commit pulls in all the common logic for romstage into the Haswell cpu directory. The bits specific to the mainboard still reside under their respective directories. The calling sequence bounces from the cpu directory to mainboard then back to the cpu directory. The reasoning is that Haswell systems use cache-as-ram for backing memory in romstage. The stack is used to allocate structures. However, now changes can be made to the romstage for Haswell and apply to all boards. Change-Id: I2bf08013c46a99235ffe4bde88a935c3378eb341 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2754 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 16 00:41:19 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Mar 18 20:48:46 2013, giving +2 See http://review.coreboot.org/2754 for details. -gerrit

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Patch merged into coreboot/master: 9b7f9b9 haswell: remove unused sys_info structure
by gerrit＠coreboot.org 18 Mar '13

18 Mar '13

the following patch was just integrated into master: commit 9b7f9b97686bd5594518828249a5e0e2e6f377e7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Feb 7 00:09:59 2013 -0600 haswell: remove unused sys_info structure This structure is not used nor the variable being instantiated on the stack. Remove them. Change-Id: If3abe2dd77104eff49665dd33570b07179bf34f5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2753 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 16 00:30:19 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Mar 18 20:48:17 2013, giving +2 See http://review.coreboot.org/2753 for details. -gerrit

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Patch merged into coreboot/master: 3d0071b haswell: adjust CAR usage
by gerrit＠coreboot.org 18 Mar '13

18 Mar '13

the following patch was just integrated into master: commit 3d0071bde363bbcd2ef3d68bac67400feced1778 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 18 14:32:50 2013 -0600 haswell: adjust CAR usage It was found that the Haswell reference code was smashing through the stack into the reference code's heap implementation. The reason for this is because our current CAR allocation is too small. Moreover there are quite a few things to coordinate between 2 code bases to get correct. This commit separates the CAR into 2 parts: 1. MRC CAR usage. 2. Coreboot CAR usage. Pointers from one region can be passed between the 2 modules, but one should not be able to affect the others as checking has been put into place in both modules. The CAR size has effectively been doubled from 0x20000 (128 KiB) to 0x40000 (256KiB). Not all of that increase was needed, but enforcing a power of 2 size only utilizes 1 MTRR. Old CAR layout with a single contiguous stack with the region starting at CONFIG_DCACHE_RAM_BASE: +---------------------------------------+ Offset CONFIG_DCACHE_RAM_SIZE | MRC global variables | | CONFIG_DCACHE_RAM_MRC_VAR_SIZE bytes | +---------------------------------------+ | ROM stage stack | | | | | +---------------------------------------+ | MRC Heap 30000 bytes | +---------------------------------------+ | ROM stage console | | CONFIG_CONSOLE_CAR_BUFFER_SIZE bytes | +---------------------------------------+ | ROM stage CAR_GLOBAL variables | +---------------------------------------+ Offset 0 There was some hard coded offsets in the reference code wrapper to start the heap past the console buffer. Even with this commit the console can smash into the following region depending on what size CONFIG_CONSOLE_CAR_BUFFER_SIZE is. As noted above This change splits the CAR region into 2 parts starting at CONFIG_DCACHE_RAM_BASE: +---------------------------------------+ | MRC Region | | CONFIG_DCACHE_RAM_MRC_VAR_SIZE bytes | +---------------------------------------+ Offset CONFIG_DCACHE_RAM_SIZE | ROM stage stack | | | | | +---------------------------------------+ | ROM stage console | | CONFIG_CONSOLE_CAR_BUFFER_SIZE bytes | +---------------------------------------+ | ROM stage CAR_GLOBAL variables | +---------------------------------------+ Offset 0 Another variable was add, CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE, which represents the expected stack usage for the romstage. A marker is checked at the base of the stack to determine if either the stack was smashed or the console encroached on the stack. Change-Id: Id76f2fe4a5cf1c776c8f0019f406593f68e443a7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2752 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 16 00:19:45 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Mar 18 20:47:50 2013, giving +2 See http://review.coreboot.org/2752 for details. -gerrit

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Patch merged into coreboot/master: 9be4c47 rmodule: add rmodules class and new type
by gerrit＠coreboot.org 18 Mar '13

18 Mar '13

the following patch was just integrated into master: commit 9be4c470bc4b9303b7b449249e1e78aeacf2773f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Jan 12 00:41:44 2013 -0600 rmodule: add rmodules class and new type Add an rmodules class so that there are default rules for compiling files that will be linked by the rmodule linker. Also, add a new type for SIPI vectors. Change-Id: Ided9e15577b34aff34dc23e5e16791c607caf399 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2751 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 16 00:07:54 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Mar 18 20:46:40 2013, giving +2 See http://review.coreboot.org/2751 for details. -gerrit

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Patch merged into coreboot/master: 7542fc7 wtm2: Disable USB port 7 (SD card) due to hang
by gerrit＠coreboot.org 18 Mar '13

18 Mar '13

the following patch was just integrated into master: commit 7542fc7dd267da8502f23ce89644dba8e9e703c5 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Mar 14 14:59:10 2013 -0700 wtm2: Disable USB port 7 (SD card) due to hang This is causing a hang in depthcharge. For now just disable this port. Change-Id: I87a6db2d8361588e82eee640c74cea690115bed5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2764 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 16 02:28:19 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Mar 18 20:46:20 2013, giving +2 See http://review.coreboot.org/2764 for details. -gerrit

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Patch merged into coreboot/master: f06111a libpayload: Fix the config file dependency in the Makefile template
by gerrit＠coreboot.org 18 Mar '13

18 Mar '13

the following patch was just integrated into master: commit f06111aaf4fdb9974e79e130b7ac95cdffcaaa7c Author: Gabe Black <gabeblack(a)google.com> Date: Tue Mar 12 15:50:08 2013 -0700 libpayload: Fix the config file dependency in the Makefile template The template had a dependency on config.h which was correct for coreboot, where this build system originally came from, but not for libpayload which uses the differently named libpayload-config.h, presumably to avoid colliding with a config.h used by the actual payload. Because libpayload-config.h is now effectively a dependency of everything, it doesn't have to be added piecemeal in Makefile.inc. Change-Id: I01f20d363cb1393fa1cdcf0dc916670db90294e9 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2763 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 16 02:16:27 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Mar 18 20:46:09 2013, giving +2 See http://review.coreboot.org/2763 for details. -gerrit

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Patch merged into coreboot/master: a2d786f libpayload: Make keycode constants available outside of curses.h.
by gerrit＠coreboot.org 18 Mar '13

18 Mar '13

the following patch was just integrated into master: commit a2d786f0e6a0db1c88d955ea80b040bebdea4396 Author: Gabe Black <gabeblack(a)google.com> Date: Tue Mar 12 15:44:56 2013 -0700 libpayload: Make keycode constants available outside of curses.h. And include the new, split out version in drivers/keyboard.c and drivers/usb/usbhid.c. Those files were including curses.h just for those definitions, but the include path was only fixed up to to point to the libpayload versions of those files if one of the variants of curses was compiled in. If neither was, gcc would fall back to the system version of that header which is wrong. Change-Id: I8c2ee0baf5f0702bd8c713c8dd4613a4bb269ce5 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2762 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 16 02:05:58 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Mar 18 20:45:47 2013, giving +2 See http://review.coreboot.org/2762 for details. -gerrit

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Patch merged into coreboot/master: 02fdf71 rmodule: include heap in bss section
by gerrit＠coreboot.org 18 Mar '13

18 Mar '13

the following patch was just integrated into master: commit 02fdf718a4b2a7053f19748a0ac0011aa576eb69 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Feb 5 11:09:49 2013 -0600 rmodule: include heap in bss section By including the heap in the bss output section the size is accounted for in a elf PT_LOAD segment. Without this change the heap wasn't being put into a PT_LOAD segment. The result is a nop w.r.t. functionality, but readelf and company will have proper MemSiz fields. Change-Id: Ibfe9bb87603dcd4c5ff1c57c6af910bbba96b02b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2750 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Mar 15 23:57:07 2013, giving +1 See http://review.coreboot.org/2750 for details. -gerrit

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coreboot March 2013