coreboot March 2013

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Patch merged into coreboot/master: 6dccedd x86 intel: Add Firmware Interface Table support
by gerrit＠coreboot.org 17 Mar '13

17 Mar '13

the following patch was just integrated into master: commit 6dcceddff53ad309b91b61661ae7deab37f272ec Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Dec 3 16:17:40 2012 -0600 x86 intel: Add Firmware Interface Table support Haswell CPUs require a FIT table in the firmware. This commit adds rudimentary support for a FIT table. The number of entries in the table is based on a configuration option. The code only generates a type 0 entry. A follow-on tool will need to be developed to populate the FIT entries as well as checksumming the table. Verified image has a FIT pointer and table when option is selected. Change-Id: I3a314016a09a1cc26bf1fb5d17aa50853d2ef4f8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2642 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Mar 14 22:52:31 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sun Mar 17 22:53:51 2013, giving +2 See http://review.coreboot.org/2642 for details. -gerrit

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Patch merged into coreboot/master: 239c2e8 haswell platforms: restructure romstage main
by gerrit＠coreboot.org 17 Mar '13

17 Mar '13

the following patch was just integrated into master: commit 239c2e843f976d5915964c8cb1923305c574f8b5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 19 11:31:17 2012 -0600 haswell platforms: restructure romstage main There was a mix of setup code sprinkled across the various components: southbridge code in the northbridge, etc. This commit reorganizes the code so that northbridge code doesn't initialize southbridge components. Additionally, the calling dram initialization no longer calls out to ME code. The main() function in the mainboard calls the necessary ME functions before and after dram initialization. The biggest change is the addition of an early_pch_init() function which initializes the BARs, GPIOs, and RCBA configuration. It is also responsible for reporting back to the caller if the board is being woken up from S3. The one sequence difference is that the RCBA config is performed before claling the reference code. Lastly the rcba configuration was changed to be table driven so that different board/configurations can use the same code. It should be possible to have board/configuration specific gpio and rcba configuration while reusing the romstage code. Change-Id: I830e41b426261dd686a2701ce054fc39f296dffa Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2681 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Mar 14 23:23:32 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sun Mar 17 22:53:28 2013, giving +2 See http://review.coreboot.org/2681 for details. -gerrit

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Patch merged into coreboot/master: 218a686 Add Intel Whitetip Mountain 1 mainboard
by gerrit＠coreboot.org 17 Mar '13

17 Mar '13

the following patch was just integrated into master: commit 218a6864ff9528ecdb381d91991c9045bbb6843f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Jan 11 09:54:55 2013 -0800 Add Intel Whitetip Mountain 1 mainboard Lots of things are still placeholder and need work. Due to the useful GPIOs being run to either the EC or the SIO1007 I have hard coded developer mode on and recovery mode off. Change-Id: I4c308bd90db03ac5bffdfde566e5adbbaabac632 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2724 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Mar 15 00:37:52 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sun Mar 17 22:52:31 2013, giving +2 See http://review.coreboot.org/2724 for details. -gerrit

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Patch merged into coreboot/master: c9fc029 bd82x6x: Add config option to force SATA link to different speeds.
by gerrit＠coreboot.org 17 Mar '13

17 Mar '13

the following patch was just integrated into master: commit c9fc0297ad6a63d9edf981a46f29f9372d11634c Author: Shawn Nematbakhsh <shawnn(a)google.com> Date: Thu Mar 14 10:44:13 2013 -0700 bd82x6x: Add config option to force SATA link to different speeds. Certain SATA devices claim to support SATA 6 Gbps, but in fact have bugs. For these devices, add a config option to force the SATA link speed to something other than default. Change-Id: I2dc1793cd58771298a392345162d39d20eb0afbb Signed-off-by: Shawn Nematbakhsh <shawnn(a)google.com> Reviewed-on: http://review.coreboot.org/2765 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 16 02:40:09 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sun Mar 17 22:51:47 2013, giving +2 See http://review.coreboot.org/2765 for details. -gerrit

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Patch merged into coreboot/master: 645b376 Pantherpoint: Add XHCI device init
by gerrit＠coreboot.org 17 Mar '13

17 Mar '13

the following patch was just integrated into master: commit 645b376ec82c5343bd197f04fa9e7bb53ee23d69 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Feb 12 14:00:47 2013 -0800 Pantherpoint: Add XHCI device init This enables power management and clock gating on XHCI. Change-Id: I124ea6c5aca034b7ec4b5286d971c2adfce25c88 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2761 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 16 01:55:30 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sun Mar 17 22:51:04 2013, giving +2 See http://review.coreboot.org/2761 for details. -gerrit

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Patch merged into coreboot/master: 8aa210b bd82x6x: don't use absolute symbols
by gerrit＠coreboot.org 17 Mar '13

17 Mar '13

the following patch was just integrated into master: commit 8aa210bbf0343b1da1ab4e164c22da13c985a796 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Feb 8 16:14:07 2013 -0600 bd82x6x: don't use absolute symbols objcopy -B provides symbols of the form _binary_<name>_(start|end|size). However, the _size variant is an absoult symbol. If one wants to relocate the smi loading the _size symbol will be relocated which is wrong since it is suppose to be a fixed size. There is no way to distinguish symbols that shouldn't be relocated vs ones that can. Instead use the _start and _end variants to determine the size. Change-Id: I55192992cf36f62a9d8dd896e5fb3043a3eacbd3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2760 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 16 01:44:44 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sun Mar 17 22:50:04 2013, giving +2 See http://review.coreboot.org/2760 for details. -gerrit

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Patch merged into coreboot/master: 058d70f Add bd82x6x XHCI(USB3) S3/S4 workaround
by gerrit＠coreboot.org 17 Mar '13

17 Mar '13

the following patch was just integrated into master: commit 058d70f163e1a46e16d8577de4e612af04b9aeca Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon Feb 11 14:39:28 2013 -0700 Add bd82x6x XHCI(USB3) S3/S4 workaround The bd82x6x requires some additional setting on S3/S4 entry. Change-Id: I24489ab94dd7cd5a4a64044f25153f5b01a45b77 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2759 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 16 01:34:38 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sun Mar 17 22:49:34 2013, giving +2 See http://review.coreboot.org/2759 for details. -gerrit

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Patch merged into coreboot/master: 783f226 Add bd82x6x PCH functions to SMM
by gerrit＠coreboot.org 17 Mar '13

17 Mar '13

the following patch was just integrated into master: commit 783f226208f0d25cc25ff3a9d56e108a09fb4cff Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon Feb 11 14:36:35 2013 -0700 Add bd82x6x PCH functions to SMM Add the PCH function to SMM for follow-on SMM patches that require these functions. Change-Id: I7f3a512c5e98446e835b59934d63a99e8af15280 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2758 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 16 01:25:01 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sun Mar 17 22:49:00 2013, giving +2 See http://review.coreboot.org/2758 for details. -gerrit

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Patch set updated for coreboot: 71a8223 superiotool: Add support for the IT8728F Super I/O
by Андрей Павлов 17 Mar '13

17 Mar '13

Андрей Павлов (7134956(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2775 -gerrit commit 71a8223eafaccab51b270310a438861c26cec1bb Author: Андрей Павлов <7134956(a)gmail.com> Date: Sun Mar 17 19:11:05 2013 +0300 superiotool: Add support for the IT8728F Super I/O $ superiotool -d superiotool r4.0-3712-gd549279 Found ITE IT8728F (id=0x8728, rev=0x1) at 0x2e Register dump: idx 02 07 20 21 22 23 24 2b 2e 2f val 00 0a 87 28 01 00 00 40 00 00 def NA NA 87 28 01 00 00 MM 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 00 03 f0 06 02 00 00 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 val 01 03 f8 04 00 50 def 00 03 f8 04 00 50 LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 val 00 02 f8 03 00 50 def 00 02 f8 03 00 50 LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 01 03 78 00 00 07 04 08 def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 f9 fa fb val 01 0a 30 0a 20 09 00 80 00 00 20 00 f0 48 00 00 def 00 02 90 02 30 09 00 00 00 00 00 MM MM MM MM MM LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 08 def 01 00 60 00 64 01 02 48 LDN 0x06 (Mouse) idx 30 70 71 f0 val 01 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 2d 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc cd ce cf e0 e1 e2 e3 e4 e9 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb val 00 f3 10 00 00 00 80 00 00 00 0a 00 00 00 00 00 20 00 00 00 00 00 00 00 20 00 00 00 00 00 01 00 00 40 00 01 00 00 00 00 00 00 00 00 00 00 00 00 21 10 42 00 00 00 00 1c 00 00 00 00 00 def 00 f3 00 00 00 00 03 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 20 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 MM 00 00 00 00 00 00 00 00 00 00 00 00 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 06 Change-Id: Ifb45d28005d78b2a99d8552b59154d11bdf44f6f Signed-off-by: Андрей Павлов <7134956(a)gmail.com> --- util/superiotool/ite.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index a6dbacf..7e167c8 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -706,6 +706,52 @@ static const struct superio_registers reg_table[] = { {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, {EOT}}}, + {0x8728, "IT8728F", { + {NOLDN, NULL, + {0x02,0x07,0x20,0x21,0x22,0x23,0x24,0x2b,0x2e,0x2f,EOT}, + {NANA,NANA,0x87,0x28,0x01,0x00,0x00,MISC,0x00,0x00,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, + {0x00,0x03,0xf0,0x06,0x02,0x00,0x00,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x00,0x03,0xf8,0x04,0x00,0x50,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x00,0x02,0xf8,0x03,0x00,0x50,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x62,0x63,0x70,0x74,0xf0,EOT}, + {0x00,0x03,0x78,0x07,0x78,0x07,0x03,0x03,EOT}}, + {0x4, "Environment controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xF9,0xFA,0xFB,EOT}, + {0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00, + 0x00,0x00,MISC,MISC,MISC,MISC,MISC,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x48,EOT}}, + {0x6, "Mouse", + {0x30,0x70,0x71,0xf0,EOT}, + {0x00,0x0c,0x02,0x00,EOT}}, + {0x7, "GPIO", + {0x25,0x26,0x27,0x28,0x29,0x2a,0x2c,0x2d,0x60, + 0x61,0x62,0x63,0x64,0x65,0x70,0x71,0x72,0x73, + 0x74,0xb0,0xb1,0xb2,0xb3,0xb4,0xb8,0xb9,0xba, + 0xbb,0xbc,0xbd,0xc0,0xc1,0xc2,0xc3,0xc4,0xc8, + 0xc9,0xca,0xcb,0xcc,0xcd,0xce,0xcf,0xe0,0xe1, + 0xe2,0xe3,0xe4,0xe9,0xf0,0xf1,0xf2,0xf3,0xf4, + 0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,EOT}, + {0x00,0xf3,0x00,0x00,0x00,0x00,0x03,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x38, + 0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x40,0x00,0x01, + 0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,MISC,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xa, "Consumer IR", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x03,0x10,0x0b,0x06,EOT}}, + {EOT}}}, {0x8761, "IT8761E", { {EOT}}}, {0x8772, "IT8772F", {

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Patch set updated for coreboot: 932610a superiotool: Add support for the IT8728F Super I/O
by Андрей Павлов 17 Mar '13

17 Mar '13

Андрей Павлов (7134956(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2775 -gerrit commit 932610a956acbbbf3a6ab843f12fc66b51e5f1e2 Author: Андрей Павлов <7134956(a)gmail.com> Date: Sun Mar 17 19:11:05 2013 +0300 superiotool: Add support for the IT8728F Super I/O $ superiotool -deV superiotool r4.0-3712-gd549279 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8728F (id=0x8728, rev=0x1) at 0x2e Register dump: idx 02 07 20 21 22 23 24 2b 2e 2f val 00 0a 87 28 01 00 00 40 00 00 def NA NA 87 28 01 00 00 MM 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 00 03 f0 06 02 00 00 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 val 01 03 f8 04 00 50 def 00 03 f8 04 00 50 LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 val 00 02 f8 03 00 50 def 00 02 f8 03 00 50 LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 01 03 78 00 00 07 04 08 def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 f9 fa fb val 01 0a 30 0a 20 09 00 80 00 00 20 00 f0 48 00 00 def 00 02 90 02 30 09 00 00 00 00 00 MM MM MM MM MM LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 08 def 01 00 60 00 64 01 02 48 LDN 0x06 (Mouse) idx 30 70 71 f0 val 01 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 2d 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc cd ce cf e0 e1 e2 e3 e4 e9 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb val 00 f3 10 00 00 00 80 00 00 00 0a 00 00 00 00 00 20 00 00 00 00 00 00 00 20 00 00 00 00 00 01 00 00 40 00 01 00 00 00 00 00 00 00 00 00 00 00 00 21 10 42 00 00 00 00 1c 00 00 00 00 00 def 00 f3 00 00 00 00 03 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 20 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 MM 00 00 00 00 00 00 00 00 00 00 00 00 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 06 Environment controller (0x0a35) Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. Probing for AMD EC Super I/O at 0xaa... Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff Probing for Infineon Super I/O at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for Infineon Super I/O at 0x4e... Failed. Returned data: id=0xff, rev=0xff Change-Id: Ifb45d28005d78b2a99d8552b59154d11bdf44f6f Signed-off-by: Андрей Павлов <7134956(a)gmail.com> --- util/superiotool/ite.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index a6dbacf..7e167c8 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -706,6 +706,52 @@ static const struct superio_registers reg_table[] = { {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, {EOT}}}, + {0x8728, "IT8728F", { + {NOLDN, NULL, + {0x02,0x07,0x20,0x21,0x22,0x23,0x24,0x2b,0x2e,0x2f,EOT}, + {NANA,NANA,0x87,0x28,0x01,0x00,0x00,MISC,0x00,0x00,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, + {0x00,0x03,0xf0,0x06,0x02,0x00,0x00,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x00,0x03,0xf8,0x04,0x00,0x50,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x00,0x02,0xf8,0x03,0x00,0x50,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x62,0x63,0x70,0x74,0xf0,EOT}, + {0x00,0x03,0x78,0x07,0x78,0x07,0x03,0x03,EOT}}, + {0x4, "Environment controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xF9,0xFA,0xFB,EOT}, + {0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00, + 0x00,0x00,MISC,MISC,MISC,MISC,MISC,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x48,EOT}}, + {0x6, "Mouse", + {0x30,0x70,0x71,0xf0,EOT}, + {0x00,0x0c,0x02,0x00,EOT}}, + {0x7, "GPIO", + {0x25,0x26,0x27,0x28,0x29,0x2a,0x2c,0x2d,0x60, + 0x61,0x62,0x63,0x64,0x65,0x70,0x71,0x72,0x73, + 0x74,0xb0,0xb1,0xb2,0xb3,0xb4,0xb8,0xb9,0xba, + 0xbb,0xbc,0xbd,0xc0,0xc1,0xc2,0xc3,0xc4,0xc8, + 0xc9,0xca,0xcb,0xcc,0xcd,0xce,0xcf,0xe0,0xe1, + 0xe2,0xe3,0xe4,0xe9,0xf0,0xf1,0xf2,0xf3,0xf4, + 0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,EOT}, + {0x00,0xf3,0x00,0x00,0x00,0x00,0x03,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x38, + 0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00, + 0x00,0x00,0x00,0x01,0x00,0x00,0x40,0x00,0x01, + 0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,MISC,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xa, "Consumer IR", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x03,0x10,0x0b,0x06,EOT}}, + {EOT}}}, {0x8761, "IT8761E", { {EOT}}}, {0x8772, "IT8772F", {

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coreboot March 2013