coreboot March 2013

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New patch to review for coreboot: 6483510 haswell: Parallel AP bringup
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2779 -gerrit commit 648351002891186c84bd2c4a5c5d876c160e393a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jan 15 08:27:05 2013 -0600 haswell: Parallel AP bringup This patch parallelizes the AP startup for Haswell-based devices. It does not touch the generic secondary startup code. Instead it provides its own MP support matching up with the Haswell BWG. It seemed to be too much trouble to support the old startup way and this new way. Because of that parallel loading is the only thing supported. A couple of things to note: 1. Micrcode needs to be loaded twice. Once before MTRR and caching is enabled. And a second time after SMM relocation. 2. The sipi_vector is entirely self-contained. Once it is loaded and written back to RAM the APs do not access memory outside of the sipi_vector load location until a sync up in ramstage. 3. SMM relocation is kicked off by an IPI to self w/ SMI set as the destination mode. The following are timings from cbmem with dev mode disabled and recovery mode enabled to boot directly into the kernel. This was done on the baskingridge CRB with a 4-core 8-thread CPU and 2 DIMMs 1GiB each. The kernel has console enabled on the serial port. Entry 70 is the device initialization, and that is where the APs are brought up. With these two examples it looks to shave off ~200 ms of boot time. Before: 1:55,382 2:57,606 (2,223) 3:3,108,983 (3,051,377) 4:3,110,084 (1,101) 8:3,113,109 (3,024) 9:3,156,694 (43,585) 10:3,156,815 (120) 30:3,157,110 (295) 40:3,158,180 (1,069) 50:3,160,157 (1,977) 60:3,160,366 (208) 70:4,221,044 (1,060,677) 75:4,221,062 (18) 80:4,227,185 (6,122) 90:4,227,669 (484) 99:4,265,596 (37,927) 1000:4,267,822 (2,225) 1001:4,268,507 (685) 1002:4,268,780 (272) 1003:4,398,676 (129,896) 1004:4,398,979 (303) 1100:7,477,601 (3,078,621) 1101:7,480,210 (2,608) After: 1:49,518 2:51,778 (2,259) 3:3,081,186 (3,029,407) 4:3,082,252 (1,066) 8:3,085,137 (2,884) 9:3,130,339 (45,202) 10:3,130,518 (178) 30:3,130,544 (26) 40:3,131,125 (580) 50:3,133,023 (1,897) 60:3,133,278 (255) 70:4,009,259 (875,980) 75:4,009,273 (13) 80:4,015,947 (6,674) 90:4,016,430 (482) 99:4,056,265 (39,835) 1000:4,058,492 (2,226) 1001:4,059,176 (684) 1002:4,059,450 (273) 1003:4,189,333 (129,883) 1004:4,189,770 (436) 1100:7,262,358 (3,072,588) 1101:7,263,926 (1,567) Booted the baskingridge board as noted above. Also analyzed serial messages with pcserial enabled. Change-Id: Ifedc7f787953647c228b11afdb725686e38c4098 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/Kconfig | 1 + src/cpu/intel/haswell/Makefile.inc | 23 ++ src/cpu/intel/haswell/haswell.h | 9 + src/cpu/intel/haswell/haswell_init.c | 145 ++++----- src/cpu/intel/haswell/mp_init.c | 550 +++++++++++++++++++++++++++++++++++ src/cpu/intel/haswell/sipi_header.c | 6 + src/cpu/intel/haswell/sipi_vector.S | 190 ++++++++++++ src/cpu/intel/haswell/smmrelocate.c | 25 +- 8 files changed, 845 insertions(+), 104 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index bf0abbc..95d0b18 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -11,6 +11,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_LAPIC select SMM_TSEG select SMM_MODULES + select RELOCATABLE_MODULES select CPU_MICROCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index b2116f2..a19a8c5 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += haswell_init.c subdirs-y += ../../x86/name +ramstage-y += mp_init.c romstage-y += romstage.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c @@ -10,3 +11,25 @@ cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc + +# AP startub stub +SIPI_ELF=$(obj)/cpu/intel/haswell/sipi_vector.elf +SIPI_BIN=$(SIPI_ELF:.elf=) +SIPI_DOTO=$(SIPI_ELF:.elf=.o) + +ramstage-srcs += $(SIPI_BIN) +rmodules-y += sipi_vector.S +rmodules-y += sipi_header.c + +$(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules.o $(dir $(SIPI_ELF))sipi_header.rmodules.o + $(CC) $(LDFLAGS) -nostdlib -r -o $@ $^ + +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0)) + +$(SIPI_BIN): $(SIPI_ELF) + $(OBJCOPY) -O binary $< $@ + +$(SIPI_BIN).ramstage.o: $(SIPI_BIN) + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cd $(dir $@); $(OBJCOPY) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) + diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 733ddd3..26807e9 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -141,8 +141,17 @@ void intel_cpu_haswell_finalize_smm(void); /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); +/* Returns 0 on success, < 0 on failure. */ +int smm_initialize(void); +void smm_initiate_relocation(void); struct bus; void bsp_init_and_start_aps(struct bus *cpu_bus); +/* Returns 0 on succes. < 0 on failure. */ +int setup_ap_init(struct bus *cpu_bus, int *max_cpus, + const void *microcode_patch); +/* Returns 0 on success, < 0 on failure. */ +int start_aps(struct bus *cpu_bus, int max_cpus); +void release_aps_for_smm_relocation(void); #endif #endif diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 9e62b31..82430b7 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -442,71 +442,30 @@ static void configure_mca(void) static unsigned ehci_debug_addr; #endif -/* - * Initialize any extra cores/threads in this package. - */ -static void intel_cores_init(device_t cpu) -{ - struct cpuid_result result; - unsigned threads_per_package, threads_per_core, i; - - /* Logical processors (threads) per core */ - result = cpuid_ext(0xb, 0); - threads_per_core = result.ebx & 0xffff; - - /* Logical processors (threads) per package */ - result = cpuid_ext(0xb, 1); - threads_per_package = result.ebx & 0xffff; - - /* Only initialize extra cores from BSP */ - if (cpu->path.apic.apic_id) - return; - - printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n", - cpu->path.apic.apic_id, threads_per_package/threads_per_core, - threads_per_core); - - for (i = 1; i < threads_per_package; ++i) { - struct device_path cpu_path; - device_t new; - - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = - cpu->path.apic.apic_id + i; - - /* Update APIC ID if no hyperthreading */ - if (threads_per_core == 1) - cpu_path.apic.apic_id <<= 1; - - /* Allocate the new cpu device structure */ - new = alloc_dev(cpu->bus, &cpu_path); - if (!new) - continue; - - printk(BIOS_DEBUG, "CPU: %u has core %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); - -#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ - if (!start_cpu(new)) { - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU %u would not start!\n", - new->path.apic.apic_id); - } -#endif - } -} - -static void bsp_init_before_ap_bringup(void) +static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { + struct device_path cpu_path; + struct cpu_info *info; char processor_name[49]; /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); + /* Ensure the local apic is enabled */ + enable_lapic(); + + /* Set the device path of the boot cpu. */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = lapicid(); + + /* Find the device structure for the boot cpu. */ + info = cpu_info(); + info->cpu = alloc_find_dev(cpu_bus, &cpu_path); + + if (info->index != 0) + printk(BIOS_CRIT, "BSP index(%d) != 0!\n", info->index); + #if CONFIG_USBDEBUG // Is this caution really needed? if(!ehci_debug_addr) @@ -523,23 +482,12 @@ static void bsp_init_before_ap_bringup(void) set_ehci_debug(ehci_debug_addr); #endif - enable_lapic(); -} - -static void ap_init(device_t cpu) -{ - /* Microcode needs to be loaded before caching is enabled. */ - intel_update_microcode_from_cbfs(); - - /* Turn on caching if we haven't already */ - x86_enable_cache(); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); - - enable_lapic(); + /* Call through the cpu driver's initialization. */ + cpu_initialize(0); } -static void cpu_common_init(device_t cpu) +/* All CPUs including BSP will run the following function. */ +static void haswell_init(device_t cpu) { /* Clear out pending MCEs */ configure_mca(); @@ -572,33 +520,40 @@ static void cpu_common_init(device_t cpu) void bsp_init_and_start_aps(struct bus *cpu_bus) { + int max_cpus; + int num_aps; + const void *microcode_patch; + /* Perform any necesarry BSP initialization before APs are brought up. * This call alos allows the BSP to prepare for any secondary effects * from calling cpu_initialize() such as smm_init(). */ - bsp_init_before_ap_bringup(); - - /* - * This calls into the gerneic initialize_cpus() which attempts to - * start APs on the APIC bus in the devicetree. No APs get started - * because there is only the BSP and a placeholder (disabled) in the - * devicetree. initialize_cpus() also does SMM initialization by way - * of smm_init(). It will eventually call cpu_initialize(0) which calls - * dev_ops->init(). For Haswell the dev_ops->init() starts up the APs - * by way of intel_cores_init(). - */ - initialize_cpus(cpu_bus); -} + bsp_init_before_ap_bringup(cpu_bus); -static void haswell_init(device_t cpu) -{ - if (cpu->path.apic.apic_id == 0) { - cpu_common_init(cpu); - /* Start up extra cores */ - intel_cores_init(cpu); - } else { - ap_init(cpu); - cpu_common_init(cpu); + microcode_patch = intel_microcode_find(); + + /* This needs to be called after the mtrr setup so the BSP mtrrs + * can be mirrored by the APs. */ + if (setup_ap_init(cpu_bus, &max_cpus, microcode_patch)) { + printk(BIOS_CRIT, "AP setup initialization failed. " + "No APs will be brought up.\n"); + return; + } + + num_aps = max_cpus - 1; + if (start_aps(cpu_bus, num_aps)) { + printk(BIOS_CRIT, "AP startup failed. Trying to continue.\n"); } + + if (smm_initialize()) { + printk(BIOS_CRIT, "SMM Initialiazation failed...\n"); + return; + } + + /* Release APs to perform SMM relocation. */ + release_aps_for_smm_relocation(); + + /* After SMM relocation a 2nd microcode load is required. */ + intel_microcode_load_unlocked(microcode_patch); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c new file mode 100644 index 0000000..b1567ba --- /dev/null +++ b/src/cpu/intel/haswell/mp_init.c @@ -0,0 +1,550 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 ChromeOS Authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <stdint.h> +#include <rmodule.h> +#include <arch/cpu.h> +#include <cpu/cpu.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> +#include <delay.h> +#include <device/device.h> +#include <device/path.h> +#include <lib.h> +#include <smp/atomic.h> +#include <smp/spinlock.h> +#include "haswell.h" + +/* This needs to match the layout in the .module_parametrs section. */ +struct sipi_params { + u16 gdtlimit; + u32 gdt; + u16 unused; + u32 idt_ptr; + u32 stack_top; + u32 stack_size; + u32 microcode_ptr; + u32 msr_table_ptr; + u32 msr_count; + u32 c_handler; + u32 c_handler_arg; + u8 apic_to_cpu_num[CONFIG_MAX_CPUS]; +} __attribute__((packed)); + +/* This also needs to match the assembly code for saved MSR encoding. */ +struct saved_msr { + u32 index; + u32 lo; + u32 hi; +} __attribute__((packed)); + + +/* The sipi vector rmodule is included in the ramstage using 'objdump -B'. */ +extern char _binary_sipi_vector_start[]; +/* These symbols are defined in c_start.S. */ +extern char gdt[]; +extern char gdt_limit[]; +extern char idtarg[]; + +/* This table keeps track of each CPU's APIC id. */ +static u8 apic_id_table[CONFIG_MAX_CPUS]; +static device_t cpu_devs[CONFIG_MAX_CPUS]; + +/* Number of APs checked that have checked in. */ +static atomic_t num_aps; +/* Barrier to stop APs from performing SMM relcoation. */ +static int smm_relocation_barrier_begin __attribute__ ((aligned (64))); + +static inline void wait_for_barrier(volatile int *barrier) +{ + while (*barrier == 0) { + asm ("pause"); + } +} + +static inline void release_barrier(volatile int *barrier) +{ + *barrier = 1; +} + +static void ap_wait_for_smm_relocation_begin(void) +{ + wait_for_barrier(&smm_relocation_barrier_begin); +} + + +/* Returns 1 if timeout waiting for APs. 0 if target aps found. */ +static int wait_for_aps(int target, int total_delay, int delay_step) +{ + int timeout = 0; + int delayed = 0; + while (atomic_read(&num_aps) != target) { + udelay(delay_step); + delayed += delay_step; + if (delayed >= total_delay) { + timeout = 1; + break; + } + } + + return timeout; +} + +void release_aps_for_smm_relocation(void) +{ + release_barrier(&smm_relocation_barrier_begin); +} + +/* The mtrr code sets up ROM caching on the BSP, but not the others. However, + * the boot loader payload disables this. In order for Linux not to complain + * ensure the caching is disabled for tha APs before going to sleep. */ +static void cleanup_rom_caching(void) +{ +#if CONFIG_CACHE_ROM + msr_t msr; + unsigned int last_var_mtrr; + + msr = rdmsr(MTRRcap_MSR); + last_var_mtrr = (msr.lo & 0xff) - 1; + + /* Check if the MTRR is valid. */ + msr = rdmsr(MTRRphysMask_MSR(last_var_mtrr)); + if ((msr.lo & MTRRphysMaskValid) == 0) + return; + msr = rdmsr(MTRRphysBase_MSR(last_var_mtrr)); + /* Assum that if the MTRR is of write protected type, the MTRR is used + * to cache the ROM. */ + if ((msr.lo & MTRR_NUM_TYPES) == MTRR_TYPE_WRPROT) { + msr.lo = msr.hi = 0; + disable_cache(); + wrmsr(MTRRphysMask_MSR(last_var_mtrr), msr); + wrmsr(MTRRphysBase_MSR(last_var_mtrr), msr); + enable_cache(); + } +#endif +} + +/* By the time APs call ap_init() caching has been setup, and microcode has + * been loaded. */ +static void ap_init(unsigned int cpu, void *microcode_ptr) +{ + struct cpu_info *info; + + /* Signal that the AP has arrived. */ + atomic_inc(&num_aps); + + /* Ensure the local apic is enabled */ + enable_lapic(); + + info = cpu_info(); + info->index = cpu; + info->cpu = cpu_devs[cpu]; + + apic_id_table[info->index] = lapicid(); + info->cpu->path.apic.apic_id = apic_id_table[info->index]; + + /* Call through the cpu driver's initialization. */ + cpu_initialize(info->index); + + ap_wait_for_smm_relocation_begin(); + + smm_initiate_relocation(); + + /* After SMM relocation a 2nd microcode load is required. */ + intel_microcode_load_unlocked(microcode_ptr); + + /* Cleanup ROM caching. */ + cleanup_rom_caching(); + + /* FIXME(adurbin): park CPUs properly -- preferably somewhere in a + * reserved part of memory that the OS cannot get to. */ + stop_this_cpu(); +} + +static void setup_default_sipi_vector_params(struct sipi_params *sp) +{ + int i; + + sp->gdt = (u32)&gdt; + sp->gdtlimit = (u32)&gdt_limit; + sp->idt_ptr = (u32)&idtarg; + sp->stack_size = CONFIG_STACK_SIZE; + sp->stack_top = (u32)&_estack; + /* Adjust the stack top to take into account cpu_info. */ + sp->stack_top -= sizeof(struct cpu_info); + /* Default to linear APIC id space. */ + for (i = 0; i < CONFIG_MAX_CPUS; i++) + sp->apic_to_cpu_num[i] = i; +} + +#define NUM_FIXED_MTRRS 11 +static unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = { + MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR, + MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, + MTRRfix4K_D8000_MSR, MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, + MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, +}; + +static inline struct saved_msr *save_msr(int index, struct saved_msr *entry) +{ + msr_t msr; + + msr = rdmsr(index); + entry->index = index; + entry->lo = msr.lo; + entry->hi = msr.hi; + + /* Return the next entry. */ + entry++; + return entry; +} + +static int save_bsp_msrs(char *start, int size) +{ + int msr_count; + int num_var_mtrrs; + struct saved_msr *msr_entry; + int i; + msr_t msr; + + /* Determine number of MTRRs need to be saved. */ + msr = rdmsr(MTRRcap_MSR); + num_var_mtrrs = msr.lo & 0xff; + + /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE. */ + msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1; + + if ((msr_count * sizeof(struct saved_msr)) > size) { + printk(BIOS_CRIT, "Cannot mirror all %d msrs.\n", msr_count); + return -1; + } + + msr_entry = (void *)start; + for (i = 0; i < NUM_FIXED_MTRRS; i++) { + msr_entry = save_msr(fixed_mtrrs[i], msr_entry); + } + + for (i = 0; i < num_var_mtrrs; i++) { + msr_entry = save_msr(MTRRphysBase_MSR(i), msr_entry); + msr_entry = save_msr(MTRRphysMask_MSR(i), msr_entry); + } + + msr_entry = save_msr(MTRRdefType_MSR, msr_entry); + + return msr_count; +} + +/* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the + * memory range is already reserved so the OS cannot use it. That region is + * free to use for AP bringup before SMM is initialized. */ +static u32 sipi_vector_location = SMM_DEFAULT_BASE; +static int sipi_vector_location_size = SMM_DEFAULT_SIZE; + +static int load_sipi_vector(const void *microcode_patch) +{ + struct rmodule sipi_mod; + int module_size; + int num_msrs; + struct sipi_params *sp; + char *mod_loc = (void *)sipi_vector_location; + const int loc_size = sipi_vector_location_size; + + if (rmodule_parse(&_binary_sipi_vector_start, &sipi_mod)) { + printk(BIOS_CRIT, "Unable to parse sipi module.\n"); + return -1; + } + + if (rmodule_entry_offset(&sipi_mod) != 0) { + printk(BIOS_CRIT, "SIPI module entry offset is not 0!\n"); + return -1; + } + + if (rmodule_load_alignment(&sipi_mod) != 4096) { + printk(BIOS_CRIT, "SIPI module load alignment(%d) != 4096.\n", + rmodule_load_alignment(&sipi_mod)); + return -1; + } + + module_size = rmodule_memory_size(&sipi_mod); + + /* Align to 4 bytes. */ + module_size += 3; + module_size &= ~3; + + if (module_size > loc_size) { + printk(BIOS_CRIT, "SIPI module size (%d) > region size (%d).\n", + module_size, loc_size); + return -1; + } + + num_msrs = save_bsp_msrs(&mod_loc[module_size], loc_size - module_size); + + if (num_msrs < 0) { + printk(BIOS_CRIT, "Error mirroring BSP's msrs.\n"); + return -1; + } + + if (rmodule_load(mod_loc, &sipi_mod)) { + printk(BIOS_CRIT, "Unable to load SIPI module.\n"); + return -1; + } + + sp = rmodule_parameters(&sipi_mod); + + if (sp == NULL) { + printk(BIOS_CRIT, "SIPI module has no parameters.\n"); + return -1; + } + + setup_default_sipi_vector_params(sp); + /* Setup MSR table. */ + sp->msr_table_ptr = (u32)&mod_loc[module_size]; + sp->msr_count = num_msrs; + /* Provide pointer to microcode patch. */ + sp->microcode_ptr = (u32)microcode_patch; + /* The microcode pointer is passed on through to the c handler so + * that it can be loaded again after SMM relocation. */ + sp->c_handler_arg = (u32)microcode_patch; + sp->c_handler = (u32)&ap_init; + + /* Make sure SIPI vector hits RAM so the APs that come up will see + * the startup code even if the caches are disabled. */ + wbinvd(); + + return 0; +} + +static int allocate_cpu_devices(struct bus *cpu_bus, int *total_hw_threads) +{ + int i; + int num_threads; + int num_cores; + int max_cpus; + struct cpu_info *info; + msr_t msr; + + info = cpu_info(); + cpu_devs[info->index] = info->cpu; + apic_id_table[info->index] = info->cpu->path.apic.apic_id; + + msr = rdmsr(CORE_THREAD_COUNT_MSR); + num_threads = (msr.lo >> 0) & 0xffff; + num_cores = (msr.lo >> 16) & 0xffff; + printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", + num_cores, num_threads); + + max_cpus = num_threads; + *total_hw_threads = num_threads; + if (num_threads > CONFIG_MAX_CPUS) { + printk(BIOS_CRIT, "CPU count(%d) exceeds CONFIG_MAX_CPUS(%d)\n", + num_threads, CONFIG_MAX_CPUS); + max_cpus = CONFIG_MAX_CPUS; + } + + for (i = 1; i < max_cpus; i++) { + struct device_path cpu_path; + device_t new; + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = info->cpu->path.apic.apic_id + i; + + /* Allocate the new cpu device structure */ + new = alloc_find_dev(cpu_bus, &cpu_path); + if (new == NULL) { + printk(BIOS_CRIT, "Could not allocte cpu device\n"); + max_cpus--; + } + cpu_devs[i] = new; + } + + return max_cpus; +} + +int setup_ap_init(struct bus *cpu_bus, int *max_cpus, + const void *microcode_patch) +{ + int num_cpus; + int hw_threads; + + /* Default to currently running CPU. */ + num_cpus = allocate_cpu_devices(cpu_bus, &hw_threads); + + /* Load the SIPI vector. */ + if (load_sipi_vector(microcode_patch)) + return -1; + + *max_cpus = num_cpus; + + if (num_cpus < hw_threads) { + printk(BIOS_CRIT, + "ERROR: More HW threads (%d) than support (%d).\n", + hw_threads, num_cpus); + return -1; + } + + return 0; +} + +/* Returns 1 for timeout. 0 on success. */ +static int apic_wait_timeout(int total_delay, int delay_step) +{ + int total = 0; + int timeout = 0; + + while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) { + udelay(delay_step); + total += delay_step; + if (total >= total_delay) { + timeout = 1; + break; + } + } + + return timeout; +} + +int start_aps(struct bus *cpu_bus, int ap_count) +{ + int sipi_vector; + + if (ap_count == 0) + return 0; + + /* The vector is sent as a 4k aligned address in one byte. */ + sipi_vector = sipi_vector_location >> 12; + + if (sipi_vector > 256) { + printk(BIOS_CRIT, "SIPI vector too large! 0x%08x\n", + sipi_vector); + return -1; + } + + printk(BIOS_DEBUG, "Attempting to start %d APs\n", ap_count); + + if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { + printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); + if (apic_wait_timeout(1000 /* 1 ms */, 50)) { + printk(BIOS_DEBUG, "timed out. Aborting.\n"); + return -1; + } else + printk(BIOS_DEBUG, "done.\n"); + } + + /* Send INIT IPI to all but self. */ + lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); + lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | + LAPIC_DM_INIT); + printk(BIOS_DEBUG, "Waiting for INIT to complete..."); + + /* Wait for 10 ms to complete. */ + if (apic_wait_timeout(10000 /* 10 ms */, 100 /* us */)) { + printk(BIOS_DEBUG, "timed out. Bailing. \n"); + return -1; + } else { + printk(BIOS_DEBUG, "done.\n"); + } + + /* Send 1st SIPI */ + if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { + printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); + if (apic_wait_timeout(1000 /* 1 ms */, 50)) { + printk(BIOS_DEBUG, "timed out. Aborting.\n"); + return -1; + } else + printk(BIOS_DEBUG, "done.\n"); + } + + lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); + lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | + LAPIC_DM_STARTUP | sipi_vector); + printk(BIOS_DEBUG, "Waiting for 1st SIPI to complete..."); + if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { + printk(BIOS_DEBUG, "timed out.\n"); + return -1; + } else { + printk(BIOS_DEBUG, "done.\n"); + } + /* Wait for CPUs to check in up to 200 us. */ + wait_for_aps(ap_count, 200 /* us */, 15 /* us */); + + /* Send 2nd SIPI */ + if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { + printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); + if (apic_wait_timeout(1000 /* 1 ms */, 50)) { + printk(BIOS_DEBUG, "timed out. Aborting.\n"); + return -1; + } else + printk(BIOS_DEBUG, "done.\n"); + } + + lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); + lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | + LAPIC_DM_STARTUP | sipi_vector); + printk(BIOS_DEBUG, "Waiting for 2nd SIPI to complete..."); + if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { + printk(BIOS_DEBUG, "timed out.\n"); + return -1; + } else { + printk(BIOS_DEBUG, "done.\n"); + } + + /* Wait for CPUs to check in. */ + if (wait_for_aps(ap_count, 10000 /* 10 ms */, 50 /* us */)) { + printk(BIOS_DEBUG, "Not all APs checked in: %d/%d.\n", + atomic_read(&num_aps), ap_count); + return -1; + } + + return 0; +} + +DECLARE_SPIN_LOCK(smm_relocation_lock); + +void smm_initiate_relocation(void) +{ + spin_lock(&smm_relocation_lock); + + if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { + printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); + if (apic_wait_timeout(1000 /* 1 ms */, 50)) { + printk(BIOS_DEBUG, "timed out. Aborting.\n"); + spin_unlock(&smm_relocation_lock); + return; + } else + printk(BIOS_DEBUG, "done.\n"); + } + + lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid())); + lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT | LAPIC_DM_SMI); + if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */)) { + printk(BIOS_DEBUG, "SMI Relocation timed out.\n"); + } else + printk(BIOS_DEBUG, "Relocation complete.\n"); + + spin_unlock(&smm_relocation_lock); +} + diff --git a/src/cpu/intel/haswell/sipi_header.c b/src/cpu/intel/haswell/sipi_header.c new file mode 100644 index 0000000..846a82d --- /dev/null +++ b/src/cpu/intel/haswell/sipi_header.c @@ -0,0 +1,6 @@ +#include <rmodule.h> + + +extern void *ap_start; + +DEFINE_RMODULE_HEADER(sipi_vector_header, ap_start, RMODULE_TYPE_SIPI_VECTOR); diff --git a/src/cpu/intel/haswell/sipi_vector.S b/src/cpu/intel/haswell/sipi_vector.S new file mode 100644 index 0000000..664a9ee --- /dev/null +++ b/src/cpu/intel/haswell/sipi_vector.S @@ -0,0 +1,190 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 ChromeOS Authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* The SIPI vector is responsible for initializing the APs in the sytem. It + * loads microcode, sets up MSRs, and enables caching before calling into + * C code. */ + +/* These segment selectors need to match the gdt entries in c_start.S. */ +#define CODE_SEG 0x10 +#define DATA_SEG 0x18 + +#define IA32_UPDT_TRIG 0x79 +#define IA32_BIOS_SIGN_ID 0x8b + +.section ".module_parameters", "aw", @progbits +ap_start_params: +gdtaddr: +.word 0 /* limit */ +.long 0 /* table */ +.word 0 /* unused */ +idt_ptr: +.long 0 +stack_top: +.long 0 +stack_size: +.long 0 +microcode_ptr: +.long 0 +msr_table_ptr: +.long 0 +msr_count: +.long 0 +c_handler: +.long 0 +c_handler_arg: +.long 0 +apic_to_cpu_num: +.fill CONFIG_MAX_CPUS,1,0xff + +.text +.code16 +.global ap_start +ap_start: + cli + xorl %eax, %eax + movl %eax, %cr3 /* Invalidate TLB*/ + + /* On hyper threaded cpus, invalidating the cache here is + * very very bad. Don't. + */ + + /* setup the data segment */ + movw %cs, %ax + movw %ax, %ds + + /* The gdtaddr needs to be releative to the data segment in order + * to properly dereference it. The .text section comes first in an + * rmodule so ap_start can be used as a proxy for the load address. */ + movl $(gdtaddr), %ebx + sub $(ap_start), %ebx + + data32 lgdt (%ebx) + + movl %cr0, %eax + andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ + orl $0x60000001, %eax /* CD, NW, PE = 1 */ + movl %eax, %cr0 + + ljmpl $CODE_SEG, $1f +1: + .code32 + movw $DATA_SEG, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + + /* Load the Interrupt descriptor table */ + mov idt_ptr, %ebx + lidt (%ebx) + + /* The CPU number is calculated by reading the initial APIC id. */ + mov $1, %eax + cpuid + /* Default APIC id in ebx[31:24]. Move it to bl. */ + bswap %ebx + mov $(apic_to_cpu_num), %eax + xor %ecx, %ecx + +1: + cmp (%eax, %ecx, 1), %bl + je 1f + inc %ecx + cmp $CONFIG_MAX_CPUS, %ecx + jne 1b + + /* This is bad. No CPU number found. However, the BSP should have setup + * the AP handler properly. Just park the CPU. */ + mov $0x80, %dx + movw $0xdead, %ax + outw %ax, %dx + jmp halt_jump +1: + /* Setup stacks for each CPU. */ + movl stack_size, %eax + mul %ecx + movl stack_top, %edx + subl %eax, %edx + mov %edx, %esp + /* Save cpu number. */ + mov %ecx, %esi + + /* Determine if one should check microcode versions. */ + mov microcode_ptr, %edi + test %edi, %edi + jz 1f /* Bypass if no microde exists. */ + + /* Get the Microcode version. */ + mov $1, %eax + cpuid + mov $IA32_BIOS_SIGN_ID, %ecx + rdmsr + /* If something already loaded skip loading again. */ + test %edx, %edx + jnz 1f + + /* Load new microcode. */ + mov $IA32_UPDT_TRIG, %ecx + xor %edx, %edx + mov %edi, %eax + /* The microcode pointer is passed in pointing to the header. Adjust + * pointer to reflect the payload (header size is 48 bytes). */ + add $48, %eax + pusha + wrmsr + popa + +1: + /* + * Load MSRs. Each entry in the table consists of: + * 0: index, + * 4: value[31:0] + * 8: value[63:32] + */ + mov msr_table_ptr, %edi + mov msr_count, %ebx + test %ebx, %ebx + jz 1f +load_msr: + mov (%edi), %ecx + mov 4(%edi), %eax + mov 8(%edi), %edx + wrmsr + add $12, %edi + dec %ebx + jnz load_msr + +1: + /* Enable caching. */ + mov %cr0, %eax + and $0x9fffffff, %eax /* CD, NW = 0 */ + mov %eax, %cr0 + + /* c_handler(cpu_num, *c_handler_arg) */ + push c_handler_arg + push %esi /* cpu_num */ + mov c_handler, %eax + call *%eax +halt_jump: + hlt + jmp halt_jump diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 1ccc9bb..4312d79 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -23,6 +23,7 @@ #include <device/pci.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> +#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> @@ -297,24 +298,30 @@ static int cpu_smm_setup(void) return 0; } -void smm_init(void) +int smm_initialize(void) { /* Return early if CPU SMM setup failed. */ if (cpu_smm_setup()) - return; + return -1; southbridge_smm_init(); - /* Initiate first SMI to kick off SMM-context relocation. Note: this - * SMI being triggered here queues up an SMI in the APs which are in - * wait-for-SIPI state. Once an AP gets an SIPI it will service the SMI - * at the SMM_DEFAULT_BASE before jumping to startup vector. */ - southbridge_trigger_smi(); - - printk(BIOS_DEBUG, "Relocation complete.\n"); + /* Run the relocation handler. */ + smm_initiate_relocation(); /* Lock down the SMRAM space. */ smm_lock(); + + return 0; +} + +void smm_init(void) +{ + /* smm_init() is normally called from initialize_cpus() in + * lapic_cpu_init.c. However, that path is no longer used. Don't reuse + * the function name because that would cause confusion. + * The smm_initialize() function above is used to setup SMM at the + * appropriate time. */ } void smm_lock(void)

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New patch to review for coreboot: 2007453 intel microcode: split up microcode loading stages
by Stefan Reinauer 19 Mar '13

19 Mar '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2778 -gerrit commit 2007453797a6db1927dc3fd2f415008306ba24eb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jan 15 15:15:32 2013 -0600 intel microcode: split up microcode loading stages This patch only applies to CONFIG_MICROCODE_IN_CBFS. The intel microcode update routine would always walk the CBFS for the microcode file. Then it would loop through the whole file looking for a match then load the microcode. This process was maintained for intel_update_microcode_from_cbfs(), however 2 new functions were exported: 1. const void *intel_microcode_find(void) 2. void intel_microcode_load_unlocked(const void *microcode_patch) The first locates a matching microcode while the second loads that mircocode. These new functions can then be used to cache the found microcode blob w/o having to re-walk the CBFS. Booted baskingridge board to Linux and noted that all microcode revisions match on all the CPUs. Change-Id: Ifde3f3e5c100911c4f984dd56d36664a8acdf7d5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/microcode/microcode.c | 128 +++++++++++++++++++++++++++++++----- src/include/cpu/intel/microcode.h | 7 ++ 2 files changed, 117 insertions(+), 18 deletions(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 713a6df..d908c25 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -82,8 +82,117 @@ static inline u32 read_microcode_rev(void) } #if CONFIG_CPU_MICROCODE_IN_CBFS -static + +#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" + +void intel_microcode_load_unlocked(const void *microcode_patch) +{ + u32 current_rev; + msr_t msr; + const struct microcode *m = microcode_patch; + + if (!m) + return; + + current_rev = read_microcode_rev(); + + /* No use loading the same revision. */ + if (current_rev == m->rev) + return; + + msr.lo = (unsigned long)m + sizeof(struct microcode); + msr.hi = 0; + wrmsr(0x79, msr); + +#if !defined(__ROMCC__) + printk(BIOS_DEBUG, "microcode: updated to revision " + "0x%x date=%04x-%02x-%02x\n", read_microcode_rev(), + m->date & 0xffff, (m->date >> 24) & 0xff, + (m->date >> 16) & 0xff); +#endif +} + +const void *intel_microcode_find(void) +{ + void *microcode_updates; + u32 eax; + u32 pf, rev, sig; + unsigned int x86_model, x86_family; + const struct microcode *m; + const char *c; + msr_t msr; + +#ifdef __PRE_RAM__ + microcode_updates = walkcbfs((char *) MICROCODE_CBFS_FILE); +#else + microcode_updates = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + MICROCODE_CBFS_FILE, + CBFS_TYPE_MICROCODE); #endif + + if (!microcode_updates) + return microcode_updates; + + /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ + msr.lo = 0; + msr.hi = 0; + wrmsr(0x8B, msr); + eax = cpuid_eax(1); + msr = rdmsr(0x8B); + rev = msr.hi; + x86_model = (eax >>4) & 0x0f; + x86_family = (eax >>8) & 0x0f; + sig = eax; + + pf = 0; + if ((x86_model >= 5)||(x86_family>6)) { + msr = rdmsr(0x17); + pf = 1 << ((msr.hi >> 18) & 7); + } +#if !defined(__ROMCC__) + /* If this code is compiled with ROMCC we're probably in + * the bootblock and don't have console output yet. + */ + printk(BIOS_DEBUG, "microcode: sig=0x%x pf=0x%x revision=0x%x\n", + sig, pf, rev); +#endif + + m = microcode_updates; + for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { + if ((m->sig == sig) && (m->pf & pf)) + return m; + + if (m->total_size) { + c += m->total_size; + } else { +#if !defined(__ROMCC__) + printk(BIOS_WARNING, "Microcode has no valid size field!\n"); +#endif + c += 2048; + } + } + + /* ROMCC doesn't like NULL. */ + return (void *)0; +} + +void intel_update_microcode_from_cbfs(void) +{ + const void *patch = intel_microcode_find(); + +#if !defined(__ROMCC__) && !defined(__PRE_RAM__) + spin_lock(&microcode_lock); +#endif + + intel_microcode_load_unlocked(patch); + +#if !defined(__ROMCC__) && !defined(__PRE_RAM__) + spin_unlock(&microcode_lock); +#endif +} + +#else /* !CONFIG_CPU_MICROCODE_IN_CBFS */ + void intel_update_microcode(const void *microcode_updates) { u32 eax; @@ -155,21 +264,4 @@ void intel_update_microcode(const void *microcode_updates) #endif } -#if CONFIG_CPU_MICROCODE_IN_CBFS - -#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" - -void intel_update_microcode_from_cbfs(void) -{ - void *microcode_blob; - -#ifdef __PRE_RAM__ - microcode_blob = walkcbfs((char *) MICROCODE_CBFS_FILE); -#else - microcode_blob = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - MICROCODE_CBFS_FILE, - CBFS_TYPE_MICROCODE); -#endif - intel_update_microcode(microcode_blob); -} #endif diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index e9c13f9..7a291e2 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -23,6 +23,13 @@ #ifndef __PRE_RAM__ #if CONFIG_CPU_MICROCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); +/* Find a microcode that matches the revision and platform family returning + * NULL if none found. */ +const void *intel_microcode_find(void); +/* It is up to the caller to determine if parallel loading is possible as + * well as ensuring the micrcode matches the family and revision (i.e. with + * intel_microcode_find()). */ +void intel_microcode_load_unlocked(const void *microcode_patch); #else void intel_update_microcode(const void *microcode_updates); #endif

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Re: [coreboot] coreboot 2013 Google Summer of Code: Call for mentors and project ideas
by smithbone＠gmail.com 19 Mar '13

19 Mar '13

On 03/15/2013 01:10 PM, Marc Jones wrote: > ever before. coreboot on shipping devices from AMD, Google, and As I haven't been very active lately what's shipping from AMD these days. I know whats from Google. Are there production mainboards that factory ship with coreboot on them? Feel free to RTFM me to something on the webpage. I took a quick look but didn't see anything. -- Richard A. Smith smithbone(a)gmail.com

3 2

Patch merged into coreboot/master: 3c734bb AMD Dinar: Remove Unused Oem.h Header File
by gerrit＠coreboot.org 19 Mar '13

19 Mar '13

the following patch was just integrated into master: commit 3c734bb355b6cf15e61e3bc8755f622d4117e7c2 Author: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Date: Fri Mar 15 12:19:45 2013 -0600 AMD Dinar: Remove Unused Oem.h Header File Having this header file in the mainboard directory breaks the dinar build on cygwin because the header file in the dinar mainboard is used instead of the correct header file src/vendorcode/amd/cimx/sb700/OEM.h. The build probably works fine on Linux systems because, due to case-sensitivity, Oem.h will not match the #include "OEM.h" statement in src/southbridge/amd/cimx/sb700/Platform.h. The Oem.h file in the dinar mainboard is not used by any other source files, and the defines in the dinar mainboard are duplicated by defines in the correct OEM.h file. Therefore, the file can be safely removed. Change-Id: I81b97eca8116d63644d335edc3bb51f90c7094d9 Signed-off-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2776 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Mon Mar 18 22:05:34 2013, giving +1 See http://review.coreboot.org/2776 for details. -gerrit

1 0

Patch set updated for coreboot: 328ace0 AMD Fam15: Add SPD read functions to wrapper code
by Kimarie Hoot 18 Mar '13

18 Mar '13

Kimarie Hoot (kimarie.hoot(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2777 -gerrit commit 328ace05ae76e16e9071eab2c607e8737d76ab0f Author: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Date: Thu Mar 7 16:42:09 2013 -0700 AMD Fam15: Add SPD read functions to wrapper code Change: This is the initial step for moving the AMD F15 & HUDSON1,2,3 SPD-read callout out of the mainboard directories and into the wrapper. The next step is to update the platforms to use this routine in BiosCallouts.c and to delete the code from the mainboard directories. The DIMM addresses should be moved into devicetree.cb. If there are significant differences or reasons that the mainboard needs to override this code, it's perfectly reasonable to keep using the version in the mainboard, but this allows us to remove duplicated code and simplify the mainboard directories. Notes: This started by duplicating what was in Dinar, and was changed to use the devicetree.cb structures. Significant cleanup and magic number reduction was done as well. It is intended that this file will not be included in ramstage as the DIMM init is all done in romstage. This is similar to what was done for Parmer/Thatcher in commit 7fb692bd - http://review.coreboot.org/#/c/2190/ Fam15tn: Move SPD read from mainboards into wrapper Yes, it would make sense to split this into two separate files and move the SMBus initialization and access into the southbridge wrapper. Maybe that can come next. Change-Id: I4e00ada288e1486cf30684403505e475f9093ec2 Signed-off-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> --- src/northbridge/amd/agesa/family15/Makefile.inc | 2 + src/northbridge/amd/agesa/family15/chip.h | 49 +++++++ src/northbridge/amd/agesa/family15/dimmSpd.c | 186 ++++++++++++++++++++++++ src/northbridge/amd/agesa/family15/dimmSpd.h | 97 ++++++++++++ 4 files changed, 334 insertions(+) diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc index 7fca122..4a75499 100644 --- a/src/northbridge/amd/agesa/family15/Makefile.inc +++ b/src/northbridge/amd/agesa/family15/Makefile.inc @@ -17,4 +17,6 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-y += dimmSpd.c + ramstage-y += northbridge.c diff --git a/src/northbridge/amd/agesa/family15/chip.h b/src/northbridge/amd/agesa/family15/chip.h new file mode 100644 index 0000000..66c44c4 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/chip.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_AGESA_CHIP_H_ +#define _NB_AGESA_CHIP_H_ + +struct northbridge_amd_agesa_family15_config +{ + /* + * Here are a couple of examples of how this would be put into the + * devicetree.cb file. Note the array is oversized to support different + * configurations of server boards. + * This should be placed after the device pci 18.x statements. + * + * Example: AMD Dinar + * register "spdAddrLookup" = " + * { // Use 8-bit SPD addresses here + * { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0 - Channel 0-3 + * { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 1 - Channel 0-3 + * }" + * Example: Tyan S8226 + * register "spdAddrLookup" = " + * { // Use 8-bit SPD addresses here + * { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 0 + * { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 1 + * }" + * + */ + + u8 spdAddrLookup[8][4][4]; +}; + +#endif diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.c b/src/northbridge/amd/agesa/family15/dimmSpd.c new file mode 100644 index 0000000..294454c --- /dev/null +++ b/src/northbridge/amd/agesa/family15/dimmSpd.c @@ -0,0 +1,186 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <device/pci_def.h> +#include <device/device.h> +#include <stdlib.h> +#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ + +/* warning: Porting.h includes an open #pragma pack(1) */ +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include "dimmSpd.h" +#include "chip.h" + +/* uncomment for source level debug - GDB gets really confused otherwise. */ +//#pragma optimize ("", off) + +/** + * Read a single SPD byte. If the first byte is being read, set up the + * address and offset. Following bytes auto increment. + */ +static UINT8 readSmbusByte(UINT16 iobase, UINT8 address, char *buffer, + int offset, int initial_offset) +{ + unsigned int status = -1; + UINT64 time_limit; + + /* clear status register */ + __outbyte(iobase + SMBUS_STATUS_REG, 0xFF); + __outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F); + + if (offset == initial_offset) { + /* Set offset, set slave address and start reading */ + __outbyte(iobase + SMBUS_CONTROL_REG, offset); + __outbyte(iobase + SMBUS_HOST_CMD_REG, address | READ_BIT); + __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_BYTE_COMMAND); + } else { + /* Issue read command - auto increments to next byte */ + __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_COMMAND); + } + /* time limit to avoid hanging for unexpected error status */ + time_limit = __rdtsc() + MAX_READ_TSC_COUNT; + while (__rdtsc() <= time_limit) { + status = __inbyte(iobase + SMBUS_STATUS_REG); + if ((status & SMBUS_INTERRUPT_MASK) == 0) + continue; /* SMBusInterrupt not set, keep waiting */ + if ((status & HOSTBUSY_MASK) != 0) + continue; /* HostBusy set, keep waiting */ + break; + } + + if (status != STATUS__COMPLETED_SUCCESSFULLY) + return AGESA_ERROR; + + buffer[0] = __inbyte(iobase + SMBUS_DATA0_REG); + return AGESA_SUCCESS; +} + +/** + * Write a single smbus byte. + */ +UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer, + int offset) +{ + unsigned int status = -1; + UINT64 time_limit; + + /* clear status register */ + __outbyte(iobase + SMBUS_STATUS_REG, 0xFF); + __outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F); + + /* set offset, set slave address, set data and start writing */ + __outbyte(iobase + SMBUS_CONTROL_REG, offset); + __outbyte(iobase + SMBUS_HOST_CMD_REG, address & (~READ_BIT)); + __outbyte(iobase + SMBUS_DATA0_REG, buffer); + __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_WRITE_BYTE_COMMAND); + + /* time limit to avoid hanging for unexpected error status */ + time_limit = __rdtsc() + MAX_READ_TSC_COUNT; + while (__rdtsc() <= time_limit) { + status = __inbyte(iobase + SMBUS_STATUS_REG); + if ((status & SMBUS_INTERRUPT_MASK) == 0) + continue; /* SMBusInterrupt not set, keep waiting */ + if ((status & HOSTBUSY_MASK) != 0) + continue; /* HostBusy set, keep waiting */ + break; + } + + if (status != STATUS__COMPLETED_SUCCESSFULLY) + return AGESA_ERROR; + + return AGESA_SUCCESS; +} + +static void setupFch(UINT16 ioBase) +{ + AMD_CONFIG_PARAMS StdHeader; + UINT32 PciData32; + UINT8 PciData8; + PCI_ADDR PciAddress; + + /* Set SMBus MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90); + PciData32 = (ioBase & 0xFFFFFFF0) | BIT0; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader); + + /* Enable SMBus MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); + LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ; + PciData8 |= BIT0; + LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); + + /* Set SMBus clock to 400 KHz */ + __outbyte(ioBase + SMBUS_CLOCK_REG, SMBUS_FREQUENCY_CONST / 400000); +} + +/** + * Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Reads 128 bytes in 7-8 ms at 400 KHz. + */ +static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer, + UINT16 count) +{ + UINT16 index; + UINT8 status; + UINT8 initial_offset = 0; + + setupFch(iobase); + + for (index = initial_offset; index < count; index++) { + status = readSmbusByte(iobase, SmbusSlaveAddress, &buffer[index], index, + initial_offset); + if (status != AGESA_SUCCESS) + return status; + } + + return status; +} + +/** + * Gets the SMBus address for an SPD from the array in devicetree.cb + * then read the SPD into the supplied buffer. + */ +AGESA_STATUS agesa_ReadSPD(UINT32 unused1, UINT32 unused2, void *infoptr) +{ + UINT8 spdAddress; + AGESA_READ_SPD_PARAMS *info = infoptr; + ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); + ROMSTAGE_CONST struct northbridge_amd_agesa_family15_config *config = NULL; + + if ((dev == 0) || (dev->chip_info == 0)) + return AGESA_ERROR; + + config = dev->chip_info; + if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) + return AGESA_ERROR; + if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) + return AGESA_ERROR; + if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) + return AGESA_ERROR; + + spdAddress = config->spdAddrLookup + [info->SocketId][info->MemChannelId][info->DimmId]; + + if (spdAddress == 0) + return AGESA_ERROR; + + return readspd(SMBUS0_BASE_ADDRESS, spdAddress, (void *)info->Buffer, 256); +} diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.h b/src/northbridge/amd/agesa/family15/dimmSpd.h new file mode 100644 index 0000000..167b4a1 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/dimmSpd.h @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _DIMMSPD_H_ +#define _DIMMSPD_H_ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define READ_BIT 0x01 + +#define SMBUS_INTERRUPT_MASK 0x02 +#define HOSTBUSY_MASK 0x01 + +#define SMBUS_READ_BYTE_COMMAND 0x48 +#define SMBUS_READ_COMMAND 0x44 + +#define SMBUS_WRITE_BYTE_COMMAND 0x48 + +#define MAX_READ_TSC_COUNT (2000000000 / 10) + +#define PMIO_INDEX_REG 0xCD6 +#define PMIO_DATA_REG 0xCD7 + +#define SMBUS_BAR_LOW_BYTE 0x2C +#define SMBUS_BAR_HIGH_BYTE 0x2D + +#define SMBUS_STATUS_REG 0x00 +#define SMBUS_SLAVE_STATUS_REG 0x01 +#define SMBUS_COMMAND_REG 0x02 +#define SMBUS_CONTROL_REG 0x03 +#define SMBUS_HOST_CMD_REG 0x04 +#define SMBUS_DATA0_REG 0x05 +#define SMBUS_CLOCK_REG 0x0E + +#define STATUS__COMPLETED_SUCCESSFULLY 0x02 + +#define SMBUS_FREQUENCY_CONST 66000000 / 4 +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +agesa_ReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT void *SpdData); + +/* + * This function prototype is only used by the AMD Dinar mainboard. The SMBus + * write is used to select which socket's SPD will be read by the subsequent + * SPD read call. This function is being placed in the F15 wrapper code with + * the other SPD read functions because the next step of the SPD read clean-up + * will be to move the SMBus read/write functions into the southbridge to make + * them more generic. Having the writeSmbusByte() function in the same file as + * the readSmbusByte() function will ensure that the writeSmbusByte() function + * is not overlooked. + */ +UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer, int offset); + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif

1 0

Patch set updated for coreboot: 17f84ed AMD Fam15: Add SPD read functions to wrapper code
by Kimarie Hoot 18 Mar '13

18 Mar '13

Kimarie Hoot (kimarie.hoot(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2777 -gerrit commit 17f84ed157c109650f881d0804d090632d1dd3d0 Author: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Date: Thu Mar 7 16:42:09 2013 -0700 AMD Fam15: Add SPD read functions to wrapper code Change: This is the initial step for moving the AMD F15 & HUDSON1,2,3 SPD-read callout out of the mainboard directories and into the wrapper. The next step is to update the platforms to use this routine in BiosCallouts.c and to delete the code from the mainboard directories. The DIMM addresses should be moved into devicetree.cb. If there are significant differences or reasons that the mainboard needs to override this code, it's perfectly reasonable to keep using the version in the mainboard, but this allows us to remove duplicated code and simplify the mainboard directories. Notes: This started by duplicating what was in Dinar, and was changed to use the devicetree.cb structures. Significant cleanup and magic number reduction was done as well. It is intended that this file will not be included in ramstage as the DIMM init is all done in romstage. This is similar to what was done for Parmer/Thatcher in commit 7fb692bd - http://review.coreboot.org/#/c/2190/ Fam15tn: Move SPD read from mainboards into wrapper Yes, it would make sense to split this into two separate files and move the SMBUS initialization and access into the southbridge wrapper. Maybe that can come next. Change-Id: I4e00ada288e1486cf30684403505e475f9093ec2 Signed-off-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> --- src/northbridge/amd/agesa/family15/Makefile.inc | 2 + src/northbridge/amd/agesa/family15/chip.h | 49 +++++++ src/northbridge/amd/agesa/family15/dimmSpd.c | 186 ++++++++++++++++++++++++ src/northbridge/amd/agesa/family15/dimmSpd.h | 97 ++++++++++++ 4 files changed, 334 insertions(+) diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc index 7fca122..4a75499 100644 --- a/src/northbridge/amd/agesa/family15/Makefile.inc +++ b/src/northbridge/amd/agesa/family15/Makefile.inc @@ -17,4 +17,6 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-y += dimmSpd.c + ramstage-y += northbridge.c diff --git a/src/northbridge/amd/agesa/family15/chip.h b/src/northbridge/amd/agesa/family15/chip.h new file mode 100644 index 0000000..66c44c4 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/chip.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_AGESA_CHIP_H_ +#define _NB_AGESA_CHIP_H_ + +struct northbridge_amd_agesa_family15_config +{ + /* + * Here are a couple of examples of how this would be put into the + * devicetree.cb file. Note the array is oversized to support different + * configurations of server boards. + * This should be placed after the device pci 18.x statements. + * + * Example: AMD Dinar + * register "spdAddrLookup" = " + * { // Use 8-bit SPD addresses here + * { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0 - Channel 0-3 + * { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 1 - Channel 0-3 + * }" + * Example: Tyan S8226 + * register "spdAddrLookup" = " + * { // Use 8-bit SPD addresses here + * { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 0 + * { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 1 + * }" + * + */ + + u8 spdAddrLookup[8][4][4]; +}; + +#endif diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.c b/src/northbridge/amd/agesa/family15/dimmSpd.c new file mode 100644 index 0000000..294454c --- /dev/null +++ b/src/northbridge/amd/agesa/family15/dimmSpd.c @@ -0,0 +1,186 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <device/pci_def.h> +#include <device/device.h> +#include <stdlib.h> +#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ + +/* warning: Porting.h includes an open #pragma pack(1) */ +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include "dimmSpd.h" +#include "chip.h" + +/* uncomment for source level debug - GDB gets really confused otherwise. */ +//#pragma optimize ("", off) + +/** + * Read a single SPD byte. If the first byte is being read, set up the + * address and offset. Following bytes auto increment. + */ +static UINT8 readSmbusByte(UINT16 iobase, UINT8 address, char *buffer, + int offset, int initial_offset) +{ + unsigned int status = -1; + UINT64 time_limit; + + /* clear status register */ + __outbyte(iobase + SMBUS_STATUS_REG, 0xFF); + __outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F); + + if (offset == initial_offset) { + /* Set offset, set slave address and start reading */ + __outbyte(iobase + SMBUS_CONTROL_REG, offset); + __outbyte(iobase + SMBUS_HOST_CMD_REG, address | READ_BIT); + __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_BYTE_COMMAND); + } else { + /* Issue read command - auto increments to next byte */ + __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_COMMAND); + } + /* time limit to avoid hanging for unexpected error status */ + time_limit = __rdtsc() + MAX_READ_TSC_COUNT; + while (__rdtsc() <= time_limit) { + status = __inbyte(iobase + SMBUS_STATUS_REG); + if ((status & SMBUS_INTERRUPT_MASK) == 0) + continue; /* SMBusInterrupt not set, keep waiting */ + if ((status & HOSTBUSY_MASK) != 0) + continue; /* HostBusy set, keep waiting */ + break; + } + + if (status != STATUS__COMPLETED_SUCCESSFULLY) + return AGESA_ERROR; + + buffer[0] = __inbyte(iobase + SMBUS_DATA0_REG); + return AGESA_SUCCESS; +} + +/** + * Write a single smbus byte. + */ +UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer, + int offset) +{ + unsigned int status = -1; + UINT64 time_limit; + + /* clear status register */ + __outbyte(iobase + SMBUS_STATUS_REG, 0xFF); + __outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F); + + /* set offset, set slave address, set data and start writing */ + __outbyte(iobase + SMBUS_CONTROL_REG, offset); + __outbyte(iobase + SMBUS_HOST_CMD_REG, address & (~READ_BIT)); + __outbyte(iobase + SMBUS_DATA0_REG, buffer); + __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_WRITE_BYTE_COMMAND); + + /* time limit to avoid hanging for unexpected error status */ + time_limit = __rdtsc() + MAX_READ_TSC_COUNT; + while (__rdtsc() <= time_limit) { + status = __inbyte(iobase + SMBUS_STATUS_REG); + if ((status & SMBUS_INTERRUPT_MASK) == 0) + continue; /* SMBusInterrupt not set, keep waiting */ + if ((status & HOSTBUSY_MASK) != 0) + continue; /* HostBusy set, keep waiting */ + break; + } + + if (status != STATUS__COMPLETED_SUCCESSFULLY) + return AGESA_ERROR; + + return AGESA_SUCCESS; +} + +static void setupFch(UINT16 ioBase) +{ + AMD_CONFIG_PARAMS StdHeader; + UINT32 PciData32; + UINT8 PciData8; + PCI_ADDR PciAddress; + + /* Set SMBus MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90); + PciData32 = (ioBase & 0xFFFFFFF0) | BIT0; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader); + + /* Enable SMBus MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); + LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ; + PciData8 |= BIT0; + LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); + + /* Set SMBus clock to 400 KHz */ + __outbyte(ioBase + SMBUS_CLOCK_REG, SMBUS_FREQUENCY_CONST / 400000); +} + +/** + * Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Reads 128 bytes in 7-8 ms at 400 KHz. + */ +static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer, + UINT16 count) +{ + UINT16 index; + UINT8 status; + UINT8 initial_offset = 0; + + setupFch(iobase); + + for (index = initial_offset; index < count; index++) { + status = readSmbusByte(iobase, SmbusSlaveAddress, &buffer[index], index, + initial_offset); + if (status != AGESA_SUCCESS) + return status; + } + + return status; +} + +/** + * Gets the SMBus address for an SPD from the array in devicetree.cb + * then read the SPD into the supplied buffer. + */ +AGESA_STATUS agesa_ReadSPD(UINT32 unused1, UINT32 unused2, void *infoptr) +{ + UINT8 spdAddress; + AGESA_READ_SPD_PARAMS *info = infoptr; + ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); + ROMSTAGE_CONST struct northbridge_amd_agesa_family15_config *config = NULL; + + if ((dev == 0) || (dev->chip_info == 0)) + return AGESA_ERROR; + + config = dev->chip_info; + if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) + return AGESA_ERROR; + if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) + return AGESA_ERROR; + if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) + return AGESA_ERROR; + + spdAddress = config->spdAddrLookup + [info->SocketId][info->MemChannelId][info->DimmId]; + + if (spdAddress == 0) + return AGESA_ERROR; + + return readspd(SMBUS0_BASE_ADDRESS, spdAddress, (void *)info->Buffer, 256); +} diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.h b/src/northbridge/amd/agesa/family15/dimmSpd.h new file mode 100644 index 0000000..167b4a1 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/dimmSpd.h @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _DIMMSPD_H_ +#define _DIMMSPD_H_ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define READ_BIT 0x01 + +#define SMBUS_INTERRUPT_MASK 0x02 +#define HOSTBUSY_MASK 0x01 + +#define SMBUS_READ_BYTE_COMMAND 0x48 +#define SMBUS_READ_COMMAND 0x44 + +#define SMBUS_WRITE_BYTE_COMMAND 0x48 + +#define MAX_READ_TSC_COUNT (2000000000 / 10) + +#define PMIO_INDEX_REG 0xCD6 +#define PMIO_DATA_REG 0xCD7 + +#define SMBUS_BAR_LOW_BYTE 0x2C +#define SMBUS_BAR_HIGH_BYTE 0x2D + +#define SMBUS_STATUS_REG 0x00 +#define SMBUS_SLAVE_STATUS_REG 0x01 +#define SMBUS_COMMAND_REG 0x02 +#define SMBUS_CONTROL_REG 0x03 +#define SMBUS_HOST_CMD_REG 0x04 +#define SMBUS_DATA0_REG 0x05 +#define SMBUS_CLOCK_REG 0x0E + +#define STATUS__COMPLETED_SUCCESSFULLY 0x02 + +#define SMBUS_FREQUENCY_CONST 66000000 / 4 +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +agesa_ReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT void *SpdData); + +/* + * This function prototype is only used by the AMD Dinar mainboard. The SMBus + * write is used to select which socket's SPD will be read by the subsequent + * SPD read call. This function is being placed in the F15 wrapper code with + * the other SPD read functions because the next step of the SPD read clean-up + * will be to move the SMBus read/write functions into the southbridge to make + * them more generic. Having the writeSmbusByte() function in the same file as + * the readSmbusByte() function will ensure that the writeSmbusByte() function + * is not overlooked. + */ +UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer, int offset); + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif

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New patch to review for coreboot: fd0fb3b AMD Fam15: Add SPD read functions to wrapper code
by Kimarie Hoot 18 Mar '13

18 Mar '13

Kimarie Hoot (kimarie.hoot(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2777 -gerrit commit fd0fb3b3a77cd12c994a9419a8dce5072ff629ea Author: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Date: Thu Mar 7 16:42:09 2013 -0700 AMD Fam15: Add SPD read functions to wrapper code Change: This is the initial step for moving the AMD F15 & HUDSON1,2,3 SPD-read callout out of the mainboard directories and into the wrapper. The next step is to update the platforms to use this routine in BiosCallouts.c and to delete the code from the mainboard directories. The DIMM addresses should be moved into devicetree.cb. If there are significant differences or reasons that the mainboard needs to override this code, it's perfectly reasonable to keep using the version in the mainboard, but this allows us to remove duplicated code and simplify the mainboard directories. Notes: This started by duplicating what was in Dinar, and was changed to use the devicetree.cb structures. Significant cleanup and magic number reduction was done as well. It is intended that this file will not be included in ramstage as the DIMM init is all done in romstage. This is similar to what was done for Parmer/Thatcher in commit 7fb692bd - http://review.coreboot.org/#/c/2190/ Fam15tn: Move SPD read from mainboards into wrapper Yes, it would make sense to split this into two separate files and move the SMBUS initialization and access into the southbridge wrapper. Maybe that can come next. Change-Id: I4e00ada288e1486cf30684403505e475f9093ec2 Signed-off-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> --- src/northbridge/amd/agesa/family15/Makefile.inc | 2 + src/northbridge/amd/agesa/family15/chip.h | 49 +++++++ src/northbridge/amd/agesa/family15/dimmSpd.c | 186 ++++++++++++++++++++++++ src/northbridge/amd/agesa/family15/dimmSpd.h | 97 ++++++++++++ 4 files changed, 334 insertions(+) diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc index 7fca122..4a75499 100644 --- a/src/northbridge/amd/agesa/family15/Makefile.inc +++ b/src/northbridge/amd/agesa/family15/Makefile.inc @@ -17,4 +17,6 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-y += dimmSpd.c + ramstage-y += northbridge.c diff --git a/src/northbridge/amd/agesa/family15/chip.h b/src/northbridge/amd/agesa/family15/chip.h new file mode 100644 index 0000000..66c44c4 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/chip.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_AGESA_CHIP_H_ +#define _NB_AGESA_CHIP_H_ + +struct northbridge_amd_agesa_family15_config +{ + /* + * Here are a couple of examples of how this would be put into the + * devicetree.cb file. Note the array is oversized to support different + * configurations of server boards. + * This should be placed after the device pci 18.x statements. + * + * Example: AMD Dinar + * register "spdAddrLookup" = " + * { // Use 8-bit SPD addresses here + * { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0 - Channel 0-3 + * { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 1 - Channel 0-3 + * }" + * Example: Tyan S8226 + * register "spdAddrLookup" = " + * { // Use 8-bit SPD addresses here + * { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 0 + * { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 1 + * }" + * + */ + + u8 spdAddrLookup[8][4][4]; +}; + +#endif diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.c b/src/northbridge/amd/agesa/family15/dimmSpd.c new file mode 100644 index 0000000..4fb8916 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/dimmSpd.c @@ -0,0 +1,186 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <device/pci_def.h> +#include <device/device.h> +#include <stdlib.h> +#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ + +/* warning: Porting.h includes an open #pragma pack(1) */ +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include "dimmSpd.h" +#include "chip.h" + +/* uncomment for source level debug - GDB gets really confused otherwise. */ +//#pragma optimize ("", off) + +/** + * Read a single SPD byte. If the first byte is being read, set up the + * address and offset. Following bytes auto increment. + */ +static UINT8 readSmbusByte(UINT16 iobase, UINT8 address, char *buffer, + int offset, int initial_offset) +{ + unsigned int status = -1; + UINT64 time_limit; + + /* clear status register */ + __outbyte(iobase + SMBUS_STATUS_REG, 0xFF); + __outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F); + + if (offset == initial_offset) { + /* Set offset, set slave address and start reading */ + __outbyte(iobase + SMBUS_CONTROL_REG, offset); + __outbyte(iobase + SMBUS_HOST_CMD_REG, address | READ_BIT); + __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_BYTE_COMMAND); + } else { + /* Issue read command - auto increments to next byte */ + __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_COMMAND); + } + /* time limit to avoid hanging for unexpected error status */ + time_limit = __rdtsc() + MAX_READ_TSC_COUNT; + while (__rdtsc() <= time_limit) { + status = __inbyte(iobase + SMBUS_STATUS_REG); + if ((status & SMBUS_INTERRUPT_MASK) == 0) + continue; /* SMBusInterrupt not set, keep waiting */ + if ((status & HOSTBUSY_MASK) != 0) + continue; /* HostBusy set, keep waiting */ + break; + } + + if (status != STATUS__COMPLETED_SUCCESSFULLY) + return AGESA_ERROR; + + buffer[0] = __inbyte(iobase + SMBUS_DATA0_REG); + return AGESA_SUCCESS; +} + +/** + * Write a single smbus byte. + */ +UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer, + int offset) +{ + unsigned int status = -1; + UINT64 time_limit; + + /* clear status register */ + __outbyte(iobase + SMBUS_STATUS_REG, 0xFF); + __outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F); + + /* set offset, set slave address, set data and start writing */ + __outbyte(iobase + SMBUS_CONTROL_REG, offset); + __outbyte(iobase + SMBUS_HOST_CMD_REG, address & (~READ_BIT)); + __outbyte(iobase + SMBUS_DATA0_REG, buffer); + __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_WRITE_BYTE_COMMAND); + + /* time limit to avoid hanging for unexpected error status */ + time_limit = __rdtsc() + MAX_READ_TSC_COUNT; + while (__rdtsc() <= time_limit) { + status = __inbyte(iobase + SMBUS_STATUS_REG); + if ((status & SMBUS_INTERRUPT_MASK) == 0) + continue; /* SMBusInterrupt not set, keep waiting */ + if ((status & HOSTBUSY_MASK) != 0) + continue; /* HostBusy set, keep waiting */ + break; + } + + if (status != STATUS__COMPLETED_SUCCESSFULLY) + return AGESA_ERROR; + + return AGESA_SUCCESS; +} + +static void setupFch(UINT16 ioBase) +{ + AMD_CONFIG_PARAMS StdHeader; + UINT32 PciData32; + UINT8 PciData8; + PCI_ADDR PciAddress; + + /* Set SMBUS MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90); + PciData32 = (ioBase & 0xFFFFFFF0) | BIT0; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader); + + /* Enable SMBUS MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); + LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ; + PciData8 |= BIT0; + LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); + + /* set SMBus clock to 400 KHz */ + __outbyte(ioBase + SMBUS_CLOCK_REG, SMBUS_FREQUENCY_CONST / 400000); +} + +/** + * Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Reads 128 bytes in 7-8 ms at 400 KHz. + */ +static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer, + UINT16 count) +{ + UINT16 index; + UINT8 status; + UINT8 initial_offset = 0; + + setupFch(iobase); + + for (index = initial_offset; index < count; index++) { + status = readSmbusByte(iobase, SmbusSlaveAddress, &buffer[index], index, + initial_offset); + if (status != AGESA_SUCCESS) + return status; + } + + return status; +} + +/** + * Gets the SMBUS address for an SPD from the array in devicetree.cb + * then read the SPD into the supplied buffer. + */ +AGESA_STATUS agesa_ReadSPD(UINT32 unused1, UINT32 unused2, void *infoptr) +{ + UINT8 spdAddress; + AGESA_READ_SPD_PARAMS *info = infoptr; + ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); + ROMSTAGE_CONST struct northbridge_amd_agesa_family15_config *config = NULL; + + if ((dev == 0) || (dev->chip_info == 0)) + return AGESA_ERROR; + + config = dev->chip_info; + if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) + return AGESA_ERROR; + if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) + return AGESA_ERROR; + if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) + return AGESA_ERROR; + + spdAddress = config->spdAddrLookup + [info->SocketId][info->MemChannelId][info->DimmId]; + + if (spdAddress == 0) + return AGESA_ERROR; + + return readspd(SMBUS0_BASE_ADDRESS, spdAddress, (void *)info->Buffer, 256); +} diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.h b/src/northbridge/amd/agesa/family15/dimmSpd.h new file mode 100644 index 0000000..7cd2747 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/dimmSpd.h @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _DIMMSPD_H_ +#define _DIMMSPD_H_ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define READ_BIT 0x01 + +#define SMBUS_INTERRUPT_MASK 0x02 +#define HOSTBUSY_MASK 0x01 + +#define SMBUS_READ_BYTE_COMMAND 0x48 +#define SMBUS_READ_COMMAND 0x44 + +#define SMBUS_WRITE_BYTE_COMMAND 0x48 + +#define MAX_READ_TSC_COUNT (2000000000 / 10) + +#define PMIO_INDEX_REG 0xCD6 +#define PMIO_DATA_REG 0xCD7 + +#define SMBUS_BAR_LOW_BYTE 0x2C +#define SMBUS_BAR_HIGH_BYTE 0x2D + +#define SMBUS_STATUS_REG 0x00 +#define SMBUS_SLAVE_STATUS_REG 0x01 +#define SMBUS_COMMAND_REG 0x02 +#define SMBUS_CONTROL_REG 0x03 +#define SMBUS_HOST_CMD_REG 0x04 +#define SMBUS_DATA0_REG 0x05 +#define SMBUS_CLOCK_REG 0x0E + +#define STATUS__COMPLETED_SUCCESSFULLY 0x02 + +#define SMBUS_FREQUENCY_CONST 66000000 / 4 +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +agesa_ReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT void *SpdData); + +/* + * This function prototype is only used by the AMD Dinar mainboard. The smbus + * write is used to select which socket's SPD will be read by the subsequent + * SPD read call. This function is being placed in the F15 wrapper code with + * the other SPD read functions because the next step of the SPD read clean-up + * will be to move the smbus read/write functions into the southbridge to make + * them more generic. Having the writeSmbusByte() function in the same file as + * the readSmbusByte() function will ensure that the writeSmbusByte() function + * is not overlooked. + */ +UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer, int offset); + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif

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New patch to review for coreboot: c6de670 AMD Dinar: Remove Unused Oem.h Header File
by Kimarie Hoot 18 Mar '13

18 Mar '13

Kimarie Hoot (kimarie.hoot(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2776 -gerrit commit c6de6702ecbc735a792e969efd9f738cc726b238 Author: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Date: Fri Mar 15 12:19:45 2013 -0600 AMD Dinar: Remove Unused Oem.h Header File Having this header file in the mainboard directory breaks the dinar build on cygwin because the header file in the dinar mainboard is used instead of the correct header file src/vendorcode/amd/cimx/sb700/OEM.h. The build probably works fine on Linux systems because, due to case-sensitivity, Oem.h will not match the #include "OEM.h" statement in src/southbridge/amd/cimx/sb700/Platform.h. The Oem.h file in the dinar mainboard is not used by any other source files, and the defines in the dinar mainboard are duplicated by defines in the correct OEM.h file. Therefore, the file can be safely removed. Change-Id: I81b97eca8116d63644d335edc3bb51f90c7094d9 Signed-off-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> --- src/mainboard/amd/dinar/Oem.h | 79 ------------------------------------------- 1 file changed, 79 deletions(-) diff --git a/src/mainboard/amd/dinar/Oem.h b/src/mainboard/amd/dinar/Oem.h deleted file mode 100644 index 767a77d..0000000 --- a/src/mainboard/amd/dinar/Oem.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AMD_SB_CIMx_OEM_H_ -#define _AMD_SB_CIMx_OEM_H_ - -#define MOVE_PCIEBAR_TO_F0000000 - -#define LEGACY_FREE 0x00 - -/** - * PCIEX_BASE_ADDRESS - Define PCIE base address - * - * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 - */ -#ifdef MOVE_PCIEBAR_TO_F0000000 -#define PCIEX_BASE_ADDRESS 0xF8000000 -#else -#define PCIEX_BASE_ADDRESS 0xE0000000 -#endif - - -#define SMBUS0_BASE_ADDRESS 0xB00 -#define SMBUS1_BASE_ADDRESS 0xB20 -#define SIO_PME_BASE_ADDRESS 0xE00 -#define SPI_BASE_ADDRESS 0xFEC10000 - -#define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address -#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address - -#define PM1_EVT_BLK_ADDRESS 0x800 // AcpiPm1EvtBlkAddr; -#define PM1_CNT_BLK_ADDRESS 0x804 // AcpiPm1CntBlkAddr; -#define PM1_TMR_BLK_ADDRESS 0x808 // AcpiPmTmrBlkAddr; -#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr; -#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; -#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr; -#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr; - -#define EC_LDN5_MAILBOX_ADDRESS 0x550 -#define EC_LDN5_IRQ 0x05 -#define EC_LDN9_MAILBOX_ADDRESS 0x3E - -#define SATA_IDE_MODE_SSID 0x43901002 -#define SATA_RAID_MODE_SSID 0x43921002 -#define SATA_RAID5_MODE_SSID 0x43931002 -#define SATA_AHCI_SSID 0x43911002 -#define OHCI0_SSID 0x43971002 -#define OHCI1_SSID 0x43981002 -#define EHCI0_SSID 0x43961002 -#define OHCI2_SSID 0x43971002 -#define OHCI3_SSID 0x43981002 -#define EHCI1_SSID 0x43961002 -#define OHCI4_SSID 0x43991002 - -#define SMBUS_SSID 0x43851002 -#define IDE_SSID 0x439C1002 -#define AZALIA_SSID 0x43831002 -#define LPC_SSID 0x439D1002 -#define P2P_SSID 0x43841002 - -#define RESERVED_VALUE 0x00 - -#endif //ifndef _AMD_SB_CIMx_OEM_H_

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Patch merged into coreboot/master: c2fe1e0 SMM: link against libgcc
by gerrit＠coreboot.org 18 Mar '13

18 Mar '13

the following patch was just integrated into master: commit c2fe1e0a0999f65f7954ba88b69e63c3d2737291 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Mar 14 17:53:19 2013 -0700 SMM: link against libgcc The non-relocatable SMM code was changed to link against libgcc a while back so that printk could use built-in division instead of a hand crafted div() function. However, the relocatable SMM code was not adapted by mistake. This patch links the relocatable SMM against libgcc, too, so we can enable it for Haswell. Change-Id: Ia64a78e2e62348d115ae4ded52d1a02c74c5cea4 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2727 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Mar 15 21:26:43 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Mar 18 20:51:26 2013, giving +2 See http://review.coreboot.org/2727 for details. -gerrit

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Patch merged into coreboot/master: 7492ec1 haswell: add romstage_after_car() function
by gerrit＠coreboot.org 18 Mar '13

18 Mar '13

the following patch was just integrated into master: commit 7492ec1ca62efee1f244d8306b03ed3d74ac2e53 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Feb 8 22:18:04 2013 -0600 haswell: add romstage_after_car() function There are changes coming to perform more complex tasks after cache-as-ram has been torn down but before ramstage is loaded. Therefore, add the romstage_after_car() function to call after cache-as-ram is torn down. Its responsibility is for loading the ramstage and any other complex tasks. For example, the saving of OS-controlled memory in the resume path has now been moved into C instead of assembly. Change-Id: Ie0c229cf83a9271c8995b31c534c8e5a696b164e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/2757 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 16 01:13:01 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Mar 18 20:50:45 2013, giving +2 See http://review.coreboot.org/2757 for details. -gerrit

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coreboot March 2013