coreboot February 2013

coreboot@coreboot.org

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Patch set updated for coreboot: d8c5961 armv7: Add 'bootblock' build class.
by David Hendricks 03 Feb '13

03 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2252 -gerrit commit d8c5961da96cb75069cd373018e4713e82257879 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Fri Feb 1 01:09:24 2013 +0800 armv7: Add 'bootblock' build class. For ARM platform, the bootblock may need more C source files to initialize UART / SPI for loading romstage. To preventing making complex and implicit dependency by using #include inside bootblock.c, we should add a new build class "bootblock". Also #ifdef __BOOT_BLOCK__ can be used to detect if the source is being compiled for boot block. For x86, the bootblock is limited to fewer assembly files so it's not using this class. (Some files shared by x86 and arm in top level or lib are also changed but nothing should be changed in x86 build process.) Change-Id: Ia81bccc366d2082397d133d9245f7ecb33b8bc8b Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- Makefile.inc | 10 ++++- src/arch/armv7/Makefile.inc | 9 +++-- src/arch/armv7/bootblock_simple.c | 2 +- src/arch/armv7/include/arch/cbfs.h | 60 ----------------------------- src/arch/armv7/lib/Makefile.inc | 1 + src/cpu/samsung/exynos5-common/Makefile.inc | 1 + src/lib/Makefile.inc | 10 +++++ src/lib/cbfs.c | 2 + src/mainboard/google/snow/bootblock.c | 3 -- 9 files changed, 30 insertions(+), 68 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 3731797..0b473e4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -58,7 +58,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage smm cpu_microcode +classes-y := ramstage romstage bootblock smm cpu_microcode ####################################################################### # Helper functions for ramstage postprocess @@ -111,6 +111,9 @@ $(error Your current configuration requires binary-only components, but you did endif endif +bootblock-c-ccopts:=-D__BOOT_BLOCK__ +bootblock-S-ccopts:=-D__BOOT_BLOCK__ + smm-c-ccopts:=-D__SMM__ smm-S-ccopts:=-D__SMM__ @@ -121,6 +124,7 @@ endif ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) +bootblock-c-deps:=$$(OPTION_TABLE_H) ####################################################################### # Add handler to compile ACPI's ASL @@ -286,6 +290,10 @@ $(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $ @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -D__PRE_RAM__ $(CFLAGS) -c -o $@ $< +$(obj)/%.bootblock.o $(abspath $(obj))/%.bootblock.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD -D__BOOT_BLOCK__ $(CFLAGS) -c -o $@ $< + ####################################################################### # Clean up rules clean-abuild: diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index e55f477..715ce1e 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -207,6 +207,9 @@ bootblock_inc += $(src)/arch/armv7/lib/id.inc bootblock_inc += $(chipset_bootblock_inc) bootblock_inc += $(objgenerated)/bootblock.inc +bootblock_custom = $(src)/$(call strip_quotes,$(CONFIG_BOOTBLOCK_CPU_INIT)) +bootblock_custom += $(src)/$(call strip_quotes,$(CONFIG_BOOTBLOCK_MAINBOARD_INIT)) + $(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ @@ -223,18 +226,18 @@ $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(o @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ -$(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(OPTION_TABLE_H) +$(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(bootblock_custom) $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d $(CC) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ -$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld +$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(stages) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m armelf_linux_eabi -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(objgenerated)/bootblock.o $(stages) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(objgenerated)/bootblock.o $(bootblock-objs) $(stages) $(LIBGCC_FILE_NAME) -Wl,--end-group endif ################################################################################ diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c index 8df7e6a..e808edc 100644 --- a/src/arch/armv7/bootblock_simple.c +++ b/src/arch/armv7/bootblock_simple.c @@ -20,9 +20,9 @@ */ #include <bootblock_common.h> -#include <arch/cbfs.h> #include <arch/hlt.h> #include <arch/stages.h> +#include <cbfs.h> #include "stages.c" diff --git a/src/arch/armv7/include/arch/cbfs.h b/src/arch/armv7/include/arch/cbfs.h deleted file mode 100644 index e34a0d2..0000000 --- a/src/arch/armv7/include/arch/cbfs.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __INCLUDE_ARCH_CBFS__ -#define __INCLUDE_ARCH_CBFS__ - -#include <cbfs_core.h> -#include <arch/byteorder.h> - -// TODO FIXME This file is only for providing CBFS function in bootblock. -// Should be removed once bootblock can link lib/* files. -#include "lib/cbfs.c" - -// mem* and ulzma are now workarounds for bootblock compilation. -void *memcpy(void *dest, const void *src, size_t n) { - char *d = (char *)dest; - const char *s = (const char*)src; - while (n-- > 0) - *d++ = *s++; - return dest; -} - -void *memset(void *dest, int c, size_t n) { - char *d = (char*)dest; - while (n-- > 0) - *d++ = c; - return dest; -} - -int memcmp(const void *ptr1, const void *ptr2, size_t n) { - const char *s1 = (const char*)ptr1, *s2 = (const char*)ptr2; - int c; - while (n-- > 0) - if ((c = *s1++ - *s2++)) - return c; - return 0; -} - -unsigned long ulzma(unsigned char *src, unsigned char *dest) { - // TODO remove this. - return -1; -} - -#endif // __INCLUDE_ARCH_CBFS__ diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index e52bc54..2470db2 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -21,3 +21,4 @@ ramstage-y += syslib.c #FIXME(dhendrix): should this be a config option? romstage-y += eabi_compat.c ramstage-y += eabi_compat.c +bootblock-y += eabi_compat.c diff --git a/src/cpu/samsung/exynos5-common/Makefile.inc b/src/cpu/samsung/exynos5-common/Makefile.inc index d919347..ff86fbd 100644 --- a/src/cpu/samsung/exynos5-common/Makefile.inc +++ b/src/cpu/samsung/exynos5-common/Makefile.inc @@ -1,2 +1,3 @@ romstage-y += spi.c ramstage-y += spi.c +bootblock-y += spi.c diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 6796448..8ff0a44 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -17,6 +17,16 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +bootblock-y += cbfs.c +ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) +bootblock-y += memset.c +endif +bootblock-y += memchr.c +ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) +bootblock-y += memcpy.c +endif +bootblock-y += memcmp.c + ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) romstage-y += memset.c endif diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 3e44582..4702f1e 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -27,6 +27,8 @@ # define CBFS_MINI_BUILD #elif defined(__SMM__) # define CBFS_MINI_BUILD +#elif defined(__BOOT_BLOCK__) + /* No LZMA in boot block. */ #else # define CBFS_CORE_WITH_LZMA # include <lib.h> diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 3887e7e..7609410 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -42,9 +42,6 @@ #define EXYNOS5_CLOCK_BASE 0x10010000 -/* TODO Move to Makefile.inc once we support adding bootblock stage files. */ -#include "cpu/samsung/exynos5-common/spi.c" - void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) { struct exynos5_clock *clk =

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New patch to review for coreboot: 2641490 exynos5250: remove CPU check from samsung_get_base_* macro
by David Hendricks 03 Feb '13

03 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2264 -gerrit commit 2641490cfd9edab12ae35b2c3e36c11b31828949 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Feb 2 20:19:58 2013 -0800 exynos5250: remove CPU check from samsung_get_base_* macro The cpu_is_exynos5() macro seems broken at the moment, so skip it. The macro is superfluous and will probably be replaced eventually, but at least this will un-break usage sites. Change-Id: Ibd360cbfa18047ad8a3488d4f24c3fc4d7415eba Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/cpu.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h index f399a42..b859823 100644 --- a/src/cpu/samsung/exynos5250/cpu.h +++ b/src/cpu/samsung/exynos5250/cpu.h @@ -81,11 +81,19 @@ #ifndef __ASSEMBLER__ +/* FIXME(dhendrix): cpu_is_exynos5() seems broken atm... */ +#if 0 #define SAMSUNG_BASE(device, base) \ static inline unsigned int samsung_get_base_##device(void) \ { \ return cpu_is_exynos5() ? EXYNOS5_##base : 0; \ } +#endif +#define SAMSUNG_BASE(device, base) \ +static inline unsigned int samsung_get_base_##device(void) \ +{ \ + return EXYNOS5_##base; \ +} SAMSUNG_BASE(adc, ADC_BASE) SAMSUNG_BASE(clock, CLOCK_BASE)

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Re: [coreboot] [ANN]Another Tiano payload project
by Patrick Georgi 02 Feb '13

02 Feb '13

Am 02.02.2013 21:17, schrieb ron minnich: > It's not a real EFI unless it can brick your machine, right? I'll add brick mode when everything else works (in fact, probably earlier: As soon as fault tolerant variables are in while flash write protection is incomplete). I know it's your most desired feature, but let's get the basic work done first. Patrick

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[ANN]Another Tiano payload project
by Patrick Georgi 02 Feb '13

02 Feb '13

Hi all, after Stefan pushed out his effort at a Tiano payload, and I got a couple of deadlines behind me, I thought it might be a nice project to implement my concept of a Tiano payload. The result as of now can be found on https://github.com/pgeorgi/edk2/commit/d53b201dcaf2257c0c3f7827cab9d83f05a9… It's branched of edk2 as of today and builds an image that can be added to coreboot as a payload using some magic incantations which are detailed in the commit message I linked to. Since I'm lazy, I just copy it over, since it explains the status of this port, too: Got corebootPkg to boot It reuses more Ovmf libraries than is good for its health or mine, it has no idea about coreboot and its tables yet. It can't store "fault tolerant" (ie. non-volatile) variables. The entry point is still 0x64 bytes off for unknown reasons, but that luckily doesn't matter since 0x32 times 0x00 0x00 are just the right instruction for x86 to survive. It's half blind since I have no GOP driver - serial console works. In short, it has tons of warts. Tons of places that can be improved. Many things left to do. But it boots into EFI Shell. Let's ship it. build instructions Tiano side: . edksetup.sh build -a IA32 -p corebootPkg/corebootPkgIa32.dsc build instructions coreboot side: build emulator/qemu-x86 image with 2MB and no payload cbfstool coreboot.rom add-flat-binary \ -f edk2/Build/corebootIa32/DEBUG_UNIXGCC/FV/COREBOOT.fd \ -n fallback/payload -l 0x800000 -e 0x800400 -c lzma 0x800000 is the location (see corebootPkgIa32.fdf) 0x800400 is the entry point (you have to believe me on that one) Regards, Patrick

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Coreboot Seabios's Makefile.inc build issue.
by Denis 'GNUtoo' Carikli 02 Feb '13

02 Feb '13

Hi, When building SeaBIOS from 1.7.1 coreboot builds correctly. But when I try master it fails this way: make[2]: *** No rule to make target `out/misc.o', needed by `/home/gnutoo/x86/coreboot/build/seabios/out/ccode32flat.o'. Stop. I've tried a lot of combinaisons in the Makefile.inc that is in payloads/external/SeaBIOS but I didn't succeed at fixing it. I also lack the time to fix it right now, and that issue has been there for a long time... However running the following command in coreboot's topdir make it succeed: make -C build/seabios Then a normal make finishes to compiles coreboot. Denis.

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New patch to review for coreboot: a95b5ab PIANO: Add FV debug utility
by Stefan Reinauer 01 Feb '13

01 Feb '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2262 -gerrit commit a95b5ab4be61f59479f6d0644e1268a4d2d88074 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Feb 1 13:19:47 2013 -0800 PIANO: Add FV debug utility This small tool prints information about an UEFI FV file. Sample output: Firmware Volume Dump Copyright (C) 2013 Google Inc. All rights reserved. Found UEFI firmware volume. GUID: 8c8ce578-8a3d-4f1c-9935-896185c32dd3 length: 0x00000000000ec000 00000048 - 9e21fd93-9c72-4c15-8c4b-e77f1db2d792 firmware volume image (708492 bytes) Found UEFI firmware volume. GUID: 8c8ce578-8a3d-4f1c-9935-896185c32dd3 length: 0x0000000000014000 00000048 - df1ccef6-f301-4a63-9661-fc6030dcc880 security core (24156 bytes) 00005ea8 - ffffffff-ffff-ffff-ffff-ffffffffffff FFS pad (57176 bytes) 00013e00 - 1ba0062e-c779-4582-8566-336ae8f78f09 raw (512 bytes) Change-Id: I2066dc0db911321edb2e673c1d0017a2b3f13b2d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/tianocoreboot/Makefile | 6 +- payloads/tianocoreboot/dumpfv.c | 184 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 189 insertions(+), 1 deletion(-) diff --git a/payloads/tianocoreboot/Makefile b/payloads/tianocoreboot/Makefile index 0d51af2..e82aa97 100644 --- a/payloads/tianocoreboot/Makefile +++ b/payloads/tianocoreboot/Makefile @@ -73,8 +73,12 @@ endif prepare: $(Q)mkdir -p $(obj) +dumpfv: dumpfv.c + $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" + $(Q)$(CC) dumpfv.c -o dumpfv -I include + clean: - $(Q)rm -rf $(obj) $(LIBPAYLOAD_DIR) .xcompile .config .config.old + $(Q)rm -rf $(obj) $(LIBPAYLOAD_DIR) .xcompile .config .config.old dumpfv .PHONY: $(PHONY) clean diff --git a/payloads/tianocoreboot/dumpfv.c b/payloads/tianocoreboot/dumpfv.c new file mode 100644 index 0000000..6399d7d --- /dev/null +++ b/payloads/tianocoreboot/dumpfv.c @@ -0,0 +1,184 @@ +/* + * This file is part of the TianoCoreBoot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <fcntl.h> +#include <errno.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <unistd.h> +#include <efi.h> + +#undef VERBOSE +#define INVENTORY + +static void print_guid(EFI_GUID *guid) +{ + printf("%08x-%04x-%04x-%02x%02x-%02x%02x%02x%02x%02x%02x", + guid->Data1, guid->Data2, guid->Data3, + guid->Data4[0], guid->Data4[1], guid->Data4[2], guid->Data4[3], + guid->Data4[4], guid->Data4[5], guid->Data4[6], guid->Data4[7]); +} + +static void dump_uefi_firmware_volume_header(EFI_FIRMWARE_VOLUME_HEADER *fvh) +{ + printf("Found UEFI firmware volume.\n"); + printf(" GUID: "); + print_guid(&(fvh->FileSystemGuid)); + printf("\n"); + printf(" length: 0x%016llx\n", (unsigned long long)fvh->FvLength); +#ifdef VERBOSE + printf(" signature: 0x%08x\n", fvh->Signature); + printf(" attributes: 0x%08x\n", fvh->Attributes); + printf(" header length: 0x%04x\n", fvh->HeaderLength); + printf(" checksum: 0x%04x\n", fvh->Checksum); + printf(" revision: 0x%02x\n", fvh->Revision); + printf(" block map:\n"); + int i = 0; + EFI_FV_BLOCK_MAP_ENTRY *fbm = &(fvh->FvBlockMap[0]); + while (fbm[i].NumBlocks || fbm[i].BlockLength) { + printf(" %2d. numblocks = 0x%08x length = 0x%08x\n", + i+1, fbm[i].NumBlocks, fbm[i].BlockLength); + i++; + } +#endif + printf("\n"); +} + +#ifdef INVENTORY +static void dump_uefi_ffs_file_header(EFI_FFS_FILE_HEADER *file) +{ + int size; + +#ifdef VERBOSE + printf("Found FFS file:\n GUID: "); +#endif + print_guid(&(file->Name)); +#ifdef VERBOSE + printf("\n integrity check: %02x %02x\n", + file->IntegrityCheck.Checksum.Header, + file->IntegrityCheck.Checksum.File); + printf(" file type: "); +#else + printf(" "); +#endif + switch (file->Type) { + case EFI_FV_FILETYPE_RAW: printf("raw"); break; + case EFI_FV_FILETYPE_FREEFORM: printf("free form"); break; + case EFI_FV_FILETYPE_SECURITY_CORE: printf("security core"); break; + case EFI_FV_FILETYPE_PEI_CORE: printf("PEIM core"); break; + case EFI_FV_FILETYPE_DXE_CORE: printf("DXE core"); break; + case EFI_FV_FILETYPE_PEIM: printf("PEIM"); break; + case EFI_FV_FILETYPE_DRIVER: printf("driver"); break; + case EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER: printf("combined PEIM driver"); break; + case EFI_FV_FILETYPE_APPLICATION: printf("application"); break; + case EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE: printf("firmware volume image"); break; + case EFI_FV_FILETYPE_FFS_PAD: printf("FFS pad"); break; + default: printf("unknown"); + } +#ifdef VERBOSE + printf("\n"); + printf(" attributes: 0x%02x\n", file->Attributes); +#endif + size = file->Size[0] | (file->Size[1] << 8) | (file->Size[2] << 16); +#ifdef VERBOSE + printf(" size: 0x%06x\n", size); + printf(" state: 0x%02x\n", file->State); +#else + printf(" (%d bytes)\n", size); +#endif +} +#endif + +int main(int argc, char **argv) +{ + int i; + void *tiano; + EFI_FIRMWARE_VOLUME_HEADER *fvh = NULL; + EFI_PEI_HOB_POINTERS hoblist; + EFI_COMMON_SECTION_HEADER *dxecore = NULL; + + printf("Firmware Volume Dump\n"); + printf("Copyright (C) 2013 Google Inc. All rights reserved.\n\n"); + + char *filename = argv[1]; + + /* Find UEFI firmware volume in CBFS */ + int file = open(filename, O_RDONLY); + if (file == -1) { + printf("Could not open %s: %s\n", filename, strerror(errno)); + exit(1); + } + + struct stat buf; + fstat(file, &buf); + + tiano = malloc(buf.st_size); + + read(file, tiano, buf.st_size); + + void *current = tiano; + + while (current < tiano + buf.st_size) { + /* Verify UEFI firmware volume consistency */ + fvh = (EFI_FIRMWARE_VOLUME_HEADER *)current; + if (fvh->Signature != 0x4856465f) { + printf("Not an UEFI firmware volume at %lx.\n", + (unsigned long)current - (unsigned long)tiano); + exit(1); + } + + /* Dump UEFI firmware volume header */ + dump_uefi_firmware_volume_header(fvh); + + /* Dump UEFI firmware file headers */ + for (i = fvh->HeaderLength; i < fvh->FvLength;) { + int size; + EFI_FFS_FILE_HEADER *ffs; + + ffs = (EFI_FFS_FILE_HEADER *)(current + i); + + size = ffs->Size[0] | (ffs->Size[1] << 8) | (ffs->Size[2] << 16); + if (size == 0xffffff) + break; +#ifdef INVENTORY + printf("%08x - ", i); + dump_uefi_ffs_file_header(ffs); +#endif + + if (ffs->Type == EFI_FV_FILETYPE_DXE_CORE) { + dxecore = (EFI_COMMON_SECTION_HEADER *)&ffs[1]; +#ifndef INVENTORY + break; +#endif + } + + i = ALIGN(i + size, 8); + } + + current += fvh->FvLength; +#ifdef INVENTORY + printf("\n"); +#endif + } + free(tiano); +} +

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Patch merged into coreboot/master: e876819 Fix libpayload xcompile xgcc path
by gerrit＠coreboot.org 01 Feb '13

01 Feb '13

the following patch was just integrated into master: commit e876819975087654c1d3325928b044acf7f89b20 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Feb 1 10:43:19 2013 -0700 Fix libpayload xcompile xgcc path The libpaylaod xcompile script path to xgcc should look for coreboot/util, not libpayload/util. Change-Id: I565801549cdcdfcf55ecef1b543a982f969f435b Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2261 Tested-by: build bot (Jenkins) Reviewed-by: Steven Sherk <steven.sherk(a)se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Feb 1 18:54:50 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 1 20:11:09 2013, giving +2 See http://review.coreboot.org/2261 for details. -gerrit

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Patch set updated for coreboot: f824186 Family 15: Update for string portability
by Mike Loptien 01 Feb '13

01 Feb '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2234 -gerrit commit f8241862bc405e35c3a0816e3d6f2ff1e180034d Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Wed Jan 30 14:12:01 2013 -0700 Family 15: Update for string portability Update function messages to be more portable by using the __func__ compiler command instead of hard coded function names. Change-Id: Ie71fec39df5e7703d35d6505dc7d5b55179e2c7e Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/northbridge/amd/agesa/family15/northbridge.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 2ab0e3e..1adf714 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -570,12 +570,12 @@ static void domain_enable_resources(device_t dev) { u32 val; /* Must be called after PCI enumeration and resource allocation */ - printk(BIOS_DEBUG, "\nFam15 - domain_enable_resources: AmdInitMid.\n"); + printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); val = agesawrapper_amdinitmid(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); } - printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); + printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__); }

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Patch set updated for coreboot: 8c710f6 Add MMCONF resource to AMD fam15tn PCI_DOMAIN
by Steven Sherk 01 Feb '13

01 Feb '13

Steven Sherk (steven.sherk(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2260 -gerrit commit 8c710f65d0cd57aacaf8c20f4f748c4e76fa5337 Author: Steven Sherk <steven.sherk(a)se-eng.com> Date: Fri Feb 1 09:22:35 2013 -0700 Add MMCONF resource to AMD fam15tn PCI_DOMAIN In the process of verifying change it was discovered the MMCONF default base address 0xA0000000 was set below mem_top 0xE0000000 and bus number 256 wasn't a relistic number. The Kconfig defaults were changed to mirror fam15 defaults base address 0xF8000000 and bus number 64. Verified changes with boot to OS. This is a port of the following: commit d5c998be99709c92f200b3b08aed2ca3fee2d519 The coreboot resource allocator doesn't respect resources claimed in the APIC_CLUSTER. Move the MMCONF resource to the PCI_DOMAIN to prevent overlap with PCI devices. original-Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com URL - http://review.coreboot.org/#/c/2167/ Change-Id: I47660061538f8889f528b9b880a82645074886a7 Signed-off-by: Steven Sherk <steven.sherk(a)se-eng.com> --- src/northbridge/amd/agesa/family15tn/Kconfig | 4 +-- src/northbridge/amd/agesa/family15tn/northbridge.c | 31 +++++++++++++--------- 2 files changed, 21 insertions(+), 14 deletions(-) diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index b78b01d..5f08593 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -33,10 +33,10 @@ config HW_MEM_HOLE_SIZE_AUTO_INC config MMCONF_BASE_ADDRESS hex - default 0xA0000000 + default 0xF8000000 config MMCONF_BUS_NUMBER int - default 256 + default 64 endif diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index eb63ead..68b6429 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -337,6 +337,19 @@ static void nb_read_resources(device_t dev) amdfam15_link_read_bases(dev, nodeid, link->link_num); } } + + /* + * This MMCONF resource must be reserved in the PCI_DOMAIN. + * It is not honored by the coreboot resource allocator if it is in + * the APIC_CLUSTER. + */ +#if CONFIG_MMCONF_SUPPORT + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +#endif } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) @@ -440,6 +453,12 @@ static void nb_set_resources(device_t dev) assign_resources(bus); } } + + /* Print the MMCONF region if it has been reserved. */ + res = find_resource(dev, 0xc0010058); + if (res) { + report_resource_stored(dev, res, " <mmconfig>"); + } } static void northbridge_init(struct device *dev) @@ -1077,22 +1096,10 @@ static void cpu_bus_noop(device_t dev) static void cpu_bus_read_resources(device_t dev) { -#if CONFIG_MMCONF_SUPPORT - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -#endif } static void cpu_bus_set_resources(device_t dev) { - struct resource *resource = find_resource(dev, 0xc0010058); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } - pci_dev_set_resources(dev); } static struct device_operations cpu_bus_ops = {

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New patch to review for coreboot: 634f38a Fix libpayload xcompile xgcc path
by Marc Jones 01 Feb '13

01 Feb '13

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2261 -gerrit commit 634f38ab57f33ab0ec9dc6a0dd270039161af8cc Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Feb 1 10:43:19 2013 -0700 Fix libpayload xcompile xgcc path The libpaylaod xcompile script path to xgcc should look for coreboot/util, not libpayload/util. Change-Id: I565801549cdcdfcf55ecef1b543a982f969f435b Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- payloads/libpayload/util/xcompile/xcompile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/util/xcompile/xcompile b/payloads/libpayload/util/xcompile/xcompile index fdc5213..c5c9655 100644 --- a/payloads/libpayload/util/xcompile/xcompile +++ b/payloads/libpayload/util/xcompile/xcompile @@ -153,7 +153,7 @@ TARCH_x86="i386" TBFDARCH_x86="i386" TCLIST_x86="i386 x86_64" TWIDTH_x86="32" -XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} +XGCCPATH=${1:-"`pwd`/../../util/crossgcc/xgcc/bin/"} # This loops over all supported architectures. for architecture in $SUPPORTED_ARCHITECTURE; do

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coreboot February 2013