coreboot February 2013

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Patch set updated for coreboot: e912829 exynos/s5p: Add helper function for reading a single MVL3 GPIO
by Ronald G. Minnich 04 Feb '13

04 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2266 -gerrit commit e912829aa3a74deb0a912d9f806619c12ae3d926 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Feb 2 17:02:36 2013 -0800 exynos/s5p: Add helper function for reading a single MVL3 GPIO This adds a helper function to read only a single GPIO which uses 3-state logic. Examples of this typically include board straps which are used to provide mainboard-specific information at the hardware- level, such as board revision or configuration options. This is part of a larger clean-up effort for Snow. We may want to genericise this for other CPUs in the future. Change-Id: Ic44f5e589cda89b419a07eca246847e9ce7dcd8d Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/gpio.h | 9 +++++ src/cpu/samsung/s5p-common/s5p_gpio.c | 70 ++++++++++++++++++++++------------- 2 files changed, 54 insertions(+), 25 deletions(-) diff --git a/src/cpu/samsung/exynos5250/gpio.h b/src/cpu/samsung/exynos5250/gpio.h index 7606262..1214384 100644 --- a/src/cpu/samsung/exynos5250/gpio.h +++ b/src/cpu/samsung/exynos5250/gpio.h @@ -477,6 +477,15 @@ void gpio_set_rate(int gpio, int mode); */ int gpio_decode_number(unsigned gpio_list[], int count); +/* + * similar to gpio_decode_number, but reads only a single GPIO + * + * @param gpio GPIO to read + * @return -1 if the value cannot be determined. Otherwise returns + * the corresponding MVL3 enum value. + */ +int gpio_read_mvl3(unsigned gpio); + void gpio_info(void); #endif /* EXYNOS5250_GPIO_H_ */ diff --git a/src/cpu/samsung/s5p-common/s5p_gpio.c b/src/cpu/samsung/s5p-common/s5p_gpio.c index 50c4519..f09d0a4 100644 --- a/src/cpu/samsung/s5p-common/s5p_gpio.c +++ b/src/cpu/samsung/s5p-common/s5p_gpio.c @@ -21,6 +21,7 @@ /* FIXME(dhendrix): fix this up so it doesn't require a bunch of #ifdefs... */ #include <common.h> //#include <arch/io.h> +#include <gpio.h> #include <arch/gpio.h> #include <console/console.h> #include <cpu/samsung/s5p-common/gpio.h> @@ -414,42 +415,61 @@ int gpio_set_value(unsigned gpio, int value) */ #define GPIO_DELAY_US 5 -/* FIXME(dhendrix): this should probably go to a more generic location */ +int gpio_read_mvl3(unsigned gpio) +{ + int high, low; + enum mvl3 value; + + if (gpio >= GPIO_MAX_PORT) + return -1; + + gpio_direction_input(gpio); + gpio_set_pull(gpio, EXYNOS_GPIO_PULL_UP); + udelay(GPIO_DELAY_US); + high = gpio_get_value(gpio); + gpio_set_pull(gpio, EXYNOS_GPIO_PULL_DOWN); + udelay(GPIO_DELAY_US); + low = gpio_get_value(gpio); + + if (high && low) /* external pullup */ + value = LOGIC_1; + else if (!high && !low) /* external pulldown */ + value = LOGIC_0; + else /* floating */ + value = LOGIC_Z; + + /* + * Check if line is externally pulled high and + * configure the internal pullup to match. For + * floating and pulldowns, the GPIO is already + * configured with an internal pulldown from the + * above test. + */ + if (value == LOGIC_1) + gpio_set_pull(gpio, EXYNOS_GPIO_PULL_UP); + + return value; +} + int gpio_decode_number(unsigned gpio_list[], int count) { int result = 0; int multiplier = 1; - int value, high, low; - int gpio, i; + int gpio, i, value; + enum mvl3 mvl3; for (i = 0; i < count; i++) { gpio = gpio_list[i]; - if (gpio >= GPIO_MAX_PORT) - return -1; - gpio_direction_input(gpio); - gpio_set_pull(gpio, EXYNOS_GPIO_PULL_UP); - udelay(GPIO_DELAY_US); - high = gpio_get_value(gpio); - gpio_set_pull(gpio, EXYNOS_GPIO_PULL_DOWN); - udelay(GPIO_DELAY_US); - low = gpio_get_value(gpio); - if (high && low) /* external pullup */ + mvl3 = gpio_read_mvl3(gpio); + if (mvl3 == LOGIC_1) value = 2; - else if (!high && !low) /* external pulldown */ + else if (mvl3 == LOGIC_0) value = 1; - else /* floating */ + else if (mvl3 == LOGIC_Z) value = 0; - - /* - * Check if line is externally pulled high and - * configure the internal pullup to match. For - * floating and pulldowns, the GPIO is already - * configured with an internal pulldown from the - * above test. - */ - if (value == 2) - gpio_set_pull(gpio, EXYNOS_GPIO_PULL_UP); + else + return -1; result += value * multiplier; multiplier *= 3;

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Patch merged into coreboot/master: d58ba2a add gpio.h for generic GPIO-related definitions
by gerrit＠coreboot.org 04 Feb '13

04 Feb '13

the following patch was just integrated into master: commit d58ba2add4b0ae955126ca746db39aa9fa98fd9f Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Feb 2 16:57:11 2013 -0800 add gpio.h for generic GPIO-related definitions This adds /src/include/gpio.h which currently contains generic GPIO enums for type (in/out/alt) and 3-state logic. The header was originally written for another FOSS project (code.google.com/p/mosys) and thus the BSD license. Change-Id: Id1dff69169e8b1ec372107737d356b0fa0d80498 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2265 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Feb 4 05:32:34 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Feb 4 05:38:32 2013, giving +2 See http://review.coreboot.org/2265 for details. -gerrit

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Patch set updated for coreboot: 748a6ce exynos/s5p: Add helper function for reading a single MVL3 GPIO
by David Hendricks 04 Feb '13

04 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2266 -gerrit commit 748a6ce14de0f79448b83d2f472acde106183e63 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Feb 2 17:02:36 2013 -0800 exynos/s5p: Add helper function for reading a single MVL3 GPIO This adds a helper function to read only a single GPIO which uses 3-state logic. Examples of this typically include board straps which are used to provide mainboard-specific information at the hardware- level, such as board revision or configuration options. This is part of a larger clean-up effort for Snow. We may want to genericise this for other CPUs in the future. Change-Id: Ic44f5e589cda89b419a07eca246847e9ce7dcd8d Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/gpio.h | 9 +++++ src/cpu/samsung/s5p-common/s5p_gpio.c | 70 ++++++++++++++++++++++------------- 2 files changed, 54 insertions(+), 25 deletions(-) diff --git a/src/cpu/samsung/exynos5250/gpio.h b/src/cpu/samsung/exynos5250/gpio.h index 7606262..1214384 100644 --- a/src/cpu/samsung/exynos5250/gpio.h +++ b/src/cpu/samsung/exynos5250/gpio.h @@ -477,6 +477,15 @@ void gpio_set_rate(int gpio, int mode); */ int gpio_decode_number(unsigned gpio_list[], int count); +/* + * similar to gpio_decode_number, but reads only a single GPIO + * + * @param gpio GPIO to read + * @return -1 if the value cannot be determined. Otherwise returns + * the corresponding MVL3 enum value. + */ +int gpio_read_mvl3(unsigned gpio); + void gpio_info(void); #endif /* EXYNOS5250_GPIO_H_ */ diff --git a/src/cpu/samsung/s5p-common/s5p_gpio.c b/src/cpu/samsung/s5p-common/s5p_gpio.c index 50c4519..f09d0a4 100644 --- a/src/cpu/samsung/s5p-common/s5p_gpio.c +++ b/src/cpu/samsung/s5p-common/s5p_gpio.c @@ -21,6 +21,7 @@ /* FIXME(dhendrix): fix this up so it doesn't require a bunch of #ifdefs... */ #include <common.h> //#include <arch/io.h> +#include <gpio.h> #include <arch/gpio.h> #include <console/console.h> #include <cpu/samsung/s5p-common/gpio.h> @@ -414,42 +415,61 @@ int gpio_set_value(unsigned gpio, int value) */ #define GPIO_DELAY_US 5 -/* FIXME(dhendrix): this should probably go to a more generic location */ +int gpio_read_mvl3(unsigned gpio) +{ + int high, low; + enum mvl3 value; + + if (gpio >= GPIO_MAX_PORT) + return -1; + + gpio_direction_input(gpio); + gpio_set_pull(gpio, EXYNOS_GPIO_PULL_UP); + udelay(GPIO_DELAY_US); + high = gpio_get_value(gpio); + gpio_set_pull(gpio, EXYNOS_GPIO_PULL_DOWN); + udelay(GPIO_DELAY_US); + low = gpio_get_value(gpio); + + if (high && low) /* external pullup */ + value = LOGIC_1; + else if (!high && !low) /* external pulldown */ + value = LOGIC_0; + else /* floating */ + value = LOGIC_Z; + + /* + * Check if line is externally pulled high and + * configure the internal pullup to match. For + * floating and pulldowns, the GPIO is already + * configured with an internal pulldown from the + * above test. + */ + if (value == LOGIC_1) + gpio_set_pull(gpio, EXYNOS_GPIO_PULL_UP); + + return value; +} + int gpio_decode_number(unsigned gpio_list[], int count) { int result = 0; int multiplier = 1; - int value, high, low; - int gpio, i; + int gpio, i, value; + enum mvl3 mvl3; for (i = 0; i < count; i++) { gpio = gpio_list[i]; - if (gpio >= GPIO_MAX_PORT) - return -1; - gpio_direction_input(gpio); - gpio_set_pull(gpio, EXYNOS_GPIO_PULL_UP); - udelay(GPIO_DELAY_US); - high = gpio_get_value(gpio); - gpio_set_pull(gpio, EXYNOS_GPIO_PULL_DOWN); - udelay(GPIO_DELAY_US); - low = gpio_get_value(gpio); - if (high && low) /* external pullup */ + mvl3 = gpio_read_mvl3(gpio); + if (mvl3 == LOGIC_1) value = 2; - else if (!high && !low) /* external pulldown */ + else if (mvl3 == LOGIC_0) value = 1; - else /* floating */ + else if (mvl3 == LOGIC_Z) value = 0; - - /* - * Check if line is externally pulled high and - * configure the internal pullup to match. For - * floating and pulldowns, the GPIO is already - * configured with an internal pulldown from the - * above test. - */ - if (value == 2) - gpio_set_pull(gpio, EXYNOS_GPIO_PULL_UP); + else + return -1; result += value * multiplier; multiplier *= 3;

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Patch set updated for coreboot: 65c920d add gpio.h for generic GPIO-related definitions
by David Hendricks 04 Feb '13

04 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2265 -gerrit commit 65c920db029e8c09f1e071627c92eb54fd67ee32 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Feb 2 16:57:11 2013 -0800 add gpio.h for generic GPIO-related definitions This adds /src/include/gpio.h which currently contains generic GPIO enums for type (in/out/alt) and 3-state logic. The header was originally written for another FOSS project (code.google.com/p/mosys) and thus the BSD license. Change-Id: Id1dff69169e8b1ec372107737d356b0fa0d80498 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/include/gpio.h | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/src/include/gpio.h b/src/include/gpio.h new file mode 100644 index 0000000..f602b1e --- /dev/null +++ b/src/include/gpio.h @@ -0,0 +1,63 @@ +/* + * Copyright 2012, Google Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Google Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef GPIO_H +#define GPIO_H + +enum gpio_types { + GPIO_IN, + GPIO_OUT, + GPIO_ALT, /* catch-all for alternate functions */ +}; + +/* + * Many-value logic (3 states). This can be used for inputs whereby presence + * of external pull-up or pull-down resistors can be added to overcome internal + * pull-ups/pull-downs and force a single value. + * + * Thus, external pull resistors can force a 0 or 1 and if the value changes + * along with internal pull-up/down enable then the input is floating. + * + * Vpd | Vpu | MVL + * ----------------- + * 0 | 0 | 0 + * ----------------- + * 0 | 1 | Z <-- floating input will follow internal pull up/down + * ----------------- + * 1 | 1 | 1 + */ +enum mvl3 { + LOGIC_0, + LOGIC_1, + LOGIC_Z, /* high impedence / tri-stated / floating */ +}; + +#endif /* GPIO_H */

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Patch set updated for coreboot: 3de55ce add gpio.h for generic GPIO-related definitions
by David Hendricks 04 Feb '13

04 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2265 -gerrit commit 3de55ceee7b39e99105216cc913efcf327aab60d Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Feb 2 16:57:11 2013 -0800 add gpio.h for generic GPIO-related definitions This adds /src/include/gpio.h which currently contains generic GPIO enums for type (in/out/alt) and 3-state logic. The header was originally written for another FOSS project (code.google.com/p/mosys) and thus the BSD license. Change-Id: Id1dff69169e8b1ec372107737d356b0fa0d80498 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/include/gpio.h | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/src/include/gpio.h b/src/include/gpio.h new file mode 100644 index 0000000..8ef6e02 --- /dev/null +++ b/src/include/gpio.h @@ -0,0 +1,62 @@ +/* + * Copyright 2012, Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Google Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef GPIO_H +#define GPIO_H + +enum gpio_types { + GPIO_IN, + GPIO_OUT, + GPIO_ALT, /* catch-all for alternate functions */ +}; + +/* + * Many-value logic (3 states). This can be used for inputs whereby presence + * of external pull-up or pull-down resistors can be added to overcome internal + * pull-ups/pull-downs and force a single value. + * + * Thus, external pull resistors can force a 0 or 1 and if the value changes + * along with internal pull-up/down enable then the input is floating. + * + * Vpd | Vpu | MVL + * ----------------- + * 0 | 0 | 0 + * ----------------- + * 0 | 1 | Z <-- floating input will follow internal pull up/down + * ----------------- + * 1 | 1 | 1 + */ +enum mvl3 { + LOGIC_0, + LOGIC_1, + LOGIC_Z, /* high impedence / tri-stated / floating */ +}; + +#endif /* GPIO_H */

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New patch to review for coreboot: 161de51 exynos/snow: Move core/memory clock-related and board ID code
by David Hendricks 04 Feb '13

04 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2271 -gerrit commit 161de5129e8c77ea1eec94e21dda4c66aaeea45e Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Feb 3 18:09:58 2013 -0800 exynos/snow: Move core/memory clock-related and board ID code This patch moves ARM core and DRAM timing functions around to simplify the dependencies for system_clock_init(). The original code was architected such that the system_clock_init() function called other functions to obtain core and memory timings. Due to the way memory timing information must be obtained on Snow, which entails decoding platform-specific board straps, the bottom- up approach resulted in having the low-level clock init code implicitly depend on board and vendor-specific info: main() ->system_clock_init() -> get_arm_ratios() -> CPU-specific code -> clock_get_mem_timings() -> board_get_revision() -> read GPIOs (3-state logic) -> Decode GPIOs in a vendor-specific manner -> Choose memory timings from module-specific look-up table ...then proceed to init clocks ...come back to main() The new approach gathers all board and vendor-specific info in a more appropriate location and passes it into system_clock_init(): main() -> get_arm_ratios() -> CPU-specific code -> get_mem_timings() -> board_get_config() -> read GPIOs (3-state logic) -> Decode GPIOs in a vendor-specific manner -> Choose memory timings from module-specific look-up table -> system_clock_init() ...back to main() Change-Id: Ie237ebff76fc2d8a4d2f4577a226ac3909e4d4e8 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/clock.c | 113 ++++- src/cpu/samsung/exynos5250/clock_init.c | 753 +------------------------------- src/cpu/samsung/exynos5250/clock_init.h | 103 +---- src/cpu/samsung/exynos5250/dmc.h | 98 +++++ src/cpu/samsung/s5p-common/Makefile.inc | 3 +- src/cpu/samsung/s5p-common/s5p_gpio.c | 1 + src/mainboard/google/snow/Makefile.inc | 6 + src/mainboard/google/snow/bootblock.c | 476 +------------------- src/mainboard/google/snow/mainboard.c | 50 ++- src/mainboard/google/snow/mainboard.h | 38 ++ src/mainboard/google/snow/memory.c | 494 +++++++++++++++++++++ src/mainboard/google/snow/romstage.c | 31 +- 12 files changed, 828 insertions(+), 1338 deletions(-) diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c index 0250d77..fc01387 100644 --- a/src/cpu/samsung/exynos5250/clock.c +++ b/src/cpu/samsung/exynos5250/clock.c @@ -26,17 +26,107 @@ #include <stdlib.h> //#include <fdtdec.h> #include <arch/io.h> -//#include <asm/arch/clock.h> -//#include <asm/arch/clk.h> -#include <cpu/samsung/exynos5-common/clk.h> #include <cpu/samsung/exynos5250/clk.h> +#include <cpu/samsung/exynos5250/clock_init.h> #include <cpu/samsung/exynos5250/cpu.h> -#include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/s5p-common/clk.h> /* input clock of PLL: SMDK5250 has 24MHz input clock */ #define CONFIG_SYS_CLK_FREQ 24000000 +struct arm_clk_ratios arm_clk_ratios[] = { + { + .arm_freq_mhz = 600, + + .apll_mdiv = 0xc8, + .apll_pdiv = 0x4, + .apll_sdiv = 0x1, + + .arm2_ratio = 0x0, + .apll_ratio = 0x1, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x2, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x1, + .arm_ratio = 0x0, + }, { + .arm_freq_mhz = 800, + + .apll_mdiv = 0x64, + .apll_pdiv = 0x3, + .apll_sdiv = 0x0, + + .arm2_ratio = 0x0, + .apll_ratio = 0x1, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x3, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x2, + .arm_ratio = 0x0, + }, { + .arm_freq_mhz = 1000, + + .apll_mdiv = 0x7d, + .apll_pdiv = 0x3, + .apll_sdiv = 0x0, + + .arm2_ratio = 0x0, + .apll_ratio = 0x1, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x4, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x2, + .arm_ratio = 0x0, + }, { + .arm_freq_mhz = 1200, + + .apll_mdiv = 0x96, + .apll_pdiv = 0x3, + .apll_sdiv = 0x0, + + .arm2_ratio = 0x0, + .apll_ratio = 0x3, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x5, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x3, + .arm_ratio = 0x0, + }, { + .arm_freq_mhz = 1400, + + .apll_mdiv = 0xaf, + .apll_pdiv = 0x3, + .apll_sdiv = 0x0, + + .arm2_ratio = 0x0, + .apll_ratio = 0x3, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x6, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x3, + .arm_ratio = 0x0, + }, { + .arm_freq_mhz = 1700, + + .apll_mdiv = 0x1a9, + .apll_pdiv = 0x6, + .apll_sdiv = 0x0, + + .arm2_ratio = 0x0, + .apll_ratio = 0x3, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x6, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x3, + .arm_ratio = 0x0, + } +}; /* src_bit div_bit prediv_bit */ static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { @@ -269,6 +359,21 @@ unsigned long get_arm_clk(void) return armclk; } +struct arm_clk_ratios *get_arm_clk_ratios(void) +{ + struct arm_clk_ratios *arm_ratio; + unsigned long arm_freq = 1700; /* FIXME: use get_arm_clk() */ + int i; + + for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios); + i++, arm_ratio++) { + if (arm_ratio->arm_freq_mhz == arm_freq) + return arm_ratio; + } + + return NULL; +} + /* exynos5: set the mmc clock */ void set_mmc_clk(int dev_index, unsigned int div) { diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index 53bab1a..4f21022 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -29,772 +29,27 @@ #include <console/console.h> -#include <cpu/samsung/exynos5-common/spl.h> +/* FIXME: remove unneeded #includes */ #include <cpu/samsung/exynos5250/clk.h> +#include <cpu/samsung/exynos5250/clock_init.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/dmc.h> #include <cpu/samsung/exynos5250/s5p-dp.h> #include <cpu/samsung/s5p-common/clk.h> -#include "clock_init.h" #include "setup.h" -struct arm_clk_ratios arm_clk_ratios[] = { - { - .arm_freq_mhz = 600, - - .apll_mdiv = 0xc8, - .apll_pdiv = 0x4, - .apll_sdiv = 0x1, - - .arm2_ratio = 0x0, - .apll_ratio = 0x1, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x2, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x1, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 800, - - .apll_mdiv = 0x64, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x1, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x3, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x2, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1000, - - .apll_mdiv = 0x7d, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x1, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x4, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x2, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1200, - - .apll_mdiv = 0x96, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x3, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x5, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x3, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1400, - - .apll_mdiv = 0xaf, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x3, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x6, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x3, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1700, - - .apll_mdiv = 0x1a9, - .apll_pdiv = 0x6, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x3, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x6, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x3, - .arm_ratio = 0x0, - } -}; - -struct mem_timings mem_timings[] = { - { - .mem_manuf = MEM_MANUF_ELPIDA, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 800, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x64, - .bpll_pdiv = 0x3, - .bpll_sdiv = 0x0, - .use_bpll = 0, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010042, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x4, - .phy1_tFS = 0x4, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x7, - .zq_mode_term = 0x1, - .zq_mode_noterm = 0, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_30_OHM, - .gate_leveling_enable = 0, - }, { - .mem_manuf = MEM_MANUF_SAMSUNG, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 800, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x64, - .bpll_pdiv = 0x3, - .bpll_sdiv = 0x0, - .use_bpll = 0, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010000, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x8, - .phy1_tFS = 0x8, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x5, - .zq_mode_term = 0x1, - .zq_mode_noterm = 1, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_40_OHM, - .gate_leveling_enable = 1, - }, - { - .mem_manuf = MEM_MANUF_ELPIDA, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 780, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x82, - .bpll_pdiv = 0x4, - .bpll_sdiv = 0x0, - .use_bpll = 1, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010042, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x4, - .phy1_tFS = 0x4, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x7, - .zq_mode_term = 0x1, - .zq_mode_noterm = 0, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_30_OHM, - .gate_leveling_enable = 0, - }, { - .mem_manuf = MEM_MANUF_SAMSUNG, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 780, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x82, - .bpll_pdiv = 0x4, - .bpll_sdiv = 0x0, - .use_bpll = 1, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010000, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x8, - .phy1_tFS = 0x8, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x5, - .zq_mode_term = 0x1, - .zq_mode_noterm = 1, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_40_OHM, - .gate_leveling_enable = 1, - } -}; - -/** - * Detect what memory is present based on board strappings - * - * Boards have various resistor stuff options that are supposed to match - * which SDRAM is present (and which revision of the board this is). This - * uses the resistor stuff options to figure out what memory manufacturer - * to use for matching in the memory tables. - * - * @return A MEM_MANUF_XXX constant, or -1 if an error occurred. - */ -/* - * FIXME(dhendrix): This unwinds into a mess of board-specific code. The - * board's romstage.c file should detect the memory type and pass in - * appropriate parameters to whatever calls this. - */ -#define BOARD_REV_ELPIDA_MEMORY 3 -#define BOARD_REV_SAMSUNG_MEMORY 4 - -static inline int board_get_revision(void) -{ - /* FIXME: yuck! */ - return BOARD_REV_ELPIDA_MEMORY; -} - -static int autodetect_memory(void) -{ - int board_rev = board_get_revision(); - - if (board_rev == -1) - return -1; - - switch (board_rev) { - case BOARD_REV_SAMSUNG_MEMORY: - return MEM_MANUF_SAMSUNG; - case BOARD_REV_ELPIDA_MEMORY: - return MEM_MANUF_ELPIDA; - } - - return -1; -} - -#ifdef CONFIG_SPL_BUILD - -#define SIGNATURE 0xdeadbeef - -/* Parameters of early board initialization in SPL */ -static struct spl_machine_param machine_param = { - .signature = SIGNATURE, - .version = 1, - .params = "vmubfasirMw", - .size = sizeof(machine_param), - - .mem_iv_size = 0x1f, - .mem_type = DDR_MODE_DDR3, - - /* - * Set uboot_size to 0x100000 bytes. - * - * This is an overly conservative value chosen to accommodate all - * possible U-Boot image. You are advised to set this value to a - * smaller realistic size via scripts that modifies the .machine_param - * section of output U-Boot image. - */ - .uboot_size = 0x100000, - - .boot_source = BOOT_MODE_OM, - .frequency_mhz = 800, - .arm_freq_mhz = 1700, - .serial_base = 0x12c30000, - .i2c_base = 0x12c60000, -// .board_rev_gpios = GPIO_D00 | (GPIO_D01 << 16), - .mem_manuf = MEM_MANUF_SAMSUNG, -// .bad_wake_gpio = GPIO_Y10, -}; - -/** - * Get the required memory type and speed (SPL version). - * - * In SPL we have no device tree, so we use the machine parameters - */ -int clock_get_mem_selection(enum ddr_mode *mem_type, - unsigned *frequency_mhz, unsigned *arm_freq, - enum mem_manuf *mem_manuf) -{ - struct spl_machine_param *params; - - params = &machine_param; - *mem_type = params->mem_type; - *frequency_mhz = params->frequency_mhz; - *arm_freq = params->arm_freq_mhz; - if (params->mem_manuf == MEM_MANUF_AUTODETECT) { - *mem_manuf = autodetect_memory(); - if (*mem_manuf == -1) - return -1; - } else { - *mem_manuf = params->mem_manuf; - } - - return 0; -} - -#else - -static const char *mem_types[DDR_MODE_COUNT] = { - "DDR2", "DDR3", "LPDDR2", "LPDDR3" -}; - -static const char *mem_manufs[MEM_MANUF_COUNT] = { - "autodetect", "Elpida", "Samsung" -}; - -int clock_get_mem_selection(enum ddr_mode *mem_type, - unsigned *frequency_mhz, unsigned *arm_freq, - enum mem_manuf *mem_manuf) -{ - const char *typestr; - int node, i; - - node = fdtdec_next_compatible(gd->fdt_blob, 0, - COMPAT_SAMSUNG_EXYNOS_DMC); - if (node < 0) - die("No memory information available in device tree"); - typestr = fdt_getprop(gd->fdt_blob, node, "mem-type", NULL); - for (i = 0; i < DDR_MODE_COUNT; i++) { - if (!stricmp(typestr, mem_types[i])) - break; - } - if (i == DDR_MODE_COUNT) - die("Invalid memory type in device tree"); - *mem_type = i; - - typestr = fdt_getprop(gd->fdt_blob, node, "mem-manuf", NULL); - for (i = 0; i < MEM_MANUF_COUNT; i++) { - if (!stricmp(typestr, mem_manufs[i])) - break; - } - if (i == MEM_MANUF_COUNT) - die("Invalid memory manufacturer in device tree"); - - if (i == MEM_MANUF_AUTODETECT) { - *mem_manuf = autodetect_memory(); - if (*mem_manuf == -1) - return -1; - } else { - *mem_manuf = i; - } - - *frequency_mhz = fdtdec_get_int(gd->fdt_blob, node, "clock-frequency", - 0); - if (!*frequency_mhz) - die("Invalid memory frequency in device tree"); - - *arm_freq = fdtdec_get_int(gd->fdt_blob, node, "arm-frequency", 0); - /* TODO: Remove all these panics/dies, and just return an error code */ - if (!*arm_freq) - die("Invalid ARM frequency in device tree"); - - return 0; -} - -const char *clock_get_mem_type_name(enum ddr_mode mem_type) -{ - if (mem_type >= 0 && mem_type < DDR_MODE_COUNT) - return mem_types[mem_type]; - - return "<unknown>"; -} - -const char *clock_get_mem_manuf_name(enum mem_manuf mem_manuf) -{ - if (mem_manuf >= 0 && mem_manuf < MEM_MANUF_COUNT) - return mem_manufs[mem_manuf]; - - return "<unknown>"; -} -#endif - -/* Get the ratios for setting ARM clock */ -struct arm_clk_ratios *get_arm_ratios(void); /* FIXME: silence compiler... */ -struct arm_clk_ratios *get_arm_ratios(void) -{ - struct arm_clk_ratios *arm_ratio; - enum ddr_mode mem_type; - enum mem_manuf mem_manuf; - unsigned frequency_mhz, arm_freq; - int i; - - /* TODO(sjg(a)chromium.org): Return NULL and have caller deal with it */ - if (clock_get_mem_selection(&mem_type, &frequency_mhz, - &arm_freq, &mem_manuf)) - ; - for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios); - i++, arm_ratio++) { - if (arm_ratio->arm_freq_mhz == arm_freq) - return arm_ratio; - } - -// die("get_arm_ratios: Failed to find ratio\n"); - return NULL; -} - -struct mem_timings *clock_get_mem_timings(void) -{ - /* FIXME: hard-coded for now */ - return &mem_timings[0]; -#if 0 - struct mem_timings *mem; - enum ddr_mode mem_type; - enum mem_manuf mem_manuf; - unsigned frequency_mhz, arm_freq; - int i; - - if (!clock_get_mem_selection(&mem_type, &frequency_mhz, - &arm_freq, &mem_manuf)) { - for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings); - i++, mem++) { - if (mem->mem_type == mem_type && - mem->frequency_mhz == frequency_mhz && - mem->mem_manuf == mem_manuf) - return mem; - } - } - return NULL; -#endif -} - -void system_clock_init(void) +void system_clock_init(struct mem_timings *mem, + struct arm_clk_ratios *arm_clk_ratio) { struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; struct exynos5_mct_regs *mct_regs = (struct exynos5_mct_regs *)EXYNOS5_MULTI_CORE_TIMER_BASE; - struct mem_timings *mem; - struct arm_clk_ratios *arm_clk_ratio; u32 val, tmp; /* Turn on the MCT as early as possible. */ mct_regs->g_tcon |= (1 << 8); - mem = clock_get_mem_timings(); - arm_clk_ratio = get_arm_ratios(); - clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK); do { val = readl(&clk->mux_stat_cpu); diff --git a/src/cpu/samsung/exynos5250/clock_init.h b/src/cpu/samsung/exynos5250/clock_init.h index 00561a0..3757e7d 100644 --- a/src/cpu/samsung/exynos5250/clock_init.h +++ b/src/cpu/samsung/exynos5250/clock_init.h @@ -25,10 +25,6 @@ #ifndef __EXYNOS_CLOCK_INIT_H #define __EXYNOS_CLOCK_INIT_H -enum { - MEM_TIMINGS_MSR_COUNT = 4, -}; - /* These are the ratio's for configuring ARM clock */ struct arm_clk_ratios { unsigned int arm_freq_mhz; /* Frequency of ARM core in MHz */ @@ -47,104 +43,17 @@ struct arm_clk_ratios { unsigned int arm_ratio; }; -/* These are the memory timings for a particular memory type and speed */ -struct mem_timings { - enum mem_manuf mem_manuf; /* Memory manufacturer */ - enum ddr_mode mem_type; /* Memory type */ - unsigned int frequency_mhz; /* Frequency of memory in MHz */ - - /* Here follow the timing parameters for the selected memory */ - uint8_t apll_mdiv; - uint8_t apll_pdiv; - uint8_t apll_sdiv; - uint8_t mpll_mdiv; - uint8_t mpll_pdiv; - uint8_t mpll_sdiv; - uint8_t cpll_mdiv; - uint8_t cpll_pdiv; - uint8_t cpll_sdiv; - uint8_t gpll_pdiv; - uint16_t gpll_mdiv; - uint8_t gpll_sdiv; - uint8_t epll_mdiv; - uint8_t epll_pdiv; - uint8_t epll_sdiv; - uint8_t vpll_mdiv; - uint8_t vpll_pdiv; - uint8_t vpll_sdiv; - uint8_t bpll_mdiv; - uint8_t bpll_pdiv; - uint8_t bpll_sdiv; - uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */ - uint8_t pclk_cdrex_ratio; - unsigned int direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; - - unsigned int timing_ref; - unsigned int timing_row; - unsigned int timing_data; - unsigned int timing_power; - - /* DQS, DQ, DEBUG offsets */ - unsigned int phy0_dqs; - unsigned int phy1_dqs; - unsigned int phy0_dq; - unsigned int phy1_dq; - uint8_t phy0_tFS; - uint8_t phy1_tFS; - uint8_t phy0_pulld_dqs; - uint8_t phy1_pulld_dqs; - - uint8_t lpddr3_ctrl_phy_reset; - uint8_t ctrl_start_point; - uint8_t ctrl_inc; - uint8_t ctrl_start; - uint8_t ctrl_dll_on; - uint8_t ctrl_ref; - - uint8_t ctrl_force; - uint8_t ctrl_rdlat; - uint8_t ctrl_bstlen; - - uint8_t fp_resync; - uint8_t iv_size; - uint8_t dfi_init_start; - uint8_t aref_en; - - uint8_t rd_fetch; - - uint8_t zq_mode_dds; - uint8_t zq_mode_term; - uint8_t zq_mode_noterm; /* 1 to allow termination disable */ - - unsigned int memcontrol; - unsigned int memconfig; - - unsigned int membaseconfig0; - unsigned int membaseconfig1; - unsigned int prechconfig_tp_cnt; - unsigned int dpwrdn_cyc; - unsigned int dsref_cyc; - unsigned int concontrol; - /* Channel and Chip Selection */ - uint8_t dmc_channels; /* number of memory channels */ - uint8_t chips_per_channel; /* number of chips per channel */ - uint8_t chips_to_configure; /* number of chips to configure */ - uint8_t send_zq_init; /* 1 to send this command */ - unsigned int impedance; /* drive strength impedeance */ - uint8_t gate_leveling_enable; /* check gate leveling is enabled */ -}; - /** - * Get the correct memory timings for our selected memory type and speed. - * - * This function can be called from SPL or the main U-Boot. + * Get the clock ratios for CPU configuration * - * @return pointer to the memory timings that we should use + * @return pointer to the clock ratios that we should use */ -struct mem_timings *clock_get_mem_timings(void); +struct arm_clk_ratios *get_arm_clk_ratios(void); /* * Initialize clock for the device */ -void system_clock_init(void); +struct mem_timings; +void system_clock_init(struct mem_timings *mem, + struct arm_clk_ratios *arm_clk_ratio); #endif diff --git a/src/cpu/samsung/exynos5250/dmc.h b/src/cpu/samsung/exynos5250/dmc.h index 9b1f293..0814c07 100644 --- a/src/cpu/samsung/exynos5250/dmc.h +++ b/src/cpu/samsung/exynos5250/dmc.h @@ -175,6 +175,10 @@ enum mem_manuf { MEM_MANUF_COUNT = 2, // fancy that. }; +enum { + MEM_TIMINGS_MSR_COUNT = 4, +}; + #define DMC_INTERLEAVE_SIZE 0x1f /* CONCONTROL register fields */ @@ -224,5 +228,99 @@ enum mem_manuf { #define PHY_CON42_CTRL_RDLAT_SHIFT 0 #define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT) +/* These are the memory timings for a particular memory type and speed */ +struct mem_timings { + enum mem_manuf mem_manuf; /* Memory manufacturer */ + enum ddr_mode mem_type; /* Memory type */ + unsigned int frequency_mhz; /* Frequency of memory in MHz */ + + /* Here follow the timing parameters for the selected memory */ + uint8_t apll_mdiv; + uint8_t apll_pdiv; + uint8_t apll_sdiv; + uint8_t mpll_mdiv; + uint8_t mpll_pdiv; + uint8_t mpll_sdiv; + uint8_t cpll_mdiv; + uint8_t cpll_pdiv; + uint8_t cpll_sdiv; + uint8_t gpll_pdiv; + uint16_t gpll_mdiv; + uint8_t gpll_sdiv; + uint8_t epll_mdiv; + uint8_t epll_pdiv; + uint8_t epll_sdiv; + uint8_t vpll_mdiv; + uint8_t vpll_pdiv; + uint8_t vpll_sdiv; + uint8_t bpll_mdiv; + uint8_t bpll_pdiv; + uint8_t bpll_sdiv; + uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */ + uint8_t pclk_cdrex_ratio; + unsigned int direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; + + unsigned int timing_ref; + unsigned int timing_row; + unsigned int timing_data; + unsigned int timing_power; + + /* DQS, DQ, DEBUG offsets */ + unsigned int phy0_dqs; + unsigned int phy1_dqs; + unsigned int phy0_dq; + unsigned int phy1_dq; + uint8_t phy0_tFS; + uint8_t phy1_tFS; + uint8_t phy0_pulld_dqs; + uint8_t phy1_pulld_dqs; + + uint8_t lpddr3_ctrl_phy_reset; + uint8_t ctrl_start_point; + uint8_t ctrl_inc; + uint8_t ctrl_start; + uint8_t ctrl_dll_on; + uint8_t ctrl_ref; + + uint8_t ctrl_force; + uint8_t ctrl_rdlat; + uint8_t ctrl_bstlen; + + uint8_t fp_resync; + uint8_t iv_size; + uint8_t dfi_init_start; + uint8_t aref_en; + + uint8_t rd_fetch; + + uint8_t zq_mode_dds; + uint8_t zq_mode_term; + uint8_t zq_mode_noterm; /* 1 to allow termination disable */ + + unsigned int memcontrol; + unsigned int memconfig; + + unsigned int membaseconfig0; + unsigned int membaseconfig1; + unsigned int prechconfig_tp_cnt; + unsigned int dpwrdn_cyc; + unsigned int dsref_cyc; + unsigned int concontrol; + /* Channel and Chip Selection */ + uint8_t dmc_channels; /* number of memory channels */ + uint8_t chips_per_channel; /* number of chips per channel */ + uint8_t chips_to_configure; /* number of chips to configure */ + uint8_t send_zq_init; /* 1 to send this command */ + unsigned int impedance; /* drive strength impedeance */ + uint8_t gate_leveling_enable; /* check gate leveling is enabled */ +}; + +/** + * Get the correct memory timings for our selected memory type and speed. + * + * @return pointer to the memory timings that we should use + */ +struct mem_timings *get_mem_timings(void); + #endif #endif diff --git a/src/cpu/samsung/s5p-common/Makefile.inc b/src/cpu/samsung/s5p-common/Makefile.inc index df67573..dc5d886 100644 --- a/src/cpu/samsung/s5p-common/Makefile.inc +++ b/src/cpu/samsung/s5p-common/Makefile.inc @@ -1,4 +1,5 @@ -bootblock-y += pwm.c +bootblock-y += pwm.c # needed by timer.c +bootblock-y += s5p_gpio.c bootblock-y += timer.c romstage-y += cpu_info.c diff --git a/src/cpu/samsung/s5p-common/s5p_gpio.c b/src/cpu/samsung/s5p-common/s5p_gpio.c index f09d0a4..0023beb 100644 --- a/src/cpu/samsung/s5p-common/s5p_gpio.c +++ b/src/cpu/samsung/s5p-common/s5p_gpio.c @@ -20,6 +20,7 @@ /* FIXME(dhendrix): fix this up so it doesn't require a bunch of #ifdefs... */ #include <common.h> +#include <gpio.h> //#include <arch/io.h> #include <gpio.h> #include <arch/gpio.h> diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index a43bcbc..130c354 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -17,6 +17,12 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +# needed for system_clock_init() +bootblock-y += mainboard.c +bootblock-y += memory.c + +romstage-y += mainboard.c +romstage-y += memory.c romstage-y += romstage.c # ramstage-y += ec.c diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index fd3c505..0d8ada1 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -42,88 +42,6 @@ #define EXYNOS5_CLOCK_BASE 0x10010000 -struct gpio_info { - unsigned int reg_addr; /* Address of register for this part */ - unsigned int max_gpio; /* Maximum GPIO in this part */ -}; - -static const struct gpio_info gpio_data[EXYNOS_GPIO_NUM_PARTS] = { - { EXYNOS5_GPIO_PART1_BASE, GPIO_MAX_PORT_PART_1 }, - { EXYNOS5_GPIO_PART2_BASE, GPIO_MAX_PORT_PART_2 }, - { EXYNOS5_GPIO_PART3_BASE, GPIO_MAX_PORT_PART_3 }, - { EXYNOS5_GPIO_PART4_BASE, GPIO_MAX_PORT_PART_4 }, - { EXYNOS5_GPIO_PART5_BASE, GPIO_MAX_PORT_PART_5 }, - { EXYNOS5_GPIO_PART6_BASE, GPIO_MAX_PORT }, -}; - -static struct s5p_gpio_bank *gpio_get_bank(unsigned int gpio) -{ - const struct gpio_info *data; - unsigned int upto; - int i; - - for (i = upto = 0, data = gpio_data; i < EXYNOS_GPIO_NUM_PARTS; - i++, upto = data->max_gpio, data++) { - if (gpio < data->max_gpio) { - struct s5p_gpio_bank *bank; - - bank = (struct s5p_gpio_bank *)data->reg_addr; - bank += (gpio - upto) / GPIO_PER_BANK; - return bank; - } - } - -#ifndef CONFIG_SPL_BUILD - assert(gpio < GPIO_MAX_PORT); /* ...which it will not be */ -#endif - return NULL; -} - -#define CON_MASK(x) (0xf << ((x) << 2)) -#define CON_SFR(x, v) ((v) << ((x) << 2)) - -/* This macro gets gpio pin offset from 0..7 */ -#define GPIO_BIT(x) ((x) & 0x7) - -void gpio_cfg_pin(int gpio, int cfg) -{ - unsigned int value; - struct s5p_gpio_bank *bank = gpio_get_bank(gpio); - - value = readl(&bank->con); - value &= ~CON_MASK(GPIO_BIT(gpio)); - value |= CON_SFR(GPIO_BIT(gpio), cfg); - writel(value, &bank->con); -} - -/* Pull mode */ -#define EXYNOS_GPIO_PULL_NONE 0x0 -#define EXYNOS_GPIO_PULL_DOWN 0x1 -#define EXYNOS_GPIO_PULL_UP 0x3 - -#define PULL_MASK(x) (0x3 << ((x) << 1)) -#define PULL_MODE(x, v) ((v) << ((x) << 1)) - -void gpio_set_pull(int gpio, int mode) -{ - unsigned int value; - struct s5p_gpio_bank *bank = gpio_get_bank(gpio); - - value = readl(&bank->pull); - value &= ~PULL_MASK(GPIO_BIT(gpio)); - - switch (mode) { - case EXYNOS_GPIO_PULL_DOWN: - case EXYNOS_GPIO_PULL_UP: - value |= PULL_MODE(GPIO_BIT(gpio), mode); - break; - default: - break; - } - - writel(value, &bank->pull); -} - static uint32_t uart3_base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; #define CONFIG_SYS_CLK_FREQ 24000000 @@ -959,393 +877,6 @@ static void power_init(void) REG_ENABLE, MAX77686_MV); } -/* FIXME(dhendrix): this will be removed in a follow-up patch */ -struct mem_timings my_mem_timings[] = { - { - .mem_manuf = MEM_MANUF_ELPIDA, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 800, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x64, - .bpll_pdiv = 0x3, - .bpll_sdiv = 0x0, - .use_bpll = 0, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010042, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x4, - .phy1_tFS = 0x4, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x7, - .zq_mode_term = 0x1, - .zq_mode_noterm = 0, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_30_OHM, - .gate_leveling_enable = 0, - }, -}; - -/* FIXME(dhendrix): this will be removed in a follow-up patch */ -struct arm_clk_ratios my_arm_clk_ratios[] = { - { - .arm_freq_mhz = 1700, - - .apll_mdiv = 0x1a9, - .apll_pdiv = 0x6, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x3, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x6, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x3, - .arm_ratio = 0x0, - } -}; - -static void clock_init(void) -{ - struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; - struct exynos5_mct_regs *mct_regs = - (struct exynos5_mct_regs *)EXYNOS5_MULTI_CORE_TIMER_BASE; - struct mem_timings *mem = &my_mem_timings[0]; - struct arm_clk_ratios *arm_clk_ratio = &my_arm_clk_ratios[0]; - u32 val, tmp; - - /* Turn on the MCT as early as possible. */ - mct_regs->g_tcon |= (1 << 8); - -// mem = clock_get_mem_timings(); -// arm_clk_ratio = get_arm_ratios(); - - clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK); - do { - val = readl(&clk->mux_stat_cpu); - } while ((val | MUX_APLL_SEL_MASK) != val); - - clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK); - do { - val = readl(&clk->mux_stat_core1); - } while ((val | MUX_MPLL_SEL_MASK) != val); - - clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK); - clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK); - clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK); - clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK); - tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK - | MUX_GPLL_SEL_MASK; - do { - val = readl(&clk->mux_stat_top2); - } while ((val | tmp) != val); - - clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK); - do { - val = readl(&clk->mux_stat_cdrex); - } while ((val | MUX_BPLL_SEL_MASK) != val); - - /* PLL locktime */ - writel(APLL_LOCK_VAL, &clk->apll_lock); - - writel(MPLL_LOCK_VAL, &clk->mpll_lock); - - writel(BPLL_LOCK_VAL, &clk->bpll_lock); - - writel(CPLL_LOCK_VAL, &clk->cpll_lock); - - writel(GPLL_LOCK_VAL, &clk->gpll_lock); - - writel(EPLL_LOCK_VAL, &clk->epll_lock); - - writel(VPLL_LOCK_VAL, &clk->vpll_lock); - - writel(CLK_REG_DISABLE, &clk->pll_div2_sel); - - writel(MUX_HPM_SEL_MASK, &clk->src_cpu); - do { - val = readl(&clk->mux_stat_cpu); - } while ((val | HPM_SEL_SCLK_MPLL) != val); - - val = arm_clk_ratio->arm2_ratio << 28 - | arm_clk_ratio->apll_ratio << 24 - | arm_clk_ratio->pclk_dbg_ratio << 20 - | arm_clk_ratio->atb_ratio << 16 - | arm_clk_ratio->periph_ratio << 12 - | arm_clk_ratio->acp_ratio << 8 - | arm_clk_ratio->cpud_ratio << 4 - | arm_clk_ratio->arm_ratio; - writel(val, &clk->div_cpu0); - do { - val = readl(&clk->div_stat_cpu0); - } while (0 != val); - - writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); - do { - val = readl(&clk->div_stat_cpu1); - } while (0 != val); - - /* Set APLL */ - writel(APLL_CON1_VAL, &clk->apll_con1); - val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, - arm_clk_ratio->apll_sdiv); - writel(val, &clk->apll_con0); - while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0) - ; - - /* Set MPLL */ - writel(MPLL_CON1_VAL, &clk->mpll_con1); - val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); - writel(val, &clk->mpll_con0); - while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0) - ; - - /* - * Configure MUX_MPLL_FOUT to choose the direct clock source - * path and avoid the fixed DIV/2 block to save power - */ - setbits_le32(&clk->pll_div2_sel, MUX_MPLL_FOUT_SEL); - - /* Set BPLL */ - if (mem->use_bpll) { - writel(BPLL_CON1_VAL, &clk->bpll_con1); - val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); - writel(val, &clk->bpll_con0); - while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0) - ; - - setbits_le32(&clk->pll_div2_sel, MUX_BPLL_FOUT_SEL); - } - - /* Set CPLL */ - writel(CPLL_CON1_VAL, &clk->cpll_con1); - val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); - writel(val, &clk->cpll_con0); - while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0) - ; - - /* Set GPLL */ - writel(GPLL_CON1_VAL, &clk->gpll_con1); - val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); - writel(val, &clk->gpll_con0); - while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0) - ; - - /* Set EPLL */ - writel(EPLL_CON2_VAL, &clk->epll_con2); - writel(EPLL_CON1_VAL, &clk->epll_con1); - val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); - writel(val, &clk->epll_con0); - while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0) - ; - - /* Set VPLL */ - writel(VPLL_CON2_VAL, &clk->vpll_con2); - writel(VPLL_CON1_VAL, &clk->vpll_con1); - val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); - writel(val, &clk->vpll_con0); - while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0) - ; - - writel(CLK_SRC_CORE0_VAL, &clk->src_core0); - writel(CLK_DIV_CORE0_VAL, &clk->div_core0); - while (readl(&clk->div_stat_core0) != 0) - ; - - writel(CLK_DIV_CORE1_VAL, &clk->div_core1); - while (readl(&clk->div_stat_core1) != 0) - ; - - writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt); - while (readl(&clk->div_stat_sysrgt) != 0) - ; - - writel(CLK_DIV_ACP_VAL, &clk->div_acp); - while (readl(&clk->div_stat_acp) != 0) - ; - - writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft); - while (readl(&clk->div_stat_syslft) != 0) - ; - - writel(CLK_SRC_TOP0_VAL, &clk->src_top0); - writel(CLK_SRC_TOP1_VAL, &clk->src_top1); - writel(TOP2_VAL, &clk->src_top2); - writel(CLK_SRC_TOP3_VAL, &clk->src_top3); - - writel(CLK_DIV_TOP0_VAL, &clk->div_top0); - while (readl(&clk->div_stat_top0)) - ; - - writel(CLK_DIV_TOP1_VAL, &clk->div_top1); - while (readl(&clk->div_stat_top1)) - ; - - writel(CLK_SRC_LEX_VAL, &clk->src_lex); - while (1) { - val = readl(&clk->mux_stat_lex); - if (val == (val | 1)) - break; - } - - writel(CLK_DIV_LEX_VAL, &clk->div_lex); - while (readl(&clk->div_stat_lex)) - ; - - writel(CLK_DIV_R0X_VAL, &clk->div_r0x); - while (readl(&clk->div_stat_r0x)) - ; - - writel(CLK_DIV_R0X_VAL, &clk->div_r0x); - while (readl(&clk->div_stat_r0x)) - ; - - writel(CLK_DIV_R1X_VAL, &clk->div_r1x); - while (readl(&clk->div_stat_r1x)) - ; - - if (mem->use_bpll) { - writel(MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL | - MUX_MCLK_DPHY_SEL, &clk->src_cdrex); - } else { - writel(CLK_REG_DISABLE, &clk->src_cdrex); - } - - writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex); - while (readl(&clk->div_stat_cdrex)) - ; - - val = readl(&clk->src_cpu); - val |= CLK_SRC_CPU_VAL; - writel(val, &clk->src_cpu); - - val = readl(&clk->src_top2); - val |= CLK_SRC_TOP2_VAL; - writel(val, &clk->src_top2); - - val = readl(&clk->src_core1); - val |= CLK_SRC_CORE1_VAL; - writel(val, &clk->src_core1); - - writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys); - writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); - while (readl(&clk->div_stat_fsys0)) - ; - - writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_core); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_top); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex); - - writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); - writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); - - writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1); - writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1); - writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2); - writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp); - writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp); - writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); - writel(CLK_DIV_ISP1_VAL, &clk->div_isp1); - writel(CLK_DIV_ISP2_VAL, &clk->div_isp2); - - /* FIMD1 SRC CLK SELECTION */ - writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0); - - val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET - | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET - | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET - | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET; - writel(val, &clk->div_fsys2); -} - #include <console/vtxprintf.h> #include <string.h> #define ZEROPAD 1 /* pad with zero */ @@ -1639,11 +1170,16 @@ int do_printk(int msg_level, const char *fmt, ...) void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { + struct mem_timings *mem; + struct arm_clk_ratios *arm_ratios; + /* FIXME: we should not need UART in bootblock, this is only done for testing purposes */ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); power_init(); - clock_init(); + mem = get_mem_timings(); + arm_ratios = get_arm_clk_ratios(); + system_clock_init(mem, arm_ratios); do_serial(); printk(BIOS_INFO, "%s: UART initialized\n", __func__); diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index f11f1fa..ffab520 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -17,18 +17,60 @@ * MA 02111-1307 USA */ +#include <stdlib.h> +#include <gpio.h> #include <device/device.h> #include <console/console.h> -// mainboard_enable is executed as first thing after -// enumerate_buses(). +#include <cpu/samsung/exynos5-common/gpio.h> +#include <cpu/samsung/exynos5250/gpio.h> -static void mainboard_enable(device_t dev) +#include "mainboard.h" + +#define SNOW_BOARD_ID0_GPIO 88 /* GPD0, pin 0 */ +#define SNOW_BOARD_ID1_GPIO 89 /* GPD0, pin 1 */ + +struct { + enum mvl3 id0, id1; + enum snow_board_config config; +} snow_id_map[] = { + /* ID0 ID1 config */ + { LOGIC_0, LOGIC_0, SNOW_CONFIG_SAMSUNG_MP }, + { LOGIC_0, LOGIC_1, SNOW_CONFIG_ELPIDA_MP }, + { LOGIC_1, LOGIC_0, SNOW_CONFIG_SAMSUNG_DVT }, + { LOGIC_1, LOGIC_1, SNOW_CONFIG_ELPIDA_DVT }, + { LOGIC_0, LOGIC_Z, SNOW_CONFIG_SAMSUNG_PVT }, + { LOGIC_1, LOGIC_Z, SNOW_CONFIG_ELPIDA_PVT }, + { LOGIC_Z, LOGIC_0, SNOW_CONFIG_SAMSUNG_MP }, + { LOGIC_Z, LOGIC_Z, SNOW_CONFIG_ELPIDA_MP }, + { LOGIC_Z, LOGIC_1, SNOW_CONFIG_RSVD }, +}; + +int board_get_config(void) { - //dev->ops->init = mainboard_init; + int i; + int id0, id1; + enum snow_board_config config = SNOW_CONFIG_UNKNOWN; + + id0 = gpio_read_mvl3(SNOW_BOARD_ID0_GPIO); + id1 = gpio_read_mvl3(SNOW_BOARD_ID1_GPIO); + if (id0 < 0 || id1 < 0) + return -1; + printk(BIOS_DEBUG, "%s: id0: %u, id1: %u\n", __func__, id0, id1); + + for (i = 0; i < ARRAY_SIZE(snow_id_map); i++) { + if (id0 == snow_id_map[i].id0 && id1 == snow_id_map[i].id1) { + config = snow_id_map[i].config; + break; + } + } + + return config; } +#if 0 struct chip_operations mainboard_ops = { .name = "Samsung/Google ARM ChromeBook", .enable_dev = mainboard_enable, }; +#endif diff --git a/src/mainboard/google/snow/mainboard.h b/src/mainboard/google/snow/mainboard.h new file mode 100644 index 0000000..0047416 --- /dev/null +++ b/src/mainboard/google/snow/mainboard.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2013 The ChromeOS Authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MAINBOARD_H +#define MAINBOARD_H + +enum snow_board_config { + SNOW_CONFIG_UNKNOWN = -1, + SNOW_CONFIG_SAMSUNG_EVT, + SNOW_CONFIG_ELPIDA_EVT, + SNOW_CONFIG_SAMSUNG_DVT, + SNOW_CONFIG_ELPIDA_DVT, + SNOW_CONFIG_SAMSUNG_PVT, + SNOW_CONFIG_ELPIDA_PVT, + SNOW_CONFIG_SAMSUNG_MP, + SNOW_CONFIG_ELPIDA_MP, + SNOW_CONFIG_RSVD, +}; + +int board_get_config(void); + +#endif /* MAINBOARD_H */ diff --git a/src/mainboard/google/snow/memory.c b/src/mainboard/google/snow/memory.c new file mode 100644 index 0000000..ba8c91f --- /dev/null +++ b/src/mainboard/google/snow/memory.c @@ -0,0 +1,494 @@ +/* + * This file is part of the coreboot project. It is based off code + * from Das U-Boot. + * + * Copyright (C) 2012 Samsung Electronics + * Copyright (C) 2013 The ChromiumOS Authors. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <stdlib.h> +#include <console/console.h> + +#include <cpu/samsung/exynos5250/setup.h> +#include <cpu/samsung/exynos5250/dmc.h> +#include <cpu/samsung/exynos5250/clock_init.h> + +#include "mainboard.h" + +struct mem_timings mem_timings[] = { + { + .mem_manuf = MEM_MANUF_ELPIDA, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 800, + .mpll_mdiv = 0x64, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x0, + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x2, + .gpll_mdiv = 0x215, + .gpll_pdiv = 0xc, + .gpll_sdiv = 0x1, + .epll_mdiv = 0x60, + .epll_pdiv = 0x3, + .epll_sdiv = 0x3, + .vpll_mdiv = 0x96, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + + .bpll_mdiv = 0x64, + .bpll_pdiv = 0x3, + .bpll_sdiv = 0x0, + .use_bpll = 0, + .pclk_cdrex_ratio = 0x5, + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010042, 0x00000d70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x8c36660f, + .timing_data = 0x3630580b, + .timing_power = 0x41000a44, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x4, + .phy1_tFS = 0x4, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x7, + .zq_mode_term = 0x1, + .zq_mode_noterm = 0, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_ENABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | + DMC_MEMCONFIGx_CHIP_COL_10 | + DMC_MEMCONFIGx_CHIP_ROW_15 | + DMC_MEMCONFIGx_CHIP_BANK_8, + .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), + .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 2, + .chips_per_channel = 2, + .chips_to_configure = 1, + .send_zq_init = 1, + .impedance = IMP_OUTPUT_DRV_30_OHM, + .gate_leveling_enable = 0, + }, { + .mem_manuf = MEM_MANUF_SAMSUNG, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 800, + .mpll_mdiv = 0x64, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x0, + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x2, + .gpll_mdiv = 0x215, + .gpll_pdiv = 0xc, + .gpll_sdiv = 0x1, + .epll_mdiv = 0x60, + .epll_pdiv = 0x3, + .epll_sdiv = 0x3, + .vpll_mdiv = 0x96, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + + .bpll_mdiv = 0x64, + .bpll_pdiv = 0x3, + .bpll_sdiv = 0x0, + .use_bpll = 0, + .pclk_cdrex_ratio = 0x5, + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010000, 0x00000d70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x8c36660f, + .timing_data = 0x3630580b, + .timing_power = 0x41000a44, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x8, + .phy1_tFS = 0x8, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x5, + .zq_mode_term = 0x1, + .zq_mode_noterm = 1, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_ENABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | + DMC_MEMCONFIGx_CHIP_COL_10 | + DMC_MEMCONFIGx_CHIP_ROW_15 | + DMC_MEMCONFIGx_CHIP_BANK_8, + .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), + .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 2, + .chips_per_channel = 2, + .chips_to_configure = 1, + .send_zq_init = 1, + .impedance = IMP_OUTPUT_DRV_40_OHM, + .gate_leveling_enable = 1, + }, + { + .mem_manuf = MEM_MANUF_ELPIDA, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 780, + .mpll_mdiv = 0x64, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x0, + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x2, + .gpll_mdiv = 0x215, + .gpll_pdiv = 0xc, + .gpll_sdiv = 0x1, + .epll_mdiv = 0x60, + .epll_pdiv = 0x3, + .epll_sdiv = 0x3, + .vpll_mdiv = 0x96, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + + .bpll_mdiv = 0x82, + .bpll_pdiv = 0x4, + .bpll_sdiv = 0x0, + .use_bpll = 1, + .pclk_cdrex_ratio = 0x5, + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010042, 0x00000d70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x8c36660f, + .timing_data = 0x3630580b, + .timing_power = 0x41000a44, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x4, + .phy1_tFS = 0x4, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x7, + .zq_mode_term = 0x1, + .zq_mode_noterm = 0, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_ENABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | + DMC_MEMCONFIGx_CHIP_COL_10 | + DMC_MEMCONFIGx_CHIP_ROW_15 | + DMC_MEMCONFIGx_CHIP_BANK_8, + .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), + .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 2, + .chips_per_channel = 2, + .chips_to_configure = 1, + .send_zq_init = 1, + .impedance = IMP_OUTPUT_DRV_30_OHM, + .gate_leveling_enable = 0, + }, { + .mem_manuf = MEM_MANUF_SAMSUNG, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 780, + .mpll_mdiv = 0x64, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x0, + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x2, + .gpll_mdiv = 0x215, + .gpll_pdiv = 0xc, + .gpll_sdiv = 0x1, + .epll_mdiv = 0x60, + .epll_pdiv = 0x3, + .epll_sdiv = 0x3, + .vpll_mdiv = 0x96, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + + .bpll_mdiv = 0x82, + .bpll_pdiv = 0x4, + .bpll_sdiv = 0x0, + .use_bpll = 1, + .pclk_cdrex_ratio = 0x5, + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010000, 0x00000d70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x8c36660f, + .timing_data = 0x3630580b, + .timing_power = 0x41000a44, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x8, + .phy1_tFS = 0x8, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x5, + .zq_mode_term = 0x1, + .zq_mode_noterm = 1, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_ENABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | + DMC_MEMCONFIGx_CHIP_COL_10 | + DMC_MEMCONFIGx_CHIP_ROW_15 | + DMC_MEMCONFIGx_CHIP_BANK_8, + .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), + .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 2, + .chips_per_channel = 2, + .chips_to_configure = 1, + .send_zq_init = 1, + .impedance = IMP_OUTPUT_DRV_40_OHM, + .gate_leveling_enable = 1, + } +}; + +struct mem_timings *get_mem_timings(void) +{ + int i; + enum snow_board_config board_config; + enum ddr_mode mem_type; + unsigned int frequency_mhz; + enum mem_manuf mem_manuf; + struct mem_timings *mem; + + board_config = board_get_config(); + switch (board_config) { + case SNOW_CONFIG_ELPIDA_EVT: + case SNOW_CONFIG_ELPIDA_DVT: + case SNOW_CONFIG_ELPIDA_PVT: + case SNOW_CONFIG_ELPIDA_MP: + mem_manuf = MEM_MANUF_ELPIDA; + mem_type = DDR_MODE_DDR3; + frequency_mhz = 800; + break; + case SNOW_CONFIG_SAMSUNG_EVT: + case SNOW_CONFIG_SAMSUNG_DVT: + case SNOW_CONFIG_SAMSUNG_PVT: + case SNOW_CONFIG_SAMSUNG_MP: + mem_manuf = MEM_MANUF_SAMSUNG; + mem_type = DDR_MODE_DDR3; + frequency_mhz = 800; + break; + default: + printk(BIOS_CRIT, "Unable to determine board config\n"); + return NULL; + } + + for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings); + i++, mem++) { + if (mem->mem_type == mem_type && + mem->frequency_mhz == frequency_mhz && + mem->mem_manuf == mem_manuf) + return mem; + } + + return NULL; +} diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index fae371a..03fd1be 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -24,13 +24,14 @@ #include <cbfs.h> #include <common.h> -#include <cpu/samsung/exynos5250/setup.h> #include <cpu/samsung/exynos5250/dmc.h> -#include <cpu/samsung/exynos5250/clock_init.h> +#include <cpu/samsung/exynos5250/setup.h> + #include <console/console.h> -#include <arch/bootblock_exit.h> #include <arch/stages.h> +#include "mainboard.h" + void main(void) { struct cbfs_media cbfs; @@ -43,28 +44,31 @@ void main(void) struct mem_timings *mem; int ret; - mem = clock_get_mem_timings(); - printk(BIOS_SPEW, "clock_get_mem_timings returns 0x%p\n", mem); + mem = get_mem_timings(); + if (!mem) { + printk(BIOS_CRIT, "Unable to auto-detect memory timings\n"); + while(1); + } printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", mem->mem_manuf, mem->mem_type, mem->mpll_mdiv, mem->frequency_mhz); - ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE); - if (ret) { - printk(BIOS_ERR, "Memory controller init failed, err: %x\n", - ret); - while(1); - } + ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE); + if (ret) { + printk(BIOS_ERR, "Memory controller init failed, err: %x\n", + ret); + while(1); + } - printk(BIOS_INFO, "ddr3_init done\n"); + printk(BIOS_INFO, "ddr3_init done\n"); /* wow, did it work? */ int i; u32 *c = (void *)CONFIG_RAMBASE; // mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); -// printk(BIOS_INFO, "mmu_setup done\n"); +// printk(BIOS_INFO, "mmu_setup done\n"); for(i = 0; i < 16384; i++) c[i] = i+32768; for(i = 0; i < 16384; i++) @@ -72,6 +76,7 @@ void main(void) printk(BIOS_SPEW, "BADc[%02x]: %02x,", i, c[i]); for(i = 0; i < 1048576; i++) c[i] = 0; + ret = init_default_cbfs_media(&cbfs); if (ret){ printk(BIOS_ERR, "init_default_cbfs_media returned %d: HALT\n",

1 0

New patch to review for coreboot: 642cc26 exynos/snow: partial clean-up of snow bootblock using build class
by David Hendricks 04 Feb '13

04 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2270 -gerrit commit 642cc2692904f5945d82bf7c17d4cc27f63ba11a Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Feb 3 19:13:36 2013 -0800 exynos/snow: partial clean-up of snow bootblock using build class This removes some duplicate code from Snow's mainboard bootblock by utilizing the bootblock build class. Change-Id: I153247370a8c5127260082dcdca3ebdc5e104fb8 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/lib/Makefile.inc | 2 + src/cpu/samsung/exynos5250/Kconfig | 4 +- src/cpu/samsung/exynos5250/Makefile.inc | 6 + src/cpu/samsung/exynos5250/clock_init.c | 36 ++++- src/cpu/samsung/s5p-common/Makefile.inc | 3 + src/cpu/samsung/s5p-common/s5p_gpio.c | 1 + src/mainboard/google/snow/bootblock.c | 277 +------------------------------- 7 files changed, 56 insertions(+), 273 deletions(-) diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 2470db2..e0445ce 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,3 +1,5 @@ +bootblock-y += syslib.c + romstage-y += cache_v7.c romstage-y += cache-cp15.c romstage-y += div0.c diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 41a1446..ec1d7af 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -18,7 +18,7 @@ config SATA_AHCI # # 0x0202_0000: vendor-provided BL1 # 0x0202_3400: bootblock, assume up to 32KB in size -# 0x0202_2600: ID section, assume 2KB in size. This will be +# 0x0202_7000: ID section, assume 2KB in size. This will be # within the bootblock section. # 0x0203_0000: romstage, assume up to 128KB in size. # 0x0207_7f00: stack pointer @@ -38,7 +38,7 @@ config BOOTBLOCK_BASE config ID_SECTION_BASE hex - default 0x02026000 + default 0x02027000 config ROMSTAGE_BASE hex diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 49285e7..3dcf461 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,6 +3,12 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 +# Clock init is done in bootblock to support UART output for +# debugging. We may add a Kconfig option to disable clock init +# in the bootblock and try moving it entirely into romstage. +bootblock-y += clock_init.c +bootblock-y += clock.c + romstage-y += clock.c romstage-y += clock_init.c romstage-y += exynos_cache.c diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index 421d880..53bab1a 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -597,6 +597,38 @@ static int autodetect_memory(void) #ifdef CONFIG_SPL_BUILD +#define SIGNATURE 0xdeadbeef + +/* Parameters of early board initialization in SPL */ +static struct spl_machine_param machine_param = { + .signature = SIGNATURE, + .version = 1, + .params = "vmubfasirMw", + .size = sizeof(machine_param), + + .mem_iv_size = 0x1f, + .mem_type = DDR_MODE_DDR3, + + /* + * Set uboot_size to 0x100000 bytes. + * + * This is an overly conservative value chosen to accommodate all + * possible U-Boot image. You are advised to set this value to a + * smaller realistic size via scripts that modifies the .machine_param + * section of output U-Boot image. + */ + .uboot_size = 0x100000, + + .boot_source = BOOT_MODE_OM, + .frequency_mhz = 800, + .arm_freq_mhz = 1700, + .serial_base = 0x12c30000, + .i2c_base = 0x12c60000, +// .board_rev_gpios = GPIO_D00 | (GPIO_D01 << 16), + .mem_manuf = MEM_MANUF_SAMSUNG, +// .bad_wake_gpio = GPIO_Y10, +}; + /** * Get the required memory type and speed (SPL version). * @@ -608,7 +640,7 @@ int clock_get_mem_selection(enum ddr_mode *mem_type, { struct spl_machine_param *params; - params = spl_get_machine_params(); + params = &machine_param; *mem_type = params->mem_type; *frequency_mhz = params->frequency_mhz; *arm_freq = params->arm_freq_mhz; @@ -719,7 +751,7 @@ struct arm_clk_ratios *get_arm_ratios(void) return arm_ratio; } - die("get_arm_ratios: Failed to find ratio\n"); +// die("get_arm_ratios: Failed to find ratio\n"); return NULL; } diff --git a/src/cpu/samsung/s5p-common/Makefile.inc b/src/cpu/samsung/s5p-common/Makefile.inc index 7de3c28..df67573 100644 --- a/src/cpu/samsung/s5p-common/Makefile.inc +++ b/src/cpu/samsung/s5p-common/Makefile.inc @@ -1,3 +1,6 @@ +bootblock-y += pwm.c +bootblock-y += timer.c + romstage-y += cpu_info.c romstage-y += pwm.c # needed by timer.c romstage-y += s5p_gpio.c diff --git a/src/cpu/samsung/s5p-common/s5p_gpio.c b/src/cpu/samsung/s5p-common/s5p_gpio.c index 8332015..f09d0a4 100644 --- a/src/cpu/samsung/s5p-common/s5p_gpio.c +++ b/src/cpu/samsung/s5p-common/s5p_gpio.c @@ -21,6 +21,7 @@ /* FIXME(dhendrix): fix this up so it doesn't require a bunch of #ifdefs... */ #include <common.h> //#include <arch/io.h> +#include <gpio.h> #include <arch/gpio.h> #include <console/console.h> #include <cpu/samsung/s5p-common/gpio.h> diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 7609410..fd3c505 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -42,112 +42,6 @@ #define EXYNOS5_CLOCK_BASE 0x10010000 -void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; - unsigned shift; - unsigned mask = 0xff; - u32 *reg; - - reg = &clk->div_peric1; - shift = 24; - clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); -} - -void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; - unsigned shift; - unsigned mask = 0xff; - u32 *reg; - - reg = &clk->div_peric1; - shift = 16; - clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); -} - -/** - * Linearly searches for the most accurate main and fine stage clock scalars - * (divisors) for a specified target frequency and scalar bit sizes by checking - * all multiples of main_scalar_bits values. Will always return scalars up to or - * slower than target. - * - * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32 - * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32 - * @param input_freq Clock frequency to be scaled in Hz - * @param target_freq Desired clock frequency in Hz - * @param best_fine_scalar Pointer to store the fine stage divisor - * - * @return best_main_scalar Main scalar for desired frequency or -1 if none - * found - */ -static int clock_calc_best_scalar(unsigned int main_scaler_bits, - unsigned int fine_scalar_bits, unsigned int input_rate, - unsigned int target_rate, unsigned int *best_fine_scalar) -{ - int i; - int best_main_scalar = -1; - unsigned int best_error = target_rate; - const unsigned int cap = (1 << fine_scalar_bits) - 1; - const unsigned int loops = 1 << main_scaler_bits; - -#if 0 - debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate, - target_rate, cap); - - assert(best_fine_scalar != NULL); - assert(main_scaler_bits <= fine_scalar_bits); -#endif - - *best_fine_scalar = 1; - - if (input_rate == 0 || target_rate == 0) - return -1; - - if (target_rate >= input_rate) - return 1; - - for (i = 1; i <= loops; i++) { - const unsigned int effective_div = MAX(MIN(input_rate / i / - target_rate, cap), 1); - const unsigned int effective_rate = input_rate / i / - effective_div; - const int error = target_rate - effective_rate; - -#if 0 - debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div, - effective_rate, error); -#endif - - if (error >= 0 && error <= best_error) { - best_error = error; - best_main_scalar = i; - *best_fine_scalar = effective_div; - } - } - - return best_main_scalar; -} - -int clock_set_rate(enum periph_id periph_id, unsigned int rate) -{ - int main; - unsigned int fine; - - main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine); - if (main < 0) { -// debug("%s: Cannot set clock rate for periph %d", -// __func__, periph_id); - return -1; - } - clock_ll_set_ratio(-1, main - 1); - clock_ll_set_pre_ratio(-1, fine - 1); - - return 0; -} - struct gpio_info { unsigned int reg_addr; /* Address of register for this part */ unsigned int max_gpio; /* Maximum GPIO in this part */ @@ -234,163 +128,6 @@ static uint32_t uart3_base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; #define CONFIG_SYS_CLK_FREQ 24000000 -/* exynos5: return pll clock frequency */ -unsigned long get_pll_clk(int pllreg); -unsigned long get_pll_clk(int pllreg) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; - unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq; - - switch (pllreg) { - case APLL: - r = readl(&clk->apll_con0); - break; - case BPLL: - r = readl(&clk->bpll_con0); - break; - case MPLL: - r = readl(&clk->mpll_con0); - break; - case EPLL: - r = readl(&clk->epll_con0); - k = readl(&clk->epll_con1); - break; - case VPLL: - r = readl(&clk->vpll_con0); - k = readl(&clk->vpll_con1); - break; - default: -// printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg); - return 0; - } - - /* - * APLL_CON: MIDV [25:16] - * MPLL_CON: MIDV [25:16] - * EPLL_CON: MIDV [24:16] - * VPLL_CON: MIDV [24:16] - */ - if (pllreg == APLL || pllreg == BPLL || pllreg == MPLL) - mask = 0x3ff; - else - mask = 0x1ff; - - m = (r >> 16) & mask; - - /* PDIV [13:8] */ - p = (r >> 8) & 0x3f; - /* SDIV [2:0] */ - s = r & 0x7; - - freq = CONFIG_SYS_CLK_FREQ; - - if (pllreg == EPLL) { - k = k & 0xffff; - /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ - fout = (m + k / 65536) * (freq / (p * (1 << s))); - } else if (pllreg == VPLL) { - k = k & 0xfff; - /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */ - fout = (m + k / 1024) * (freq / (p * (1 << s))); - } else { - /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */ - fout = m * (freq / (p * (1 << s))); - } - - return fout; -} - -/* src_bit div_bit prediv_bit */ -static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { - {0, 4, 0, -1}, - {4, 4, 4, -1}, - {8, 4, 8, -1}, - {12, 4, 12, -1}, - {0, 4, 0, 8}, - {4, 4, 16, 24}, - {8, 4, 0, 8}, - {12, 4, 16, 24}, - {-1, -1, -1, -1}, - {16, 4, 0, 8}, /* PERIPH_ID_SROMC */ - {20, 4, 16, 24}, - {24, 4, 0, 8}, - {0, 4, 0, 4}, - {4, 4, 12, 16}, - {-1, 4, -1, -1}, - {-1, 4, -1, -1}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {-1, -1, -1, -1}, - {-1, -1, -1, -1}, - {-1, -1, -1, -1}, /* PERIPH_ID_I2S1 */ - {24, 1, 20, -1}, /* PERIPH_ID_SATA */ -}; - -static unsigned long my_clock_get_periph_rate(enum periph_id peripheral) -{ -// struct exynos5_clock *clk = -// (struct exynos5_clock *)samsung_get_base_clock(); - struct exynos5_clock *clk = - (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; - struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; -// struct clk_bit_info bit_info = { 12, 4, 12, -1 }; - unsigned long sclk, sub_clk; - unsigned int src, div, sub_div; - - switch (peripheral) { - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - case PERIPH_ID_UART3: - src = readl(&clk->src_peric0); - div = readl(&clk->div_peric0); - break; - case PERIPH_ID_I2C0: - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - case PERIPH_ID_I2C3: - case PERIPH_ID_I2C4: - case PERIPH_ID_I2C5: - case PERIPH_ID_I2C6: - case PERIPH_ID_I2C7: - src = 0; - sclk = get_pll_clk(MPLL); - sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit) & 0x7) + 1; - div = ((readl(&clk->div_top0) >> bit_info->prediv_bit) & 0x7) + 1; - return (sclk / sub_div) / div; - default: - return -1; - }; - - src = (src >> bit_info->src_bit) & ((1 << bit_info->n_src_bits) - 1); - if (src == SRC_MPLL) - sclk = get_pll_clk(MPLL); - else if (src == SRC_EPLL) - sclk = get_pll_clk(EPLL); - else if (src == SRC_VPLL) - sclk = get_pll_clk(VPLL); - else - return 0; - - sub_div = (div >> bit_info->div_bit) & 0xf; - sub_clk = sclk / (sub_div + 1); - - return sub_clk; -} - static void serial_setbrg_dev(void) { // struct s5p_uart *const uart = s5p_get_base_uart(dev_index); @@ -401,7 +138,7 @@ static void serial_setbrg_dev(void) // enum periph_id periph; // periph = exynos5_get_periph_id(base_port); - uclk = my_clock_get_periph_rate(PERIPH_ID_UART3); + uclk = clock_get_periph_rate(PERIPH_ID_UART3); val = uclk / baudrate; writel(val / 16 - 1, &uart->ubrdiv); @@ -569,7 +306,7 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) { unsigned long freq, pres = 16, div; - freq = my_clock_get_periph_rate(PERIPH_ID_I2C0); + freq = clock_get_periph_rate(PERIPH_ID_I2C0); /* calculate prescaler and divisor values */ if ((freq / pres / (16 + 1)) > speed) /* set prescaler to 512 */ @@ -1222,7 +959,8 @@ static void power_init(void) REG_ENABLE, MAX77686_MV); } -struct mem_timings mem_timings[] = { +/* FIXME(dhendrix): this will be removed in a follow-up patch */ +struct mem_timings my_mem_timings[] = { { .mem_manuf = MEM_MANUF_ELPIDA, .mem_type = DDR_MODE_DDR3, @@ -1330,7 +1068,8 @@ struct mem_timings mem_timings[] = { }, }; -struct arm_clk_ratios arm_clk_ratios[] = { +/* FIXME(dhendrix): this will be removed in a follow-up patch */ +struct arm_clk_ratios my_arm_clk_ratios[] = { { .arm_freq_mhz = 1700, @@ -1354,8 +1093,8 @@ static void clock_init(void) struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; struct exynos5_mct_regs *mct_regs = (struct exynos5_mct_regs *)EXYNOS5_MULTI_CORE_TIMER_BASE; - struct mem_timings *mem = &mem_timings[0]; - struct arm_clk_ratios *arm_clk_ratio = &arm_clk_ratios[0]; + struct mem_timings *mem = &my_mem_timings[0]; + struct arm_clk_ratios *arm_clk_ratio = &my_arm_clk_ratios[0]; u32 val, tmp; /* Turn on the MCT as early as possible. */

1 0

New patch to review for coreboot: 70d59ee exynos5250: make lowlevel_init_c.c benign
by David Hendricks 04 Feb '13

04 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2269 -gerrit commit 70d59ee5d1679c104df56bd8af28fe7696500d44 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Feb 3 18:50:37 2013 -0800 exynos5250: make lowlevel_init_c.c benign This file has mostly (but not entirely) been replaced by coreboot stage files. We'll keep it around for a bit longer as a reference, but in the meantime we'll stop compiling it as to avoid comptilation issues as we change other parts of the code. Change-Id: I669fb1e5a1517f35979590957d581bd33df53d29 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 3 --- src/cpu/samsung/exynos5250/lowlevel_init_c.c | 6 ++++++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 6eee503..49285e7 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -6,7 +6,6 @@ romstage-y += clock.c romstage-y += clock_init.c romstage-y += exynos_cache.c -romstage-y += lowlevel_init_c.c romstage-y += pinmux.c romstage-y += power.c romstage-y += soc.c @@ -23,7 +22,6 @@ romstage-y += dmc_init_ddr3.c ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += exynos_cache.c -ramstage-y += lowlevel_init_c.c ramstage-y += pinmux.c ramstage-y += power.c ramstage-y += soc.c @@ -31,7 +29,6 @@ ramstage-y += uart.c #ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c -ramstage-$(CONFIG_SPL_BUILD) += lowlevel_init_c.c exynos5250_add_bl1: $(obj)/coreboot.pre printf " DD Adding Samsung Exynos5250 BL1\n" diff --git a/src/cpu/samsung/exynos5250/lowlevel_init_c.c b/src/cpu/samsung/exynos5250/lowlevel_init_c.c index 848ebee..daa691f 100644 --- a/src/cpu/samsung/exynos5250/lowlevel_init_c.c +++ b/src/cpu/samsung/exynos5250/lowlevel_init_c.c @@ -23,6 +23,12 @@ * MA 02111-1307 USA */ +/* + * FIXME: This file is essentially the "bootblock" leftover from U-Boot. For + * now it serves as a reference until all the resume-related stuff is added + * to the appropriate bootblock/romstage/ramstage files in coreboot. + */ + #include <common.h> #include <config.h> #include <cpu/samsung/exynos5-common/exynos5-common.h>

1 0

Patch set updated for coreboot: 94c3b0a exynos/s5p: Add helper function for reading a single MVL3 GPIO
by David Hendricks 04 Feb '13

04 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2266 -gerrit commit 94c3b0a80f06d974a2b3eadaa31b5340dc43601a Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Feb 2 17:02:36 2013 -0800 exynos/s5p: Add helper function for reading a single MVL3 GPIO This adds a helper function to read only a single GPIO which uses 3-state logic. Examples of this typically include board straps which are used to provide mainboard-specific information at the hardware- level, such as board revision or configuration options. This is part of a larger clean-up effort for Snow. We may want to genericise this for other CPUs in the future. Change-Id: Ic44f5e589cda89b419a07eca246847e9ce7dcd8d Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/gpio.h | 9 +++++ src/cpu/samsung/s5p-common/s5p_gpio.c | 69 ++++++++++++++++++++++------------- 2 files changed, 53 insertions(+), 25 deletions(-) diff --git a/src/cpu/samsung/exynos5250/gpio.h b/src/cpu/samsung/exynos5250/gpio.h index 7606262..1214384 100644 --- a/src/cpu/samsung/exynos5250/gpio.h +++ b/src/cpu/samsung/exynos5250/gpio.h @@ -477,6 +477,15 @@ void gpio_set_rate(int gpio, int mode); */ int gpio_decode_number(unsigned gpio_list[], int count); +/* + * similar to gpio_decode_number, but reads only a single GPIO + * + * @param gpio GPIO to read + * @return -1 if the value cannot be determined. Otherwise returns + * the corresponding MVL3 enum value. + */ +int gpio_read_mvl3(unsigned gpio); + void gpio_info(void); #endif /* EXYNOS5250_GPIO_H_ */ diff --git a/src/cpu/samsung/s5p-common/s5p_gpio.c b/src/cpu/samsung/s5p-common/s5p_gpio.c index 50c4519..8332015 100644 --- a/src/cpu/samsung/s5p-common/s5p_gpio.c +++ b/src/cpu/samsung/s5p-common/s5p_gpio.c @@ -414,42 +414,61 @@ int gpio_set_value(unsigned gpio, int value) */ #define GPIO_DELAY_US 5 -/* FIXME(dhendrix): this should probably go to a more generic location */ +int gpio_read_mvl3(unsigned gpio) +{ + int high, low; + enum mvl3 value; + + if (gpio >= GPIO_MAX_PORT) + return -1; + + gpio_direction_input(gpio); + gpio_set_pull(gpio, EXYNOS_GPIO_PULL_UP); + udelay(GPIO_DELAY_US); + high = gpio_get_value(gpio); + gpio_set_pull(gpio, EXYNOS_GPIO_PULL_DOWN); + udelay(GPIO_DELAY_US); + low = gpio_get_value(gpio); + + if (high && low) /* external pullup */ + value = LOGIC_1; + else if (!high && !low) /* external pulldown */ + value = LOGIC_0; + else /* floating */ + value = LOGIC_Z; + + /* + * Check if line is externally pulled high and + * configure the internal pullup to match. For + * floating and pulldowns, the GPIO is already + * configured with an internal pulldown from the + * above test. + */ + if (value == LOGIC_1) + gpio_set_pull(gpio, EXYNOS_GPIO_PULL_UP); + + return value; +} + int gpio_decode_number(unsigned gpio_list[], int count) { int result = 0; int multiplier = 1; - int value, high, low; - int gpio, i; + int gpio, i, value; + enum mvl3 mvl3; for (i = 0; i < count; i++) { gpio = gpio_list[i]; - if (gpio >= GPIO_MAX_PORT) - return -1; - gpio_direction_input(gpio); - gpio_set_pull(gpio, EXYNOS_GPIO_PULL_UP); - udelay(GPIO_DELAY_US); - high = gpio_get_value(gpio); - gpio_set_pull(gpio, EXYNOS_GPIO_PULL_DOWN); - udelay(GPIO_DELAY_US); - low = gpio_get_value(gpio); - if (high && low) /* external pullup */ + mvl3 = gpio_read_mvl3(gpio); + if (mvl3 == LOGIC_1) value = 2; - else if (!high && !low) /* external pulldown */ + else if (mvl3 == LOGIC_0) value = 1; - else /* floating */ + else if (mvl3 == LOGIC_Z) value = 0; - - /* - * Check if line is externally pulled high and - * configure the internal pullup to match. For - * floating and pulldowns, the GPIO is already - * configured with an internal pulldown from the - * above test. - */ - if (value == 2) - gpio_set_pull(gpio, EXYNOS_GPIO_PULL_UP); + else + return -1; result += value * multiplier; multiplier *= 3;

1 0

Patch set updated for coreboot: 92c06f3 add gpio.h for generic GPIO-related definitions
by David Hendricks 04 Feb '13

04 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2265 -gerrit commit 92c06f391765b44805d647e7e437f57c7952b7de Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Feb 2 16:57:11 2013 -0800 add gpio.h for generic GPIO-related definitions This adds /src/include/gpio.h which currently contains generic GPIO enums for type (in/out/alt) and 3-state logic. The header was originally written for another FOSS project (mosys) and thus the BSD license. Change-Id: Id1dff69169e8b1ec372107737d356b0fa0d80498 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/include/gpio.h | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/src/include/gpio.h b/src/include/gpio.h new file mode 100644 index 0000000..f602b1e --- /dev/null +++ b/src/include/gpio.h @@ -0,0 +1,63 @@ +/* + * Copyright 2012, Google Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Google Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef GPIO_H +#define GPIO_H + +enum gpio_types { + GPIO_IN, + GPIO_OUT, + GPIO_ALT, /* catch-all for alternate functions */ +}; + +/* + * Many-value logic (3 states). This can be used for inputs whereby presence + * of external pull-up or pull-down resistors can be added to overcome internal + * pull-ups/pull-downs and force a single value. + * + * Thus, external pull resistors can force a 0 or 1 and if the value changes + * along with internal pull-up/down enable then the input is floating. + * + * Vpd | Vpu | MVL + * ----------------- + * 0 | 0 | 0 + * ----------------- + * 0 | 1 | Z <-- floating input will follow internal pull up/down + * ----------------- + * 1 | 1 | 1 + */ +enum mvl3 { + LOGIC_0, + LOGIC_1, + LOGIC_Z, /* high impedence / tri-stated / floating */ +}; + +#endif /* GPIO_H */

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coreboot February 2013