coreboot February 2013

coreboot@coreboot.org

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Patch merged into coreboot/master: 5be6673 cbfstool: Update example file.
by gerrit＠coreboot.org 04 Feb '13

04 Feb '13

the following patch was just integrated into master: commit 5be66730cf6d1a3814cd227d34f4265ffcf82ee1 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Jan 29 10:30:17 2013 +0800 cbfstool: Update example file. The syntax of cbfstool has been changed for a while (using getopt). Updated EXAMPLE file to show the right way to test cbfstool. Change-Id: I5cb41b76712d8c2403fffc9fdad83c61fb2af98c Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/2215 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Jan 29 05:00:34 2013, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Mon Feb 4 11:12:15 2013, giving +2 See http://review.coreboot.org/2215 for details. -gerrit

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New patch to review for coreboot: fc00372 Makefile.inc: Redirect error output of dnsdomainname
by Zheng Bao 04 Feb '13

04 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2274 -gerrit commit fc00372439be201cb2f2fb50bace3dfa66e81a6b Author: zbao <fishbaozi(a)gmail.com> Date: Mon Feb 4 18:11:27 2013 +0800 Makefile.inc: Redirect error output of dnsdomainname Sometimes dnsdomainname fails and says: "dnsdomainname: Unknown host" Change-Id: I05b8545c267d1ed35f63339542131da6c5b9e7a8 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 0b473e4..d4c55d0 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -229,7 +229,7 @@ $(obj)/build.h: .xcompile printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> $(obj)/build.ht printf "#define COREBOOT_COMPILE_BY \"$(subst \,@,$(shell PATH=$$PATH:/usr/ucb whoami))\"\n" >> $(obj)/build.ht printf "#define COREBOOT_COMPILE_HOST \"$(shell hostname -s 2>/dev/null || hostname 2>/dev/null)\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILE_DOMAIN \"$(shell test `uname -s` = "Linux" && dnsdomainname || domainname 2>/dev/null)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILE_DOMAIN \"$(shell test `uname -s` = "Linux" && dnsdomainname 2>/dev/null || domainname 2>/dev/null)\"\n" >> $(obj)/build.ht printf "#endif\n" >> $(obj)/build.ht mv $(obj)/build.ht $(obj)/build.h

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New patch to review for coreboot: f6c17ab crossgcc: add armv7a-eabi to list of working toolchains
by David Hendricks 04 Feb '13

04 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2273 -gerrit commit f6c17ab85c7c43b70c1364ed5874e332929078a0 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Feb 4 01:37:50 2013 -0800 crossgcc: add armv7a-eabi to list of working toolchains Change-Id: Ibf221db4ca60d802b460d56f5fcca95ff49fc542 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- util/crossgcc/README | 1 + 1 file changed, 1 insertion(+) diff --git a/util/crossgcc/README b/util/crossgcc/README index e29f5e1..e4a3e42 100644 --- a/util/crossgcc/README +++ b/util/crossgcc/README @@ -8,6 +8,7 @@ known working: x86_64-elf powerpc-elf mipsel-elf + armv7a-eabi known broken: alpha-elf

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Simple diagram for modern laptop booting flow
by Антон Кочков 04 Feb '13

04 Feb '13

Hello! Here is simple diagram for booting flow of modern Intel laptops. Feel free to ask questions, request for improvements, giving hints. Why Intel? Just because it is more complex than modern AMD systems. Why laptop? Same reason - more complex than desktop. If you have an idea howto merge laptop and desktop booting in one diagram - please share. Attaching both png result and MS Visio 2010 source. Best regards, Anton Kochkov.

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Patch set updated for coreboot: f02922b exynos/snow: Move core/memory clock-related and board ID code
by David Hendricks 04 Feb '13

04 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2271 -gerrit commit f02922b414f52068b05af17366e0f86b1c304eab Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Feb 3 18:09:58 2013 -0800 exynos/snow: Move core/memory clock-related and board ID code This patch moves ARM core and DRAM timing functions around to simplify the dependencies for system_clock_init(). The original code was architected such that the system_clock_init() function called other functions to obtain core and memory timings. Due to the way memory timing information must be obtained on Snow, which entails decoding platform-specific board straps, the bottom- up approach resulted in having the low-level clock init code implicitly depend on board and vendor-specific info: main() ->system_clock_init() -> get_arm_ratios() -> CPU-specific code -> clock_get_mem_timings() -> board_get_revision() -> read GPIOs (3-state logic) -> Decode GPIOs in a vendor-specific manner -> Choose memory timings from module-specific look-up table ...then proceed to init clocks ...come back to main() The new approach gathers all board and vendor-specific info in a more appropriate location and passes it into system_clock_init(): main() -> get_arm_ratios() -> CPU-specific code -> get_mem_timings() -> board_get_config() -> read GPIOs (3-state logic) -> Decode GPIOs in a vendor-specific manner -> Choose memory timings from module-specific look-up table -> system_clock_init() ...back to main() Change-Id: Ie237ebff76fc2d8a4d2f4577a226ac3909e4d4e8 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/clock.c | 113 ++++- src/cpu/samsung/exynos5250/clock_init.c | 753 +------------------------------- src/cpu/samsung/exynos5250/clock_init.h | 103 +---- src/cpu/samsung/exynos5250/dmc.h | 98 +++++ src/cpu/samsung/s5p-common/Makefile.inc | 3 +- src/cpu/samsung/s5p-common/s5p_gpio.c | 1 + src/mainboard/google/snow/Makefile.inc | 6 + src/mainboard/google/snow/bootblock.c | 476 +------------------- src/mainboard/google/snow/mainboard.c | 50 ++- src/mainboard/google/snow/mainboard.h | 38 ++ src/mainboard/google/snow/memory.c | 494 +++++++++++++++++++++ src/mainboard/google/snow/romstage.c | 31 +- 12 files changed, 828 insertions(+), 1338 deletions(-) diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c index 0250d77..fc01387 100644 --- a/src/cpu/samsung/exynos5250/clock.c +++ b/src/cpu/samsung/exynos5250/clock.c @@ -26,17 +26,107 @@ #include <stdlib.h> //#include <fdtdec.h> #include <arch/io.h> -//#include <asm/arch/clock.h> -//#include <asm/arch/clk.h> -#include <cpu/samsung/exynos5-common/clk.h> #include <cpu/samsung/exynos5250/clk.h> +#include <cpu/samsung/exynos5250/clock_init.h> #include <cpu/samsung/exynos5250/cpu.h> -#include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/s5p-common/clk.h> /* input clock of PLL: SMDK5250 has 24MHz input clock */ #define CONFIG_SYS_CLK_FREQ 24000000 +struct arm_clk_ratios arm_clk_ratios[] = { + { + .arm_freq_mhz = 600, + + .apll_mdiv = 0xc8, + .apll_pdiv = 0x4, + .apll_sdiv = 0x1, + + .arm2_ratio = 0x0, + .apll_ratio = 0x1, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x2, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x1, + .arm_ratio = 0x0, + }, { + .arm_freq_mhz = 800, + + .apll_mdiv = 0x64, + .apll_pdiv = 0x3, + .apll_sdiv = 0x0, + + .arm2_ratio = 0x0, + .apll_ratio = 0x1, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x3, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x2, + .arm_ratio = 0x0, + }, { + .arm_freq_mhz = 1000, + + .apll_mdiv = 0x7d, + .apll_pdiv = 0x3, + .apll_sdiv = 0x0, + + .arm2_ratio = 0x0, + .apll_ratio = 0x1, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x4, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x2, + .arm_ratio = 0x0, + }, { + .arm_freq_mhz = 1200, + + .apll_mdiv = 0x96, + .apll_pdiv = 0x3, + .apll_sdiv = 0x0, + + .arm2_ratio = 0x0, + .apll_ratio = 0x3, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x5, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x3, + .arm_ratio = 0x0, + }, { + .arm_freq_mhz = 1400, + + .apll_mdiv = 0xaf, + .apll_pdiv = 0x3, + .apll_sdiv = 0x0, + + .arm2_ratio = 0x0, + .apll_ratio = 0x3, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x6, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x3, + .arm_ratio = 0x0, + }, { + .arm_freq_mhz = 1700, + + .apll_mdiv = 0x1a9, + .apll_pdiv = 0x6, + .apll_sdiv = 0x0, + + .arm2_ratio = 0x0, + .apll_ratio = 0x3, + .pclk_dbg_ratio = 0x1, + .atb_ratio = 0x6, + .periph_ratio = 0x7, + .acp_ratio = 0x7, + .cpud_ratio = 0x3, + .arm_ratio = 0x0, + } +}; /* src_bit div_bit prediv_bit */ static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { @@ -269,6 +359,21 @@ unsigned long get_arm_clk(void) return armclk; } +struct arm_clk_ratios *get_arm_clk_ratios(void) +{ + struct arm_clk_ratios *arm_ratio; + unsigned long arm_freq = 1700; /* FIXME: use get_arm_clk() */ + int i; + + for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios); + i++, arm_ratio++) { + if (arm_ratio->arm_freq_mhz == arm_freq) + return arm_ratio; + } + + return NULL; +} + /* exynos5: set the mmc clock */ void set_mmc_clk(int dev_index, unsigned int div) { diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index 53bab1a..4f21022 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -29,772 +29,27 @@ #include <console/console.h> -#include <cpu/samsung/exynos5-common/spl.h> +/* FIXME: remove unneeded #includes */ #include <cpu/samsung/exynos5250/clk.h> +#include <cpu/samsung/exynos5250/clock_init.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/dmc.h> #include <cpu/samsung/exynos5250/s5p-dp.h> #include <cpu/samsung/s5p-common/clk.h> -#include "clock_init.h" #include "setup.h" -struct arm_clk_ratios arm_clk_ratios[] = { - { - .arm_freq_mhz = 600, - - .apll_mdiv = 0xc8, - .apll_pdiv = 0x4, - .apll_sdiv = 0x1, - - .arm2_ratio = 0x0, - .apll_ratio = 0x1, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x2, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x1, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 800, - - .apll_mdiv = 0x64, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x1, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x3, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x2, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1000, - - .apll_mdiv = 0x7d, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x1, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x4, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x2, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1200, - - .apll_mdiv = 0x96, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x3, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x5, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x3, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1400, - - .apll_mdiv = 0xaf, - .apll_pdiv = 0x3, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x3, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x6, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x3, - .arm_ratio = 0x0, - }, { - .arm_freq_mhz = 1700, - - .apll_mdiv = 0x1a9, - .apll_pdiv = 0x6, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x3, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x6, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x3, - .arm_ratio = 0x0, - } -}; - -struct mem_timings mem_timings[] = { - { - .mem_manuf = MEM_MANUF_ELPIDA, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 800, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x64, - .bpll_pdiv = 0x3, - .bpll_sdiv = 0x0, - .use_bpll = 0, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010042, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x4, - .phy1_tFS = 0x4, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x7, - .zq_mode_term = 0x1, - .zq_mode_noterm = 0, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_30_OHM, - .gate_leveling_enable = 0, - }, { - .mem_manuf = MEM_MANUF_SAMSUNG, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 800, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x64, - .bpll_pdiv = 0x3, - .bpll_sdiv = 0x0, - .use_bpll = 0, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010000, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x8, - .phy1_tFS = 0x8, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x5, - .zq_mode_term = 0x1, - .zq_mode_noterm = 1, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_40_OHM, - .gate_leveling_enable = 1, - }, - { - .mem_manuf = MEM_MANUF_ELPIDA, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 780, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x82, - .bpll_pdiv = 0x4, - .bpll_sdiv = 0x0, - .use_bpll = 1, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010042, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x4, - .phy1_tFS = 0x4, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x7, - .zq_mode_term = 0x1, - .zq_mode_noterm = 0, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_30_OHM, - .gate_leveling_enable = 0, - }, { - .mem_manuf = MEM_MANUF_SAMSUNG, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 780, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x82, - .bpll_pdiv = 0x4, - .bpll_sdiv = 0x0, - .use_bpll = 1, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010000, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x8, - .phy1_tFS = 0x8, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x5, - .zq_mode_term = 0x1, - .zq_mode_noterm = 1, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_40_OHM, - .gate_leveling_enable = 1, - } -}; - -/** - * Detect what memory is present based on board strappings - * - * Boards have various resistor stuff options that are supposed to match - * which SDRAM is present (and which revision of the board this is). This - * uses the resistor stuff options to figure out what memory manufacturer - * to use for matching in the memory tables. - * - * @return A MEM_MANUF_XXX constant, or -1 if an error occurred. - */ -/* - * FIXME(dhendrix): This unwinds into a mess of board-specific code. The - * board's romstage.c file should detect the memory type and pass in - * appropriate parameters to whatever calls this. - */ -#define BOARD_REV_ELPIDA_MEMORY 3 -#define BOARD_REV_SAMSUNG_MEMORY 4 - -static inline int board_get_revision(void) -{ - /* FIXME: yuck! */ - return BOARD_REV_ELPIDA_MEMORY; -} - -static int autodetect_memory(void) -{ - int board_rev = board_get_revision(); - - if (board_rev == -1) - return -1; - - switch (board_rev) { - case BOARD_REV_SAMSUNG_MEMORY: - return MEM_MANUF_SAMSUNG; - case BOARD_REV_ELPIDA_MEMORY: - return MEM_MANUF_ELPIDA; - } - - return -1; -} - -#ifdef CONFIG_SPL_BUILD - -#define SIGNATURE 0xdeadbeef - -/* Parameters of early board initialization in SPL */ -static struct spl_machine_param machine_param = { - .signature = SIGNATURE, - .version = 1, - .params = "vmubfasirMw", - .size = sizeof(machine_param), - - .mem_iv_size = 0x1f, - .mem_type = DDR_MODE_DDR3, - - /* - * Set uboot_size to 0x100000 bytes. - * - * This is an overly conservative value chosen to accommodate all - * possible U-Boot image. You are advised to set this value to a - * smaller realistic size via scripts that modifies the .machine_param - * section of output U-Boot image. - */ - .uboot_size = 0x100000, - - .boot_source = BOOT_MODE_OM, - .frequency_mhz = 800, - .arm_freq_mhz = 1700, - .serial_base = 0x12c30000, - .i2c_base = 0x12c60000, -// .board_rev_gpios = GPIO_D00 | (GPIO_D01 << 16), - .mem_manuf = MEM_MANUF_SAMSUNG, -// .bad_wake_gpio = GPIO_Y10, -}; - -/** - * Get the required memory type and speed (SPL version). - * - * In SPL we have no device tree, so we use the machine parameters - */ -int clock_get_mem_selection(enum ddr_mode *mem_type, - unsigned *frequency_mhz, unsigned *arm_freq, - enum mem_manuf *mem_manuf) -{ - struct spl_machine_param *params; - - params = &machine_param; - *mem_type = params->mem_type; - *frequency_mhz = params->frequency_mhz; - *arm_freq = params->arm_freq_mhz; - if (params->mem_manuf == MEM_MANUF_AUTODETECT) { - *mem_manuf = autodetect_memory(); - if (*mem_manuf == -1) - return -1; - } else { - *mem_manuf = params->mem_manuf; - } - - return 0; -} - -#else - -static const char *mem_types[DDR_MODE_COUNT] = { - "DDR2", "DDR3", "LPDDR2", "LPDDR3" -}; - -static const char *mem_manufs[MEM_MANUF_COUNT] = { - "autodetect", "Elpida", "Samsung" -}; - -int clock_get_mem_selection(enum ddr_mode *mem_type, - unsigned *frequency_mhz, unsigned *arm_freq, - enum mem_manuf *mem_manuf) -{ - const char *typestr; - int node, i; - - node = fdtdec_next_compatible(gd->fdt_blob, 0, - COMPAT_SAMSUNG_EXYNOS_DMC); - if (node < 0) - die("No memory information available in device tree"); - typestr = fdt_getprop(gd->fdt_blob, node, "mem-type", NULL); - for (i = 0; i < DDR_MODE_COUNT; i++) { - if (!stricmp(typestr, mem_types[i])) - break; - } - if (i == DDR_MODE_COUNT) - die("Invalid memory type in device tree"); - *mem_type = i; - - typestr = fdt_getprop(gd->fdt_blob, node, "mem-manuf", NULL); - for (i = 0; i < MEM_MANUF_COUNT; i++) { - if (!stricmp(typestr, mem_manufs[i])) - break; - } - if (i == MEM_MANUF_COUNT) - die("Invalid memory manufacturer in device tree"); - - if (i == MEM_MANUF_AUTODETECT) { - *mem_manuf = autodetect_memory(); - if (*mem_manuf == -1) - return -1; - } else { - *mem_manuf = i; - } - - *frequency_mhz = fdtdec_get_int(gd->fdt_blob, node, "clock-frequency", - 0); - if (!*frequency_mhz) - die("Invalid memory frequency in device tree"); - - *arm_freq = fdtdec_get_int(gd->fdt_blob, node, "arm-frequency", 0); - /* TODO: Remove all these panics/dies, and just return an error code */ - if (!*arm_freq) - die("Invalid ARM frequency in device tree"); - - return 0; -} - -const char *clock_get_mem_type_name(enum ddr_mode mem_type) -{ - if (mem_type >= 0 && mem_type < DDR_MODE_COUNT) - return mem_types[mem_type]; - - return "<unknown>"; -} - -const char *clock_get_mem_manuf_name(enum mem_manuf mem_manuf) -{ - if (mem_manuf >= 0 && mem_manuf < MEM_MANUF_COUNT) - return mem_manufs[mem_manuf]; - - return "<unknown>"; -} -#endif - -/* Get the ratios for setting ARM clock */ -struct arm_clk_ratios *get_arm_ratios(void); /* FIXME: silence compiler... */ -struct arm_clk_ratios *get_arm_ratios(void) -{ - struct arm_clk_ratios *arm_ratio; - enum ddr_mode mem_type; - enum mem_manuf mem_manuf; - unsigned frequency_mhz, arm_freq; - int i; - - /* TODO(sjg(a)chromium.org): Return NULL and have caller deal with it */ - if (clock_get_mem_selection(&mem_type, &frequency_mhz, - &arm_freq, &mem_manuf)) - ; - for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios); - i++, arm_ratio++) { - if (arm_ratio->arm_freq_mhz == arm_freq) - return arm_ratio; - } - -// die("get_arm_ratios: Failed to find ratio\n"); - return NULL; -} - -struct mem_timings *clock_get_mem_timings(void) -{ - /* FIXME: hard-coded for now */ - return &mem_timings[0]; -#if 0 - struct mem_timings *mem; - enum ddr_mode mem_type; - enum mem_manuf mem_manuf; - unsigned frequency_mhz, arm_freq; - int i; - - if (!clock_get_mem_selection(&mem_type, &frequency_mhz, - &arm_freq, &mem_manuf)) { - for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings); - i++, mem++) { - if (mem->mem_type == mem_type && - mem->frequency_mhz == frequency_mhz && - mem->mem_manuf == mem_manuf) - return mem; - } - } - return NULL; -#endif -} - -void system_clock_init(void) +void system_clock_init(struct mem_timings *mem, + struct arm_clk_ratios *arm_clk_ratio) { struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; struct exynos5_mct_regs *mct_regs = (struct exynos5_mct_regs *)EXYNOS5_MULTI_CORE_TIMER_BASE; - struct mem_timings *mem; - struct arm_clk_ratios *arm_clk_ratio; u32 val, tmp; /* Turn on the MCT as early as possible. */ mct_regs->g_tcon |= (1 << 8); - mem = clock_get_mem_timings(); - arm_clk_ratio = get_arm_ratios(); - clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK); do { val = readl(&clk->mux_stat_cpu); diff --git a/src/cpu/samsung/exynos5250/clock_init.h b/src/cpu/samsung/exynos5250/clock_init.h index 00561a0..3757e7d 100644 --- a/src/cpu/samsung/exynos5250/clock_init.h +++ b/src/cpu/samsung/exynos5250/clock_init.h @@ -25,10 +25,6 @@ #ifndef __EXYNOS_CLOCK_INIT_H #define __EXYNOS_CLOCK_INIT_H -enum { - MEM_TIMINGS_MSR_COUNT = 4, -}; - /* These are the ratio's for configuring ARM clock */ struct arm_clk_ratios { unsigned int arm_freq_mhz; /* Frequency of ARM core in MHz */ @@ -47,104 +43,17 @@ struct arm_clk_ratios { unsigned int arm_ratio; }; -/* These are the memory timings for a particular memory type and speed */ -struct mem_timings { - enum mem_manuf mem_manuf; /* Memory manufacturer */ - enum ddr_mode mem_type; /* Memory type */ - unsigned int frequency_mhz; /* Frequency of memory in MHz */ - - /* Here follow the timing parameters for the selected memory */ - uint8_t apll_mdiv; - uint8_t apll_pdiv; - uint8_t apll_sdiv; - uint8_t mpll_mdiv; - uint8_t mpll_pdiv; - uint8_t mpll_sdiv; - uint8_t cpll_mdiv; - uint8_t cpll_pdiv; - uint8_t cpll_sdiv; - uint8_t gpll_pdiv; - uint16_t gpll_mdiv; - uint8_t gpll_sdiv; - uint8_t epll_mdiv; - uint8_t epll_pdiv; - uint8_t epll_sdiv; - uint8_t vpll_mdiv; - uint8_t vpll_pdiv; - uint8_t vpll_sdiv; - uint8_t bpll_mdiv; - uint8_t bpll_pdiv; - uint8_t bpll_sdiv; - uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */ - uint8_t pclk_cdrex_ratio; - unsigned int direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; - - unsigned int timing_ref; - unsigned int timing_row; - unsigned int timing_data; - unsigned int timing_power; - - /* DQS, DQ, DEBUG offsets */ - unsigned int phy0_dqs; - unsigned int phy1_dqs; - unsigned int phy0_dq; - unsigned int phy1_dq; - uint8_t phy0_tFS; - uint8_t phy1_tFS; - uint8_t phy0_pulld_dqs; - uint8_t phy1_pulld_dqs; - - uint8_t lpddr3_ctrl_phy_reset; - uint8_t ctrl_start_point; - uint8_t ctrl_inc; - uint8_t ctrl_start; - uint8_t ctrl_dll_on; - uint8_t ctrl_ref; - - uint8_t ctrl_force; - uint8_t ctrl_rdlat; - uint8_t ctrl_bstlen; - - uint8_t fp_resync; - uint8_t iv_size; - uint8_t dfi_init_start; - uint8_t aref_en; - - uint8_t rd_fetch; - - uint8_t zq_mode_dds; - uint8_t zq_mode_term; - uint8_t zq_mode_noterm; /* 1 to allow termination disable */ - - unsigned int memcontrol; - unsigned int memconfig; - - unsigned int membaseconfig0; - unsigned int membaseconfig1; - unsigned int prechconfig_tp_cnt; - unsigned int dpwrdn_cyc; - unsigned int dsref_cyc; - unsigned int concontrol; - /* Channel and Chip Selection */ - uint8_t dmc_channels; /* number of memory channels */ - uint8_t chips_per_channel; /* number of chips per channel */ - uint8_t chips_to_configure; /* number of chips to configure */ - uint8_t send_zq_init; /* 1 to send this command */ - unsigned int impedance; /* drive strength impedeance */ - uint8_t gate_leveling_enable; /* check gate leveling is enabled */ -}; - /** - * Get the correct memory timings for our selected memory type and speed. - * - * This function can be called from SPL or the main U-Boot. + * Get the clock ratios for CPU configuration * - * @return pointer to the memory timings that we should use + * @return pointer to the clock ratios that we should use */ -struct mem_timings *clock_get_mem_timings(void); +struct arm_clk_ratios *get_arm_clk_ratios(void); /* * Initialize clock for the device */ -void system_clock_init(void); +struct mem_timings; +void system_clock_init(struct mem_timings *mem, + struct arm_clk_ratios *arm_clk_ratio); #endif diff --git a/src/cpu/samsung/exynos5250/dmc.h b/src/cpu/samsung/exynos5250/dmc.h index 9b1f293..0814c07 100644 --- a/src/cpu/samsung/exynos5250/dmc.h +++ b/src/cpu/samsung/exynos5250/dmc.h @@ -175,6 +175,10 @@ enum mem_manuf { MEM_MANUF_COUNT = 2, // fancy that. }; +enum { + MEM_TIMINGS_MSR_COUNT = 4, +}; + #define DMC_INTERLEAVE_SIZE 0x1f /* CONCONTROL register fields */ @@ -224,5 +228,99 @@ enum mem_manuf { #define PHY_CON42_CTRL_RDLAT_SHIFT 0 #define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT) +/* These are the memory timings for a particular memory type and speed */ +struct mem_timings { + enum mem_manuf mem_manuf; /* Memory manufacturer */ + enum ddr_mode mem_type; /* Memory type */ + unsigned int frequency_mhz; /* Frequency of memory in MHz */ + + /* Here follow the timing parameters for the selected memory */ + uint8_t apll_mdiv; + uint8_t apll_pdiv; + uint8_t apll_sdiv; + uint8_t mpll_mdiv; + uint8_t mpll_pdiv; + uint8_t mpll_sdiv; + uint8_t cpll_mdiv; + uint8_t cpll_pdiv; + uint8_t cpll_sdiv; + uint8_t gpll_pdiv; + uint16_t gpll_mdiv; + uint8_t gpll_sdiv; + uint8_t epll_mdiv; + uint8_t epll_pdiv; + uint8_t epll_sdiv; + uint8_t vpll_mdiv; + uint8_t vpll_pdiv; + uint8_t vpll_sdiv; + uint8_t bpll_mdiv; + uint8_t bpll_pdiv; + uint8_t bpll_sdiv; + uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */ + uint8_t pclk_cdrex_ratio; + unsigned int direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; + + unsigned int timing_ref; + unsigned int timing_row; + unsigned int timing_data; + unsigned int timing_power; + + /* DQS, DQ, DEBUG offsets */ + unsigned int phy0_dqs; + unsigned int phy1_dqs; + unsigned int phy0_dq; + unsigned int phy1_dq; + uint8_t phy0_tFS; + uint8_t phy1_tFS; + uint8_t phy0_pulld_dqs; + uint8_t phy1_pulld_dqs; + + uint8_t lpddr3_ctrl_phy_reset; + uint8_t ctrl_start_point; + uint8_t ctrl_inc; + uint8_t ctrl_start; + uint8_t ctrl_dll_on; + uint8_t ctrl_ref; + + uint8_t ctrl_force; + uint8_t ctrl_rdlat; + uint8_t ctrl_bstlen; + + uint8_t fp_resync; + uint8_t iv_size; + uint8_t dfi_init_start; + uint8_t aref_en; + + uint8_t rd_fetch; + + uint8_t zq_mode_dds; + uint8_t zq_mode_term; + uint8_t zq_mode_noterm; /* 1 to allow termination disable */ + + unsigned int memcontrol; + unsigned int memconfig; + + unsigned int membaseconfig0; + unsigned int membaseconfig1; + unsigned int prechconfig_tp_cnt; + unsigned int dpwrdn_cyc; + unsigned int dsref_cyc; + unsigned int concontrol; + /* Channel and Chip Selection */ + uint8_t dmc_channels; /* number of memory channels */ + uint8_t chips_per_channel; /* number of chips per channel */ + uint8_t chips_to_configure; /* number of chips to configure */ + uint8_t send_zq_init; /* 1 to send this command */ + unsigned int impedance; /* drive strength impedeance */ + uint8_t gate_leveling_enable; /* check gate leveling is enabled */ +}; + +/** + * Get the correct memory timings for our selected memory type and speed. + * + * @return pointer to the memory timings that we should use + */ +struct mem_timings *get_mem_timings(void); + #endif #endif diff --git a/src/cpu/samsung/s5p-common/Makefile.inc b/src/cpu/samsung/s5p-common/Makefile.inc index df67573..dc5d886 100644 --- a/src/cpu/samsung/s5p-common/Makefile.inc +++ b/src/cpu/samsung/s5p-common/Makefile.inc @@ -1,4 +1,5 @@ -bootblock-y += pwm.c +bootblock-y += pwm.c # needed by timer.c +bootblock-y += s5p_gpio.c bootblock-y += timer.c romstage-y += cpu_info.c diff --git a/src/cpu/samsung/s5p-common/s5p_gpio.c b/src/cpu/samsung/s5p-common/s5p_gpio.c index f09d0a4..0023beb 100644 --- a/src/cpu/samsung/s5p-common/s5p_gpio.c +++ b/src/cpu/samsung/s5p-common/s5p_gpio.c @@ -20,6 +20,7 @@ /* FIXME(dhendrix): fix this up so it doesn't require a bunch of #ifdefs... */ #include <common.h> +#include <gpio.h> //#include <arch/io.h> #include <gpio.h> #include <arch/gpio.h> diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index a43bcbc..130c354 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -17,6 +17,12 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +# needed for system_clock_init() +bootblock-y += mainboard.c +bootblock-y += memory.c + +romstage-y += mainboard.c +romstage-y += memory.c romstage-y += romstage.c # ramstage-y += ec.c diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 58d347d..08af315 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -42,88 +42,6 @@ #define EXYNOS5_CLOCK_BASE 0x10010000 -struct gpio_info { - unsigned int reg_addr; /* Address of register for this part */ - unsigned int max_gpio; /* Maximum GPIO in this part */ -}; - -static const struct gpio_info gpio_data[EXYNOS_GPIO_NUM_PARTS] = { - { EXYNOS5_GPIO_PART1_BASE, GPIO_MAX_PORT_PART_1 }, - { EXYNOS5_GPIO_PART2_BASE, GPIO_MAX_PORT_PART_2 }, - { EXYNOS5_GPIO_PART3_BASE, GPIO_MAX_PORT_PART_3 }, - { EXYNOS5_GPIO_PART4_BASE, GPIO_MAX_PORT_PART_4 }, - { EXYNOS5_GPIO_PART5_BASE, GPIO_MAX_PORT_PART_5 }, - { EXYNOS5_GPIO_PART6_BASE, GPIO_MAX_PORT }, -}; - -static struct s5p_gpio_bank *gpio_get_bank(unsigned int gpio) -{ - const struct gpio_info *data; - unsigned int upto; - int i; - - for (i = upto = 0, data = gpio_data; i < EXYNOS_GPIO_NUM_PARTS; - i++, upto = data->max_gpio, data++) { - if (gpio < data->max_gpio) { - struct s5p_gpio_bank *bank; - - bank = (struct s5p_gpio_bank *)data->reg_addr; - bank += (gpio - upto) / GPIO_PER_BANK; - return bank; - } - } - -#ifndef CONFIG_SPL_BUILD - assert(gpio < GPIO_MAX_PORT); /* ...which it will not be */ -#endif - return NULL; -} - -#define CON_MASK(x) (0xf << ((x) << 2)) -#define CON_SFR(x, v) ((v) << ((x) << 2)) - -/* This macro gets gpio pin offset from 0..7 */ -#define GPIO_BIT(x) ((x) & 0x7) - -void gpio_cfg_pin(int gpio, int cfg) -{ - unsigned int value; - struct s5p_gpio_bank *bank = gpio_get_bank(gpio); - - value = readl(&bank->con); - value &= ~CON_MASK(GPIO_BIT(gpio)); - value |= CON_SFR(GPIO_BIT(gpio), cfg); - writel(value, &bank->con); -} - -/* Pull mode */ -#define EXYNOS_GPIO_PULL_NONE 0x0 -#define EXYNOS_GPIO_PULL_DOWN 0x1 -#define EXYNOS_GPIO_PULL_UP 0x3 - -#define PULL_MASK(x) (0x3 << ((x) << 1)) -#define PULL_MODE(x, v) ((v) << ((x) << 1)) - -void gpio_set_pull(int gpio, int mode) -{ - unsigned int value; - struct s5p_gpio_bank *bank = gpio_get_bank(gpio); - - value = readl(&bank->pull); - value &= ~PULL_MASK(GPIO_BIT(gpio)); - - switch (mode) { - case EXYNOS_GPIO_PULL_DOWN: - case EXYNOS_GPIO_PULL_UP: - value |= PULL_MODE(GPIO_BIT(gpio), mode); - break; - default: - break; - } - - writel(value, &bank->pull); -} - static uint32_t uart3_base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; #define CONFIG_SYS_CLK_FREQ 24000000 @@ -945,393 +863,6 @@ static void power_init(void) REG_ENABLE, MAX77686_MV); } -/* FIXME(dhendrix): this will be removed in a follow-up patch */ -struct mem_timings my_mem_timings[] = { - { - .mem_manuf = MEM_MANUF_ELPIDA, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 800, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x64, - .bpll_pdiv = 0x3, - .bpll_sdiv = 0x0, - .use_bpll = 0, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010042, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x4, - .phy1_tFS = 0x4, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x7, - .zq_mode_term = 0x1, - .zq_mode_noterm = 0, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_30_OHM, - .gate_leveling_enable = 0, - }, -}; - -/* FIXME(dhendrix): this will be removed in a follow-up patch */ -struct arm_clk_ratios my_arm_clk_ratios[] = { - { - .arm_freq_mhz = 1700, - - .apll_mdiv = 0x1a9, - .apll_pdiv = 0x6, - .apll_sdiv = 0x0, - - .arm2_ratio = 0x0, - .apll_ratio = 0x3, - .pclk_dbg_ratio = 0x1, - .atb_ratio = 0x6, - .periph_ratio = 0x7, - .acp_ratio = 0x7, - .cpud_ratio = 0x3, - .arm_ratio = 0x0, - } -}; - -static void clock_init(void) -{ - struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; - struct exynos5_mct_regs *mct_regs = - (struct exynos5_mct_regs *)EXYNOS5_MULTI_CORE_TIMER_BASE; - struct mem_timings *mem = &my_mem_timings[0]; - struct arm_clk_ratios *arm_clk_ratio = &my_arm_clk_ratios[0]; - u32 val, tmp; - - /* Turn on the MCT as early as possible. */ - mct_regs->g_tcon |= (1 << 8); - -// mem = clock_get_mem_timings(); -// arm_clk_ratio = get_arm_ratios(); - - clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK); - do { - val = readl(&clk->mux_stat_cpu); - } while ((val | MUX_APLL_SEL_MASK) != val); - - clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK); - do { - val = readl(&clk->mux_stat_core1); - } while ((val | MUX_MPLL_SEL_MASK) != val); - - clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK); - clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK); - clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK); - clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK); - tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK - | MUX_GPLL_SEL_MASK; - do { - val = readl(&clk->mux_stat_top2); - } while ((val | tmp) != val); - - clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK); - do { - val = readl(&clk->mux_stat_cdrex); - } while ((val | MUX_BPLL_SEL_MASK) != val); - - /* PLL locktime */ - writel(APLL_LOCK_VAL, &clk->apll_lock); - - writel(MPLL_LOCK_VAL, &clk->mpll_lock); - - writel(BPLL_LOCK_VAL, &clk->bpll_lock); - - writel(CPLL_LOCK_VAL, &clk->cpll_lock); - - writel(GPLL_LOCK_VAL, &clk->gpll_lock); - - writel(EPLL_LOCK_VAL, &clk->epll_lock); - - writel(VPLL_LOCK_VAL, &clk->vpll_lock); - - writel(CLK_REG_DISABLE, &clk->pll_div2_sel); - - writel(MUX_HPM_SEL_MASK, &clk->src_cpu); - do { - val = readl(&clk->mux_stat_cpu); - } while ((val | HPM_SEL_SCLK_MPLL) != val); - - val = arm_clk_ratio->arm2_ratio << 28 - | arm_clk_ratio->apll_ratio << 24 - | arm_clk_ratio->pclk_dbg_ratio << 20 - | arm_clk_ratio->atb_ratio << 16 - | arm_clk_ratio->periph_ratio << 12 - | arm_clk_ratio->acp_ratio << 8 - | arm_clk_ratio->cpud_ratio << 4 - | arm_clk_ratio->arm_ratio; - writel(val, &clk->div_cpu0); - do { - val = readl(&clk->div_stat_cpu0); - } while (0 != val); - - writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); - do { - val = readl(&clk->div_stat_cpu1); - } while (0 != val); - - /* Set APLL */ - writel(APLL_CON1_VAL, &clk->apll_con1); - val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, - arm_clk_ratio->apll_sdiv); - writel(val, &clk->apll_con0); - while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0) - ; - - /* Set MPLL */ - writel(MPLL_CON1_VAL, &clk->mpll_con1); - val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); - writel(val, &clk->mpll_con0); - while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0) - ; - - /* - * Configure MUX_MPLL_FOUT to choose the direct clock source - * path and avoid the fixed DIV/2 block to save power - */ - setbits_le32(&clk->pll_div2_sel, MUX_MPLL_FOUT_SEL); - - /* Set BPLL */ - if (mem->use_bpll) { - writel(BPLL_CON1_VAL, &clk->bpll_con1); - val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); - writel(val, &clk->bpll_con0); - while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0) - ; - - setbits_le32(&clk->pll_div2_sel, MUX_BPLL_FOUT_SEL); - } - - /* Set CPLL */ - writel(CPLL_CON1_VAL, &clk->cpll_con1); - val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); - writel(val, &clk->cpll_con0); - while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0) - ; - - /* Set GPLL */ - writel(GPLL_CON1_VAL, &clk->gpll_con1); - val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); - writel(val, &clk->gpll_con0); - while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0) - ; - - /* Set EPLL */ - writel(EPLL_CON2_VAL, &clk->epll_con2); - writel(EPLL_CON1_VAL, &clk->epll_con1); - val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); - writel(val, &clk->epll_con0); - while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0) - ; - - /* Set VPLL */ - writel(VPLL_CON2_VAL, &clk->vpll_con2); - writel(VPLL_CON1_VAL, &clk->vpll_con1); - val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); - writel(val, &clk->vpll_con0); - while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0) - ; - - writel(CLK_SRC_CORE0_VAL, &clk->src_core0); - writel(CLK_DIV_CORE0_VAL, &clk->div_core0); - while (readl(&clk->div_stat_core0) != 0) - ; - - writel(CLK_DIV_CORE1_VAL, &clk->div_core1); - while (readl(&clk->div_stat_core1) != 0) - ; - - writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt); - while (readl(&clk->div_stat_sysrgt) != 0) - ; - - writel(CLK_DIV_ACP_VAL, &clk->div_acp); - while (readl(&clk->div_stat_acp) != 0) - ; - - writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft); - while (readl(&clk->div_stat_syslft) != 0) - ; - - writel(CLK_SRC_TOP0_VAL, &clk->src_top0); - writel(CLK_SRC_TOP1_VAL, &clk->src_top1); - writel(TOP2_VAL, &clk->src_top2); - writel(CLK_SRC_TOP3_VAL, &clk->src_top3); - - writel(CLK_DIV_TOP0_VAL, &clk->div_top0); - while (readl(&clk->div_stat_top0)) - ; - - writel(CLK_DIV_TOP1_VAL, &clk->div_top1); - while (readl(&clk->div_stat_top1)) - ; - - writel(CLK_SRC_LEX_VAL, &clk->src_lex); - while (1) { - val = readl(&clk->mux_stat_lex); - if (val == (val | 1)) - break; - } - - writel(CLK_DIV_LEX_VAL, &clk->div_lex); - while (readl(&clk->div_stat_lex)) - ; - - writel(CLK_DIV_R0X_VAL, &clk->div_r0x); - while (readl(&clk->div_stat_r0x)) - ; - - writel(CLK_DIV_R0X_VAL, &clk->div_r0x); - while (readl(&clk->div_stat_r0x)) - ; - - writel(CLK_DIV_R1X_VAL, &clk->div_r1x); - while (readl(&clk->div_stat_r1x)) - ; - - if (mem->use_bpll) { - writel(MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL | - MUX_MCLK_DPHY_SEL, &clk->src_cdrex); - } else { - writel(CLK_REG_DISABLE, &clk->src_cdrex); - } - - writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex); - while (readl(&clk->div_stat_cdrex)) - ; - - val = readl(&clk->src_cpu); - val |= CLK_SRC_CPU_VAL; - writel(val, &clk->src_cpu); - - val = readl(&clk->src_top2); - val |= CLK_SRC_TOP2_VAL; - writel(val, &clk->src_top2); - - val = readl(&clk->src_core1); - val |= CLK_SRC_CORE1_VAL; - writel(val, &clk->src_core1); - - writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys); - writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); - while (readl(&clk->div_stat_fsys0)) - ; - - writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_core); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_top); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x); - writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex); - - writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); - writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); - - writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1); - writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1); - writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2); - writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp); - writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp); - writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); - writel(CLK_DIV_ISP1_VAL, &clk->div_isp1); - writel(CLK_DIV_ISP2_VAL, &clk->div_isp2); - - /* FIMD1 SRC CLK SELECTION */ - writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0); - - val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET - | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET - | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET - | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET; - writel(val, &clk->div_fsys2); -} - #include <console/vtxprintf.h> #include <string.h> #define ZEROPAD 1 /* pad with zero */ @@ -1625,11 +1156,16 @@ int do_printk(int msg_level, const char *fmt, ...) void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { + struct mem_timings *mem; + struct arm_clk_ratios *arm_ratios; + /* FIXME: we should not need UART in bootblock, this is only done for testing purposes */ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); power_init(); - clock_init(); + mem = get_mem_timings(); + arm_ratios = get_arm_clk_ratios(); + system_clock_init(mem, arm_ratios); do_serial(); printk(BIOS_INFO, "%s: UART initialized\n", __func__); diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index f11f1fa..ffab520 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -17,18 +17,60 @@ * MA 02111-1307 USA */ +#include <stdlib.h> +#include <gpio.h> #include <device/device.h> #include <console/console.h> -// mainboard_enable is executed as first thing after -// enumerate_buses(). +#include <cpu/samsung/exynos5-common/gpio.h> +#include <cpu/samsung/exynos5250/gpio.h> -static void mainboard_enable(device_t dev) +#include "mainboard.h" + +#define SNOW_BOARD_ID0_GPIO 88 /* GPD0, pin 0 */ +#define SNOW_BOARD_ID1_GPIO 89 /* GPD0, pin 1 */ + +struct { + enum mvl3 id0, id1; + enum snow_board_config config; +} snow_id_map[] = { + /* ID0 ID1 config */ + { LOGIC_0, LOGIC_0, SNOW_CONFIG_SAMSUNG_MP }, + { LOGIC_0, LOGIC_1, SNOW_CONFIG_ELPIDA_MP }, + { LOGIC_1, LOGIC_0, SNOW_CONFIG_SAMSUNG_DVT }, + { LOGIC_1, LOGIC_1, SNOW_CONFIG_ELPIDA_DVT }, + { LOGIC_0, LOGIC_Z, SNOW_CONFIG_SAMSUNG_PVT }, + { LOGIC_1, LOGIC_Z, SNOW_CONFIG_ELPIDA_PVT }, + { LOGIC_Z, LOGIC_0, SNOW_CONFIG_SAMSUNG_MP }, + { LOGIC_Z, LOGIC_Z, SNOW_CONFIG_ELPIDA_MP }, + { LOGIC_Z, LOGIC_1, SNOW_CONFIG_RSVD }, +}; + +int board_get_config(void) { - //dev->ops->init = mainboard_init; + int i; + int id0, id1; + enum snow_board_config config = SNOW_CONFIG_UNKNOWN; + + id0 = gpio_read_mvl3(SNOW_BOARD_ID0_GPIO); + id1 = gpio_read_mvl3(SNOW_BOARD_ID1_GPIO); + if (id0 < 0 || id1 < 0) + return -1; + printk(BIOS_DEBUG, "%s: id0: %u, id1: %u\n", __func__, id0, id1); + + for (i = 0; i < ARRAY_SIZE(snow_id_map); i++) { + if (id0 == snow_id_map[i].id0 && id1 == snow_id_map[i].id1) { + config = snow_id_map[i].config; + break; + } + } + + return config; } +#if 0 struct chip_operations mainboard_ops = { .name = "Samsung/Google ARM ChromeBook", .enable_dev = mainboard_enable, }; +#endif diff --git a/src/mainboard/google/snow/mainboard.h b/src/mainboard/google/snow/mainboard.h new file mode 100644 index 0000000..0047416 --- /dev/null +++ b/src/mainboard/google/snow/mainboard.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2013 The ChromeOS Authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MAINBOARD_H +#define MAINBOARD_H + +enum snow_board_config { + SNOW_CONFIG_UNKNOWN = -1, + SNOW_CONFIG_SAMSUNG_EVT, + SNOW_CONFIG_ELPIDA_EVT, + SNOW_CONFIG_SAMSUNG_DVT, + SNOW_CONFIG_ELPIDA_DVT, + SNOW_CONFIG_SAMSUNG_PVT, + SNOW_CONFIG_ELPIDA_PVT, + SNOW_CONFIG_SAMSUNG_MP, + SNOW_CONFIG_ELPIDA_MP, + SNOW_CONFIG_RSVD, +}; + +int board_get_config(void); + +#endif /* MAINBOARD_H */ diff --git a/src/mainboard/google/snow/memory.c b/src/mainboard/google/snow/memory.c new file mode 100644 index 0000000..b19425d --- /dev/null +++ b/src/mainboard/google/snow/memory.c @@ -0,0 +1,494 @@ +/* + * This file is part of the coreboot project. It is based off code + * from Das U-Boot. + * + * Copyright (C) 2012 Samsung Electronics + * Copyright (C) 2013 The ChromiumOS Authors. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <stdlib.h> +#include <console/console.h> + +#include <cpu/samsung/exynos5250/setup.h> +#include <cpu/samsung/exynos5250/dmc.h> +#include <cpu/samsung/exynos5250/clock_init.h> + +#include "mainboard.h" + +struct mem_timings mem_timings[] = { + { + .mem_manuf = MEM_MANUF_ELPIDA, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 800, + .mpll_mdiv = 0x64, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x0, + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x2, + .gpll_mdiv = 0x215, + .gpll_pdiv = 0xc, + .gpll_sdiv = 0x1, + .epll_mdiv = 0x60, + .epll_pdiv = 0x3, + .epll_sdiv = 0x3, + .vpll_mdiv = 0x96, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + + .bpll_mdiv = 0x64, + .bpll_pdiv = 0x3, + .bpll_sdiv = 0x0, + .use_bpll = 0, + .pclk_cdrex_ratio = 0x5, + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010042, 0x00000d70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x8c36660f, + .timing_data = 0x3630580b, + .timing_power = 0x41000a44, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x4, + .phy1_tFS = 0x4, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x7, + .zq_mode_term = 0x1, + .zq_mode_noterm = 0, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_ENABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | + DMC_MEMCONFIGx_CHIP_COL_10 | + DMC_MEMCONFIGx_CHIP_ROW_15 | + DMC_MEMCONFIGx_CHIP_BANK_8, + .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), + .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 2, + .chips_per_channel = 2, + .chips_to_configure = 1, + .send_zq_init = 1, + .impedance = IMP_OUTPUT_DRV_30_OHM, + .gate_leveling_enable = 0, + }, { + .mem_manuf = MEM_MANUF_SAMSUNG, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 800, + .mpll_mdiv = 0x64, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x0, + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x2, + .gpll_mdiv = 0x215, + .gpll_pdiv = 0xc, + .gpll_sdiv = 0x1, + .epll_mdiv = 0x60, + .epll_pdiv = 0x3, + .epll_sdiv = 0x3, + .vpll_mdiv = 0x96, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + + .bpll_mdiv = 0x64, + .bpll_pdiv = 0x3, + .bpll_sdiv = 0x0, + .use_bpll = 0, + .pclk_cdrex_ratio = 0x5, + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010000, 0x00000d70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x8c36660f, + .timing_data = 0x3630580b, + .timing_power = 0x41000a44, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x8, + .phy1_tFS = 0x8, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x5, + .zq_mode_term = 0x1, + .zq_mode_noterm = 1, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_ENABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | + DMC_MEMCONFIGx_CHIP_COL_10 | + DMC_MEMCONFIGx_CHIP_ROW_15 | + DMC_MEMCONFIGx_CHIP_BANK_8, + .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), + .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 2, + .chips_per_channel = 2, + .chips_to_configure = 1, + .send_zq_init = 1, + .impedance = IMP_OUTPUT_DRV_40_OHM, + .gate_leveling_enable = 1, + }, + { + .mem_manuf = MEM_MANUF_ELPIDA, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 780, + .mpll_mdiv = 0x64, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x0, + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x2, + .gpll_mdiv = 0x215, + .gpll_pdiv = 0xc, + .gpll_sdiv = 0x1, + .epll_mdiv = 0x60, + .epll_pdiv = 0x3, + .epll_sdiv = 0x3, + .vpll_mdiv = 0x96, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + + .bpll_mdiv = 0x82, + .bpll_pdiv = 0x4, + .bpll_sdiv = 0x0, + .use_bpll = 1, + .pclk_cdrex_ratio = 0x5, + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010042, 0x00000d70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x8c36660f, + .timing_data = 0x3630580b, + .timing_power = 0x41000a44, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x4, + .phy1_tFS = 0x4, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x7, + .zq_mode_term = 0x1, + .zq_mode_noterm = 0, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_ENABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | + DMC_MEMCONFIGx_CHIP_COL_10 | + DMC_MEMCONFIGx_CHIP_ROW_15 | + DMC_MEMCONFIGx_CHIP_BANK_8, + .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), + .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 2, + .chips_per_channel = 2, + .chips_to_configure = 1, + .send_zq_init = 1, + .impedance = IMP_OUTPUT_DRV_30_OHM, + .gate_leveling_enable = 0, + }, { + .mem_manuf = MEM_MANUF_SAMSUNG, + .mem_type = DDR_MODE_DDR3, + .frequency_mhz = 780, + .mpll_mdiv = 0x64, + .mpll_pdiv = 0x3, + .mpll_sdiv = 0x0, + .cpll_mdiv = 0xde, + .cpll_pdiv = 0x4, + .cpll_sdiv = 0x2, + .gpll_mdiv = 0x215, + .gpll_pdiv = 0xc, + .gpll_sdiv = 0x1, + .epll_mdiv = 0x60, + .epll_pdiv = 0x3, + .epll_sdiv = 0x3, + .vpll_mdiv = 0x96, + .vpll_pdiv = 0x3, + .vpll_sdiv = 0x2, + + .bpll_mdiv = 0x82, + .bpll_pdiv = 0x4, + .bpll_sdiv = 0x0, + .use_bpll = 1, + .pclk_cdrex_ratio = 0x5, + .direct_cmd_msr = { + 0x00020018, 0x00030000, 0x00010000, 0x00000d70 + }, + .timing_ref = 0x000000bb, + .timing_row = 0x8c36660f, + .timing_data = 0x3630580b, + .timing_power = 0x41000a44, + .phy0_dqs = 0x08080808, + .phy1_dqs = 0x08080808, + .phy0_dq = 0x08080808, + .phy1_dq = 0x08080808, + .phy0_tFS = 0x8, + .phy1_tFS = 0x8, + .phy0_pulld_dqs = 0xf, + .phy1_pulld_dqs = 0xf, + + .lpddr3_ctrl_phy_reset = 0x1, + .ctrl_start_point = 0x10, + .ctrl_inc = 0x10, + .ctrl_start = 0x1, + .ctrl_dll_on = 0x1, + .ctrl_ref = 0x8, + + .ctrl_force = 0x1a, + .ctrl_rdlat = 0x0b, + .ctrl_bstlen = 0x08, + + .fp_resync = 0x8, + .iv_size = 0x7, + .dfi_init_start = 1, + .aref_en = 1, + + .rd_fetch = 0x3, + + .zq_mode_dds = 0x5, + .zq_mode_term = 0x1, + .zq_mode_noterm = 1, + + /* + * Dynamic Clock: Always Running + * Memory Burst length: 8 + * Number of chips: 1 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 0 Cycle + */ + .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | + DMC_MEMCONTROL_DPWRDN_DISABLE | + DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | + DMC_MEMCONTROL_TP_DISABLE | + DMC_MEMCONTROL_DSREF_ENABLE | + DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | + DMC_MEMCONTROL_MEM_TYPE_DDR3 | + DMC_MEMCONTROL_MEM_WIDTH_32BIT | + DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_BL_8 | + DMC_MEMCONTROL_PZQ_DISABLE | + DMC_MEMCONTROL_MRR_BYTE_7_0, + .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | + DMC_MEMCONFIGx_CHIP_COL_10 | + DMC_MEMCONFIGx_CHIP_ROW_15 | + DMC_MEMCONFIGx_CHIP_BANK_8, + .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), + .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), + .prechconfig_tp_cnt = 0xff, + .dpwrdn_cyc = 0xff, + .dsref_cyc = 0xffff, + .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | + DMC_CONCONTROL_TIMEOUT_LEVEL0 | + DMC_CONCONTROL_RD_FETCH_DISABLE | + DMC_CONCONTROL_EMPTY_DISABLE | + DMC_CONCONTROL_AREF_EN_DISABLE | + DMC_CONCONTROL_IO_PD_CON_DISABLE, + .dmc_channels = 2, + .chips_per_channel = 2, + .chips_to_configure = 1, + .send_zq_init = 1, + .impedance = IMP_OUTPUT_DRV_40_OHM, + .gate_leveling_enable = 1, + } +}; + +struct mem_timings *get_mem_timings(void) +{ + int i; + enum snow_board_config board_config; + enum ddr_mode mem_type; + unsigned int frequency_mhz; + enum mem_manuf mem_manuf; + struct mem_timings *mem; + + board_config = board_get_config(); + switch (board_config) { + case SNOW_CONFIG_ELPIDA_EVT: + case SNOW_CONFIG_ELPIDA_DVT: + case SNOW_CONFIG_ELPIDA_PVT: + case SNOW_CONFIG_ELPIDA_MP: + mem_manuf = MEM_MANUF_ELPIDA; + mem_type = DDR_MODE_DDR3; + frequency_mhz = 800; + break; + case SNOW_CONFIG_SAMSUNG_EVT: + case SNOW_CONFIG_SAMSUNG_DVT: + case SNOW_CONFIG_SAMSUNG_PVT: + case SNOW_CONFIG_SAMSUNG_MP: + mem_manuf = MEM_MANUF_SAMSUNG; + mem_type = DDR_MODE_DDR3; + frequency_mhz = 800; + break; + default: + printk(BIOS_CRIT, "Unable to determine board config\n"); + return NULL; + } + + for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings); + i++, mem++) { + if (mem->mem_type == mem_type && + mem->frequency_mhz == frequency_mhz && + mem->mem_manuf == mem_manuf) + return mem; + } + + return NULL; +} diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index fae371a..03fd1be 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -24,13 +24,14 @@ #include <cbfs.h> #include <common.h> -#include <cpu/samsung/exynos5250/setup.h> #include <cpu/samsung/exynos5250/dmc.h> -#include <cpu/samsung/exynos5250/clock_init.h> +#include <cpu/samsung/exynos5250/setup.h> + #include <console/console.h> -#include <arch/bootblock_exit.h> #include <arch/stages.h> +#include "mainboard.h" + void main(void) { struct cbfs_media cbfs; @@ -43,28 +44,31 @@ void main(void) struct mem_timings *mem; int ret; - mem = clock_get_mem_timings(); - printk(BIOS_SPEW, "clock_get_mem_timings returns 0x%p\n", mem); + mem = get_mem_timings(); + if (!mem) { + printk(BIOS_CRIT, "Unable to auto-detect memory timings\n"); + while(1); + } printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", mem->mem_manuf, mem->mem_type, mem->mpll_mdiv, mem->frequency_mhz); - ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE); - if (ret) { - printk(BIOS_ERR, "Memory controller init failed, err: %x\n", - ret); - while(1); - } + ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE); + if (ret) { + printk(BIOS_ERR, "Memory controller init failed, err: %x\n", + ret); + while(1); + } - printk(BIOS_INFO, "ddr3_init done\n"); + printk(BIOS_INFO, "ddr3_init done\n"); /* wow, did it work? */ int i; u32 *c = (void *)CONFIG_RAMBASE; // mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); -// printk(BIOS_INFO, "mmu_setup done\n"); +// printk(BIOS_INFO, "mmu_setup done\n"); for(i = 0; i < 16384; i++) c[i] = i+32768; for(i = 0; i < 16384; i++) @@ -72,6 +76,7 @@ void main(void) printk(BIOS_SPEW, "BADc[%02x]: %02x,", i, c[i]); for(i = 0; i < 1048576; i++) c[i] = 0; + ret = init_default_cbfs_media(&cbfs); if (ret){ printk(BIOS_ERR, "init_default_cbfs_media returned %d: HALT\n",

1 0

Patch merged into coreboot/master: 18ee01e exynos5250: make lowlevel_init_c.c benign
by gerrit＠coreboot.org 04 Feb '13

04 Feb '13

the following patch was just integrated into master: commit 18ee01ed05429df70d90133be0f0e0e4ff1daf51 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Feb 3 18:50:37 2013 -0800 exynos5250: make lowlevel_init_c.c benign This file has mostly (but not entirely) been replaced by coreboot stage files. We'll keep it around for a bit longer as a reference, but in the meantime we'll stop compiling it as to avoid comptilation issues as we change other parts of the code. Change-Id: I669fb1e5a1517f35979590957d581bd33df53d29 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2269 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Feb 4 05:02:59 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Feb 4 06:09:22 2013, giving +2 See http://review.coreboot.org/2269 for details. -gerrit

1 0

Patch merged into coreboot/master: 2354ef8 exynos/snow: get rid of board-specific arbitration code
by gerrit＠coreboot.org 04 Feb '13

04 Feb '13

the following patch was just integrated into master: commit 2354ef8869a287cf4c7de792c17485ad82b026cf Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Feb 3 20:47:38 2013 -0800 exynos/snow: get rid of board-specific arbitration code Snow's AP, EC, PMU, and smarty battery share a bus. Both the AP and EC can act as a master, so to avoid conflicts an arbitration mechanism consisting of two GPIOs is used. By default, the AP "owns" the bus unless it is off (in which case the EC doesn't monitor the arbitration pins). This means the boot firmware does not need to worry about these lines. The payload may if it needs to communicate with the EC, though. In any case, board-specific bus arbitration logic does not belong in a low-level driver that is supposed to be generic for an entire CPU family. If the payload needs to talk to the EC, we'll deal with it there. Change-Id: I0774d4592af2b21b6ad668441532c5ceab988404 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2272 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Feb 4 06:03:56 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Feb 4 06:08:20 2013, giving +2 See http://review.coreboot.org/2272 for details. -gerrit

1 0

New patch to review for coreboot: 0e6da85 exynos/snow: get rid of board-specific arbitration code
by David Hendricks 04 Feb '13

04 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2272 -gerrit commit 0e6da8510ce6f104941f4a64eaa31c46464b3f35 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Feb 3 20:47:38 2013 -0800 exynos/snow: get rid of board-specific arbitration code Snow's AP, EC, PMU, and smarty battery share a bus. Both the AP and EC can act as a master, so to avoid conflicts an arbitration mechanism consisting of two GPIOs is used. By default, the AP "owns" the bus unless it is off (in which case the EC doesn't monitor the arbitration pins). This means the boot firmware does not need to worry about these lines. The payload may if it needs to communicate with the EC, though. In any case, board-specific bus arbitration logic does not belong in a low-level driver that is supposed to be generic for an entire CPU family. If the payload needs to talk to the EC, we'll deal with it there. Change-Id: I0774d4592af2b21b6ad668441532c5ceab988404 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/spl.h | 4 ---- src/cpu/samsung/s5p-common/s3c24x0_i2c.c | 19 +------------------ src/mainboard/google/snow/bootblock.c | 14 -------------- src/mainboard/google/snow/smdk5250_spl.c | 15 --------------- 4 files changed, 1 insertion(+), 51 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/spl.h b/src/cpu/samsung/exynos5-common/spl.h index 439e1b0..afa9a8e 100644 --- a/src/cpu/samsung/exynos5-common/spl.h +++ b/src/cpu/samsung/exynos5-common/spl.h @@ -91,8 +91,4 @@ struct spl_machine_param *spl_get_machine_params(void); */ void spl_early_init(void); -/* FIXME(dhendrix): for early i2c init */ -void board_i2c_release_bus(int node); -int board_i2c_claim_bus(int node); - #endif /* __ASM_ARCH_EXYNOS_SPL_H__ */ diff --git a/src/cpu/samsung/s5p-common/s3c24x0_i2c.c b/src/cpu/samsung/s5p-common/s3c24x0_i2c.c index 0b6f768..2940b09 100644 --- a/src/cpu/samsung/s5p-common/s3c24x0_i2c.c +++ b/src/cpu/samsung/s5p-common/s3c24x0_i2c.c @@ -39,9 +39,6 @@ #include "device/i2c.h" #include "s3c24x0_i2c.h" -/* for board_i2c_* */ -#include "cpu/samsung/exynos5-common/spl.h" - #define I2C_WRITE 0 #define I2C_READ 1 @@ -531,12 +528,7 @@ int i2c_probe(uchar chip) * address was <ACK>ed (i.e. there was a chip at that address which * drove the data line low). */ - if (board_i2c_claim_bus(i2c->node)) { - debug("I2C cannot claim bus %d\n", i2c->bus_num); - return -1; - } ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, 0, 0, buf, 1); - board_i2c_release_bus(i2c->node); return ret != I2C_OK; } @@ -578,13 +570,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) i2c = get_bus(g_current_bus); if (!i2c) return -1; - if (board_i2c_claim_bus(i2c->node)) { - debug("I2C cannot claim bus %d\n", i2c->bus_num); - return -1; - } ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, &xaddr[4 - alen], alen, buffer, len); - board_i2c_release_bus(i2c->node); if (ret) { debug("I2c read: failed %d\n", ret); return 1; @@ -628,13 +615,9 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) i2c = get_bus(g_current_bus); if (!i2c) return -1; - if (board_i2c_claim_bus(i2c->node)) { - debug("I2C cannot claim bus %d\n", i2c->bus_num); - return -1; - } + ret = i2c_transfer(i2c->regs, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, len); - board_i2c_release_bus(i2c->node); return ret != 0; } diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 7609410..9055a76 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -912,15 +912,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) #endif if (!i2c) return -1; -#if 0 - if (board_i2c_claim_bus(i2c->node)) { - debug("I2C cannot claim bus %d\n", i2c->bus_num); - return -1; - } -#endif ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, &xaddr[4 - alen], alen, buffer, len); - //board_i2c_release_bus(i2c->node); if (ret) { //debug("I2c read: failed %d\n", ret); return 1; @@ -965,15 +958,8 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) i2c = &i2c0; if (!i2c) return -1; -#if 0 - if (board_i2c_claim_bus(i2c->node)) { - //debug("I2C cannot claim bus %d\n", i2c->bus_num); - return -1; - } -#endif ret = i2c_transfer(i2c->regs, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, len); - //board_i2c_release_bus(i2c->node); return ret != 0; } diff --git a/src/mainboard/google/snow/smdk5250_spl.c b/src/mainboard/google/snow/smdk5250_spl.c index 0dbd4e1..33f27b1 100644 --- a/src/mainboard/google/snow/smdk5250_spl.c +++ b/src/mainboard/google/snow/smdk5250_spl.c @@ -87,18 +87,3 @@ int board_wakeup_permitted(void) return !is_bad_wake; } - -/* - * TODO(sjg(a)chromium.org): - * Declared there here for SPL, since there is no core i2c subsystem and - * cmd_i2c.c is not included. - */ -void board_i2c_release_bus(int node) -{ -} - -int board_i2c_claim_bus(int node) -{ - /* EC is not allowed to touch the bus until we enter U-Boot */ - return 0; -}

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Patch merged into coreboot/master: aa6701c exynos/snow: partial clean-up of snow bootblock using build class
by gerrit＠coreboot.org 04 Feb '13

04 Feb '13

the following patch was just integrated into master: commit aa6701c090c013c1783b138e02277090615508ee Author: David Hendricks <dhendrix(a)chromium.org> Date: Sun Feb 3 19:13:36 2013 -0800 exynos/snow: partial clean-up of snow bootblock using build class This removes some duplicate code from Snow's mainboard bootblock by utilizing the bootblock build class. Change-Id: I153247370a8c5127260082dcdca3ebdc5e104fb8 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2270 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Feb 4 05:10:20 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Feb 4 05:53:42 2013, giving +2 See http://review.coreboot.org/2270 for details. -gerrit

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Patch merged into coreboot/master: ad7f98c exynos/s5p: Add helper function for reading a single MVL3 GPIO
by gerrit＠coreboot.org 04 Feb '13

04 Feb '13

the following patch was just integrated into master: commit ad7f98cb0163d0ef2b0e6f75d334cdbd6faf846c Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Feb 2 17:02:36 2013 -0800 exynos/s5p: Add helper function for reading a single MVL3 GPIO This adds a helper function to read only a single GPIO which uses 3-state logic. Examples of this typically include board straps which are used to provide mainboard-specific information at the hardware- level, such as board revision or configuration options. This is part of a larger clean-up effort for Snow. We may want to genericise this for other CPUs in the future. Change-Id: Ic44f5e589cda89b419a07eca246847e9ce7dcd8d Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2266 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Feb 4 05:46:55 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Feb 4 05:52:18 2013, giving +2 See http://review.coreboot.org/2266 for details. -gerrit

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coreboot February 2013