coreboot February 2013

coreboot@coreboot.org

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Patch set updated for coreboot: 3a950ab lib: Prevent unaligned memory access and fix endianess in LZMA decode library.
by Hung-Te Lin 01 Feb '13

01 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2246 -gerrit commit 3a950ab119a28d545ff4fd45805f9e67ebe8e3a8 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Jan 31 12:14:46 2013 +0800 lib: Prevent unaligned memory access and fix endianess in LZMA decode library. LZMA decode library used to retrieve output size by: outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE); 'src' is aligned but LZMA_PROPERTIES_SIZE may refer to an unaligned address like src+5, and using that as integer pointer may fail on platforms like ARM. Also this will fail on systems using big-endian (outSize was encoded in little-endian). To fix this, reconstruct outSize in little-endian way. Change-Id: If678e735cb270c3e5e29f36f1fad318096bf7d59 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/lib/lzma.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/lib/lzma.c b/src/lib/lzma.c index f0b88c1..cd60b3f 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -29,9 +29,15 @@ unsigned long ulzma(unsigned char * src, unsigned char * dst) #endif /* in pre-ram, it must go on the stack */ unsigned char scratchpad[15980]; + unsigned char *cp; memcpy(properties, src, LZMA_PROPERTIES_SIZE); - outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE); + /* The outSize in LZMA stream is a 64bit integer stored in little-endian + * (ref: lzma.cc@LZMACompress: put_64). To prevent accessing by + * unaligned memory address and to load in correct endianess, read each + * byte and re-costruct. */ + cp = src + LZMA_PROPERTIES_SIZE; + outSize = cp[3] << 24 | cp[2] << 16 | cp[1] << 8 | cp[0]; if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) { printk(BIOS_WARNING, "lzma: Incorrect stream properties.\n"); return 0;

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Patch set updated for coreboot: 120bd66 lib: Prevent unaligned memory access and fix endianess in LZMA decode library.
by Hung-Te Lin 01 Feb '13

01 Feb '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2246 -gerrit commit 120bd66b5ffbc7ca52a7255191d1c3025c6a2803 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Jan 31 12:14:46 2013 +0800 lib: Prevent unaligned memory access and fix endianess in LZMA decode library. LZMA decode library used to retrieve output size by: outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE); 'src' is aligned but LZMA_PROPERTIES_SIZE may refer to an unaligned address like src+5, and using that as integer pointer may fail on platforms like ARM. Also this will fail on systems using big-endian (outSize was encoded in little-endian). To fix this, reconstruct outSize in little-endian way. Change-Id: If678e735cb270c3e5e29f36f1fad318096bf7d59 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/lib/lzma.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/lib/lzma.c b/src/lib/lzma.c index f0b88c1..7a62b84 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -29,9 +29,15 @@ unsigned long ulzma(unsigned char * src, unsigned char * dst) #endif /* in pre-ram, it must go on the stack */ unsigned char scratchpad[15980]; + unsigned char *cp; memcpy(properties, src, LZMA_PROPERTIES_SIZE); - outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE); + /* The outSize in LZMA stream is a 64bit integer stored in little-endian + * (ref: lzma.cc@LZMACompress: put_64). To prevent accessing by + * unaligned memory access and to load endianess correctly, read each + * byte and re-costruct. */ + cp = src + LZMA_PROPERTIES_SIZE; + outSize = cp[3] << 24 | cp[2] << 16 | cp[1] << 8 | cp[0]; if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) { printk(BIOS_WARNING, "lzma: Incorrect stream properties.\n"); return 0;

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New patch to review for coreboot: 32e20ad clean-up for arch/armv7/Makefile.inc
by David Hendricks 01 Feb '13

01 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2257 -gerrit commit 32e20ad580f6f9cc744380910a0dc49cd68cae9a Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 31 17:49:22 2013 -0800 clean-up for arch/armv7/Makefile.inc This removes a few lines which are obsolete or unneeded. We may want to do something with SMP eventually (can we use it for decompression?) but for now we'll assume non-bootstrap cores are idle until the OS does something with them. Change-Id: Iff6b196e008e803bcfd00e5de07cf471bd2357ea Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 35 ----------------------------------- 1 file changed, 35 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 78fa671..e55f477 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -25,7 +25,6 @@ # Take care of subdirectories subdirs-y += boot/ subdirs-y += lib/ -# subdirs-y += smp/ ################################################################################ # Build the final rom image @@ -60,10 +59,6 @@ endif $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp - if [ -f $(objcbfs)/coreboot_ap.elf ]; \ - then \ - $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ap.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ap -c $(CBFS_COMPRESS_FLAG) ; \ - fi $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) @printf " PAYLOAD none (as specified by user)\n" @@ -131,20 +126,6 @@ else $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif -################################################################################ -# Ramstage for AP CPU (AMD K8, obsolete?) - -#$(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/armv7/init/ldscript_apc.lb -# @printf " CC $(subst $(obj)/,,$(@))\n" -# $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/init/ldscript_apc.lb $< - -#$(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H) -# @printf " CC $(subst $(obj)/,,$(@))\n" -# $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ - -################################################################################ -# done - CFLAGS += \ -ffixed-r8\ -march=armv7-a\ @@ -153,10 +134,6 @@ CFLAGS += \ -mthumb\ -mthumb-interwork -# For various headers imported from Linux -CFLAGS += -D__LINUX_ARM_ARCH__=7 - -#crt0s = $(src)/arch/armv7/bootblock.inc ldscripts = ldscripts += $(src)/arch/armv7/romstage.ld @@ -173,19 +150,10 @@ ifeq ($(CONFIG_LLSHELL),y) crt0s += $(src)/arch/armv7/llshell/llshell.inc endif -# FIXME: do we need romstage.inc? Maybe just get rid of this entirely. -#crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc - $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h @printf " CC romstage.inc\n" $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ -#$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc -# @printf " POST romstage.inc\n" -# sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \ -# -e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp -# mv $@.tmp $@ - # Things that appear in every board romstage-srcs += $(objgenerated)/crt0.s ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c @@ -251,8 +219,6 @@ $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm -#BOOTBLOCK_OBJS = $(objgenerated)/bootblock.o $(bootblock_exit_o) - $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ @@ -274,7 +240,6 @@ endif ################################################################################ # Build the romstage -# FIXME(dhendrix): added debug printfs $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(stages_o) $(objgenerated)/romstage_null.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)

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Patch merged into coreboot/master: 7fb692b Fam15tn: Move SPD read from mainboards into wrapper
by gerrit＠coreboot.org 01 Feb '13

01 Feb '13

the following patch was just integrated into master: commit 7fb692bd867b271834be797029a6b4f72e4601bd Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sun Jan 20 10:38:58 2013 -0700 Fam15tn: Move SPD read from mainboards into wrapper Continuing with the mainboard cleanup for F15tn, move the functions to read the SPD from the mainboards for Thatcher and Parmer into the wrapper for the northbridge/amd/agesa/family15tn. Move the SPD address customization for the mainboard into the devicetree.cb file. Unrelated side note - Porting.h has an un-closed #pragma pack(1) that can cause confusing side-effects. AGESA's structures all use this, but coreboot's don't. Be sure to include the coreboot .h files BEFORE Porting.h is included, not after. This fix has been tested. Change-Id: I89cdd225be61f60c6b8e7020e6f8b879983bbd96 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2190 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Jan 31 19:59:42 2013, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu Jan 31 23:02:10 2013, giving +2 See http://review.coreboot.org/2190 for details. -gerrit

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Patch set updated for coreboot: 1ead10d lib: Prevent unaligned memory access in LZMA decode library.
by Ronald G. Minnich 01 Feb '13

01 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2246 -gerrit commit 1ead10d4f4718bede6279db834eb3d34960749e2 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Jan 31 12:14:46 2013 +0800 lib: Prevent unaligned memory access in LZMA decode library. LZMA decode library used to retrieve output size by: outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE); 'src' is aligned but LZMA_PROPERTIES_SIZE may refer to an unaligned address like src+5, and using that as integer pointer may fail on platforms like ARM. To fix this, use memcpy to copy into aligned variable outSize. Change-Id: If678e735cb270c3e5e29f36f1fad318096bf7d59 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/lib/lzma.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/lib/lzma.c b/src/lib/lzma.c index f0b88c1..a2d91d1 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -31,7 +31,8 @@ unsigned long ulzma(unsigned char * src, unsigned char * dst) unsigned char scratchpad[15980]; memcpy(properties, src, LZMA_PROPERTIES_SIZE); - outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE); + /* Do memcpy to prevent unaligned memory access. */ + memcpy(&outSize, src + LZMA_PROPERTIES_SIZE, sizeof(outSize)); if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) { printk(BIOS_WARNING, "lzma: Incorrect stream properties.\n"); return 0;

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Patch merged into coreboot/master: 50c0a50 armv7: unify stage hand-off routines
by gerrit＠coreboot.org 01 Feb '13

01 Feb '13

the following patch was just integrated into master: commit 50c0a50ac6a3fa54ed1286e8b76f933701b6d053 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 31 17:05:50 2013 -0800 armv7: unify stage hand-off routines This replaces the current stage-specific exit/entry functions with generic versions. Now all stages compile with stage_entry(), which is placed at .text.stage_entry.armv7, and stage_exit(). Snow's ramstage files are also updated to avoid build breakage. Change-Id: I953a2c4b8121bd4b66c3362557997a9ca3aa53b0 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2254 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Feb 1 03:17:48 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Feb 1 03:01:42 2013, giving +2 See http://review.coreboot.org/2254 for details. -gerrit

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Re: [coreboot] Guide lines: Prepend commit summary with component (was: New patch to review for coreboot: 0b41858 Clean up the mmu setup a bit)
by Peter Stuge 01 Feb '13

01 Feb '13

David Hendricks wrote: > If you wish to focus only on a particular part of the codebase It's more about getting an overview of what has changed. It is impossible to discern whether "Fix MMU setup" is at all relevant for my ThinkPad from the message alone. Maybe some setup was wrong - what do I know. "armv7: Fix MMU setup" however makes it clear what the change is. > specify the directories/files you wish to look at when running git log. It's the other way around, for creating an overview. The commit message represents the commit. The commit contains a root tree. Commits only affecting subsets of the code isn't really an accurate representation of how the repository works. > Actually, I think it would look kind of ugly to do "git log src/arch/x86" > and see every commit cluttered with some cookie-cutter prefix. Maybe - or maybe it is simply expected. Within x86 it's possible that there will be several different and distinct parts. //Peter

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Re: [coreboot] Different Google copyright notices: »The Chromium OS Authors.« or Google, Inc.
by Peter Stuge 01 Feb '13

01 Feb '13

ron minnich wrote: > > In the community we can of course not know what is correct when, > > ah yes well I do kind of wonder if *I* know what I'm doing half the > time :-) I guess the concern was that perhaps there was a single correct notice to be used, and that some of you guys made a mistake somewhere. I don't expect that you make such mistakes, but I guess that's what Paul meant. //Peter

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Patch set updated for coreboot: 21f5a2e snow: make romstage init DRAM controller and call ramstage
by David Hendricks 01 Feb '13

01 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2245 -gerrit commit 21f5a2ee7aa069ca8a53040c5962cca77e734098 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Jan 30 15:55:36 2013 -0800 snow: make romstage init DRAM controller and call ramstage This is a first cut at a romstage. It sets up memory, although that needs some work; and finds and loads a ramstage. Change-Id: I02a0eb48828500bf83c3c57d4bacb396e58bf9a5 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/romstage.c | 89 +++++++++++++++++++++++++++++------- 1 file changed, 72 insertions(+), 17 deletions(-) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 3f3f3ec..fae371a 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -19,35 +19,90 @@ #include <types.h> #include <system.h> -#include <cache.h> - -#if 0 -#include <arch/io.h> -/* FIXME: make i2c.h use standard types */ -#define uchar unsigned char -#define uint unsigned int -#include <device/i2c.h> +#include <cache.h> +#include <cbfs.h> +#include <common.h> -#include <cpu/samsung/s5p-common/s3c24x0_i2c.h> -#include "cpu/samsung/exynos5250/dmc.h" -#include <cpu/samsung/exynos5250/power.h> +#include <cpu/samsung/exynos5250/setup.h> +#include <cpu/samsung/exynos5250/dmc.h> #include <cpu/samsung/exynos5250/clock_init.h> -#include <cpu/samsung/exynos5-common/uart.h> -#endif #include <console/console.h> +#include <arch/bootblock_exit.h> +#include <arch/stages.h> -void main(void); void main(void) { -// volatile unsigned long *pshold = (unsigned long *)0x1004330c; + struct cbfs_media cbfs; // i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); // power_init(); // clock_init(); // exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); console_init(); printk(BIOS_INFO, "hello from romstage\n"); + struct mem_timings *mem; + int ret; + + mem = clock_get_mem_timings(); + printk(BIOS_SPEW, "clock_get_mem_timings returns 0x%p\n", mem); + printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", + mem->mem_manuf, + mem->mem_type, + mem->mpll_mdiv, + mem->frequency_mhz); + + ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE); + if (ret) { + printk(BIOS_ERR, "Memory controller init failed, err: %x\n", + ret); + while(1); + } + + printk(BIOS_INFO, "ddr3_init done\n"); + /* wow, did it work? */ + int i; + u32 *c = (void *)CONFIG_RAMBASE; + +// mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); +// printk(BIOS_INFO, "mmu_setup done\n"); + for(i = 0; i < 16384; i++) + c[i] = i+32768; + for(i = 0; i < 16384; i++) + if (c[i] != i+32768) + printk(BIOS_SPEW, "BADc[%02x]: %02x,", i, c[i]); + for(i = 0; i < 1048576; i++) + c[i] = 0; + ret = init_default_cbfs_media(&cbfs); + if (ret){ + printk(BIOS_ERR, "init_default_cbfs_media returned %d: HALT\n", + ret); + while (1); + } + + struct cbfs_stage *stage = (struct cbfs_stage *) + cbfs_get_file_content(&cbfs, "fallback/coreboot_ram", + CBFS_TYPE_STAGE); + printk(BIOS_ERR, "Stage: %p\n", stage); + printk(BIOS_ERR, "loading stage %s @ 0x%x (0x%x bytes),entry @ 0x%p\n", + "ram stage", + (uint32_t) stage->load, stage->memlen, + (void *)(u32)stage->entry); + +#if 0 + /* for reference and testing ... we should be able to remove soon */ +// c = (void *)(u32)(stage->load + stage->len); + c = (void *)(u32)(stage->load); + printk(BIOS_ERR, "memzero 0x%x words starting at %p\n", + (stage->memlen /*- stage->len*/)/4, c); + for(i = 0; i < (stage->memlen /*- stage->len*/)/4; i++){ + printk(BIOS_INFO, "%p, ", &c[i]); + c[i] = 0; + } +#endif + + void *entry = cbfs_load_stage(&cbfs, "fallback/coreboot_ram"); + printk(BIOS_INFO, "entry is %p\n", entry); -// *pshold &= ~0x100; /* shut down */ - mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024); + printk(BIOS_INFO, "sayonara, romstage!\n"); + stage_exit((unsigned long)entry); }

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Patch set updated for coreboot: 92ef230 exynos5250: hard-code array index for memory timings
by David Hendricks 01 Feb '13

01 Feb '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2256 -gerrit commit 92ef2301ee0fe8c5e92aceccbaa6cc17e30c8427 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jan 31 17:25:16 2013 -0800 exynos5250: hard-code array index for memory timings Discovering memory timings is a bit complicated due to the need to obtain and decode board config. To make things worse, the imported code makes a mess of dependencies. Hard-code the memory timings for now to get us further along (the instability won't really matter until we're loading depthcharge anyway). Change-Id: I1f341ad597db0c31ed4ae6bc703fc22b6596a803 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/clock_init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index 565abe1..421d880 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -725,6 +725,9 @@ struct arm_clk_ratios *get_arm_ratios(void) struct mem_timings *clock_get_mem_timings(void) { + /* FIXME: hard-coded for now */ + return &mem_timings[0]; +#if 0 struct mem_timings *mem; enum ddr_mode mem_type; enum mem_manuf mem_manuf; @@ -742,6 +745,7 @@ struct mem_timings *clock_get_mem_timings(void) } } return NULL; +#endif } void system_clock_init(void)

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coreboot February 2013