December 2013 - coreboot - mail.coreboot.org

Re: [coreboot] No VGA output on e350m1 after flashing. what to do?
by Reiner Luett Sept. 12, 2017

Sept. 12, 2017

Hi! On 30.06.2013 19:28, Christian Weinz wrote: > Maybe I didn't include the VGA option in the make menuconfig process. > How can I solve this problem? You need to add the VGA Option ROM (VGA BIOS -> Add VGA BIOS image). I've extracted it from the UEFI, but you also could use these: http://www.coreboot.org/index.php?title=ASRock_E350M1&oldid=11114 at the end of the page or you also may be able to use the default AMD fam14 (Persimmon) vbios. You will need to agree to the click through: http://wwwd.amd.com/support/vbioslic.nsf/userverify?openform http://www.coreboot.org/AMD_DB-FT1_PERSIMMON It's a pity, that bios_extract didn't work for now. You could use the AMI Aptio EFI MMTool with wine: http://win-lite.de/benutzer/fernando/BIOS-Tools/AMI_Aptio_EFI_MMTool_v4.50.… You need to extract OntarioEFIVbios with PCI ID 1002,9802 as Option ROM. Regards, Reiner --

5 6

#95: Run coreboot in VirtualBox
by coreboot Dec. 10, 2014

Dec. 10, 2014

#95: Run coreboot in VirtualBox ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: misc | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ It would be nice if we could test coreboot images in VirtualBox, see http://virtualbox.org/. VirtualBox does not (yet) provide a simple mechanism to use a different BIOS in their emulated machines (something like "-L" in qemu). Instead the BIOS image (a custom bochs BIOS + LGPL'g VGABIOS) is converted to C code (an array of bytes, or the like) and merged into the VirtualBox executable. The relevant files are {{{ src/VBox/Devices/PC/DevPcBios.cpp bldprogs/bin2c.c }}} if someone want to hack VirtualBox to easily support using coreboot images instead of their usual BIOS. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/95> coreboot <http://www.coreboot.org/>

2 8

EHCI debug port finder
by Carl-Daniel Hailfinger May 30, 2014

May 30, 2014

I wanted to know which physical port of my multiple USB controllers have the debug capability. There was no way to find that easily, so I created a tool which will do most of the work for the user. Example output: The following PCI devices support a USB debug port (says lspci): 0000:00:1d.7 The following PCI devices support a USB debug port (says the kernel): 0000:00:1d.7 PCI device 0000:00:1d.7, USB bus 3, USB physical port 1 Currently connected high-speed devices: /: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=ehci_hcd/6p, 480M |__ Port 2: Dev 20, If 0, Class=stor., Driver=usb-storage, 480M The output can be improved, but it's a good start. Regards, Carl-Daniel -- http://www.hailfinger.org/

5 13

Dual SPI Flash adapter attempt 2.0
by Oliver Schinagl March 9, 2014

March 9, 2014

Hi list(s), Here's my second attempt at routing the previously mailed png of my schema. It was a lot trickier to route then my previous version, but I think it worked out! As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1 should be 10k or ideally 100k, as Peter mentioned earlier. Hopefully there's no obvious mistakes and can start working on alternative layouts (so it is insert-able in different angles). DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow. That said, DRC check passes when I set the copper width/distance to 7mil's instead of the current 8 mils. I'm planning on having these PCB's manufactured by Seeed studio and their minimal width is much smaller. Minimum trace width: 6mil Minimum trace/vias/pads space : 6mil Minimum silkscreen width : 4mil Minimum silkscreen text size : 32mil I've used a grid size of 10mil and distances of 8 mils, as I didn't want to rely on the minimum of seed. The silkscreen I positioned using a grid size of 5 mil's however. Not sure what they mean with a 'minimum silkscreen text size' however. Anyhow, feedback greatly appreciated, so I can start working on alternative layouts :)

8 19

fixed AMD SPI speed settings (leading to problems on E350M1/USB3)
by Stefan Tauner Feb. 2, 2014

Feb. 2, 2014

Hi, andor reported a problem where flashrom does reproducibly not work with coreboot but does with the vendor BIOS http://paste.flashrom.org/view.php?id=1614 Apparently it is related to fast reads and/or the frequency. We have forced the fastReadEnable bit in the SPI_Cntrl0 from 1 to 0 and also set NormSpeed in SPI_Cntrl1 to 16.5 Mhz (previously was 0 i.e. 66 MHz) in flashrom and the problem vanished. Coreboot hard codes the fast read setting in src/southbridge/amd/cimx/sb800/bootblock.c: static void enable_spi_fast_mode(void) { u8 byte; u32 dword; device_t dev = PCI_DEV(0, 0x14, 0x03); // set temp MMIO base volatile u32 *spi_base = (void *)0xa0000000; u32 save = pci_io_read_config32(dev, 0xa0); pci_io_write_config32(dev, 0xa0, (u32) spi_base | 2); // early enable of SPI 33 MHz fast mode read byte = spi_base[3]; spi_base[3] = (byte & ~(3 << 14)) | (1 << 14); spi_base[0] = spi_base[0] | (1 << 18); // fast read enable pci_io_write_config32(dev, 0xa0, save); } Marc suggested that this should be configurable in the devicetree or by a kconfig setting. Also, the statements using "byte" do not make a lot of sense to me. Shouldn't that be a u32 instead? The public documentation of the fastReadEnable is lacking any detail and I don't have access to the NDAed version of the RRG. Is my theory correct that the controller uses the 0x0B opcode with a fixed frequency (33 MHz?) instead of 0x03 with the frequency set by NormSpeed? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

#186: 3com 3c905tx / gpxe boot problem
by coreboot Jan. 11, 2014

Jan. 11, 2014

#186: 3com 3c905tx / gpxe boot problem -----------------------------------+---------------------------------- Reporter: jeroenkrabbendam@… | Owner: stepan@… Type: defect | Status: new Priority: minor | Milestone: Component: coreboot | Keywords: gpxe Dependencies: | Patch Status: there is no patch -----------------------------------+---------------------------------- Although (or: just because) novice in the field, I encountered some problems with netbooting with coreboot. Mobo's tried: Asus P2B, VTech with bios id ITE8671-2A69KV3IC-00. All mobo's boot '''harddisk''' fine with Asus P2B / Gigabyte GA-6BX{CE} respectively. NIC ROM is started, and loads the kernel by tftp. This is vvvveeeerrrryyy slow! Although loading, the kernel is never able to start itself. Same kernel on HDU is no problem at all (GRUB2) Note: the gpxe-image is on the nic, coreboot payload is seabios. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/186> coreboot <http://www.coreboot.org/>

1 1

Super I/O: Nuvoton NCT6779D support (Incomplete and stuck)
by Alec Ari Jan. 2, 2014

Jan. 2, 2014

Hello everyone! Please note I am not subscribed to the coreboot mailing list so if you want to contact me, please do so directly or CC my email address. I wrote an incomplete port to the Nuvoton NCT6779D Super I/O chip ( http://review.coreboot.org/4589 ) I am not sure if publicly sharing the datasheet is OK or not (if it is alright, let me know so I can post it as I am not under an NDA with Nuvoton by any means) but anyone with Super I/O and general hardware / electrical engineering should be able to easily finish up the port as most of the work is already done and just needs some tidying up (comments in patch indicate possible issues and things I am stuck on.) The Super I/O is currently used with several ASUS boards such as some of their Intel Z77 chipset motherboards (Sabertooth and Maximus V series) F2A85V-PRO (AMD FM2 A-series CPUs) and possibly a few others. A few other coreboot developers are working on some boards right now that use it, so hopefully my patch will assist their efforts. Thank you, happy coding, and New Years. Alec Ari

1 1

Asus M2V-MX SE: Resume from S3 broken: `CBFS: ERROR: No file header found at 0x0 - try next aligned address: 0x40.`
by Paul Menzel Jan. 2, 2014

Jan. 2, 2014

Dear coreboot folks, using coreboot with the attached configuration (with CBMEM) on the Asus M2V-MX SE [1], resume from S3 does not work for me. $ more serial.log […] [ 818.013737] PM: Syncing filesystems ... done. [ 818.021643] (NULL device *): firmware: agent loaded rt2870.bin into memory [ 818.028721] Freezing user space processes ... (elapsed 0.01 seconds) done. [ 818.050706] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done. [ 818.070691] Suspending console(s) (use no_console_suspend to debug) coreboot-4.0-5045-g0fd505b Tue Dec 17 00:36:07 CET 2013 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8035 pos=0x8a, filtered freq_cap=0x35 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. freq_cap1=0x35, freq_cap2=0x35 dev1 old_freq=0x0, freq=0x5, needs_reset=0x1 dev2 old_freq=0x0, freq=0x5, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x1 after optimize_link_read_pointers_chain, reset_needed=0x1 01K8M890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 01ht reset - soft reset coreboot-4.0-5045-g0fd505b Tue Dec 17 00:36:07 CET 2013 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8035 pos=0x8a, filtered freq_cap=0x35 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. freq_cap1=0x35, freq_cap2=0x35 dev1 old_freq=0x5, freq=0x5, needs_reset=0x0 dev2 old_freq=0x5, freq=0x5, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 00K8M890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 00after enable_fid_change toggle LDTSTP# done Current fid_cur: 0x2, fid_max: 0xa Requested fid_new: 0xa FidVid table step fidvid: 0xa toggle LDTSTP# done toggle LDTSTP# done Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000cfee0 Device error Device error Enabling dual channel memory Unbuffered 400MHz 400MHz set_ecc: ECC disabled Interleaved RAM end at 0x00200000 kB Ram3 IN TEST WAKEUP 400Wakeup! before resume errata #125 before exit errata - timer enabled before exit errata - after mdelay pcidev is 8000c290 after exit errata Exiting memory from self refresh: done DQS RESTORE FROM NVRAM: c2000 Loading 113222 of size 4 to nvram pos:0 Loading 18181718 of size 4 to nvram pos:4 Loading 17171617 of size 4 to nvram pos:8 Loading 16 of size 1 to nvram pos:12 Loading 202520 of size 4 to nvram pos:13 Loading 14141413 of size 4 to nvram pos:17 Loading 16141415 of size 4 to nvram pos:21 Loading 14 of size 1 to nvram pos:25 Loading 29 of size 1 to nvram pos:26 Loading 0 of size 1 to nvram pos:27 Loading 0 of size 1 to nvram pos:28 Loading 0 of size 1 to nvram pos:29 Loading 113222 of size 4 to nvram pos:30 Loading 18171717 of size 4 to nvram pos:34 Loading 16161717 of size 4 to nvram pos:38 Loading 17 of size 1 to nvram pos:42 Loading 202520 of size 4 to nvram pos:43 Loading 14151514 of size 4 to nvram pos:47 Loading 15151414 of size 4 to nvram pos:51 Loading 14 of size 1 to nvram pos:55 Loading 2c of size 1 to nvram pos:56 Loading 0 of size 1 to nvram pos:57 Loading 0 of size 1 to nvram pos:58 Loading 0 of size 1 to nvram pos:59 Loading 7410809b of size 4 to nvram pos:60 Mem running ! Ram4 v_esp=000cff28 IN TEST WAKEUP 400IN TEST WAKEUP 400CBMEM region 7dec0000-7dffffff (cbmem_reinit) IN TEST WAKEUP 400Will copy coreboot region to: 7dedc200 Copying data from cache to RAM -- switching to use RAM as stack... Done Disabling cache as ram now Clearing initial memory region: Loading image. CBFS: ERROR: No file header found at 0x0 - try next aligned address: 0x40. It then just hangs there. $ sudo ./cbmem -l CBMEM table of contents: ID START LENGTH 0. FREE SPACE 7dfe4200 0001be00 1. GDT 7dec0200 00000200 2. CONSOLE 7dec0400 00010000 3. TIME STAMP 7ded0400 00000200 4. ACPI 7ded0600 0000b400 5. SMBIOS 7dedba00 00000800 6. ACPI RESUME 7dedc200 00100000 7. COREBOOT 7dfdc200 00008000 $ sudo cbmem -t # truncated with the error message 10 entries total: 10:start of ramstage Could not open /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq: No such file or directory Thanks, Paul [1] http://www.coreboot.org/ASUS_M2V-MX_SE

3 4

Re: [coreboot] BadBIOS Thoughts
by Alex G. Jan. 1, 2014

Jan. 1, 2014

On 11/20/2013 09:23 AM, ron minnich wrote: > I've got a student coming in January and he's going to work on > ChromeOS on AMD CPUs, starting with the Gizmo. If, at that time, > someone has a suggestion for an AMD laptop which might be suitable, > let me know. Would you care to elaborate on that? As much as I hate HP, they do seem to have some of the best AMD-based laptops. I would look at the ProBook 655 G1 / 645 G1 or the HP ProBook 6475b. Alex P.S. One fornicating annoying downside is that HP's firmware really sucks. Suspend-and-not-crash-and-overheat (TM) is sometimes working, while Resume-and-not-defecate (TM) seems to be slightly more reliable.

3 2

Re: [coreboot] Coreboot and the NSA's expressed preference for subverting BIOSes
by Sam Kuper Dec. 31, 2013

Dec. 31, 2013

On 31/12/2013, David Hendricks <david.hendricks(a)gmail.com> wrote: > On Sun, Dec 29, 2013 at 5:06 PM, David Collier-Brown > <davecb.42(a)gmail.com>wrote: >> May I request you loudly announce how one checksums one's coreboot, >> and in principle other BIOSes, so that one can see if anyone has changed >> firmware critical to one's security. > > For Chromebooks, full verification is built into coreboot and also utilizes > hardware write-protection Which other Coreboot-supported systems/motherboards have hardware write-protection (or can be easily modified to at least write-protect the BIOS)? Regards, Sam

1 0