coreboot December 2013

coreboot@coreboot.org

40 participants
108 discussions

Re: [coreboot] compile coreboot for my lenovo x60s failed with No rule to make target `vgabiosx60s.bin',
by QingPei Wang 24 Dec '13

24 Dec '13

it looks like you do not put your vgabios into the proper place. Coreboot does not compile that, then you need to find the vgabios by yourself or you just disable the vgabios from the config file Best wishes QingPei Wang Phone: 86+18930528086 On Tue, Dec 24, 2013 at 3:25 PM, Ye Jincai <samssmarm(a)gmail.com> wrote: > Merry Chrismas Eeverone, > > I compile coreboot for my lenovo failed with , where can i sovle the > vgabiosx60s.bin missing, thanks advances! > > SCONFIG mainboard/lenovo/x60/devicetree.cb > CC mainboard/lenovo/x60/static.romstage.o > CC arch/x86/boot/cbmem.romstage.o > CC arch/x86/lib/cbfs_and_run.romstage.o > CC arch/x86/lib/memcpy.romstage.o > CC arch/x86/lib/memmove.romstage.o > CC arch/x86/lib/memset.romstage.o > CC arch/x86/lib/rom_media.romstage.o > CC arch/x86/lib/romstage_console.romstage.o > CC console/console.romstage.o > CC console/die.romstage.o > CC console/post.romstage.o > CC console/vtxprintf.romstage.o > CC cpu/x86/car.romstage.o > CC cpu/x86/lapic/apic_timer.romstage.o > CC cpu/x86/lapic/boot_cpu.romstage.o > CC device/device_romstage.romstage.o > CC drivers/pc80/mc146818rtc_early.romstage.o > CC ec/lenovo/pmh7/pmh7.romstage.o > CC lib/cbfs.romstage.o > CC lib/cbmem.romstage.o > CC lib/cbmem_console.romstage.o > CC lib/compute_ip_checksum.romstage.o > CC lib/gcc.romstage.o > CC lib/lzma.romstage.o > CC lib/memchr.romstage.o > CC lib/memcmp.romstage.o > CC lib/ramtest.romstage.o > CC lib/timestamp.romstage.o > CC lib/uart8250.romstage.o > CC mainboard/lenovo/x60/dock.romstage.o > CC northbridge/intel/i945/debug.romstage.o > CC northbridge/intel/i945/early_init.romstage.o > CC northbridge/intel/i945/errata.romstage.o > CC northbridge/intel/i945/raminit.romstage.o > CC southbridge/intel/i82801gx/early_lpc.romstage.o > CC southbridge/intel/i82801gx/early_smbus.romstage.o > GEN generated/romstage_null.ld > HOSTCC util/romcc/romcc (this may take a while) > ROMCC generated/bootblock.inc > GEN generated/bootblock_inc.S > CC generated/bootblock.s > CC generated/bootblock.o > GEN generated/bootblock.ld > LINK cbfs/fallback/bootblock.debug > OBJCOPY cbfs/fallback/bootblock.elf > OBJCOPY cbfs/fallback/bootblock.bin > OPTION cmos_layout.bin > make: *** No rule to make target `vgabiosx60s.bin', needed by > `build/coreboot.pre1'. Stop. > > -- > Fourier > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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compile coreboot for my lenovo x60s failed with No rule to make target `vgabiosx60s.bin',
by Ye Jincai 24 Dec '13

24 Dec '13

Merry Chrismas Eeverone, I compile coreboot for my lenovo failed with , where can i sovle the vgabiosx60s.bin missing, thanks advances! SCONFIG mainboard/lenovo/x60/devicetree.cb CC mainboard/lenovo/x60/static.romstage.o CC arch/x86/boot/cbmem.romstage.o CC arch/x86/lib/cbfs_and_run.romstage.o CC arch/x86/lib/memcpy.romstage.o CC arch/x86/lib/memmove.romstage.o CC arch/x86/lib/memset.romstage.o CC arch/x86/lib/rom_media.romstage.o CC arch/x86/lib/romstage_console.romstage.o CC console/console.romstage.o CC console/die.romstage.o CC console/post.romstage.o CC console/vtxprintf.romstage.o CC cpu/x86/car.romstage.o CC cpu/x86/lapic/apic_timer.romstage.o CC cpu/x86/lapic/boot_cpu.romstage.o CC device/device_romstage.romstage.o CC drivers/pc80/mc146818rtc_early.romstage.o CC ec/lenovo/pmh7/pmh7.romstage.o CC lib/cbfs.romstage.o CC lib/cbmem.romstage.o CC lib/cbmem_console.romstage.o CC lib/compute_ip_checksum.romstage.o CC lib/gcc.romstage.o CC lib/lzma.romstage.o CC lib/memchr.romstage.o CC lib/memcmp.romstage.o CC lib/ramtest.romstage.o CC lib/timestamp.romstage.o CC lib/uart8250.romstage.o CC mainboard/lenovo/x60/dock.romstage.o CC northbridge/intel/i945/debug.romstage.o CC northbridge/intel/i945/early_init.romstage.o CC northbridge/intel/i945/errata.romstage.o CC northbridge/intel/i945/raminit.romstage.o CC southbridge/intel/i82801gx/early_lpc.romstage.o CC southbridge/intel/i82801gx/early_smbus.romstage.o GEN generated/romstage_null.ld HOSTCC util/romcc/romcc (this may take a while) ROMCC generated/bootblock.inc GEN generated/bootblock_inc.S CC generated/bootblock.s CC generated/bootblock.o GEN generated/bootblock.ld LINK cbfs/fallback/bootblock.debug OBJCOPY cbfs/fallback/bootblock.elf OBJCOPY cbfs/fallback/bootblock.bin OPTION cmos_layout.bin make: *** No rule to make target `vgabiosx60s.bin', needed by `build/coreboot.pre1'. Stop. -- Fourier

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Re: [coreboot] Binary situation
by Sam Kuper 24 Dec '13

24 Dec '13

On 24/12/2013, David Hubbard <david.c.hubbard+coreboot(a)gmail.com> wrote: > On Mon, Dec 23, 2013 at 3:21 PM, Rudolf Marek <r.marek(a)assembler.cz> wrote: >> Some time ago Patrick started a >> https://www.coreboot.org/Binary_situation page which I updated in the past >> days. It monitors the various blobs and >> firmwares in the Intel and AMD systems. Great work, thank you! > It might be helpful to document the intended use case for each device. > Basically, the industry has started using overloaded meanings for words > that a newcomer might find hard to decipher. As a newcomer, I agree :)

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Binary situation
by Rudolf Marek 24 Dec '13

24 Dec '13

Hi all https://www.coreboot.org/Binary_situation Some time ago Patrick started a https://www.coreboot.org/Binary_situation page which I updated in the past days. It monitors the various blobs and firmwares in the Intel and AMD systems. Good news is that Roxfan and I managed to get some ideas about AMD XHCI firmware and I added also some information about SMU, GEC and IMC firmwares. The page has some links were you can get more detailed information. As for now it looks we now know all processors types for each firmware :) Please don't expect more about that, it could be small step for some future "free" firmwares, but for me it current state enough. As for the AMD systems, XHCI firmware "bad" intentions can be most likely stopped by IOMMU, same is valid for "GEC". IMC can be safely left unused. This leaves only the SMU firmware which may or may not have some DMA capability. As for the Intel systems, my biggest fear is ME firmware, which is even designed to do things sideways. From all above think best would be to concentrate on VGA BIOS replacements and possibly a MRC.bin replacement, which runs on x86 CPU. I'm considering the rest of the firmwares as part of the hardware although it would be nice to audit at least the function which could be now possible even it will take long time. Please try not to start any flamewar about "firmwares should be free" instead please help and audit the firmwares or write a replacements. Please note that even devices without any loadable firmware may do bad things. Don't forget about that. Firmwares just gives us good opportunity to see things otherwise impossible to see (chip mask rom for example). Thanks Rudolf

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#200: How Many Calories Are In A Hardees Bacon Egg And Cheese Biscuit
by coreboot 23 Dec '13

23 Dec '13

#200: How Many Calories Are In A Hardees Bacon Egg And Cheese Biscuit ----------------------------------+---------------------------------- Reporter: mikayla-battles@… | Owner: uwe@… Type: enhancement | Status: new Priority: major | Milestone: Cosmetic fixes Component: coreinfo | Keywords: bacon bacon bacon Dependencies: | Patch Status: there is no patch ----------------------------------+---------------------------------- Scoop out just what we need every morning plus microwave. At this point it ought to be cooked enough to hold its form. Also, you might lose out on vital vitamins plus minerals these as vitamin D plus zinc. Add the rocket to the different cut and wait for the bacon to cook how you like it. When you've had several practice with how to create homemade bacon, you are able to striving changing it. Performing such queries appears to be rather addictive because Internet points out, as those that try to stump the algorithm tend to run out of celebrities before Google runs out of answers. Scallops could be fried, broiled, or baked into a casserole. However now they have won and is indexed amidst the Golden Globe Awards winners, which is no mean feat. Should you enjoy sub sandwiches, you might discover the diet effortless to keep. However, one look at the labels of these goods shows how chemically processed these products is. Bacon's Essays enjoy a excellent charm and appeal for visitors thanks to their numerous merits or attributes like wisdom, marvelous diction, captivating design of composing, big range of topics, pragmatic approach, sensuousness, wealth of metaphor plus analogy as well as the dispersed meditations of Bacon, whose sharp wit, worldly wisdom and practical approach towards aspects prepared his essays unsurpassable plus masterpieces of English literature. Folks all over may be found United Nations agency are attempting to create inside choices thus as to attain success inside existence.<br><br>It appears which no matter what you makes, bacon only makes it greater. I was interesting in finding more info on this firm whilst writing this food product review! With this performed, remove the entrails carefully, proceeding inside much the same way as in removing the entrails of a poultry. Whole Foods tends to stock Vosges chocolate as do other specialty food retailers, but you are able to also order it online when you can't find it nearby. So, the wellness benefits of bacon are nor absolutely as few as frequently portrayed. Bake at 375 for about 25 to 25 minutes, until [http://bacon4.me/ bacon] reaches desired doneness. Some of these methods were even chosen to protect eyes from dangerous glare - performing because a make-shift pair of sunglasses. Today's glasses aren't prepared with the same standard materials because they used to be considering people aren't wearing the same pair of eyeglasses for because long as they utilized to. Local diners served steamed mussels in a fragrant broth, which is best sopped up with a good piece of crusty bread. I have moreover come up with the bacon-chocolate law: which which can not be improved by the addition of bacon could be produced better by adding chocolate. In these a ham, the proportion of fat plus lean is about right, however whenever ham is bought with all the rind removed, much of the fat is moreover taken off. The shell fishermen and ladies inside the OysterFest shucking competition can come out 24 perfect oysters found on the half-shell in really a couple of minutes.<br><br>Five Best Bacon Wrapped Appetizers Unless on a special diet, most people love bacon. 1 fourth teaspoon of cayenne pepper f. Baking soda and vinegar breaks down fat residue plus freshen the drain of unpleasant odours. They are made basically from Egg whites, soybean oil, textured soy protein concentrate, modified corn starch, wheat gluten, all-natural and artificial tastes from non-meat sources. This is a great dip recipe for tomato bacon dip. Rub the scallops with salt and pepper plus then add the tomato and olive oil mixture with it. I turned over the slices with tongs and got them crispy about both sides. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/200> coreboot <http://www.coreboot.org/>

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[ANNOUNCE] SeaBIOS 1.7.4
by Kevin O'Connor 23 Dec '13

23 Dec '13

The 1.7.4 version of SeaBIOS has now been released. For more information on the release, please see: http://seabios.org/Releases New in this release: * Support for obtaining ACPI tables directly from QEMU. * Initial support for XHCI USB controllers (initially for QEMU only). * Support for booting from "pvscsi" devices on QEMU. * Enhanced floppy driver - improved support for real hardware. * coreboot cbmem console support. * Optional support for using the 9-segment instead of the e-segment for local variables. * Improved internal timer code and accuracy. * SeaVGABIOS improvements * Better support for legacy X.org releases with incomplete x86emu emulation. * Support for using an internal stack to reduce caller's stack usage. * Back port of new "bochs dispi" interface video modes. * Several bug fixes and code cleanups * Source code separated out into additional hardware and firmware directories. * Update to latest version of Kconfig For information on obtaining SeaBIOS, please see: http://seabios.org/Download

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Re: [coreboot] coreboot on amd A85 can't work
by Rudolf Marek 23 Dec '13

23 Dec '13

Hi 陈军根, Please put to cc the mailing list. > I can't find spdAddressLookup in dimmSpd.c(coreboot v4),but I find Ahh yes it seems to move to generic wrapper code. You will need to modify devicetree.cb where is the table and then it is generated as static.c > ROMSTAGE_CONST struct northbridge_amd_agesa_family15tn_config ROMSTAGE_CONST > northbridge_amd_agesa_family15tn_info_6 = { > .spdAddrLookup = > { > { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD > addresses > { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD > addresses > }, > }; > in build/mainboard/asus/f2a85-m/static.c > I changed the spdAddrLookup to > { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses > { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD > addresses > and > { {0xA0, 0x00}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses > { {0xA2, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD > addressese > > but I got the same error messages > > "assertion Failed:file > > 'src/vendorcode/amd/agesa/f15tn/proc/mem/main/mmexcludedimm.c',line 236". > Do you have other options? Yes, we need to find out what is the right mapping for the SPD, and that SPD can be read. Yes you will need to do the i2c SPD address mapping procedure as I described in last email: > If you don't like the ad-hoc method, try booting original BIOS with only one DIMM in chanel 0 and do following from Linux: > > modprobe i2c-dev > modprobe i2c-piix4 > i2cdetect -l > > This will show i2c bus of PIIX4 aka hudson, if you have a video drivers loaded it will be some non-zero number. I use zero as an example: > > i2cdetect 0 > > This will detect the chips on SPD bus. If you plug your DIMM to channel zero and see address 0x50 is used then the first line has valid first entry. The second entry in first line will be zero for you because you have only 2 dimms. > > So repeat the steps and plug it to second slot and see what address you will get. It could be 0x51 or 0x52 as suggested above. You could also check if you get at least some valid data. You can do that by adding some debug information to readspd() in coreboot/src/northbridge/amd/agesa/family15tn/dimmSpd.c Maybe someone put some multiplexer or you have SPD on secondary controller. You will need to include #include <console/console.h> and do printk(BIOS_DEBUG, "...%x ...", ....) Then you can also enable debug messages for AGESA, which you can do by uncommenting #define IDSOPT_IDS_ENABLED in mainboard directory OptionsIds.h I dont think we have a menu config option for that... we should have... I hope it will work. we are usually also on IRC channel #coreboot at irc.freenode.net Btw does your memory need 1.3 1.5 or 1.65 volts? Can you check original BIOS what is the voltage applied there? Thanks Rudolf > thank you very much! > cjg > > ------------------ Original ------------------ > *From: * "Rudolf Marek"<r.marek(a)assembler.cz>; > *Date: * Tue, Dec 17, 2013 03:57 PM > *To: * "陈军根"<cjg(a)bolod.net>; > *Cc: * "coreboot"<coreboot(a)coreboot.org>; > *Subject: * Re: [coreboot] coreboot on amd A85 can't work > On 13.12.2013 08:57, 陈军根 wrote: > > Dear all: > > I run coreboot in ASUS F2A85-MLE CPU is A10-5800k, kingston ddr3 > > Hi > > Please note that the board is F2A85-M without the "LE". Maybe there is something > different. Try using only one dimm in different slots. > > The "M" version has 4 DIMMS your seems to use only 2 dimms: You can also try to > edit: > > spdAddressLookup in dimmSpd.c in the mainboard directory. > // socket 0 > { > > {0x50 << 1, 0x52 << 1}, // channel 0 dimms > {0x51 << 1, 0x53 << 1}, // channel 1 dimms > > To something else like: > > {0x50 << 1, 0x00}, // channel 0 dimms > {0x51 << 1, 0x00}, // channel 1 dimms > Or: > > {0x50 << 1, 0x00}, // channel 0 dimms > {0x52 << 1, 0x00}, // channel 1 dimms > > If you don't like the ad-hoc method, try booting original BIOS with only one > DIMM in chanel 0 and do following from Linux: > > modprobe i2c-dev > modprobe i2c-piix4 > i2cdetect -l > > This will show i2c bus of PIIX4 aka hudson, if you have a video drivers loaded > it will be some non-zero number. I use zero as an example: > > i2cdetect 0 > > This will detect the chips on SPD bus. If you plug your DIMM to channel zero and > see address 0x50 is used then the first line has valid first entry. The second > entry in first line will be zero for you because you have only 2 dimms. > > So repeat the steps and plug it to second slot and see what address you will > get. It could be 0x51 or 0x52 as suggested above. > > Thanks > Rudolf > > > 1600(kvr1600d3n9/4g),coreboot halt at "assertion Failed:file > > 'src/vendorcode/amd/agesa/f15tn/proc/mem/main/mmexcludedimm.c',line 236". I > > don't know how to do, can anyone help me? > > thanks very much! > > > >

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Re: [coreboot] coreboot on amd A85 can't work
by Rudolf Marek 21 Dec '13

21 Dec '13

> I have had great success with an AMD A10-5800K using an ASUS F2A85-M/CSM Hi David, Please note that cjg has a different motherboard. It is a "LE" version with only two dimm slots. Thanks Rudolf > > David > > > On Fri, Dec 20, 2013 at 8:31 PM, 陈军根 <cjg(a)bolod.net <mailto:cjg@bolod.net>> > wrote: > > hello,David: > I turn on the debug message and save the message to file(minicom4.cap in > attachment) ,I'm a newer with coreboot, and I can't find what's wrong with > the DIMM,would you kindly look this document? > And which type of CPU is in your booted ok mainboard? > thank you very much__ > ------------------ Original ------------------ > *From: * "David Hubbard"<david.c.hubbard+coreboot(a)gmail.com > <mailto:david.c.hubbard%2Bcoreboot@gmail.com>>; > *Date: * Tue, Dec 17, 2013 05:56 AM > *To: * "Idwer Vollering"<vidwer(a)gmail.com <mailto:vidwer@gmail.com>>; __ > *Cc: * "coreboot"<coreboot(a)coreboot.org <mailto:coreboot@coreboot.org>>; "陈 > 军根"<cjg(a)bolod.net <mailto:cjg@bolod.net>>; __ > *Subject: * Re: [coreboot] coreboot on amd A85 can't work > I am also very familiar with that particular message. I had a failing CPU > and I ended up replacing parts until it booted ok. > > Like Idwer said: it is not able to initialize any DDR3 RAM. There is a > #define that will turn on verbose output about the DDR3 link training if the > Vendor BIOS (from Asus) thinks the memory is ok. > > David > __ > > > >

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Re: [coreboot] coreboot on amd A85 can't work
by David Hubbard 21 Dec '13

21 Dec '13

On Sat, Dec 21, 2013 at 12:03 AM, 陈军根 <cjg(a)bolod.net> wrote: > David: > I will buy a new A10-5800k CPU and try again, Your mainboard cound > not work at first,did it work ok Olny replaced a CPU ? and which type DDR3 > RAM is in your mainboard? > thanks. > The F2A85 worked ok and I replaced the CPU. I replaced an A10-5800K with an A10-5800K, but the second one worked. I have this ram in the board (2 x 2GB): G.SKILL 2GB 240-Pin DDR3 1600 (PC3 12800) F3-12800CL9D-4GBNQ http://www.newegg.com/Product/Product.aspx?Item=N82E16820231193 > > > ------------------ Original ------------------ > *From: * "David Hubbard"<david.c.hubbard+coreboot(a)gmail.com>; > *Date: * Sat, Dec 21, 2013 02:46 PM > *To: * "陈军根"<cjg(a)bolod.net>; "Coreboot"<coreboot(a)coreboot.org>; > *Subject: * Re: [coreboot] coreboot on amd A85 can't work > > Ok, the log looks like the one I got when my machine was unable to find > the RAM. > > I suggest a different CPU. I realize that's a hard thing to do, and it's > ok to use the exact same type of CPU (A10-5800K). It fixed the problem for > my F2A85 and A10-5800K. > > The only other option I can think of is to not use coreboot, just stick > with the vendor BIOS. But I am willing to try things until coreboot works > for you. > > Rudolf Marek and some of the people at sage (se-eng.com) may have other > suggestions. > > David >

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Re: [coreboot] coreboot on amd A85 can't work
by David Hubbard 21 Dec '13

21 Dec '13

Ok, the log looks like the one I got when my machine was unable to find the RAM. I suggest a different CPU. I realize that's a hard thing to do, and it's ok to use the exact same type of CPU (A10-5800K). It fixed the problem for my F2A85 and A10-5800K. The only other option I can think of is to not use coreboot, just stick with the vendor BIOS. But I am willing to try things until coreboot works for you. Rudolf Marek and some of the people at sage (se-eng.com) may have other suggestions. David

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coreboot December 2013