coreboot August 2012

coreboot@coreboot.org

30 participants
321 discussions

Patch set updated for coreboot: df28e7e VIA Nano: Add support for VIA Nano CPUs
by Alexandru Gagniuc 27 Aug '12

27 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1257 -gerrit commit df28e7ec541ab07bdf1814720c4302e7b2bab1ba Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Aug 7 19:38:32 2012 -0500 VIA Nano: Add support for VIA Nano CPUs Add code to do the following for the VIA Nano CPUs - Update microcode - Set maximum frequency - Initialize power states - Set up cache Attempting to change the voltage or frequency of the CPU without applying the microcode update will hang the CPU, so we only do transitions if we can verify the microcode has been updated. The microcode is updated directly from CBFS. No microcode is included in ramstage. The microcode is not included in this commit. To get the microcode, run bios_extract on the manufacturer supplied BIOS, and look for the file marked "P6 Microcode". Include this file in CBFS. You can have the build system include this file automatically by selecting Expert Mode, then look under 'Chipset' -> 'Include CPU microcode in CBFS' -> Include external microcode file (check) 'Path and filename of CPU microcode' should contain the location of the microcode file previously extracted. Change-Id: I586aaca5715e047b42ef901d66772ace0e6b655e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/via/Kconfig | 1 + src/cpu/via/Makefile.inc | 6 +- src/cpu/via/nano/Kconfig | 41 ++++++++ src/cpu/via/nano/Makefile.inc | 33 +++++++ src/cpu/via/nano/nano_init.c | 204 ++++++++++++++++++++++++++++++++++++++++ src/cpu/via/nano/update_ucode.c | 150 +++++++++++++++++++++++++++++ src/cpu/via/nano/update_ucode.h | 73 ++++++++++++++ 7 files changed, 505 insertions(+), 3 deletions(-) diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig index 570d408..5c38c91 100644 --- a/src/cpu/via/Kconfig +++ b/src/cpu/via/Kconfig @@ -1,2 +1,3 @@ source src/cpu/via/c3/Kconfig source src/cpu/via/c7/Kconfig +source src/cpu/via/nano/Kconfig diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc index 2616111..f1e198d 100644 --- a/src/cpu/via/Makefile.inc +++ b/src/cpu/via/Makefile.inc @@ -1,3 +1,3 @@ -subdirs-$(CONFIG_CPU_VIA_C7) += c7 -subdirs-$(CONFIG_CPU_VIA_C3) += c3 - +subdirs-$(CONFIG_CPU_VIA_C7) += c7 +subdirs-$(CONFIG_CPU_VIA_C3) += c3 +subdirs-$(CONFIG_CPU_VIA_NANO) += nano diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig new file mode 100644 index 0000000..3b1c213 --- /dev/null +++ b/src/cpu/via/nano/Kconfig @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +config CPU_VIA_NANO + bool + +if CPU_VIA_NANO + +config CPU_SPECIFIC_OPTIONS + def_bool y + select UDELAY_TSC + select MMX + select SSE2 + select CACHE_AS_RAM + select CPU_MICROCODE_IN_CBFS + +config DCACHE_RAM_BASE + hex + default 0xffe00000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif # CPU_VIA_NANO diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc new file mode 100644 index 0000000..6b0c1e9 --- /dev/null +++ b/src/cpu/via/nano/Makefile.inc @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm + +driver-y += nano_init.c +ramstage-y += update_ucode.c + +# We need to hear from VIA to get permission to include this file in the +# official coreboot repository. Until then, we leave this commented out +# cpu-microcode-y += nano_ucode_blob.c + +cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c new file mode 100644 index 0000000..417119f --- /dev/null +++ b/src/cpu/via/nano/nano_init.c @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "update_ucode.h" +#include <console/console.h> +#include <device/device.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <delay.h> + +#define MODEL_NANO 0x2 +#define MODEL_NANO_3000_B0 0x8 +#define MODEL_NANO_3000_B2 0xa + +#define MSR_IA32_PERF_STATUS 0x00000198 +#define MSR_IA32_PERF_CTL 0x00000199 +#define MSR_IA32_MISC_ENABLE 0x000001a0 +#define NANO_MYSTERIOUS_MSR 0x120e + +static void nano_finish_fid_vid_transition(void) +{ + + msr_t msr; + /* Wait until the power transition ends */ + int cnt = 0; + do { + udelay(16); + msr = rdmsr(MSR_IA32_PERF_STATUS); + cnt++; + if (cnt > 128) { + printk(BIOS_WARNING, + "Error while updating multiplier and voltage\n"); + break; + } + } while (msr.lo & ((1 << 16) | (1 << 17))); + + /* Print the new FID and Voltage */ + u8 cur_vid = (msr.lo >> 0) & 0xff; + u8 cur_fid = (msr.lo >> 8) & 0xff; + printk(BIOS_INFO, "New CPU multiplier: %dx\n", cur_fid); + printk(BIOS_INFO, "New Voltage ID : %dx\n", cur_vid); +} + +static void nano_set_max_fid_vid(void) +{ + msr_t msr; + /* Get voltage and frequency info */ + msr = rdmsr(MSR_IA32_PERF_STATUS); + u8 min_fid = (msr.hi >> 24); + u8 max_fid = (msr.hi >> 8) & 0xff; + u8 min_vid = (msr.hi >> 16) & 0xff; + u8 max_vid = (msr.hi >> 0) & 0xff; + u8 cur_vid = (msr.lo >> 0) & 0xff; + u8 cur_fid = (msr.lo >> 8) & 0xff; + + printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n", + cur_fid, min_fid, max_fid); + printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n", + cur_vid, min_vid, max_vid); + + if( (cur_fid != max_fid) || (cur_vid != max_vid) ) { + /* Set highest frequency and VID */ + msr.lo = msr.hi; + msr.hi = 0; + wrmsr(MSR_IA32_PERF_CTL, msr); + /* Wait for the transition to complete, otherwise, the CPU + * might reset itself repeatedly */ + nano_finish_fid_vid_transition(); + } + /* As a side note, if we didn't update the microcode by this point, the + * second PLL will not lock correctly. The clock will still be provided + * by the first PLL, and execution will continue normally, ___until___ + * the CPU switches PLL. Once that happens we will no longer have a + * working clock source, and the CPU will hang + * Moral of the story: update the microcode, or don't change FID + * This check is handled before calling nano_power() */ +} + +static void nano_power(void) +{ + msr_t msr; + /* Enable Powersaver */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= (1 << 16); + wrmsr(MSR_IA32_MISC_ENABLE, msr); + + /* Enable 6 bit or 7-bit VRM support + * This MSR is not documented by VIA docs, other than setting these + * bits */ + msr = rdmsr(NANO_MYSTERIOUS_MSR); + msr.lo |= ( (1<<7) | (1<<4) ); + /* FIXME: Do we have a 6-bit or 7-bit VRM? + * set bit [5] for 7-bit, or don't set it for 6 bit VRM + * This will probably require a Kconfig option + * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */ + msr.lo |= (1<<5); + wrmsr(NANO_MYSTERIOUS_MSR, msr); + + /* Set the maximum frequency and voltage */ + nano_set_max_fid_vid(); + + /* Enable TM3 */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= ( (1<<3) | (1<<13) ); + wrmsr(MSR_IA32_MISC_ENABLE, msr); + + u8 stepping = ( cpuid_eax(0x1) ) &0xf; + if(stepping >= MODEL_NANO_3000_B0) { + /* Hello Nano 3000. The Terminator needs a CPU upgrade */ + /* Enable C1e, C2e, C3e, and C4e states */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= ( (1<<25) | (1<<26) | (1<<31)); /* C1e, C2e, C3e */ + msr.hi |= (1<<0); /* C4e */ + wrmsr(MSR_IA32_MISC_ENABLE, msr); + } + + /* Lock on Powersaver */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= (1<<20); + wrmsr(MSR_IA32_MISC_ENABLE, msr); +} + +static void nano_init(device_t dev) +{ + struct cpuinfo_x86 c; + + get_fms(&c, dev->device); + + /* We didn't test this on the Nano 1000/2000 series, so warn the user */ + if(c.x86_mask < MODEL_NANO_3000_B0) { + printk(BIOS_EMERG, "WARNING: This CPU has not been tested. " + "Please report any issues encountered. \n"); + } + switch (c.x86_mask) { + case MODEL_NANO: + printk(BIOS_INFO, "VIA Nano"); + break; + case MODEL_NANO_3000_B0: + printk(BIOS_INFO, "VIA Nano 3000 rev B0"); + break; + case MODEL_NANO_3000_B2: + printk(BIOS_INFO, "VIA Nano 3000 rev B2"); + break; + default: + printk(BIOS_EMERG, "Stepping not recognized: %x\n", c.x86_mask); + } + printk(BIOS_INFO, "\n"); + + /* We only read microcode from CBFS. If we don't have any microcode in + * CBFS, we'll just get back with 0 updates. User choice FTW. */ + unsigned int n_updates = nano_update_ucode(); + + if(n_updates != 0){ + nano_power(); + } else { + /* Changing the frequency or voltage without first updating the + * microcode will hang the CPU, so just don't do it */ + printk(BIOS_EMERG, "WARNING: CPU Microcode not updated.\n" + " Will not change frequency, as this may hang the CPU.\n"); + } + + /* Turn on cache */ + x86_enable_cache(); + /* Set up Memory Type Range Registers */ + x86_setup_mtrrs(); + x86_mtrr_check(); + /* Enable the local cpu apics */ + setup_lapic(); +} + +static struct device_operations cpu_dev_ops = { + .init = nano_init, +}; + +static struct cpu_device_id cpu_table[] = { + {X86_VENDOR_CENTAUR, 0x06f2}, // VIA NANO 1000/2000 Series + {X86_VENDOR_CENTAUR, 0x06f8}, // VIA NANO 3000 rev B0 + {X86_VENDOR_CENTAUR, 0x06fa}, // VIA NANO 3000 rev B2 + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c new file mode 100644 index 0000000..8f7ee22 --- /dev/null +++ b/src/cpu/via/nano/update_ucode.c @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "update_ucode.h" +#include <cpu/x86/msr.h> +#include <console/console.h> +#include <stddef.h> +#include <cpu/cpu.h> +#include <arch/cpu.h> +#include <cbfs.h> + +static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode) +{ + printk(BIOS_SPEW, "Attempting to apply microcode update\n"); + + msr_t msr; + /* Address of ucode block goes in msr.lo for 32-bit mode + * Now remember, we need to pass the address of the actual microcode, + * not the header. The header is just there to help us. */ + msr.lo = (unsigned int)(&(ucode->ucode_start)); + msr.hi = 0; + wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr); + + /* Let's see if we updated succesfully */ + msr = rdmsr(MSR_UCODE_UPDATE_STATUS); + + return msr.lo & 0x07; +} + +static void nano_print_ucode_info(const nano_ucode_header *ucode) +{ + printk(BIOS_SPEW, "Microcode update information:\n"); + printk(BIOS_SPEW, "Name: %8s\n", ucode->name ); + printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month, + ucode->day, ucode->year ); +} + +static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) +{ + /* We must have a valid signature */ + if(ucode->signature != NANO_UCODE_SIGNATURE) + return NANO_UCODE_SIGNATURE_ERROR; + /* The size of the head must be exactly 12 double words */ + if( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE) + return NANO_UCODE_WRONG_SIZE; + + /* How about a checksum ? Checksum must be 0 + * Two's complement done over the entire file, including the header */ + int i; + u32 check = 0; + u32 *raw = (void*) ucode; + for(i = 0 ; i < ((ucode->total_size) >> 2); i++) { + check += raw[i]; + } + if(check != 0) + return NANO_UCODE_CHECKSUM_FAIL; + /* Made it here huh? Then it looks valid to us. + * If there's anything else wrong, the CPU will reject the update */ + return NANO_UCODE_VALID; +} + +static void nano_print_ucode_status(ucode_update_status stat) +{ + switch(stat) + { + case UCODE_UPDATE_SUCCESS: + printk(BIOS_INFO, "Microcode update succesful.\n"); + break; + case UCODE_UPDATE_FAIL: + printk(BIOS_ALERT, "Microcode update failed, bad environment." + "Update was not applied.\n"); + break; + case UCODE_UPDATE_WRONG_CPU: + printk(BIOS_ALERT, "Update not applicable to this CPU.\n"); + break; + case UCODE_INVALID_UPDATE_BLOCK: + printk(BIOS_ALERT, "Microcode block invalid." + "Update was not applied.\n"); + break; + default: + printk(BIOS_ALERT, "Unknown status. No update applied.\n"); + } +} + +unsigned int nano_update_ucode(void) +{ + size_t i; + unsigned int n_updates = 0; + const struct cbfs_file *cbfs_ucode; + u32 fms = cpuid_eax(0x1); + + cbfs_ucode = cbfs_find("cpu_microcode_blob.bin"); + /* Oops, did you forget to include the microcode ? */ + if(cbfs_ucode == NULL) { + printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. " + "Aborting microcode updates\n"); + return 0; + } + + /* Considering we are running with eXecute-In-Place (XIP), there's no + * need to worry that accessing data from ROM will slow us down. + * Microcode data should be aligned to a 4-byte boundary, but CBFS + * already does that for us (Do you, CBFS?) */ + const u32 *ucode_data = CBFS_SUBHEADER(cbfs_ucode); + const u32 ucode_len = ntohl(cbfs_ucode->len); + + /* We might do a lot of loops searching for the microcode updates, but + * keep in mind, nano_ucode_is_valid searches for the signature before + * doing anything else. */ + for( i = 0; i < (ucode_len >> 2); /* don't increment i here */ ) + { + ucode_update_status stat; + const nano_ucode_header * ucode = (void *)(&ucode_data[i]); + if(nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) { + i++; + continue; + } + /* Since we have a valid microcode, there's no need to search + * in this region, so we restart our search at the end of this + * microcode */ + i += (ucode->total_size >> 2); + /* Is the microcode compatible with our CPU? */ + if(ucode->applicable_fms != fms) continue; + /* For our most curious users */ + nano_print_ucode_info(ucode); + /* The meat of the pie */ + stat = nano_apply_ucode(ucode); + /* The user might want to know how the update went */ + nano_print_ucode_status(stat); + if(stat == UCODE_UPDATE_SUCCESS) n_updates++; + } + + return n_updates; +} diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h new file mode 100644 index 0000000..6a22d18 --- /dev/null +++ b/src/cpu/via/nano/update_ucode.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __UPDATE_UCODE_H +#define __UPDATE_UCODE_H + +#include <console/console.h> +#include <cpu/cpu.h> + +#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 +#define MSR_IA32_BIOS_SIGN_ID 0x0000008b +#define MSR_UCODE_UPDATE_STATUS 0x00001205 + +#define NANO_UCODE_SIGNATURE 0x53415252 +#define NANO_UCODE_HEADER_SIZE 0x30 + +/* These are values returned by the CPU after we attempt microcode updates. + * We care what these values are exactly, so we define them to be sure */ +typedef enum { + UCODE_UPDATE_NOT_ATTEMPTED = 0x0, + UCODE_UPDATE_SUCCESS = 0x1, + UCODE_UPDATE_FAIL = 0x2, + UCODE_UPDATE_WRONG_CPU = 0x3, + UCODE_INVALID_UPDATE_BLOCK = 0x4, +} ucode_update_status; + + +typedef enum { + NANO_UCODE_VALID = 0, /* We only care that valid == 0 */ + NANO_UCODE_SIGNATURE_ERROR, + NANO_UCODE_WRONG_SIZE, + NANO_UCODE_CHECKSUM_FAIL, +} ucode_validity; + +typedef struct { + u32 signature; /* NANO_UCODE_SIGNATURE */ + u32 update_revision; /* Revision of the update header */ + u16 year; /* Year of patch release */ + u8 day; /* Day of patch release */ + u8 month; /* Month of patch release */ + u32 applicable_fms; /* Fam/model/stepping to which ucode applies */ + u32 checksum; /* Two's complement checksum of ucode+header */ + u32 loader_revision; /* Revision of hardware ucode update loader*/ + u32 rfu_1; /* Reservod for future use */ + u32 payload_size; /* Size of the ucode payload only */ + u32 total_size; /* Size of the ucode, including header */ + char name[8]; /* ASCII string of ucode filename */ + u32 rfu_2; /* Reservod for future use */ + /* First double-word of the ucode payload + * Its address represents the beginning of the ucode update we need to + * send to the CPU */ + u32 ucode_start; + +} nano_ucode_header; + +unsigned int nano_update_ucode(void); + +#endif /* __UPDATE_UCODE_H */

1 0

Patch set updated for coreboot: f9db41b buildsystem: Make CPU microcode updating more configurable
by Alexandru Gagniuc 27 Aug '12

27 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245 -gerrit commit f9db41bf4575235910a6488d840127c2be7b449f Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jul 20 00:11:21 2012 -0500 buildsystem: Make CPU microcode updating more configurable This patch aims to improve the microcode in CBFS handling that was brought by the last patches from Stefan and the Chromium team. Choices in Kconfig - 1) Generate microcode from tree (default) - 2) Include external microcode file - 3) Do not put microcode in CBFS The idea is to give the user full control over including non-free blobs in the final ROM image. MICROCODE_INCLUDE_PATH Kconfig variable is eliminated. Microcode is handled by a special class, cpu_microcode, as such: cpu_microcode-y += microcode_file.c MICROCODE_IN_CBFS should, in the future, be eliminated. Right now it is needed by intel microcode updating. Once all intel cpus are converted to cbfs updating, this variable can go away. These files are then compiled and assembled into a binary CBFS file. The advantage of doing it this way versus the current method is that 1) The rule is CPU-agnostic 2) Gives user more control over if and how to include microcode blobs 3) The rules for building the microcode binary are kept in src/cpu/Makefile.inc, and thus would not clobber the other makefiles, which are already overloaded and very difficult to navigate. Change-Id: I38d0c9851691aa112e93031860e94895857ebb76 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 28 ++++------ src/cpu/Kconfig | 88 ++++++++++++++++++++++++++++-- src/cpu/Makefile.inc | 37 +++++++++++++ src/cpu/intel/microcode/Makefile.inc | 20 ++----- src/cpu/intel/microcode/microcode.c | 8 +-- src/cpu/intel/microcode/microcode_blob.c | 22 -------- src/cpu/intel/model_206ax/Kconfig | 2 +- src/cpu/intel/model_206ax/Makefile.inc | 2 + src/cpu/intel/model_206ax/microcode_blob.c | 22 ++++++++ src/include/cpu/intel/microcode.h | 2 +- 11 files changed, 169 insertions(+), 64 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index adc41bf..bcf0e6e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -59,7 +59,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage driver smm +classes-y := ramstage romstage driver smm cpu_microcode romstage-c-ccopts:=-D__PRE_RAM__ romstage-S-ccopts:=-D__PRE_RAM__ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 810e168..c58f3be 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -1,6 +1,8 @@ +################################################################################ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> ## Copyright (C) 2009-2010 coresystems GmbH ## Copyright (C) 2009 Ronald G. Minnich ## @@ -17,8 +19,8 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +################################################################################ -####################################################################### # Take care of subdirectories subdirs-y += boot # subdirs-y += init @@ -34,13 +36,7 @@ cmos_layout.bin-type = 0x01aa OPTION_TABLE_H:=$(obj)/option_table.h endif -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) -cbfs-files-y += microcode_blob.bin -microcode_blob.bin-file = $(obj)/microcode_blob.bin -microcode_blob.bin-type = 0x53 -endif - -####################################################################### +################################################################################ # Build the final rom image COREBOOT_ROM_DEPENDENCIES:= ifeq ($(CONFIG_PAYLOAD_ELF),y) @@ -125,7 +121,7 @@ cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) bootsplash.jpg-type := bootsplash -####################################################################### +################################################################################ # i386 specific tools NVRAMTOOL:=$(objutil)/nvramtool/nvramtool @@ -137,7 +133,7 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l @printf " OPTION $(subst $(obj)/,,$(@))\n" $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ -####################################################################### +################################################################################ # Common recipes for all stages $(objcbfs)/%.bin: $(objcbfs)/%.elf @@ -152,7 +148,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp mv $@.tmp $@ -####################################################################### +################################################################################ # Build the coreboot_ram (stage 2) $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @@ -176,7 +172,7 @@ $(objgenerated)/ramstage.a: $$(ramstage-objs) rm -f $@ $(AR) cr $@ $^ -####################################################################### +################################################################################ # Ramstage for AP CPU (AMD K8, obsolete?) $(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/x86/init/ldscript_apc.lb @@ -187,7 +183,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $( @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ -####################################################################### +################################################################################ # done crt0s = $(src)/arch/x86/init/prologue.inc @@ -268,7 +264,7 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c endif -####################################################################### +################################################################################ # Build the final rom image $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL) @@ -278,7 +274,7 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(objcbfs)/base_xip.txt) mv $@.tmp $@ -####################################################################### +################################################################################ # Build the bootblock bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb @@ -335,7 +331,7 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< endif -####################################################################### +################################################################################ # Build the romstage $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index baf686e..1ed721f 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -62,10 +62,90 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -config MICROCODE_IN_CBFS - bool "Look for microcode in CBFS" +endif # ARCH_X86 + +config CPU_MICROCODE_IN_CBFS + bool default n + +choice + prompt "Include CPU microcode in CBFS" + default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS + default CPU_MICROCODE_CBFS_NONE if !CPU_MICROCODE_IN_CBFS + +config CPU_MICROCODE_CBFS_GENERATE + bool "Generate from tree" help - Load microcode updates from CBFS instead of compiling them in. + Select this option if you want microcode updates to be assembled when + building coreboot and included in the final image as a separate CBFS + file. Microcode will not be hard-coded into ramstage. -endif # ARCH_X86 + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select this option. + +config CPU_MICROCODE_CBFS_EXTERNAL + bool "Include external microcode file" + help + Select this option if you want to include an external file containing + the CPU microcode. This will be included as a separate file in CBFS. + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select "Generate from tree" + +config CPU_MICROCODE_FILE + string "Path and filename of CPU microcode" + depends on CPU_MICROCODE_CBFS_EXTERNAL + default "cpu_microcode.bin" + help + The path and filename of the file containing the CPU microcode. + +config CPU_MICROCODE_CBFS_NONE + bool "Do not include microcode updates" + help + Select this option if you do not want CPU microcode included in CBFS. + Note that for some CPUs, the microcode is hard-coded into the source + tree and is not loaded from CBFS. In this case, microcode will still + be updated. There is a push to move all microcode to CBFS, but this + change is not implemented for all CPUs. + + This option currently applies to: + - Intel SandyBridge/IvyBridge + - VIA Nano + + Microcode may be added to the ROM image at a later time with cbfstool, + if desired. + + If unsure, select "Generate from tree" + + The GOOD: + Microcode updates intend to solve issues that have been discovered + after CPU production. The expected effect is that systems work as + intended with the updated microcode, but we have also seen cases where + issues were solved by not applying microcode updates. + + The BAD: + Note that some operating system include these same microcode patches, + so you may need to also disable microcode updates in your operating + system for this option to have an effect. + + The UGLY: + A word of CAUTION: some CPUs depend on microcode updates to function + correctly. Not updating the microcode may leave the CPU operating at + less than optimal performance, or may cause outright hangups. + There are CPUs where coreboot cannot properly initialize the CPU + without microcode updates + For example, if running with the factory microcode, some Intel + SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs + will hang when changing the frequency. + + Make sure you have a way of flashing the ROM externally before + selecting this option. + +endchoice diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 57273cf..938a8df 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,3 +1,40 @@ +################################################################################ +## Subdirectories +################################################################################ subdirs-y += amd subdirs-y += intel subdirs-y += via + +################################################################################ +## Rules for building the microcode blob in CBFS +################################################################################ + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE), y) + +cbfs-files-y += cpu_microcode_blob.bin + +cpu_microcode_blob.bin-type = 0x53 + +# External microcode file, or are we generating one ? +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) +cpu_microcode_blob.bin-file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) +else +cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin +endif + +# In case we have more than one "source" (cough) files containing microcode, we +# Link them together in one large blob, so that we get all the microcode updates +# in one file. This makes it easier for objcopy in the final step. +# The --entry=0 is just here to suppress the LD warning. It does not affect the +# final microcode file. +$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs) + @printf " LD $(subst $(obj)/,,$(@))\n" + $(LD) -static --entry=0 $< -o $@ + +# We have a lot of useless data in the large blob, and we are only interested in +# the data section, so we only copy that part to the final microcode file +$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o + @printf " MICROCODE $(subst $(obj)/,,$(@))\n" + $(OBJCOPY) -j .data -O binary $< $@ + +endif diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index f4d0102..22655c9 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,15 +1,5 @@ -ramstage-y += microcode.c - - -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) - -SRC_PATH = src/cpu/intel/microcode -FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h -$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c - $(CC) $(FLAGS) -MMD -c -o $@ $< - -$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o - objcopy -j .data -O binary $< $@ - --include $(obj)/microcode_blob.d -endif +################################################################################ +## One small file with the awesome super-power of updating the cpu microcode +## directly from CBFS. You have been WARNED!!! +################################################################################ +ramstage-y += microcode.c \ No newline at end of file diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index e84bad9..a4471ca 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,7 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS #ifdef __PRE_RAM__ #include <arch/cbfs.h> #else @@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS static #endif void intel_update_microcode(const void *microcode_updates) @@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates) } } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS -#define MICROCODE_CBFS_FILE "microcode_blob.bin" +#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" void intel_update_microcode_from_cbfs(void) { diff --git a/src/cpu/intel/microcode/microcode_blob.c b/src/cpu/intel/microcode/microcode_blob.c deleted file mode 100644 index 69238a9..0000000 --- a/src/cpu/intel/microcode/microcode_blob.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -unsigned microcode[] = { -#include <microcode_blob.h> -}; diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 6635868..5c543b8 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select MICROCODE_IN_CBFS + select CPU_MICROCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e9b8e6d..6ab4840 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -5,4 +5,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c + cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c new file mode 100644 index 0000000..c2538e8 --- /dev/null +++ b/src/cpu/intel/model_206ax/microcode_blob.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned microcode[] = { +#include "microcode_blob.h" +}; diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 289e919..e9c13f9 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -21,7 +21,7 @@ #define __CPU__INTEL__MICROCODE__ #ifndef __PRE_RAM__ -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); #else void intel_update_microcode(const void *microcode_updates);

1 0

Patch set updated for coreboot: e9fd448 Remove chip.h files without config structure
by Kyösti Mälkki 27 Aug '12

27 Aug '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1473 -gerrit commit e9fd4483a7fe8df91e76813c667407f19a9041b9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Aug 24 21:54:10 2012 +0300 Remove chip.h files without config structure Also deletes files not included in build: src/southbridge/amd/cimx/sb700/chip_name.c src/southbridge/amd/cimx/sb800/chip_name.c src/southbridge/amd/cimx/sb900/chip_name.c Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/family10/chip.h | 21 ------------ src/cpu/amd/agesa/family10/chip_name.c | 1 - src/cpu/amd/agesa/family12/chip.h | 21 ------------ src/cpu/amd/agesa/family12/chip_name.c | 1 - src/cpu/amd/agesa/family14/chip.h | 21 ------------ src/cpu/amd/agesa/family14/chip_name.c | 1 - src/cpu/amd/agesa/family15/chip.h | 21 ------------ src/cpu/amd/agesa/family15/chip_name.c | 1 - src/cpu/amd/agesa/family15tn/chip.h | 21 ------------ src/cpu/amd/agesa/family15tn/chip_name.c | 1 - src/cpu/amd/sc520/chip.h | 2 -- src/cpu/amd/sc520/sc520.c | 1 - src/cpu/amd/socket_754/chip.h | 2 -- src/cpu/amd/socket_754/socket_754.c | 1 - src/cpu/amd/socket_939/chip.h | 2 -- src/cpu/amd/socket_939/socket_939.c | 1 - src/cpu/amd/socket_940/chip.h | 2 -- src/cpu/amd/socket_940/socket_940.c | 1 - src/cpu/amd/socket_AM2/chip.h | 2 -- src/cpu/amd/socket_AM2/socket_AM2.c | 1 - src/cpu/amd/socket_AM2r2/chip.h | 21 ------------ src/cpu/amd/socket_AM2r2/socket_AM2r2.c | 1 - src/cpu/amd/socket_AM3/chip.h | 21 ------------ src/cpu/amd/socket_AM3/socket_AM3.c | 1 - src/cpu/amd/socket_ASB2/chip.h | 21 ------------ src/cpu/amd/socket_ASB2/socket_ASB2.c | 1 - src/cpu/amd/socket_C32/chip.h | 21 ------------ src/cpu/amd/socket_C32/socket_C32.c | 1 - src/cpu/amd/socket_F/chip.h | 2 -- src/cpu/amd/socket_F/socket_F.c | 1 - src/cpu/amd/socket_F_1207/chip.h | 21 ------------ src/cpu/amd/socket_F_1207/socket_F_1207.c | 1 - src/cpu/amd/socket_S1G1/chip.h | 2 -- src/cpu/amd/socket_S1G1/socket_S1G1.c | 1 - src/cpu/intel/ep80579/chip.h | 21 ------------ src/cpu/intel/ep80579/ep80579.c | 1 - src/cpu/intel/slot_1/chip.h | 22 ------------ src/cpu/intel/slot_1/slot_1.c | 1 - src/cpu/intel/slot_2/chip.h | 2 -- src/cpu/intel/slot_2/slot_2.c | 1 - src/cpu/intel/socket_441/chip.h | 21 ------------ src/cpu/intel/socket_441/socket_441.c | 1 - src/cpu/intel/socket_BGA956/chip.h | 2 -- src/cpu/intel/socket_BGA956/socket_BGA956.c | 1 - src/cpu/intel/socket_FC_PGA370/chip.h | 22 ------------ src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c | 1 - src/cpu/intel/socket_LGA771/chip.h | 2 -- src/cpu/intel/socket_LGA771/socket_LGA771.c | 1 - src/cpu/intel/socket_PGA370/chip.h | 2 -- src/cpu/intel/socket_PGA370/socket_PGA370.c | 1 - src/cpu/intel/socket_mFCBGA479/chip.h | 2 -- src/cpu/intel/socket_mFCBGA479/socket_mFCBGA479.c | 1 - src/cpu/intel/socket_mFCPGA478/chip.h | 2 -- src/cpu/intel/socket_mFCPGA478/socket_mFCPGA478.c | 1 - src/cpu/intel/socket_mPGA478/chip.h | 2 -- src/cpu/intel/socket_mPGA478/socket_mPGA478.c | 1 - src/cpu/intel/socket_mPGA479M/chip.h | 2 -- src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c | 1 - src/cpu/intel/socket_mPGA603/chip.h | 2 -- .../intel/socket_mPGA603/socket_mPGA603_400Mhz.c | 1 - src/cpu/intel/socket_mPGA604/chip.h | 2 -- src/cpu/intel/socket_mPGA604/socket_mPGA604.c | 1 - src/cpu/intel/socket_rPGA989/chip.h | 2 -- src/cpu/intel/socket_rPGA989/socket_rPGA989.c | 1 - src/drivers/generic/debug/chip.h | 2 -- src/drivers/generic/debug/debug_dev.c | 1 - src/drivers/i2c/adm1026/adm1026.c | 1 - src/drivers/i2c/adm1026/chip.h | 2 -- src/drivers/i2c/adm1027/adm1027.c | 1 - src/drivers/i2c/adm1027/chip.h | 2 -- src/drivers/i2c/adt7463/adt7463.c | 1 - src/drivers/i2c/adt7463/chip.h | 2 -- src/drivers/i2c/i2cmux/chip.h | 2 -- src/drivers/i2c/i2cmux/i2cmux.c | 1 - src/drivers/i2c/i2cmux2/chip.h | 2 -- src/drivers/i2c/i2cmux2/i2cmux2.c | 1 - src/drivers/i2c/lm63/chip.h | 2 -- src/drivers/i2c/lm63/lm63.c | 1 - src/drivers/i2c/w83795/chip.h | 2 -- src/mainboard/emulation/qemu-x86/chip.h | 2 -- src/mainboard/emulation/qemu-x86/northbridge.c | 1 - src/northbridge/amd/agesa/family10/chip.h | 23 ------------- src/northbridge/amd/agesa/family10/northbridge.c | 2 -- .../amd/agesa/family10/root_complex/chip.h | 23 ------------- src/northbridge/amd/agesa/family12/chip.h | 23 ------------- src/northbridge/amd/agesa/family12/northbridge.c | 1 - .../amd/agesa/family12/root_complex/chip.h | 23 ------------- src/northbridge/amd/agesa/family14/chip.h | 23 ------------- src/northbridge/amd/agesa/family14/northbridge.c | 1 - .../amd/agesa/family14/root_complex/chip.h | 23 ------------- src/northbridge/amd/agesa/family15/chip.h | 23 ------------- src/northbridge/amd/agesa/family15/northbridge.c | 2 -- .../amd/agesa/family15/root_complex/chip.h | 23 ------------- src/northbridge/amd/agesa/family15tn/chip.h | 23 ------------- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 -- .../amd/agesa/family15tn/root_complex/chip.h | 23 ------------- src/northbridge/amd/amdfam10/chip.h | 23 ------------- src/northbridge/amd/amdfam10/northbridge.c | 2 -- src/northbridge/amd/amdfam10/root_complex/chip.h | 23 ------------- src/northbridge/amd/amdk8/chip.h | 4 --- src/northbridge/amd/amdk8/northbridge.c | 2 -- src/northbridge/amd/amdk8/root_complex/chip.h | 4 --- src/northbridge/amd/gx1/chip.h | 4 --- src/northbridge/amd/gx1/northbridge.c | 1 - src/northbridge/amd/gx2/chip.h | 24 ------------- src/northbridge/amd/gx2/northbridge.c | 1 - src/northbridge/amd/gx2/northbridgeinit.c | 1 - src/northbridge/amd/lx/chip.h | 23 ------------- src/northbridge/amd/lx/northbridge.c | 1 - src/northbridge/amd/lx/northbridgeinit.c | 1 - src/northbridge/intel/e7501/chip.h | 4 --- src/northbridge/intel/e7501/northbridge.c | 1 - src/northbridge/intel/e7505/chip.h | 4 --- src/northbridge/intel/e7505/northbridge.c | 1 - src/northbridge/intel/i440bx/chip.h | 24 ------------- src/northbridge/intel/i440bx/northbridge.c | 1 - src/northbridge/intel/i440lx/chip.h | 24 ------------- src/northbridge/intel/i440lx/northbridge.c | 1 - src/northbridge/intel/i5000/chip.h | 22 ------------ src/northbridge/intel/i5000/northbridge.c | 1 - src/northbridge/intel/i82810/chip.h | 23 ------------- src/northbridge/intel/i82810/northbridge.c | 1 - src/northbridge/intel/i82830/chip.h | 23 ------------- src/northbridge/intel/i82830/northbridge.c | 1 - src/northbridge/intel/i855/chip.h | 24 ------------- src/northbridge/intel/i855/northbridge.c | 1 - src/northbridge/intel/i945/chip.h | 22 ------------ src/northbridge/intel/i945/northbridge.c | 1 - src/northbridge/intel/sch/chip.h | 22 ------------ src/northbridge/intel/sch/northbridge.c | 1 - src/northbridge/rdc/r8610/chip.h | 23 ------------- src/northbridge/rdc/r8610/northbridge.c | 1 - src/northbridge/via/cn400/agp.c | 1 - src/northbridge/via/cn400/chip.h | 23 ------------- src/northbridge/via/cn400/northbridge.c | 1 - src/northbridge/via/cn400/vga.c | 1 - src/northbridge/via/cn400/vlink.c | 1 - src/northbridge/via/cn700/agp.c | 1 - src/northbridge/via/cn700/chip.h | 23 ------------- src/northbridge/via/cn700/northbridge.c | 1 - src/northbridge/via/cn700/vga.c | 1 - src/northbridge/via/cx700/chip.h | 22 ------------ src/northbridge/via/cx700/northbridge.c | 1 - src/northbridge/via/cx700/vga.c | 1 - src/northbridge/via/vt8601/chip.h | 4 --- src/northbridge/via/vt8601/northbridge.c | 1 - src/northbridge/via/vt8623/chip.h | 4 --- src/northbridge/via/vt8623/northbridge.c | 1 - src/northbridge/via/vt8623/vga.c | 1 - src/northbridge/via/vx800/chip.h | 22 ------------ src/northbridge/via/vx800/ide.c | 5 --- src/northbridge/via/vx800/lpc.c | 1 - src/northbridge/via/vx800/northbridge.c | 1 - src/northbridge/via/vx800/vga.c | 1 - src/southbridge/amd/cimx/sb700/chip_name.c | 25 -------------- src/southbridge/amd/cimx/sb800/chip_name.c | 25 -------------- src/southbridge/amd/cimx/sb900/chip_name.c | 25 -------------- src/southbridge/intel/i82801cx/chip.h | 8 ----- src/southbridge/intel/i82801cx/i82801cx.h | 1 - src/southbridge/intel/pxhd/chip.h | 5 --- src/southbridge/intel/pxhd/pxhd.h | 1 - src/southbridge/ti/pcixx12/chip.h | 28 --------------- src/southbridge/ti/pcixx12/pcixx12.c | 2 -- src/superio/fintek/f71805f/chip.h | 33 ------------------ src/superio/fintek/f71805f/superio.c | 1 - src/superio/fintek/f71859/chip.h | 31 ----------------- src/superio/fintek/f71859/superio.c | 1 - src/superio/intel/i3100/chip.h | 30 ---------------- src/superio/intel/i3100/superio.c | 1 - src/superio/ite/it8661f/chip.h | 33 ------------------ src/superio/ite/it8661f/superio.c | 1 - src/superio/ite/it8705f/chip.h | 33 ------------------ src/superio/ite/it8705f/superio.c | 3 -- src/superio/nsc/pc87382/chip.h | 30 ---------------- src/superio/nsc/pc87382/superio.c | 1 - src/superio/nsc/pc87384/chip.h | 30 ---------------- src/superio/nsc/pc87384/superio.c | 1 - src/superio/nsc/pc87392/chip.h | 30 ---------------- src/superio/nsc/pc87392/superio.c | 1 - src/superio/smsc/lpc47n217/chip.h | 30 ---------------- src/superio/smsc/lpc47n217/superio.c | 4 --- src/superio/via/vt1211/chip.h | 30 ---------------- src/superio/via/vt1211/vt1211.c | 1 - util/sconfig/main.c | 40 ++++++++++++---------- util/sconfig/sconfig.h | 1 + 185 files changed, 22 insertions(+), 1550 deletions(-) diff --git a/src/cpu/amd/agesa/family10/chip.h b/src/cpu/amd/agesa/family10/chip.h deleted file mode 100644 index 4f9fa77..0000000 --- a/src/cpu/amd/agesa/family10/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_agesa_family10_config { -}; diff --git a/src/cpu/amd/agesa/family10/chip_name.c b/src/cpu/amd/agesa/family10/chip_name.c index d99769c..656b4a2 100644 --- a/src/cpu/amd/agesa/family10/chip_name.c +++ b/src/cpu/amd/agesa/family10/chip_name.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_agesa_family10_ops = { CHIP_NAME("AMD CPU Family 10h") diff --git a/src/cpu/amd/agesa/family12/chip.h b/src/cpu/amd/agesa/family12/chip.h deleted file mode 100644 index 0eaa0e2..0000000 --- a/src/cpu/amd/agesa/family12/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_agesa_family12_config { -}; diff --git a/src/cpu/amd/agesa/family12/chip_name.c b/src/cpu/amd/agesa/family12/chip_name.c index 5de72c7..6574615 100644 --- a/src/cpu/amd/agesa/family12/chip_name.c +++ b/src/cpu/amd/agesa/family12/chip_name.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_agesa_family12_ops = { CHIP_NAME("AMD CPU Family 12h") diff --git a/src/cpu/amd/agesa/family14/chip.h b/src/cpu/amd/agesa/family14/chip.h deleted file mode 100644 index 59c7cfe..0000000 --- a/src/cpu/amd/agesa/family14/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_agesa_family14_config { -}; diff --git a/src/cpu/amd/agesa/family14/chip_name.c b/src/cpu/amd/agesa/family14/chip_name.c index 2c296f5..474edc7 100644 --- a/src/cpu/amd/agesa/family14/chip_name.c +++ b/src/cpu/amd/agesa/family14/chip_name.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_agesa_family14_ops = { CHIP_NAME("AMD CPU Family 14h") diff --git a/src/cpu/amd/agesa/family15/chip.h b/src/cpu/amd/agesa/family15/chip.h deleted file mode 100644 index e6daaef..0000000 --- a/src/cpu/amd/agesa/family15/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_agesa_family15_config { -}; diff --git a/src/cpu/amd/agesa/family15/chip_name.c b/src/cpu/amd/agesa/family15/chip_name.c index 963a423..3ca6e9f 100644 --- a/src/cpu/amd/agesa/family15/chip_name.c +++ b/src/cpu/amd/agesa/family15/chip_name.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_agesa_family15_ops = { CHIP_NAME("AMD CPU Family 15h") diff --git a/src/cpu/amd/agesa/family15tn/chip.h b/src/cpu/amd/agesa/family15tn/chip.h deleted file mode 100644 index 5ad93c5..0000000 --- a/src/cpu/amd/agesa/family15tn/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_agesa_family15tn_config { -}; diff --git a/src/cpu/amd/agesa/family15tn/chip_name.c b/src/cpu/amd/agesa/family15tn/chip_name.c index a2a5519..d923260 100644 --- a/src/cpu/amd/agesa/family15tn/chip_name.c +++ b/src/cpu/amd/agesa/family15tn/chip_name.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_agesa_family15tn_ops = { CHIP_NAME("AMD CPU Family 15h") diff --git a/src/cpu/amd/sc520/chip.h b/src/cpu/amd/sc520/chip.h deleted file mode 100644 index 64f3a85..0000000 --- a/src/cpu/amd/sc520/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_amd_sc520_config { -}; diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c index 059e4fd..382eb87 100644 --- a/src/cpu/amd/sc520/sc520.c +++ b/src/cpu/amd/sc520/sc520.c @@ -14,7 +14,6 @@ #include <string.h> #include <bitops.h> #include <delay.h> -#include "chip.h" /* * set up basic things ... diff --git a/src/cpu/amd/socket_754/chip.h b/src/cpu/amd/socket_754/chip.h deleted file mode 100644 index 197145f..0000000 --- a/src/cpu/amd/socket_754/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_amd_socket_754_config { -}; diff --git a/src/cpu/amd/socket_754/socket_754.c b/src/cpu/amd/socket_754/socket_754.c index 8fdcf57..f75c1ec 100644 --- a/src/cpu/amd/socket_754/socket_754.c +++ b/src/cpu/amd/socket_754/socket_754.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_754_ops = { diff --git a/src/cpu/amd/socket_939/chip.h b/src/cpu/amd/socket_939/chip.h deleted file mode 100644 index ca93451..0000000 --- a/src/cpu/amd/socket_939/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_amd_socket_939_config { -}; diff --git a/src/cpu/amd/socket_939/socket_939.c b/src/cpu/amd/socket_939/socket_939.c index 6563752..a44a8a6 100644 --- a/src/cpu/amd/socket_939/socket_939.c +++ b/src/cpu/amd/socket_939/socket_939.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_939_ops = { CHIP_NAME("Socket 939 CPU") diff --git a/src/cpu/amd/socket_940/chip.h b/src/cpu/amd/socket_940/chip.h deleted file mode 100644 index 8b96614..0000000 --- a/src/cpu/amd/socket_940/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_amd_socket_940_config { -}; diff --git a/src/cpu/amd/socket_940/socket_940.c b/src/cpu/amd/socket_940/socket_940.c index 54531ef..872f040 100644 --- a/src/cpu/amd/socket_940/socket_940.c +++ b/src/cpu/amd/socket_940/socket_940.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_940_ops = { CHIP_NAME("Socket 940 CPU") diff --git a/src/cpu/amd/socket_AM2/chip.h b/src/cpu/amd/socket_AM2/chip.h deleted file mode 100644 index 5d9e875..0000000 --- a/src/cpu/amd/socket_AM2/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_amd_socket_AM2_config { -}; diff --git a/src/cpu/amd/socket_AM2/socket_AM2.c b/src/cpu/amd/socket_AM2/socket_AM2.c index 474e19d..60378ab 100644 --- a/src/cpu/amd/socket_AM2/socket_AM2.c +++ b/src/cpu/amd/socket_AM2/socket_AM2.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_AM2_ops = { CHIP_NAME("Socket AM2 CPU") diff --git a/src/cpu/amd/socket_AM2r2/chip.h b/src/cpu/amd/socket_AM2r2/chip.h deleted file mode 100644 index 1c93a99..0000000 --- a/src/cpu/amd/socket_AM2r2/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_socket_AM2r2_config { -}; diff --git a/src/cpu/amd/socket_AM2r2/socket_AM2r2.c b/src/cpu/amd/socket_AM2r2/socket_AM2r2.c index 3f98e53..d618563 100644 --- a/src/cpu/amd/socket_AM2r2/socket_AM2r2.c +++ b/src/cpu/amd/socket_AM2r2/socket_AM2r2.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_AM2r2_ops = { CHIP_NAME("socket AM2r2") diff --git a/src/cpu/amd/socket_AM3/chip.h b/src/cpu/amd/socket_AM3/chip.h deleted file mode 100644 index 70f6b1f..0000000 --- a/src/cpu/amd/socket_AM3/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_socket_AM3_config { -}; diff --git a/src/cpu/amd/socket_AM3/socket_AM3.c b/src/cpu/amd/socket_AM3/socket_AM3.c index 75b3970..91871e8 100644 --- a/src/cpu/amd/socket_AM3/socket_AM3.c +++ b/src/cpu/amd/socket_AM3/socket_AM3.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_AM3_ops = { CHIP_NAME("socket AM3") diff --git a/src/cpu/amd/socket_ASB2/chip.h b/src/cpu/amd/socket_ASB2/chip.h deleted file mode 100644 index 5939c2b..0000000 --- a/src/cpu/amd/socket_ASB2/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_socket_ASB2_config { -}; diff --git a/src/cpu/amd/socket_ASB2/socket_ASB2.c b/src/cpu/amd/socket_ASB2/socket_ASB2.c index fd3b522..3c38a8c 100644 --- a/src/cpu/amd/socket_ASB2/socket_ASB2.c +++ b/src/cpu/amd/socket_ASB2/socket_ASB2.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_ASB2_ops = { CHIP_NAME("socket ASB2") diff --git a/src/cpu/amd/socket_C32/chip.h b/src/cpu/amd/socket_C32/chip.h deleted file mode 100644 index e9d57c7..0000000 --- a/src/cpu/amd/socket_C32/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_socket_C32_config { -}; diff --git a/src/cpu/amd/socket_C32/socket_C32.c b/src/cpu/amd/socket_C32/socket_C32.c index 266bfa0..4f90458 100644 --- a/src/cpu/amd/socket_C32/socket_C32.c +++ b/src/cpu/amd/socket_C32/socket_C32.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_C32_ops = { CHIP_NAME("socket C32") diff --git a/src/cpu/amd/socket_F/chip.h b/src/cpu/amd/socket_F/chip.h deleted file mode 100644 index cb582d3..0000000 --- a/src/cpu/amd/socket_F/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_amd_socket_F_config { -}; diff --git a/src/cpu/amd/socket_F/socket_F.c b/src/cpu/amd/socket_F/socket_F.c index 93db628..80c3e35 100644 --- a/src/cpu/amd/socket_F/socket_F.c +++ b/src/cpu/amd/socket_F/socket_F.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_F_ops = { CHIP_NAME("Socket F CPU") diff --git a/src/cpu/amd/socket_F_1207/chip.h b/src/cpu/amd/socket_F_1207/chip.h deleted file mode 100644 index 3f7d824..0000000 --- a/src/cpu/amd/socket_F_1207/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_socket_F_1207_config { -}; diff --git a/src/cpu/amd/socket_F_1207/socket_F_1207.c b/src/cpu/amd/socket_F_1207/socket_F_1207.c index a95e8ea..e84f435 100644 --- a/src/cpu/amd/socket_F_1207/socket_F_1207.c +++ b/src/cpu/amd/socket_F_1207/socket_F_1207.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_F_1207_ops = { CHIP_NAME("socket F_1207") diff --git a/src/cpu/amd/socket_S1G1/chip.h b/src/cpu/amd/socket_S1G1/chip.h deleted file mode 100644 index 3109da2..0000000 --- a/src/cpu/amd/socket_S1G1/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_amd_socket_S1G1_config { -}; diff --git a/src/cpu/amd/socket_S1G1/socket_S1G1.c b/src/cpu/amd/socket_S1G1/socket_S1G1.c index 352ecc3..0b9702c 100644 --- a/src/cpu/amd/socket_S1G1/socket_S1G1.c +++ b/src/cpu/amd/socket_S1G1/socket_S1G1.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_S1G1_ops = { CHIP_NAME("Socket S1G1 CPU") diff --git a/src/cpu/intel/ep80579/chip.h b/src/cpu/intel/ep80579/chip.h deleted file mode 100644 index 08e7529..0000000 --- a/src/cpu/intel/ep80579/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_intel_ep80579_config { -}; diff --git a/src/cpu/intel/ep80579/ep80579.c b/src/cpu/intel/ep80579/ep80579.c index fd964a4..7d6e715 100644 --- a/src/cpu/intel/ep80579/ep80579.c +++ b/src/cpu/intel/ep80579/ep80579.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_ep80579_ops = { CHIP_NAME("EP80579 CPU") diff --git a/src/cpu/intel/slot_1/chip.h b/src/cpu/intel/slot_1/chip.h deleted file mode 100644 index 8650f90..0000000 --- a/src/cpu/intel/slot_1/chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_intel_slot_1_config { -}; diff --git a/src/cpu/intel/slot_1/slot_1.c b/src/cpu/intel/slot_1/slot_1.c index 548127f..df48248 100644 --- a/src/cpu/intel/slot_1/slot_1.c +++ b/src/cpu/intel/slot_1/slot_1.c @@ -19,7 +19,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_slot_1_ops = { CHIP_NAME("Slot 1 CPU") diff --git a/src/cpu/intel/slot_2/chip.h b/src/cpu/intel/slot_2/chip.h deleted file mode 100644 index d7bb2b1..0000000 --- a/src/cpu/intel/slot_2/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_slot_2_config { -}; diff --git a/src/cpu/intel/slot_2/slot_2.c b/src/cpu/intel/slot_2/slot_2.c index ddc2f3b..994b25a 100644 --- a/src/cpu/intel/slot_2/slot_2.c +++ b/src/cpu/intel/slot_2/slot_2.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_slot_2_ops = { diff --git a/src/cpu/intel/socket_441/chip.h b/src/cpu/intel/socket_441/chip.h deleted file mode 100644 index 70c4ac8..0000000 --- a/src/cpu/intel/socket_441/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_intel_socket_441_config { -}; diff --git a/src/cpu/intel/socket_441/socket_441.c b/src/cpu/intel/socket_441/socket_441.c index eb57dce..319a402 100644 --- a/src/cpu/intel/socket_441/socket_441.c +++ b/src/cpu/intel/socket_441/socket_441.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_441_ops = { CHIP_NAME("Socket 441 CPU") diff --git a/src/cpu/intel/socket_BGA956/chip.h b/src/cpu/intel/socket_BGA956/chip.h deleted file mode 100644 index 399200d..0000000 --- a/src/cpu/intel/socket_BGA956/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_BGA956_config { -}; diff --git a/src/cpu/intel/socket_BGA956/socket_BGA956.c b/src/cpu/intel/socket_BGA956/socket_BGA956.c index 53667c1..def7cc9 100644 --- a/src/cpu/intel/socket_BGA956/socket_BGA956.c +++ b/src/cpu/intel/socket_BGA956/socket_BGA956.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_BGA956_ops = { CHIP_NAME("Socket BGA956 CPU") diff --git a/src/cpu/intel/socket_FC_PGA370/chip.h b/src/cpu/intel/socket_FC_PGA370/chip.h deleted file mode 100644 index 7148d47..0000000 --- a/src/cpu/intel/socket_FC_PGA370/chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Joseph Smith <joe(a)settoplinux.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_intel_socket_FC_PGA370_config { -}; diff --git a/src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c b/src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c index e3bca8f..62186f2 100644 --- a/src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c +++ b/src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c @@ -19,7 +19,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_FC_PGA370_ops = { CHIP_NAME("(FC)PGA370 CPU") diff --git a/src/cpu/intel/socket_LGA771/chip.h b/src/cpu/intel/socket_LGA771/chip.h deleted file mode 100644 index fc51d77..0000000 --- a/src/cpu/intel/socket_LGA771/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_LGA771_config { -}; diff --git a/src/cpu/intel/socket_LGA771/socket_LGA771.c b/src/cpu/intel/socket_LGA771/socket_LGA771.c index 21a7dc9..85570ba 100644 --- a/src/cpu/intel/socket_LGA771/socket_LGA771.c +++ b/src/cpu/intel/socket_LGA771/socket_LGA771.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_LGA771_ops = { diff --git a/src/cpu/intel/socket_PGA370/chip.h b/src/cpu/intel/socket_PGA370/chip.h deleted file mode 100644 index c2c70ec..0000000 --- a/src/cpu/intel/socket_PGA370/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_PGA370_config { -}; diff --git a/src/cpu/intel/socket_PGA370/socket_PGA370.c b/src/cpu/intel/socket_PGA370/socket_PGA370.c index fffd983..f7c1c2a 100644 --- a/src/cpu/intel/socket_PGA370/socket_PGA370.c +++ b/src/cpu/intel/socket_PGA370/socket_PGA370.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_PGA370_ops = { CHIP_NAME("Socket PGA370 CPU") diff --git a/src/cpu/intel/socket_mFCBGA479/chip.h b/src/cpu/intel/socket_mFCBGA479/chip.h deleted file mode 100644 index 57e432c..0000000 --- a/src/cpu/intel/socket_mFCBGA479/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_mFCBGA479_config { -}; diff --git a/src/cpu/intel/socket_mFCBGA479/socket_mFCBGA479.c b/src/cpu/intel/socket_mFCBGA479/socket_mFCBGA479.c index 4c0bc72..02849b9 100644 --- a/src/cpu/intel/socket_mFCBGA479/socket_mFCBGA479.c +++ b/src/cpu/intel/socket_mFCBGA479/socket_mFCBGA479.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_mFCBGA479_ops = { CHIP_NAME("Micro-FCBGA 479 CPU") diff --git a/src/cpu/intel/socket_mFCPGA478/chip.h b/src/cpu/intel/socket_mFCPGA478/chip.h deleted file mode 100644 index 50268f5..0000000 --- a/src/cpu/intel/socket_mFCPGA478/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_mFCPGA478_config { -}; diff --git a/src/cpu/intel/socket_mFCPGA478/socket_mFCPGA478.c b/src/cpu/intel/socket_mFCPGA478/socket_mFCPGA478.c index 117a929..5b001bd 100644 --- a/src/cpu/intel/socket_mFCPGA478/socket_mFCPGA478.c +++ b/src/cpu/intel/socket_mFCPGA478/socket_mFCPGA478.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_mFCPGA478_ops = { diff --git a/src/cpu/intel/socket_mPGA478/chip.h b/src/cpu/intel/socket_mPGA478/chip.h deleted file mode 100644 index 3dafc9a..0000000 --- a/src/cpu/intel/socket_mPGA478/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_mPGA478_config { -}; diff --git a/src/cpu/intel/socket_mPGA478/socket_mPGA478.c b/src/cpu/intel/socket_mPGA478/socket_mPGA478.c index da32966..4480bde 100644 --- a/src/cpu/intel/socket_mPGA478/socket_mPGA478.c +++ b/src/cpu/intel/socket_mPGA478/socket_mPGA478.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_mPGA478_ops = { diff --git a/src/cpu/intel/socket_mPGA479M/chip.h b/src/cpu/intel/socket_mPGA479M/chip.h deleted file mode 100644 index c0c5cd4..0000000 --- a/src/cpu/intel/socket_mPGA479M/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_mPGA479M_config { -}; diff --git a/src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c b/src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c index de824b5..b151c47 100644 --- a/src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c +++ b/src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_mPGA479M_ops = { diff --git a/src/cpu/intel/socket_mPGA603/chip.h b/src/cpu/intel/socket_mPGA603/chip.h deleted file mode 100644 index b39982a..0000000 --- a/src/cpu/intel/socket_mPGA603/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_mPGA603_config { -}; diff --git a/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c b/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c index 2436f96..f5f8e5b 100644 --- a/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c +++ b/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_mPGA603_ops = { diff --git a/src/cpu/intel/socket_mPGA604/chip.h b/src/cpu/intel/socket_mPGA604/chip.h deleted file mode 100644 index 3a09b82..0000000 --- a/src/cpu/intel/socket_mPGA604/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_mPGA604_config { -}; diff --git a/src/cpu/intel/socket_mPGA604/socket_mPGA604.c b/src/cpu/intel/socket_mPGA604/socket_mPGA604.c index df372b2..74bdc0d 100644 --- a/src/cpu/intel/socket_mPGA604/socket_mPGA604.c +++ b/src/cpu/intel/socket_mPGA604/socket_mPGA604.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_mPGA604_ops = { diff --git a/src/cpu/intel/socket_rPGA989/chip.h b/src/cpu/intel/socket_rPGA989/chip.h deleted file mode 100644 index ee3b396..0000000 --- a/src/cpu/intel/socket_rPGA989/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_rPGA989_config { -}; diff --git a/src/cpu/intel/socket_rPGA989/socket_rPGA989.c b/src/cpu/intel/socket_rPGA989/socket_rPGA989.c index 2484571..6e05b57 100644 --- a/src/cpu/intel/socket_rPGA989/socket_rPGA989.c +++ b/src/cpu/intel/socket_rPGA989/socket_rPGA989.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_rPGA989_ops = { CHIP_NAME("Socket rPGA989 CPU") diff --git a/src/drivers/generic/debug/chip.h b/src/drivers/generic/debug/chip.h deleted file mode 100644 index 661fd54..0000000 --- a/src/drivers/generic/debug/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_generic_debug_config { -}; diff --git a/src/drivers/generic/debug/debug_dev.c b/src/drivers/generic/debug/debug_dev.c index 60d610f..57f8077 100644 --- a/src/drivers/generic/debug/debug_dev.c +++ b/src/drivers/generic/debug/debug_dev.c @@ -7,7 +7,6 @@ #include <cpu/x86/msr.h> #include <reset.h> #include <delay.h> -#include "chip.h" static void print_pci_regs(struct device *dev) { diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c index 5b06629..ab85eb5 100644 --- a/src/drivers/i2c/adm1026/adm1026.c +++ b/src/drivers/i2c/adm1026/adm1026.c @@ -5,7 +5,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <cpu/x86/msr.h> -#include "chip.h" #define ADM1026_DEVICE 0x2d /* Either 0x2c or 0x2d or 0x2e */ #define ADM1026_REG_CONFIG1 0x00 diff --git a/src/drivers/i2c/adm1026/chip.h b/src/drivers/i2c/adm1026/chip.h deleted file mode 100644 index f8324ad..0000000 --- a/src/drivers/i2c/adm1026/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_i2c_adm1026_config { -}; diff --git a/src/drivers/i2c/adm1027/adm1027.c b/src/drivers/i2c/adm1027/adm1027.c index e97ec69..e83f2c4 100644 --- a/src/drivers/i2c/adm1027/adm1027.c +++ b/src/drivers/i2c/adm1027/adm1027.c @@ -5,7 +5,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <cpu/x86/msr.h> -#include "chip.h" #define ADM1027_REG_CONFIG1 0x40 #define CFG1_STRT 0x01 diff --git a/src/drivers/i2c/adm1027/chip.h b/src/drivers/i2c/adm1027/chip.h deleted file mode 100644 index 8836817..0000000 --- a/src/drivers/i2c/adm1027/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_i2c_adm1027_config { -}; diff --git a/src/drivers/i2c/adt7463/adt7463.c b/src/drivers/i2c/adt7463/adt7463.c index 3967bf7..a791fb4 100644 --- a/src/drivers/i2c/adt7463/adt7463.c +++ b/src/drivers/i2c/adt7463/adt7463.c @@ -23,7 +23,6 @@ #include <device/device.h> #include <console/console.h> #include <device/smbus.h> -#include "chip.h" /** * Do some S2881-specific HWM initialization for the ADT7463 chip. diff --git a/src/drivers/i2c/adt7463/chip.h b/src/drivers/i2c/adt7463/chip.h deleted file mode 100644 index 351d548..0000000 --- a/src/drivers/i2c/adt7463/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_i2c_adt7463_config { -}; diff --git a/src/drivers/i2c/i2cmux/chip.h b/src/drivers/i2c/i2cmux/chip.h deleted file mode 100644 index 0cfd837..0000000 --- a/src/drivers/i2c/i2cmux/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_i2c_i2cmux_config { -}; diff --git a/src/drivers/i2c/i2cmux/i2cmux.c b/src/drivers/i2c/i2cmux/i2cmux.c index 44bf390..b318508 100644 --- a/src/drivers/i2c/i2cmux/i2cmux.c +++ b/src/drivers/i2c/i2cmux/i2cmux.c @@ -5,7 +5,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <cpu/x86/msr.h> -#include "chip.h" static void i2cmux_set_link(device_t dev, unsigned int link) { diff --git a/src/drivers/i2c/i2cmux2/chip.h b/src/drivers/i2c/i2cmux2/chip.h deleted file mode 100644 index dafa1d7..0000000 --- a/src/drivers/i2c/i2cmux2/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_i2c_i2cmux2_config { -}; diff --git a/src/drivers/i2c/i2cmux2/i2cmux2.c b/src/drivers/i2c/i2cmux2/i2cmux2.c index dc8ec25..a7d40e2 100644 --- a/src/drivers/i2c/i2cmux2/i2cmux2.c +++ b/src/drivers/i2c/i2cmux2/i2cmux2.c @@ -5,7 +5,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <cpu/x86/msr.h> -#include "chip.h" static void i2cmux2_set_link(device_t dev, unsigned int link) { diff --git a/src/drivers/i2c/lm63/chip.h b/src/drivers/i2c/lm63/chip.h deleted file mode 100644 index 1c5bc7a..0000000 --- a/src/drivers/i2c/lm63/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_i2c_lm63_config { -}; diff --git a/src/drivers/i2c/lm63/lm63.c b/src/drivers/i2c/lm63/lm63.c index d98a245..47a5489 100644 --- a/src/drivers/i2c/lm63/lm63.c +++ b/src/drivers/i2c/lm63/lm63.c @@ -5,7 +5,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <cpu/x86/msr.h> -#include "chip.h" static void lm63_init(device_t dev) { diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h deleted file mode 100644 index b5162c1..0000000 --- a/src/drivers/i2c/w83795/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_i2c_w83795_config { -}; diff --git a/src/mainboard/emulation/qemu-x86/chip.h b/src/mainboard/emulation/qemu-x86/chip.h deleted file mode 100644 index 0aa8173..0000000 --- a/src/mainboard/emulation/qemu-x86/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct mainboard_emulation_qemu_x86_config {}; - diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c index f1669bb..6103229 100644 --- a/src/mainboard/emulation/qemu-x86/northbridge.c +++ b/src/mainboard/emulation/qemu-x86/northbridge.c @@ -8,7 +8,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include <delay.h> #include <smbios.h> diff --git a/src/northbridge/amd/agesa/family10/chip.h b/src/northbridge/amd/agesa/family10/chip.h deleted file mode 100644 index f95d5b1..0000000 --- a/src/northbridge/amd/agesa/family10/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family10_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 4b3859b..ddb7619 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -39,10 +39,8 @@ #include <Porting.h> #include <AGESA.h> #include <Options.h> -#include "root_complex/chip.h" #include "northbridge.h" #include "amdfam10.h" -#include "chip.h" extern uint32_t agesawrapper_amdinitmid(void); diff --git a/src/northbridge/amd/agesa/family10/root_complex/chip.h b/src/northbridge/amd/agesa/family10/root_complex/chip.h deleted file mode 100644 index 80adb8e..0000000 --- a/src/northbridge/amd/agesa/family10/root_complex/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family10_root_complex_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family12/chip.h b/src/northbridge/amd/agesa/family12/chip.h deleted file mode 100644 index 39efd52..0000000 --- a/src/northbridge/amd/agesa/family12/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family12_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 6689e71..b24681b 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -33,7 +33,6 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> -#include "chip.h" #include "northbridge.h" #include "SbEarly.h" #include "agesawrapper.h" diff --git a/src/northbridge/amd/agesa/family12/root_complex/chip.h b/src/northbridge/amd/agesa/family12/root_complex/chip.h deleted file mode 100644 index 556f343..0000000 --- a/src/northbridge/amd/agesa/family12/root_complex/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family12_root_complex_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family14/chip.h b/src/northbridge/amd/agesa/family14/chip.h deleted file mode 100644 index 46ea78a..0000000 --- a/src/northbridge/amd/agesa/family14/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family14_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 875dbbb..a635901 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -34,7 +34,6 @@ #include <cpu/amd/mtrr.h> #include "agesawrapper.h" -#include "chip.h" #include "northbridge.h" #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> diff --git a/src/northbridge/amd/agesa/family14/root_complex/chip.h b/src/northbridge/amd/agesa/family14/root_complex/chip.h deleted file mode 100644 index cf95179..0000000 --- a/src/northbridge/amd/agesa/family14/root_complex/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family14_root_complex_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family15/chip.h b/src/northbridge/amd/agesa/family15/chip.h deleted file mode 100644 index b06318b..0000000 --- a/src/northbridge/amd/agesa/family15/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family15_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 96cfca2..253ae1c 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -40,9 +40,7 @@ #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> #include "agesawrapper.h" -#include "root_complex/chip.h" #include "northbridge.h" -#include "chip.h" #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) diff --git a/src/northbridge/amd/agesa/family15/root_complex/chip.h b/src/northbridge/amd/agesa/family15/root_complex/chip.h deleted file mode 100644 index 8f670f6..0000000 --- a/src/northbridge/amd/agesa/family15/root_complex/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family15_root_complex_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family15tn/chip.h b/src/northbridge/amd/agesa/family15tn/chip.h deleted file mode 100644 index 091de82..0000000 --- a/src/northbridge/amd/agesa/family15tn/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family15tn_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index fb30277..67550eb 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -40,9 +40,7 @@ #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> #include "agesawrapper.h" -#include "root_complex/chip.h" #include "northbridge.h" -#include "chip.h" #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) diff --git a/src/northbridge/amd/agesa/family15tn/root_complex/chip.h b/src/northbridge/amd/agesa/family15tn/root_complex/chip.h deleted file mode 100644 index 0306fdd..0000000 --- a/src/northbridge/amd/agesa/family15tn/root_complex/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family15tn_root_complex_config -{ -}; - diff --git a/src/northbridge/amd/amdfam10/chip.h b/src/northbridge/amd/amdfam10/chip.h deleted file mode 100644 index a8161cb..0000000 --- a/src/northbridge/amd/amdfam10/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_amdfam10_config -{ -}; - diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 865a3bc..f035d3a 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -37,8 +37,6 @@ #include <pc80/mc146818rtc.h> #endif -#include "chip.h" -#include "root_complex/chip.h" #include "northbridge.h" #include "amdfam10.h" diff --git a/src/northbridge/amd/amdfam10/root_complex/chip.h b/src/northbridge/amd/amdfam10/root_complex/chip.h deleted file mode 100644 index 8c93020..0000000 --- a/src/northbridge/amd/amdfam10/root_complex/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_amdfam10_root_complex_config -{ -}; - diff --git a/src/northbridge/amd/amdk8/chip.h b/src/northbridge/amd/amdk8/chip.h deleted file mode 100644 index a2331f4..0000000 --- a/src/northbridge/amd/amdk8/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -struct northbridge_amd_amdk8_config -{ -}; - diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index d94ee9a..ff7e030 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -25,8 +25,6 @@ #include <pc80/mc146818rtc.h> #endif -#include "chip.h" -#include "root_complex/chip.h" #include "northbridge.h" #include "amdk8.h" diff --git a/src/northbridge/amd/amdk8/root_complex/chip.h b/src/northbridge/amd/amdk8/root_complex/chip.h deleted file mode 100644 index a9b6b5b..0000000 --- a/src/northbridge/amd/amdk8/root_complex/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -struct northbridge_amd_amdk8_root_complex_config -{ -}; - diff --git a/src/northbridge/amd/gx1/chip.h b/src/northbridge/amd/gx1/chip.h deleted file mode 100644 index 0378b61..0000000 --- a/src/northbridge/amd/gx1/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -struct northbridge_amd_gx1_config -{ -}; - diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index 5c59f73..fbea3b5 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -7,7 +7,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include "northbridge.h" #include <cpu/amd/gx1def.h> #include <cpu/x86/cache.h> diff --git a/src/northbridge/amd/gx2/chip.h b/src/northbridge/amd/gx2/chip.h deleted file mode 100644 index 1e266c6..0000000 --- a/src/northbridge/amd/gx2/chip.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_gx2_config -{ - -}; - diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index 8da37b4..12096d8 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include "northbridge.h" #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index 37fcf7e..f51bcc6 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include "northbridge.h" #include <cpu/amd/gx2def.h> #include <cpu/x86/msr.h> diff --git a/src/northbridge/amd/lx/chip.h b/src/northbridge/amd/lx/chip.h deleted file mode 100644 index 12b50fb..0000000 --- a/src/northbridge/amd/lx/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_lx_config { -}; - diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 9ceceb8..5f98b40 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -33,7 +33,6 @@ #include <cpu/x86/cache.h> #include <cpu/amd/vr.h> #include <cpu/cpu.h> -#include "chip.h" #include "northbridge.h" #include "../../../southbridge/amd/cs5536/cs5536.h" diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 54cc057..6288608 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include "northbridge.h" #include <cpu/amd/lxdef.h> #include <cpu/x86/msr.h> diff --git a/src/northbridge/intel/e7501/chip.h b/src/northbridge/intel/e7501/chip.h deleted file mode 100644 index 112c03c..0000000 --- a/src/northbridge/intel/e7501/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -struct northbridge_intel_e7501_config -{ -}; - diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 1fa77d7..c70f032 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -7,7 +7,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> diff --git a/src/northbridge/intel/e7505/chip.h b/src/northbridge/intel/e7505/chip.h deleted file mode 100644 index 8fd3cdc..0000000 --- a/src/northbridge/intel/e7505/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -struct northbridge_intel_e7505_config -{ -}; - diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 9046f43..b6d24fa 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -7,7 +7,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include "e7505.h" #if CONFIG_WRITE_HIGH_TABLES diff --git a/src/northbridge/intel/i440bx/chip.h b/src/northbridge/intel/i440bx/chip.h deleted file mode 100644 index 15ecb4d..0000000 --- a/src/northbridge/intel/i440bx/chip.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_i440bx_config -{ -}; - diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 18e5716..39bd6b9 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -9,7 +9,6 @@ #include <bitops.h> #include <cpu/cpu.h> #include <pc80/keyboard.h> -#include "chip.h" #include "northbridge.h" #include "i440bx.h" diff --git a/src/northbridge/intel/i440lx/chip.h b/src/northbridge/intel/i440lx/chip.h deleted file mode 100644 index 19a9b26..0000000 --- a/src/northbridge/intel/i440lx/chip.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Maciej Pijanka <maciej.pijanka(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_i440lx_config -{ -}; - diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index f34b5ab..57fcfcb 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -30,7 +30,6 @@ #include <bitops.h> #include <cpu/cpu.h> #include <pc80/keyboard.h> -#include "chip.h" #include "northbridge.h" #include "i440lx.h" diff --git a/src/northbridge/intel/i5000/chip.h b/src/northbridge/intel/i5000/chip.h deleted file mode 100644 index 214ffcf..0000000 --- a/src/northbridge/intel/i5000/chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_i5000_config { -}; - diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index ea3665c..1548f19 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -29,7 +29,6 @@ #include <cpu/cpu.h> #include <arch/acpi.h> #include <cbmem.h> -#include "chip.h" #if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif diff --git a/src/northbridge/intel/i82810/chip.h b/src/northbridge/intel/i82810/chip.h deleted file mode 100644 index c571677..0000000 --- a/src/northbridge/intel/i82810/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_i82810_config { -}; - diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 5c51b9a..4c09d44 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -29,7 +29,6 @@ #include <string.h> #include <bitops.h> #include <cpu/cpu.h> -#include "chip.h" #include "northbridge.h" #include "i82810.h" diff --git a/src/northbridge/intel/i82830/chip.h b/src/northbridge/intel/i82830/chip.h deleted file mode 100644 index d0360fe..0000000 --- a/src/northbridge/intel/i82830/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Joseph Smith <joe(a)smittys.pointclark.net> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_i82830_config { -}; - diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index f3341d4..95ac2ed 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -28,7 +28,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include "i82830.h" static void northbridge_init(device_t dev) diff --git a/src/northbridge/intel/i855/chip.h b/src/northbridge/intel/i855/chip.h deleted file mode 100644 index 40b1d38..0000000 --- a/src/northbridge/intel/i855/chip.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Jon Dufresne <jon.dufresne(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_i855_config -{ -}; - diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index b59ba50..74e2c76 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -31,7 +31,6 @@ #include <bitops.h> #include <cpu/x86/cache.h> #include <cpu/cpu.h> -#include "chip.h" static void northbridge_init(device_t dev) { diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h deleted file mode 100644 index 2deb985..0000000 --- a/src/northbridge/intel/i945/chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_i945_config { -}; - diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 41b15cf..684bb71 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -29,7 +29,6 @@ #include <bitops.h> #include <cpu/cpu.h> #include <arch/acpi.h> -#include "chip.h" #include "i945.h" static int get_pcie_bar(u32 *base, u32 *len) diff --git a/src/northbridge/intel/sch/chip.h b/src/northbridge/intel/sch/chip.h deleted file mode 100644 index b3aebd3..0000000 --- a/src/northbridge/intel/sch/chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_sch_config { -}; - diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 48556e2..16ada2f 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -29,7 +29,6 @@ #include <bitops.h> #include <cpu/cpu.h> #include <arch/acpi.h> -#include "chip.h" #include "sch.h" static int get_pcie_bar(u32 *base, u32 *len) diff --git a/src/northbridge/rdc/r8610/chip.h b/src/northbridge/rdc/r8610/chip.h deleted file mode 100644 index 150f032..0000000 --- a/src/northbridge/rdc/r8610/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_rdc_r8610_config { -}; - diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index 250ace0..65fd5eb 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -30,7 +30,6 @@ #include <string.h> #include <bitops.h> #include <smbios.h> -#include "chip.h" #if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> diff --git a/src/northbridge/via/cn400/agp.c b/src/northbridge/via/cn400/agp.c index a302759..f6dbc69 100644 --- a/src/northbridge/via/cn400/agp.c +++ b/src/northbridge/via/cn400/agp.c @@ -24,7 +24,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "chip.h" #include "northbridge.h" #include "cn400.h" diff --git a/src/northbridge/via/cn400/chip.h b/src/northbridge/via/cn400/chip.h deleted file mode 100644 index e403d35..0000000 --- a/src/northbridge/via/cn400/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_via_cn400_config { -}; - diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index 74e0edf..61d7345 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -30,7 +30,6 @@ #include <string.h> #include <bitops.h> #include <cpu/cpu.h> -#include "chip.h" #include "northbridge.h" #include "cn400.h" diff --git a/src/northbridge/via/cn400/vga.c b/src/northbridge/via/cn400/vga.c index 7641a81..8c75a4f 100644 --- a/src/northbridge/via/cn400/vga.c +++ b/src/northbridge/via/cn400/vga.c @@ -34,7 +34,6 @@ #include <bitops.h> #include <cpu/cpu.h> #include <arch/interrupt.h> -#include "chip.h" #include "northbridge.h" #include "cn400.h" diff --git a/src/northbridge/via/cn400/vlink.c b/src/northbridge/via/cn400/vlink.c index dc574c1..85a0fc6 100644 --- a/src/northbridge/via/cn400/vlink.c +++ b/src/northbridge/via/cn400/vlink.c @@ -22,7 +22,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "chip.h" #include "northbridge.h" #include "cn400.h" diff --git a/src/northbridge/via/cn700/agp.c b/src/northbridge/via/cn700/agp.c index 327fac4..ba84f79 100644 --- a/src/northbridge/via/cn700/agp.c +++ b/src/northbridge/via/cn700/agp.c @@ -24,7 +24,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "chip.h" #include "northbridge.h" #include "cn700.h" diff --git a/src/northbridge/via/cn700/chip.h b/src/northbridge/via/cn700/chip.h deleted file mode 100644 index 5b1515d..0000000 --- a/src/northbridge/via/cn700/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_via_cn700_config { -}; - diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index ced4c2f..837ec85 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -30,7 +30,6 @@ #include <string.h> #include <bitops.h> #include <cpu/cpu.h> -#include "chip.h" #include "northbridge.h" #include "cn700.h" diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c index 33d1fe0..d184644 100644 --- a/src/northbridge/via/cn700/vga.c +++ b/src/northbridge/via/cn700/vga.c @@ -34,7 +34,6 @@ #include <bitops.h> #include <cpu/cpu.h> #include <arch/interrupt.h> -#include "chip.h" #include "northbridge.h" #include "cn700.h" diff --git a/src/northbridge/via/cx700/chip.h b/src/northbridge/via/cx700/chip.h deleted file mode 100644 index 0e8491b..0000000 --- a/src/northbridge/via/cx700/chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_via_cx700_config { -}; - diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index 4fca723..1df9ce0 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -29,7 +29,6 @@ #include <bitops.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include "chip.h" #include "northbridge.h" #if CONFIG_WRITE_HIGH_TABLES diff --git a/src/northbridge/via/cx700/vga.c b/src/northbridge/via/cx700/vga.c index 91dd864..821edc4 100644 --- a/src/northbridge/via/cx700/vga.c +++ b/src/northbridge/via/cx700/vga.c @@ -31,7 +31,6 @@ #include <cpu/x86/msr.h> #include <arch/interrupt.h> #include "registers.h" -#include "chip.h" #include "northbridge.h" /* PCI Domain 1 Device 0 Function 0 */ diff --git a/src/northbridge/via/vt8601/chip.h b/src/northbridge/via/vt8601/chip.h deleted file mode 100644 index c65e12e..0000000 --- a/src/northbridge/via/vt8601/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -struct northbridge_via_vt8601_config -{ -}; - diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 92adf32..f5f084c 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -9,7 +9,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include "northbridge.h" /* diff --git a/src/northbridge/via/vt8623/chip.h b/src/northbridge/via/vt8623/chip.h deleted file mode 100644 index 5fb3f80..0000000 --- a/src/northbridge/via/vt8623/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -struct northbridge_via_vt8623_config -{ -}; - diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 5ea2212..76cd7a0 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -11,7 +11,6 @@ #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> -#include "chip.h" #include "northbridge.h" /* diff --git a/src/northbridge/via/vt8623/vga.c b/src/northbridge/via/vt8623/vga.c index 933c733..20857a6 100644 --- a/src/northbridge/via/vt8623/vga.c +++ b/src/northbridge/via/vt8623/vga.c @@ -30,7 +30,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <arch/interrupt.h> -#include "chip.h" #include "northbridge.h" static int via_vt8623_int15_handler(struct eregs *regs) diff --git a/src/northbridge/via/vx800/chip.h b/src/northbridge/via/vx800/chip.h deleted file mode 100644 index 64df31a..0000000 --- a/src/northbridge/via/vx800/chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_via_vx800_config { -}; - diff --git a/src/northbridge/via/vx800/ide.c b/src/northbridge/via/vx800/ide.c index 9fa8f35..4ed4879 100644 --- a/src/northbridge/via/vx800/ide.c +++ b/src/northbridge/via/vx800/ide.c @@ -22,7 +22,6 @@ #include <device/pci_ops.h> #include <device/pci_ids.h> #include <console/console.h> -#include "chip.h" #include <arch/io.h> #include "vx800.h" @@ -191,10 +190,6 @@ static void ide_init(struct device *dev) pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); #if 0 - - struct southbridge_via_vt8237r_config *sb = - (struct southbridge_via_vt8237r_config *)dev->chip_info; - u8 enables; u32 cablesel; diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index b9941d1..b5cd5a3 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -28,7 +28,6 @@ #include <pc80/keyboard.h> #include <pc80/i8259.h> #include "vx800.h" -#include "chip.h" static const unsigned char pciIrqs[4] = { 0xa, 0x9, 0xb, 0xa }; diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index f3cfa41..6274e23 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -31,7 +31,6 @@ #include <string.h> #include <bitops.h> #include <cpu/cpu.h> -#include "chip.h" #include "northbridge.h" #include "vx800.h" diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index e438012..bb7de9e 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -33,7 +33,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <arch/interrupt.h> -#include "chip.h" #include "northbridge.h" /* PCI Domain 1 Device 0 Function 0 */ diff --git a/src/southbridge/amd/cimx/sb700/chip_name.c b/src/southbridge/amd/cimx/sb700/chip_name.c deleted file mode 100644 index 13d2276..0000000 --- a/src/southbridge/amd/cimx/sb700/chip_name.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include "chip.h" - -struct chip_operations southbridge_amd_cimx_sb700_ops = { - CHIP_NAME("AMD South Bridge SB700") -}; diff --git a/src/southbridge/amd/cimx/sb800/chip_name.c b/src/southbridge/amd/cimx/sb800/chip_name.c deleted file mode 100644 index 9ce89d6..0000000 --- a/src/southbridge/amd/cimx/sb800/chip_name.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include "chip.h" - -struct chip_operations southbridge_amd_cimx_sb800_ops = { - CHIP_NAME("AMD South Bridge SB800") -}; diff --git a/src/southbridge/amd/cimx/sb900/chip_name.c b/src/southbridge/amd/cimx/sb900/chip_name.c deleted file mode 100644 index dd875dc..0000000 --- a/src/southbridge/amd/cimx/sb900/chip_name.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include "chip.h" - -struct chip_operations southbridge_amd_cimx_sb900_ops = { - CHIP_NAME("AMD South Bridge SB900") -}; diff --git a/src/southbridge/intel/i82801cx/chip.h b/src/southbridge/intel/i82801cx/chip.h deleted file mode 100644 index 5618521..0000000 --- a/src/southbridge/intel/i82801cx/chip.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef I82801CX_CHIP_H -#define I82801CX_CHIP_H - -struct southbridge_intel_i82801cx_config -{ -}; - -#endif /* I82801CX_CHIP_H */ diff --git a/src/southbridge/intel/i82801cx/i82801cx.h b/src/southbridge/intel/i82801cx/i82801cx.h index da518a3..2842883 100644 --- a/src/southbridge/intel/i82801cx/i82801cx.h +++ b/src/southbridge/intel/i82801cx/i82801cx.h @@ -3,7 +3,6 @@ #if !defined(__PRE_RAM__) #include <device/device.h> -#include "chip.h" void i82801cx_enable(device_t dev); void i82801cx_hard_reset(void); #endif diff --git a/src/southbridge/intel/pxhd/chip.h b/src/southbridge/intel/pxhd/chip.h deleted file mode 100644 index 27d88a8..0000000 --- a/src/southbridge/intel/pxhd/chip.h +++ /dev/null @@ -1,5 +0,0 @@ -struct southbridge_intel_pxhd_config -{ - /* nothing */ -}; - diff --git a/src/southbridge/intel/pxhd/pxhd.h b/src/southbridge/intel/pxhd/pxhd.h index c3e6ce5..b0e8cdb 100644 --- a/src/southbridge/intel/pxhd/pxhd.h +++ b/src/southbridge/intel/pxhd/pxhd.h @@ -1,6 +1,5 @@ #ifndef PXHD_H #define PXHD_H -#include "chip.h" #endif /* PXHD_H */ diff --git a/src/southbridge/ti/pcixx12/chip.h b/src/southbridge/ti/pcixx12/chip.h deleted file mode 100644 index 03151a8..0000000 --- a/src/southbridge/ti/pcixx12/chip.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _SOUTHBRIDGE_TI_PCIXX12 -#define _SOUTHBRIDGE_TI_PCIXX12 - -struct southbridge_ti_pcixx12_config { - int dummy; - -}; - -#endif /* _SOUTHBRIDGE_TI_PCIXX12 */ diff --git a/src/southbridge/ti/pcixx12/pcixx12.c b/src/southbridge/ti/pcixx12/pcixx12.c index 0ea3b11..5e62292 100644 --- a/src/southbridge/ti/pcixx12/pcixx12.c +++ b/src/southbridge/ti/pcixx12/pcixx12.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <console/console.h> #include <device/cardbus.h> -#include "chip.h" static void pcixx12_init(device_t dev) { @@ -62,7 +61,6 @@ static const struct pci_driver ti_pcixx12_driver __pci_driver = { static void southbridge_init(device_t dev) { - // struct southbridge_ti_pcixx12_config *config = dev->chip_info; } struct chip_operations southbridge_ti_pcixx12_ops = { diff --git a/src/superio/fintek/f71805f/chip.h b/src/superio/fintek/f71805f/chip.h deleted file mode 100644 index 603dbee..0000000 --- a/src/superio/fintek/f71805f/chip.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_FINTEK_F71805F_CHIP_H -#define SUPERIO_FINTEK_F71805F_CHIP_H - -#include <device/device.h> -#include <uart8250.h> - -/* This chip doesn't have keyboard and mouse support. */ - -struct superio_fintek_f71805f_config { - -}; - -#endif diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c index 5f17946..afe5b8c 100644 --- a/src/superio/fintek/f71805f/superio.c +++ b/src/superio/fintek/f71805f/superio.c @@ -24,7 +24,6 @@ #include <console/console.h> #include <stdlib.h> #include <uart8250.h> -#include "chip.h" #include "f71805f.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f71859/chip.h b/src/superio/fintek/f71859/chip.h deleted file mode 100644 index bd45ac0..0000000 --- a/src/superio/fintek/f71859/chip.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Marc Jones <marcj303(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_FINTEK_F71859_CHIP_H -#define SUPERIO_FINTEK_F71859_CHIP_H - -#include <device/device.h> -#include <uart8250.h> - -struct superio_fintek_f71859_config { - -}; - -#endif diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index 809140b..a0158ba 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -25,7 +25,6 @@ #include <console/console.h> #include <stdlib.h> #include <uart8250.h> -#include "chip.h" #include "f71859.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/intel/i3100/chip.h b/src/superio/intel/i3100/chip.h deleted file mode 100644 index 05e2f45..0000000 --- a/src/superio/intel/i3100/chip.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_INTEL_I3100_CHIP_H -#define SUPERIO_INTEL_I3100_CHIP_H - -#include <device/device.h> -#include <uart8250.h> - -struct superio_intel_i3100_config { -}; - -#endif diff --git a/src/superio/intel/i3100/superio.c b/src/superio/intel/i3100/superio.c index 74862eb..b8c107d 100644 --- a/src/superio/intel/i3100/superio.c +++ b/src/superio/intel/i3100/superio.c @@ -22,7 +22,6 @@ #include <device/device.h> #include <device/pnp.h> #include <uart8250.h> -#include "chip.h" #include "i3100.h" #include <arch/io.h> diff --git a/src/superio/ite/it8661f/chip.h b/src/superio/ite/it8661f/chip.h deleted file mode 100644 index 1d9d1f9..0000000 --- a/src/superio/ite/it8661f/chip.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_ITE_IT8661F_CHIP_H -#define SUPERIO_ITE_IT8661F_CHIP_H - -/* This chip doesn't have keyboard and mouse support. */ - -#include <device/device.h> -#include <uart8250.h> - -struct superio_ite_it8661f_config { - -}; - -#endif diff --git a/src/superio/ite/it8661f/superio.c b/src/superio/ite/it8661f/superio.c index fcf54e7..a348a7f 100644 --- a/src/superio/ite/it8661f/superio.c +++ b/src/superio/ite/it8661f/superio.c @@ -22,7 +22,6 @@ #include <device/pnp.h> #include <uart8250.h> #include <stdlib.h> -#include "chip.h" #include "it8661f.h" /* TODO: Add pnp_enter_ext_func_mode() etc. and wrap functions. */ diff --git a/src/superio/ite/it8705f/chip.h b/src/superio/ite/it8705f/chip.h deleted file mode 100644 index ac2ba77..0000000 --- a/src/superio/ite/it8705f/chip.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_ITE_IT8705F_CHIP_H -#define SUPERIO_ITE_IT8705F_CHIP_H - -/* This chip doesn't have keyboard and mouse support. */ - -#include <device/device.h> -#include <uart8250.h> - -struct superio_ite_it8705f_config { - -}; - -#endif diff --git a/src/superio/ite/it8705f/superio.c b/src/superio/ite/it8705f/superio.c index 8f14a34..8992ea2 100644 --- a/src/superio/ite/it8705f/superio.c +++ b/src/superio/ite/it8705f/superio.c @@ -22,13 +22,10 @@ #include <device/pnp.h> #include <uart8250.h> #include <stdlib.h> -#include "chip.h" #include "it8705f.h" static void init(device_t dev) { - struct superio_ite_it8705f_config *conf = dev->chip_info; - if (!dev->enabled) return; diff --git a/src/superio/nsc/pc87382/chip.h b/src/superio/nsc/pc87382/chip.h deleted file mode 100644 index a9f0200..0000000 --- a/src/superio/nsc/pc87382/chip.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_NSC_PC87382_CHIP_H -#define SUPERIO_NSC_PC87382_CHIP_H - -#include <uart8250.h> - -struct superio_nsc_pc87382_config { - -}; - -#endif diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 7f4afe3..9d4bee0 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -27,7 +27,6 @@ #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "chip.h" #include "pc87382.h" static void init(device_t dev) diff --git a/src/superio/nsc/pc87384/chip.h b/src/superio/nsc/pc87384/chip.h deleted file mode 100644 index 1c49725..0000000 --- a/src/superio/nsc/pc87384/chip.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_NSC_PC87384_CHIP_H -#define SUPERIO_NSC_PC87384_CHIP_H - -#include <uart8250.h> - -struct superio_nsc_pc87384_config { - -}; - -#endif diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c index 11ddc82..39177fd 100644 --- a/src/superio/nsc/pc87384/superio.c +++ b/src/superio/nsc/pc87384/superio.c @@ -27,7 +27,6 @@ #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "chip.h" #include "pc87384.h" static struct device_operations ops = { diff --git a/src/superio/nsc/pc87392/chip.h b/src/superio/nsc/pc87392/chip.h deleted file mode 100644 index a6ebf1b..0000000 --- a/src/superio/nsc/pc87392/chip.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_NSC_PC87392_CHIP_H -#define SUPERIO_NSC_PC87392_CHIP_H - -#include <uart8250.h> - -struct superio_nsc_pc87392_config { - -}; - -#endif diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index 1b527ad..81c679c 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -26,7 +26,6 @@ #include <bitops.h> #include <uart8250.h> #include <stdlib.h> -#include "chip.h" #include "pc87392.h" static void init(device_t dev) diff --git a/src/superio/smsc/lpc47n217/chip.h b/src/superio/smsc/lpc47n217/chip.h deleted file mode 100644 index b0fbe8c..0000000 --- a/src/superio/smsc/lpc47n217/chip.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_SMSC_LPC47N217_CHIP_H -#define SUPERIO_SMSC_LPC47N217_CHIP_H - -#include <uart8250.h> - -struct superio_smsc_lpc47n217_config { - -}; - -#endif diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index 01c96b1..2658831 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -33,7 +33,6 @@ #include <uart8250.h> #include <assert.h> #include <stdlib.h> -#include "chip.h" #include "lpc47n217.h" /* Forward declarations */ @@ -133,9 +132,6 @@ static void lpc47n217_pnp_enable(device_t dev) */ static void lpc47n217_init(device_t dev) { - /* TODO: Reserved for future. */ - /* struct superio_smsc_lpc47n217_config* conf = dev->chip_info; */ - if (!dev->enabled) return; } diff --git a/src/superio/via/vt1211/chip.h b/src/superio/via/vt1211/chip.h deleted file mode 100644 index 89d64cd..0000000 --- a/src/superio/via/vt1211/chip.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Nick Barker <nick.barker9(a)btinternet.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_VIA_VT1211_CHIP_H -#define SUPERIO_VIA_VT1211_CHIP_H - -#include <uart8250.h> - -struct superio_via_vt1211_config { - -}; - -#endif diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index e681d6e..abcae77 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -26,7 +26,6 @@ #include <uart8250.h> #include <stdlib.h> #include "vt1211.h" -#include "chip.h" static u8 hwm_io_regs[] = { 0x10,0x03, 0x11,0x10, 0x12,0x0d, 0x13,0x7f, diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 3aa57f9..f066d7b 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -179,25 +179,24 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) { } void add_header(struct device *dev) { - if ((dev->chiph_exists) || (scan_mode == KCONFIG_MODE)){ - int include_exists = 0; - struct header *h = &headers; - while (h->next) { - int result = strcmp(dev->name, h->next->name); - if (result == 0) { - include_exists = 1; - break; - } - if (result < 0) break; - h = h->next; - } - if (!include_exists) { - struct header *tmp = h->next; - h->next = malloc(sizeof(struct header)); - memset(h->next, 0, sizeof(struct header)); - h->next->name = dev->name; - h->next->next = tmp; + int include_exists = 0; + struct header *h = &headers; + while (h->next) { + int result = strcmp(dev->name, h->next->name); + if (result == 0) { + include_exists = 1; + break; } + if (result < 0) break; + h = h->next; + } + if (!include_exists) { + struct header *tmp = h->next; + h->next = malloc(sizeof(struct header)); + memset(h->next, 0, sizeof(struct header)); + h->next->chiph_exists = dev->chiph_exists; + h->next->name = dev->name; + h->next->next = tmp; } } @@ -617,8 +616,10 @@ int main(int argc, char** argv) { h = &headers; while (h->next) { h = h->next; - fprintf(autogen, "#include \"%s/chip.h\"\n", h->name); + if (h->chiph_exists) + fprintf(autogen, "#include \"%s/chip.h\"\n", h->name); } + fprintf(autogen, "\n#ifndef __PRE_RAM__\n"); h = &headers; while (h->next) { h = h->next; @@ -627,6 +628,7 @@ int main(int argc, char** argv) { fprintf(autogen, "extern struct chip_operations %s_ops;\n", name_underscore); free(name_underscore); } + fprintf(autogen, "#endif\n"); walk_device_tree(autogen, &root, inherit_subsystem_ids, NULL); fprintf(autogen, "\n/* pass 0 */\n"); diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index 1576600..b8a231a 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -86,6 +86,7 @@ struct device *head; struct header; struct header { char *name; + int chiph_exists; struct header *next; };

1 0

Patch set updated for coreboot: b4a6409 Every chip must have chip_operations
by Kyösti Mälkki 27 Aug '12

27 Aug '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1472 -gerrit commit b4a6409a8db16e92922f207612f009ce5d1f13f8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Aug 21 17:54:26 2012 +0300 Every chip must have chip_operations Forcing this rule, chip_ops can be added in the static devicetree regardless of the existence of the chip.h files. Take care of NULL .name case in dummy chip_operations. Fix typo in mPGA603 socket. Change-Id: Iec1c23484e85cab3f80a34f2b082088f38ac4de9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/smbios.c | 3 ++- .../intel/socket_mPGA603/socket_mPGA603_400Mhz.c | 2 +- src/devices/Makefile.inc | 3 +++ src/devices/dummy_chip_ops.c | 27 ++++++++++++++++++++++ util/sconfig/main.c | 13 ++++------- 5 files changed, 37 insertions(+), 11 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 8877f60..a171707 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -278,7 +278,8 @@ static int smbios_walk_device_tree(device_t tree, int *handle, unsigned long *cu int len = 0; for(dev = tree; dev; dev = dev->next) { - printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), dev->chip_ops ? dev->chip_ops->name : ""); + printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), + (dev->chip_ops && dev->chip_ops->name) ? dev->chip_ops->name : ""); if (dev->ops && dev->ops->get_smbios_data) len += dev->ops->get_smbios_data(dev, handle, current); diff --git a/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c b/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c index 9154608..2436f96 100644 --- a/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c +++ b/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c @@ -2,6 +2,6 @@ #include "chip.h" -struct chip_opertations cpu_intel_socket_mPGA603_ops = { +struct chip_operations cpu_intel_socket_mPGA603_ops = { CHIP_NAME("Socket mPGA603 400Mhz CPU") }; diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 9a2f71e..cde8b3f 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -11,6 +11,9 @@ ramstage-y += pnp_device.c ramstage-y += pci_ops.c ramstage-y += smbus_ops.c +# Work-around for chip.h removal +ramstage-y += dummy_chip_ops.c + romstage-y+= device_romstage.c subdirs-y += oprom diff --git a/src/devices/dummy_chip_ops.c b/src/devices/dummy_chip_ops.c new file mode 100644 index 0000000..b29a566 --- /dev/null +++ b/src/devices/dummy_chip_ops.c @@ -0,0 +1,27 @@ +#include <device/device.h> + +/* Dummy chip_operations, so every chip has one for sure. + * Temporary work-around before total chip.h removal. + */ + +struct chip_operations cpu_via_c3_ops = {}; +struct chip_operations cpu_via_c7_ops = {}; +struct chip_operations drivers_ati_ragexl_ops = {}; +struct chip_operations drivers_dec_21143_ops = {}; +struct chip_operations drivers_generic_generic_ops = {}; +struct chip_operations drivers_oxford_oxpcie_ops = {}; +struct chip_operations drivers_realtek_ops = {}; +struct chip_operations drivers_sil_3114_ops = {}; +struct chip_operations drivers_trident_blade3d_ops = {}; +struct chip_operations southbridge_amd_amd8131_ops = {}; +struct chip_operations southbridge_amd_amd8132_ops = {}; +struct chip_operations southbridge_amd_amd8151_ops = {}; +struct chip_operations southbridge_broadcom_bcm21000_ops = {}; +struct chip_operations southbridge_broadcom_bcm5780_ops = {}; +struct chip_operations southbridge_intel_i82870_ops = {}; +struct chip_operations southbridge_rdc_r8610_ops = {}; +struct chip_operations southbridge_via_k8t890_ops = {}; +struct chip_operations superio_serverengines_pilot_ops = {}; +struct chip_operations superio_smsc_lpc47n207_ops = {}; +struct chip_operations superio_smsc_sio1007_ops = {}; + diff --git a/util/sconfig/main.c b/util/sconfig/main.c index fe4c3b8..3aa57f9 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -418,16 +418,11 @@ static void pass1(FILE *fil, struct device *ptr) fprintf(fil, "\t.link_list = NULL,\n"); if (ptr->sibling) fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); - if (ptr->chip->chiph_exists) { - fprintf(fil, "#ifndef __PRE_RAM__\n"); - fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); - fprintf(fil, "#endif\n"); + fprintf(fil, "#ifndef __PRE_RAM__\n"); + fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); + fprintf(fil, "#endif\n"); + if (ptr->chip->chiph_exists) fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id); - } else if (ptr->chip->chip == &mainboard) { - fprintf(fil, "#ifndef __PRE_RAM__\n"); - fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); - fprintf(fil, "#endif\n"); - } if (ptr->nextdev) fprintf(fil, "\t.next=&%s\n", ptr->nextdev->name); fprintf(fil, "};\n");

1 0

Patch set updated for coreboot: feb249a Remove chip.h files without config structure
by Kyösti Mälkki 27 Aug '12

27 Aug '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1473 -gerrit commit feb249a8aebdfbe173d65cf6ac49b4093712fde1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Aug 24 21:54:10 2012 +0300 Remove chip.h files without config structure Also deletes files not included in build: src/southbridge/amd/cimx/sb700/chip_name.c src/southbridge/amd/cimx/sb800/chip_name.c src/southbridge/amd/cimx/sb900/chip_name.c Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/family10/chip.h | 21 ------------ src/cpu/amd/agesa/family10/chip_name.c | 1 - src/cpu/amd/agesa/family12/chip.h | 21 ------------ src/cpu/amd/agesa/family12/chip_name.c | 1 - src/cpu/amd/agesa/family14/chip.h | 21 ------------ src/cpu/amd/agesa/family14/chip_name.c | 1 - src/cpu/amd/agesa/family15/chip.h | 21 ------------ src/cpu/amd/agesa/family15/chip_name.c | 1 - src/cpu/amd/agesa/family15tn/chip.h | 21 ------------ src/cpu/amd/agesa/family15tn/chip_name.c | 1 - src/cpu/amd/sc520/chip.h | 2 -- src/cpu/amd/sc520/sc520.c | 1 - src/cpu/amd/socket_754/chip.h | 2 -- src/cpu/amd/socket_754/socket_754.c | 1 - src/cpu/amd/socket_939/chip.h | 2 -- src/cpu/amd/socket_939/socket_939.c | 1 - src/cpu/amd/socket_940/chip.h | 2 -- src/cpu/amd/socket_940/socket_940.c | 1 - src/cpu/amd/socket_AM2/chip.h | 2 -- src/cpu/amd/socket_AM2/socket_AM2.c | 1 - src/cpu/amd/socket_AM2r2/chip.h | 21 ------------ src/cpu/amd/socket_AM2r2/socket_AM2r2.c | 1 - src/cpu/amd/socket_AM3/chip.h | 21 ------------ src/cpu/amd/socket_AM3/socket_AM3.c | 1 - src/cpu/amd/socket_ASB2/chip.h | 21 ------------ src/cpu/amd/socket_ASB2/socket_ASB2.c | 1 - src/cpu/amd/socket_C32/chip.h | 21 ------------ src/cpu/amd/socket_C32/socket_C32.c | 1 - src/cpu/amd/socket_F/chip.h | 2 -- src/cpu/amd/socket_F/socket_F.c | 1 - src/cpu/amd/socket_F_1207/chip.h | 21 ------------ src/cpu/amd/socket_F_1207/socket_F_1207.c | 1 - src/cpu/amd/socket_S1G1/chip.h | 2 -- src/cpu/amd/socket_S1G1/socket_S1G1.c | 1 - src/cpu/intel/ep80579/chip.h | 21 ------------ src/cpu/intel/ep80579/ep80579.c | 1 - src/cpu/intel/slot_1/chip.h | 22 ------------ src/cpu/intel/slot_1/slot_1.c | 1 - src/cpu/intel/slot_2/chip.h | 2 -- src/cpu/intel/slot_2/slot_2.c | 1 - src/cpu/intel/socket_441/chip.h | 21 ------------ src/cpu/intel/socket_441/socket_441.c | 1 - src/cpu/intel/socket_BGA956/chip.h | 2 -- src/cpu/intel/socket_BGA956/socket_BGA956.c | 1 - src/cpu/intel/socket_FC_PGA370/chip.h | 22 ------------ src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c | 1 - src/cpu/intel/socket_LGA771/chip.h | 2 -- src/cpu/intel/socket_LGA771/socket_LGA771.c | 1 - src/cpu/intel/socket_PGA370/chip.h | 2 -- src/cpu/intel/socket_PGA370/socket_PGA370.c | 1 - src/cpu/intel/socket_mFCBGA479/chip.h | 2 -- src/cpu/intel/socket_mFCBGA479/socket_mFCBGA479.c | 1 - src/cpu/intel/socket_mFCPGA478/chip.h | 2 -- src/cpu/intel/socket_mFCPGA478/socket_mFCPGA478.c | 1 - src/cpu/intel/socket_mPGA478/chip.h | 2 -- src/cpu/intel/socket_mPGA478/socket_mPGA478.c | 1 - src/cpu/intel/socket_mPGA479M/chip.h | 2 -- src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c | 1 - src/cpu/intel/socket_mPGA603/chip.h | 2 -- .../intel/socket_mPGA603/socket_mPGA603_400Mhz.c | 1 - src/cpu/intel/socket_mPGA604/chip.h | 2 -- src/cpu/intel/socket_mPGA604/socket_mPGA604.c | 1 - src/cpu/intel/socket_rPGA989/chip.h | 2 -- src/cpu/intel/socket_rPGA989/socket_rPGA989.c | 1 - src/drivers/generic/debug/chip.h | 2 -- src/drivers/generic/debug/debug_dev.c | 1 - src/drivers/i2c/adm1026/adm1026.c | 1 - src/drivers/i2c/adm1026/chip.h | 2 -- src/drivers/i2c/adm1027/adm1027.c | 1 - src/drivers/i2c/adm1027/chip.h | 2 -- src/drivers/i2c/adt7463/adt7463.c | 1 - src/drivers/i2c/adt7463/chip.h | 2 -- src/drivers/i2c/i2cmux/chip.h | 2 -- src/drivers/i2c/i2cmux/i2cmux.c | 1 - src/drivers/i2c/i2cmux2/chip.h | 2 -- src/drivers/i2c/i2cmux2/i2cmux2.c | 1 - src/drivers/i2c/lm63/chip.h | 2 -- src/drivers/i2c/lm63/lm63.c | 1 - src/drivers/i2c/w83795/chip.h | 2 -- src/mainboard/emulation/qemu-x86/chip.h | 2 -- src/mainboard/emulation/qemu-x86/northbridge.c | 1 - src/northbridge/amd/agesa/family10/chip.h | 23 ------------- src/northbridge/amd/agesa/family10/northbridge.c | 2 -- .../amd/agesa/family10/root_complex/chip.h | 23 ------------- src/northbridge/amd/agesa/family12/chip.h | 23 ------------- src/northbridge/amd/agesa/family12/northbridge.c | 1 - .../amd/agesa/family12/root_complex/chip.h | 23 ------------- src/northbridge/amd/agesa/family14/chip.h | 23 ------------- src/northbridge/amd/agesa/family14/northbridge.c | 1 - .../amd/agesa/family14/root_complex/chip.h | 23 ------------- src/northbridge/amd/agesa/family15/chip.h | 23 ------------- src/northbridge/amd/agesa/family15/northbridge.c | 2 -- .../amd/agesa/family15/root_complex/chip.h | 23 ------------- src/northbridge/amd/agesa/family15tn/chip.h | 23 ------------- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 -- .../amd/agesa/family15tn/root_complex/chip.h | 23 ------------- src/northbridge/amd/amdfam10/chip.h | 23 ------------- src/northbridge/amd/amdfam10/northbridge.c | 1 - src/northbridge/amd/amdfam10/root_complex/chip.h | 23 ------------- src/northbridge/amd/amdk8/chip.h | 4 --- src/northbridge/amd/amdk8/northbridge.c | 1 - src/northbridge/amd/amdk8/root_complex/chip.h | 4 --- src/northbridge/amd/gx1/chip.h | 4 --- src/northbridge/amd/gx1/northbridge.c | 1 - src/northbridge/amd/gx2/chip.h | 24 ------------- src/northbridge/amd/gx2/northbridge.c | 1 - src/northbridge/amd/gx2/northbridgeinit.c | 1 - src/northbridge/amd/lx/chip.h | 23 ------------- src/northbridge/amd/lx/northbridge.c | 1 - src/northbridge/amd/lx/northbridgeinit.c | 1 - src/northbridge/intel/e7501/chip.h | 4 --- src/northbridge/intel/e7501/northbridge.c | 1 - src/northbridge/intel/e7505/chip.h | 4 --- src/northbridge/intel/e7505/northbridge.c | 1 - src/northbridge/intel/i440bx/chip.h | 24 ------------- src/northbridge/intel/i440bx/northbridge.c | 1 - src/northbridge/intel/i440lx/chip.h | 24 ------------- src/northbridge/intel/i440lx/northbridge.c | 1 - src/northbridge/intel/i5000/chip.h | 22 ------------ src/northbridge/intel/i5000/northbridge.c | 1 - src/northbridge/intel/i82810/chip.h | 23 ------------- src/northbridge/intel/i82810/northbridge.c | 1 - src/northbridge/intel/i82830/chip.h | 23 ------------- src/northbridge/intel/i82830/northbridge.c | 1 - src/northbridge/intel/i855/chip.h | 24 ------------- src/northbridge/intel/i855/northbridge.c | 1 - src/northbridge/intel/i945/chip.h | 22 ------------ src/northbridge/intel/i945/northbridge.c | 1 - src/northbridge/intel/sch/chip.h | 22 ------------ src/northbridge/intel/sch/northbridge.c | 1 - src/northbridge/rdc/r8610/chip.h | 23 ------------- src/northbridge/rdc/r8610/northbridge.c | 1 - src/northbridge/via/cn400/agp.c | 1 - src/northbridge/via/cn400/chip.h | 23 ------------- src/northbridge/via/cn400/northbridge.c | 1 - src/northbridge/via/cn400/vga.c | 1 - src/northbridge/via/cn400/vlink.c | 1 - src/northbridge/via/cn700/agp.c | 1 - src/northbridge/via/cn700/chip.h | 23 ------------- src/northbridge/via/cn700/northbridge.c | 1 - src/northbridge/via/cn700/vga.c | 1 - src/northbridge/via/cx700/chip.h | 22 ------------ src/northbridge/via/cx700/northbridge.c | 1 - src/northbridge/via/cx700/vga.c | 1 - src/northbridge/via/vt8601/chip.h | 4 --- src/northbridge/via/vt8601/northbridge.c | 1 - src/northbridge/via/vt8623/chip.h | 4 --- src/northbridge/via/vt8623/northbridge.c | 1 - src/northbridge/via/vt8623/vga.c | 1 - src/northbridge/via/vx800/chip.h | 22 ------------ src/northbridge/via/vx800/ide.c | 5 --- src/northbridge/via/vx800/lpc.c | 1 - src/northbridge/via/vx800/northbridge.c | 1 - src/northbridge/via/vx800/vga.c | 1 - src/southbridge/amd/cimx/sb700/chip_name.c | 25 -------------- src/southbridge/amd/cimx/sb800/chip_name.c | 25 -------------- src/southbridge/amd/cimx/sb900/chip_name.c | 25 -------------- src/southbridge/intel/i82801cx/chip.h | 8 ----- src/southbridge/intel/i82801cx/i82801cx.h | 1 - src/southbridge/intel/pxhd/chip.h | 5 --- src/southbridge/intel/pxhd/pxhd.h | 1 - src/southbridge/ti/pcixx12/chip.h | 28 --------------- src/southbridge/ti/pcixx12/pcixx12.c | 2 -- src/superio/fintek/f71805f/chip.h | 33 ------------------ src/superio/fintek/f71805f/superio.c | 1 - src/superio/fintek/f71859/chip.h | 31 ----------------- src/superio/fintek/f71859/superio.c | 1 - src/superio/intel/i3100/chip.h | 30 ---------------- src/superio/intel/i3100/superio.c | 1 - src/superio/ite/it8661f/chip.h | 33 ------------------ src/superio/ite/it8661f/superio.c | 1 - src/superio/ite/it8705f/chip.h | 33 ------------------ src/superio/ite/it8705f/superio.c | 3 -- src/superio/nsc/pc87382/chip.h | 30 ---------------- src/superio/nsc/pc87382/superio.c | 1 - src/superio/nsc/pc87384/chip.h | 30 ---------------- src/superio/nsc/pc87384/superio.c | 1 - src/superio/nsc/pc87392/chip.h | 30 ---------------- src/superio/nsc/pc87392/superio.c | 1 - src/superio/smsc/lpc47n217/chip.h | 30 ---------------- src/superio/smsc/lpc47n217/superio.c | 4 --- src/superio/via/vt1211/chip.h | 30 ---------------- src/superio/via/vt1211/vt1211.c | 1 - util/sconfig/main.c | 40 ++++++++++++---------- util/sconfig/sconfig.h | 1 + 185 files changed, 22 insertions(+), 1548 deletions(-) diff --git a/src/cpu/amd/agesa/family10/chip.h b/src/cpu/amd/agesa/family10/chip.h deleted file mode 100644 index 4f9fa77..0000000 --- a/src/cpu/amd/agesa/family10/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_agesa_family10_config { -}; diff --git a/src/cpu/amd/agesa/family10/chip_name.c b/src/cpu/amd/agesa/family10/chip_name.c index d99769c..656b4a2 100644 --- a/src/cpu/amd/agesa/family10/chip_name.c +++ b/src/cpu/amd/agesa/family10/chip_name.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_agesa_family10_ops = { CHIP_NAME("AMD CPU Family 10h") diff --git a/src/cpu/amd/agesa/family12/chip.h b/src/cpu/amd/agesa/family12/chip.h deleted file mode 100644 index 0eaa0e2..0000000 --- a/src/cpu/amd/agesa/family12/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_agesa_family12_config { -}; diff --git a/src/cpu/amd/agesa/family12/chip_name.c b/src/cpu/amd/agesa/family12/chip_name.c index 5de72c7..6574615 100644 --- a/src/cpu/amd/agesa/family12/chip_name.c +++ b/src/cpu/amd/agesa/family12/chip_name.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_agesa_family12_ops = { CHIP_NAME("AMD CPU Family 12h") diff --git a/src/cpu/amd/agesa/family14/chip.h b/src/cpu/amd/agesa/family14/chip.h deleted file mode 100644 index 59c7cfe..0000000 --- a/src/cpu/amd/agesa/family14/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_agesa_family14_config { -}; diff --git a/src/cpu/amd/agesa/family14/chip_name.c b/src/cpu/amd/agesa/family14/chip_name.c index 2c296f5..474edc7 100644 --- a/src/cpu/amd/agesa/family14/chip_name.c +++ b/src/cpu/amd/agesa/family14/chip_name.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_agesa_family14_ops = { CHIP_NAME("AMD CPU Family 14h") diff --git a/src/cpu/amd/agesa/family15/chip.h b/src/cpu/amd/agesa/family15/chip.h deleted file mode 100644 index e6daaef..0000000 --- a/src/cpu/amd/agesa/family15/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_agesa_family15_config { -}; diff --git a/src/cpu/amd/agesa/family15/chip_name.c b/src/cpu/amd/agesa/family15/chip_name.c index 963a423..3ca6e9f 100644 --- a/src/cpu/amd/agesa/family15/chip_name.c +++ b/src/cpu/amd/agesa/family15/chip_name.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_agesa_family15_ops = { CHIP_NAME("AMD CPU Family 15h") diff --git a/src/cpu/amd/agesa/family15tn/chip.h b/src/cpu/amd/agesa/family15tn/chip.h deleted file mode 100644 index 5ad93c5..0000000 --- a/src/cpu/amd/agesa/family15tn/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_agesa_family15tn_config { -}; diff --git a/src/cpu/amd/agesa/family15tn/chip_name.c b/src/cpu/amd/agesa/family15tn/chip_name.c index a2a5519..d923260 100644 --- a/src/cpu/amd/agesa/family15tn/chip_name.c +++ b/src/cpu/amd/agesa/family15tn/chip_name.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_agesa_family15tn_ops = { CHIP_NAME("AMD CPU Family 15h") diff --git a/src/cpu/amd/sc520/chip.h b/src/cpu/amd/sc520/chip.h deleted file mode 100644 index 64f3a85..0000000 --- a/src/cpu/amd/sc520/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_amd_sc520_config { -}; diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c index 059e4fd..382eb87 100644 --- a/src/cpu/amd/sc520/sc520.c +++ b/src/cpu/amd/sc520/sc520.c @@ -14,7 +14,6 @@ #include <string.h> #include <bitops.h> #include <delay.h> -#include "chip.h" /* * set up basic things ... diff --git a/src/cpu/amd/socket_754/chip.h b/src/cpu/amd/socket_754/chip.h deleted file mode 100644 index 197145f..0000000 --- a/src/cpu/amd/socket_754/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_amd_socket_754_config { -}; diff --git a/src/cpu/amd/socket_754/socket_754.c b/src/cpu/amd/socket_754/socket_754.c index 8fdcf57..f75c1ec 100644 --- a/src/cpu/amd/socket_754/socket_754.c +++ b/src/cpu/amd/socket_754/socket_754.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_754_ops = { diff --git a/src/cpu/amd/socket_939/chip.h b/src/cpu/amd/socket_939/chip.h deleted file mode 100644 index ca93451..0000000 --- a/src/cpu/amd/socket_939/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_amd_socket_939_config { -}; diff --git a/src/cpu/amd/socket_939/socket_939.c b/src/cpu/amd/socket_939/socket_939.c index 6563752..a44a8a6 100644 --- a/src/cpu/amd/socket_939/socket_939.c +++ b/src/cpu/amd/socket_939/socket_939.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_939_ops = { CHIP_NAME("Socket 939 CPU") diff --git a/src/cpu/amd/socket_940/chip.h b/src/cpu/amd/socket_940/chip.h deleted file mode 100644 index 8b96614..0000000 --- a/src/cpu/amd/socket_940/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_amd_socket_940_config { -}; diff --git a/src/cpu/amd/socket_940/socket_940.c b/src/cpu/amd/socket_940/socket_940.c index 54531ef..872f040 100644 --- a/src/cpu/amd/socket_940/socket_940.c +++ b/src/cpu/amd/socket_940/socket_940.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_940_ops = { CHIP_NAME("Socket 940 CPU") diff --git a/src/cpu/amd/socket_AM2/chip.h b/src/cpu/amd/socket_AM2/chip.h deleted file mode 100644 index 5d9e875..0000000 --- a/src/cpu/amd/socket_AM2/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_amd_socket_AM2_config { -}; diff --git a/src/cpu/amd/socket_AM2/socket_AM2.c b/src/cpu/amd/socket_AM2/socket_AM2.c index 474e19d..60378ab 100644 --- a/src/cpu/amd/socket_AM2/socket_AM2.c +++ b/src/cpu/amd/socket_AM2/socket_AM2.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_AM2_ops = { CHIP_NAME("Socket AM2 CPU") diff --git a/src/cpu/amd/socket_AM2r2/chip.h b/src/cpu/amd/socket_AM2r2/chip.h deleted file mode 100644 index 1c93a99..0000000 --- a/src/cpu/amd/socket_AM2r2/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_socket_AM2r2_config { -}; diff --git a/src/cpu/amd/socket_AM2r2/socket_AM2r2.c b/src/cpu/amd/socket_AM2r2/socket_AM2r2.c index 3f98e53..d618563 100644 --- a/src/cpu/amd/socket_AM2r2/socket_AM2r2.c +++ b/src/cpu/amd/socket_AM2r2/socket_AM2r2.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_AM2r2_ops = { CHIP_NAME("socket AM2r2") diff --git a/src/cpu/amd/socket_AM3/chip.h b/src/cpu/amd/socket_AM3/chip.h deleted file mode 100644 index 70f6b1f..0000000 --- a/src/cpu/amd/socket_AM3/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_socket_AM3_config { -}; diff --git a/src/cpu/amd/socket_AM3/socket_AM3.c b/src/cpu/amd/socket_AM3/socket_AM3.c index 75b3970..91871e8 100644 --- a/src/cpu/amd/socket_AM3/socket_AM3.c +++ b/src/cpu/amd/socket_AM3/socket_AM3.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_AM3_ops = { CHIP_NAME("socket AM3") diff --git a/src/cpu/amd/socket_ASB2/chip.h b/src/cpu/amd/socket_ASB2/chip.h deleted file mode 100644 index 5939c2b..0000000 --- a/src/cpu/amd/socket_ASB2/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_socket_ASB2_config { -}; diff --git a/src/cpu/amd/socket_ASB2/socket_ASB2.c b/src/cpu/amd/socket_ASB2/socket_ASB2.c index fd3b522..3c38a8c 100644 --- a/src/cpu/amd/socket_ASB2/socket_ASB2.c +++ b/src/cpu/amd/socket_ASB2/socket_ASB2.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_ASB2_ops = { CHIP_NAME("socket ASB2") diff --git a/src/cpu/amd/socket_C32/chip.h b/src/cpu/amd/socket_C32/chip.h deleted file mode 100644 index e9d57c7..0000000 --- a/src/cpu/amd/socket_C32/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_socket_C32_config { -}; diff --git a/src/cpu/amd/socket_C32/socket_C32.c b/src/cpu/amd/socket_C32/socket_C32.c index 266bfa0..4f90458 100644 --- a/src/cpu/amd/socket_C32/socket_C32.c +++ b/src/cpu/amd/socket_C32/socket_C32.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_C32_ops = { CHIP_NAME("socket C32") diff --git a/src/cpu/amd/socket_F/chip.h b/src/cpu/amd/socket_F/chip.h deleted file mode 100644 index cb582d3..0000000 --- a/src/cpu/amd/socket_F/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_amd_socket_F_config { -}; diff --git a/src/cpu/amd/socket_F/socket_F.c b/src/cpu/amd/socket_F/socket_F.c index 93db628..80c3e35 100644 --- a/src/cpu/amd/socket_F/socket_F.c +++ b/src/cpu/amd/socket_F/socket_F.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_F_ops = { CHIP_NAME("Socket F CPU") diff --git a/src/cpu/amd/socket_F_1207/chip.h b/src/cpu/amd/socket_F_1207/chip.h deleted file mode 100644 index 3f7d824..0000000 --- a/src/cpu/amd/socket_F_1207/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_amd_socket_F_1207_config { -}; diff --git a/src/cpu/amd/socket_F_1207/socket_F_1207.c b/src/cpu/amd/socket_F_1207/socket_F_1207.c index a95e8ea..e84f435 100644 --- a/src/cpu/amd/socket_F_1207/socket_F_1207.c +++ b/src/cpu/amd/socket_F_1207/socket_F_1207.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_F_1207_ops = { CHIP_NAME("socket F_1207") diff --git a/src/cpu/amd/socket_S1G1/chip.h b/src/cpu/amd/socket_S1G1/chip.h deleted file mode 100644 index 3109da2..0000000 --- a/src/cpu/amd/socket_S1G1/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_amd_socket_S1G1_config { -}; diff --git a/src/cpu/amd/socket_S1G1/socket_S1G1.c b/src/cpu/amd/socket_S1G1/socket_S1G1.c index 352ecc3..0b9702c 100644 --- a/src/cpu/amd/socket_S1G1/socket_S1G1.c +++ b/src/cpu/amd/socket_S1G1/socket_S1G1.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_amd_socket_S1G1_ops = { CHIP_NAME("Socket S1G1 CPU") diff --git a/src/cpu/intel/ep80579/chip.h b/src/cpu/intel/ep80579/chip.h deleted file mode 100644 index 08e7529..0000000 --- a/src/cpu/intel/ep80579/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_intel_ep80579_config { -}; diff --git a/src/cpu/intel/ep80579/ep80579.c b/src/cpu/intel/ep80579/ep80579.c index fd964a4..7d6e715 100644 --- a/src/cpu/intel/ep80579/ep80579.c +++ b/src/cpu/intel/ep80579/ep80579.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_ep80579_ops = { CHIP_NAME("EP80579 CPU") diff --git a/src/cpu/intel/slot_1/chip.h b/src/cpu/intel/slot_1/chip.h deleted file mode 100644 index 8650f90..0000000 --- a/src/cpu/intel/slot_1/chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_intel_slot_1_config { -}; diff --git a/src/cpu/intel/slot_1/slot_1.c b/src/cpu/intel/slot_1/slot_1.c index 548127f..df48248 100644 --- a/src/cpu/intel/slot_1/slot_1.c +++ b/src/cpu/intel/slot_1/slot_1.c @@ -19,7 +19,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_slot_1_ops = { CHIP_NAME("Slot 1 CPU") diff --git a/src/cpu/intel/slot_2/chip.h b/src/cpu/intel/slot_2/chip.h deleted file mode 100644 index d7bb2b1..0000000 --- a/src/cpu/intel/slot_2/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_slot_2_config { -}; diff --git a/src/cpu/intel/slot_2/slot_2.c b/src/cpu/intel/slot_2/slot_2.c index ddc2f3b..994b25a 100644 --- a/src/cpu/intel/slot_2/slot_2.c +++ b/src/cpu/intel/slot_2/slot_2.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_slot_2_ops = { diff --git a/src/cpu/intel/socket_441/chip.h b/src/cpu/intel/socket_441/chip.h deleted file mode 100644 index 70c4ac8..0000000 --- a/src/cpu/intel/socket_441/chip.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_intel_socket_441_config { -}; diff --git a/src/cpu/intel/socket_441/socket_441.c b/src/cpu/intel/socket_441/socket_441.c index eb57dce..319a402 100644 --- a/src/cpu/intel/socket_441/socket_441.c +++ b/src/cpu/intel/socket_441/socket_441.c @@ -18,7 +18,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_441_ops = { CHIP_NAME("Socket 441 CPU") diff --git a/src/cpu/intel/socket_BGA956/chip.h b/src/cpu/intel/socket_BGA956/chip.h deleted file mode 100644 index 399200d..0000000 --- a/src/cpu/intel/socket_BGA956/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_BGA956_config { -}; diff --git a/src/cpu/intel/socket_BGA956/socket_BGA956.c b/src/cpu/intel/socket_BGA956/socket_BGA956.c index 53667c1..def7cc9 100644 --- a/src/cpu/intel/socket_BGA956/socket_BGA956.c +++ b/src/cpu/intel/socket_BGA956/socket_BGA956.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_BGA956_ops = { CHIP_NAME("Socket BGA956 CPU") diff --git a/src/cpu/intel/socket_FC_PGA370/chip.h b/src/cpu/intel/socket_FC_PGA370/chip.h deleted file mode 100644 index 7148d47..0000000 --- a/src/cpu/intel/socket_FC_PGA370/chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Joseph Smith <joe(a)settoplinux.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct cpu_intel_socket_FC_PGA370_config { -}; diff --git a/src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c b/src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c index e3bca8f..62186f2 100644 --- a/src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c +++ b/src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c @@ -19,7 +19,6 @@ */ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_FC_PGA370_ops = { CHIP_NAME("(FC)PGA370 CPU") diff --git a/src/cpu/intel/socket_LGA771/chip.h b/src/cpu/intel/socket_LGA771/chip.h deleted file mode 100644 index fc51d77..0000000 --- a/src/cpu/intel/socket_LGA771/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_LGA771_config { -}; diff --git a/src/cpu/intel/socket_LGA771/socket_LGA771.c b/src/cpu/intel/socket_LGA771/socket_LGA771.c index 21a7dc9..85570ba 100644 --- a/src/cpu/intel/socket_LGA771/socket_LGA771.c +++ b/src/cpu/intel/socket_LGA771/socket_LGA771.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_LGA771_ops = { diff --git a/src/cpu/intel/socket_PGA370/chip.h b/src/cpu/intel/socket_PGA370/chip.h deleted file mode 100644 index c2c70ec..0000000 --- a/src/cpu/intel/socket_PGA370/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_PGA370_config { -}; diff --git a/src/cpu/intel/socket_PGA370/socket_PGA370.c b/src/cpu/intel/socket_PGA370/socket_PGA370.c index fffd983..f7c1c2a 100644 --- a/src/cpu/intel/socket_PGA370/socket_PGA370.c +++ b/src/cpu/intel/socket_PGA370/socket_PGA370.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_PGA370_ops = { CHIP_NAME("Socket PGA370 CPU") diff --git a/src/cpu/intel/socket_mFCBGA479/chip.h b/src/cpu/intel/socket_mFCBGA479/chip.h deleted file mode 100644 index 57e432c..0000000 --- a/src/cpu/intel/socket_mFCBGA479/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_mFCBGA479_config { -}; diff --git a/src/cpu/intel/socket_mFCBGA479/socket_mFCBGA479.c b/src/cpu/intel/socket_mFCBGA479/socket_mFCBGA479.c index 4c0bc72..02849b9 100644 --- a/src/cpu/intel/socket_mFCBGA479/socket_mFCBGA479.c +++ b/src/cpu/intel/socket_mFCBGA479/socket_mFCBGA479.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_mFCBGA479_ops = { CHIP_NAME("Micro-FCBGA 479 CPU") diff --git a/src/cpu/intel/socket_mFCPGA478/chip.h b/src/cpu/intel/socket_mFCPGA478/chip.h deleted file mode 100644 index 50268f5..0000000 --- a/src/cpu/intel/socket_mFCPGA478/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_mFCPGA478_config { -}; diff --git a/src/cpu/intel/socket_mFCPGA478/socket_mFCPGA478.c b/src/cpu/intel/socket_mFCPGA478/socket_mFCPGA478.c index 117a929..5b001bd 100644 --- a/src/cpu/intel/socket_mFCPGA478/socket_mFCPGA478.c +++ b/src/cpu/intel/socket_mFCPGA478/socket_mFCPGA478.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_mFCPGA478_ops = { diff --git a/src/cpu/intel/socket_mPGA478/chip.h b/src/cpu/intel/socket_mPGA478/chip.h deleted file mode 100644 index 3dafc9a..0000000 --- a/src/cpu/intel/socket_mPGA478/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_mPGA478_config { -}; diff --git a/src/cpu/intel/socket_mPGA478/socket_mPGA478.c b/src/cpu/intel/socket_mPGA478/socket_mPGA478.c index da32966..4480bde 100644 --- a/src/cpu/intel/socket_mPGA478/socket_mPGA478.c +++ b/src/cpu/intel/socket_mPGA478/socket_mPGA478.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_mPGA478_ops = { diff --git a/src/cpu/intel/socket_mPGA479M/chip.h b/src/cpu/intel/socket_mPGA479M/chip.h deleted file mode 100644 index c0c5cd4..0000000 --- a/src/cpu/intel/socket_mPGA479M/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_mPGA479M_config { -}; diff --git a/src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c b/src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c index de824b5..b151c47 100644 --- a/src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c +++ b/src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_mPGA479M_ops = { diff --git a/src/cpu/intel/socket_mPGA603/chip.h b/src/cpu/intel/socket_mPGA603/chip.h deleted file mode 100644 index b39982a..0000000 --- a/src/cpu/intel/socket_mPGA603/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_mPGA603_config { -}; diff --git a/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c b/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c index 2436f96..f5f8e5b 100644 --- a/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c +++ b/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_mPGA603_ops = { diff --git a/src/cpu/intel/socket_mPGA604/chip.h b/src/cpu/intel/socket_mPGA604/chip.h deleted file mode 100644 index 3a09b82..0000000 --- a/src/cpu/intel/socket_mPGA604/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_mPGA604_config { -}; diff --git a/src/cpu/intel/socket_mPGA604/socket_mPGA604.c b/src/cpu/intel/socket_mPGA604/socket_mPGA604.c index df372b2..74bdc0d 100644 --- a/src/cpu/intel/socket_mPGA604/socket_mPGA604.c +++ b/src/cpu/intel/socket_mPGA604/socket_mPGA604.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_mPGA604_ops = { diff --git a/src/cpu/intel/socket_rPGA989/chip.h b/src/cpu/intel/socket_rPGA989/chip.h deleted file mode 100644 index ee3b396..0000000 --- a/src/cpu/intel/socket_rPGA989/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct cpu_intel_socket_rPGA989_config { -}; diff --git a/src/cpu/intel/socket_rPGA989/socket_rPGA989.c b/src/cpu/intel/socket_rPGA989/socket_rPGA989.c index 2484571..6e05b57 100644 --- a/src/cpu/intel/socket_rPGA989/socket_rPGA989.c +++ b/src/cpu/intel/socket_rPGA989/socket_rPGA989.c @@ -1,5 +1,4 @@ #include <device/device.h> -#include "chip.h" struct chip_operations cpu_intel_socket_rPGA989_ops = { CHIP_NAME("Socket rPGA989 CPU") diff --git a/src/drivers/generic/debug/chip.h b/src/drivers/generic/debug/chip.h deleted file mode 100644 index 661fd54..0000000 --- a/src/drivers/generic/debug/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_generic_debug_config { -}; diff --git a/src/drivers/generic/debug/debug_dev.c b/src/drivers/generic/debug/debug_dev.c index 60d610f..57f8077 100644 --- a/src/drivers/generic/debug/debug_dev.c +++ b/src/drivers/generic/debug/debug_dev.c @@ -7,7 +7,6 @@ #include <cpu/x86/msr.h> #include <reset.h> #include <delay.h> -#include "chip.h" static void print_pci_regs(struct device *dev) { diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c index 5b06629..ab85eb5 100644 --- a/src/drivers/i2c/adm1026/adm1026.c +++ b/src/drivers/i2c/adm1026/adm1026.c @@ -5,7 +5,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <cpu/x86/msr.h> -#include "chip.h" #define ADM1026_DEVICE 0x2d /* Either 0x2c or 0x2d or 0x2e */ #define ADM1026_REG_CONFIG1 0x00 diff --git a/src/drivers/i2c/adm1026/chip.h b/src/drivers/i2c/adm1026/chip.h deleted file mode 100644 index f8324ad..0000000 --- a/src/drivers/i2c/adm1026/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_i2c_adm1026_config { -}; diff --git a/src/drivers/i2c/adm1027/adm1027.c b/src/drivers/i2c/adm1027/adm1027.c index e97ec69..e83f2c4 100644 --- a/src/drivers/i2c/adm1027/adm1027.c +++ b/src/drivers/i2c/adm1027/adm1027.c @@ -5,7 +5,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <cpu/x86/msr.h> -#include "chip.h" #define ADM1027_REG_CONFIG1 0x40 #define CFG1_STRT 0x01 diff --git a/src/drivers/i2c/adm1027/chip.h b/src/drivers/i2c/adm1027/chip.h deleted file mode 100644 index 8836817..0000000 --- a/src/drivers/i2c/adm1027/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_i2c_adm1027_config { -}; diff --git a/src/drivers/i2c/adt7463/adt7463.c b/src/drivers/i2c/adt7463/adt7463.c index 3967bf7..a791fb4 100644 --- a/src/drivers/i2c/adt7463/adt7463.c +++ b/src/drivers/i2c/adt7463/adt7463.c @@ -23,7 +23,6 @@ #include <device/device.h> #include <console/console.h> #include <device/smbus.h> -#include "chip.h" /** * Do some S2881-specific HWM initialization for the ADT7463 chip. diff --git a/src/drivers/i2c/adt7463/chip.h b/src/drivers/i2c/adt7463/chip.h deleted file mode 100644 index 351d548..0000000 --- a/src/drivers/i2c/adt7463/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_i2c_adt7463_config { -}; diff --git a/src/drivers/i2c/i2cmux/chip.h b/src/drivers/i2c/i2cmux/chip.h deleted file mode 100644 index 0cfd837..0000000 --- a/src/drivers/i2c/i2cmux/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_i2c_i2cmux_config { -}; diff --git a/src/drivers/i2c/i2cmux/i2cmux.c b/src/drivers/i2c/i2cmux/i2cmux.c index 44bf390..b318508 100644 --- a/src/drivers/i2c/i2cmux/i2cmux.c +++ b/src/drivers/i2c/i2cmux/i2cmux.c @@ -5,7 +5,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <cpu/x86/msr.h> -#include "chip.h" static void i2cmux_set_link(device_t dev, unsigned int link) { diff --git a/src/drivers/i2c/i2cmux2/chip.h b/src/drivers/i2c/i2cmux2/chip.h deleted file mode 100644 index dafa1d7..0000000 --- a/src/drivers/i2c/i2cmux2/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_i2c_i2cmux2_config { -}; diff --git a/src/drivers/i2c/i2cmux2/i2cmux2.c b/src/drivers/i2c/i2cmux2/i2cmux2.c index dc8ec25..a7d40e2 100644 --- a/src/drivers/i2c/i2cmux2/i2cmux2.c +++ b/src/drivers/i2c/i2cmux2/i2cmux2.c @@ -5,7 +5,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <cpu/x86/msr.h> -#include "chip.h" static void i2cmux2_set_link(device_t dev, unsigned int link) { diff --git a/src/drivers/i2c/lm63/chip.h b/src/drivers/i2c/lm63/chip.h deleted file mode 100644 index 1c5bc7a..0000000 --- a/src/drivers/i2c/lm63/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_i2c_lm63_config { -}; diff --git a/src/drivers/i2c/lm63/lm63.c b/src/drivers/i2c/lm63/lm63.c index d98a245..47a5489 100644 --- a/src/drivers/i2c/lm63/lm63.c +++ b/src/drivers/i2c/lm63/lm63.c @@ -5,7 +5,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <cpu/x86/msr.h> -#include "chip.h" static void lm63_init(device_t dev) { diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h deleted file mode 100644 index b5162c1..0000000 --- a/src/drivers/i2c/w83795/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct drivers_i2c_w83795_config { -}; diff --git a/src/mainboard/emulation/qemu-x86/chip.h b/src/mainboard/emulation/qemu-x86/chip.h deleted file mode 100644 index 0aa8173..0000000 --- a/src/mainboard/emulation/qemu-x86/chip.h +++ /dev/null @@ -1,2 +0,0 @@ -struct mainboard_emulation_qemu_x86_config {}; - diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c index f1669bb..6103229 100644 --- a/src/mainboard/emulation/qemu-x86/northbridge.c +++ b/src/mainboard/emulation/qemu-x86/northbridge.c @@ -8,7 +8,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include <delay.h> #include <smbios.h> diff --git a/src/northbridge/amd/agesa/family10/chip.h b/src/northbridge/amd/agesa/family10/chip.h deleted file mode 100644 index f95d5b1..0000000 --- a/src/northbridge/amd/agesa/family10/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family10_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 4b3859b..ddb7619 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -39,10 +39,8 @@ #include <Porting.h> #include <AGESA.h> #include <Options.h> -#include "root_complex/chip.h" #include "northbridge.h" #include "amdfam10.h" -#include "chip.h" extern uint32_t agesawrapper_amdinitmid(void); diff --git a/src/northbridge/amd/agesa/family10/root_complex/chip.h b/src/northbridge/amd/agesa/family10/root_complex/chip.h deleted file mode 100644 index 80adb8e..0000000 --- a/src/northbridge/amd/agesa/family10/root_complex/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family10_root_complex_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family12/chip.h b/src/northbridge/amd/agesa/family12/chip.h deleted file mode 100644 index 39efd52..0000000 --- a/src/northbridge/amd/agesa/family12/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family12_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 6689e71..b24681b 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -33,7 +33,6 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> -#include "chip.h" #include "northbridge.h" #include "SbEarly.h" #include "agesawrapper.h" diff --git a/src/northbridge/amd/agesa/family12/root_complex/chip.h b/src/northbridge/amd/agesa/family12/root_complex/chip.h deleted file mode 100644 index 556f343..0000000 --- a/src/northbridge/amd/agesa/family12/root_complex/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family12_root_complex_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family14/chip.h b/src/northbridge/amd/agesa/family14/chip.h deleted file mode 100644 index 46ea78a..0000000 --- a/src/northbridge/amd/agesa/family14/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family14_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 875dbbb..a635901 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -34,7 +34,6 @@ #include <cpu/amd/mtrr.h> #include "agesawrapper.h" -#include "chip.h" #include "northbridge.h" #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> diff --git a/src/northbridge/amd/agesa/family14/root_complex/chip.h b/src/northbridge/amd/agesa/family14/root_complex/chip.h deleted file mode 100644 index cf95179..0000000 --- a/src/northbridge/amd/agesa/family14/root_complex/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family14_root_complex_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family15/chip.h b/src/northbridge/amd/agesa/family15/chip.h deleted file mode 100644 index b06318b..0000000 --- a/src/northbridge/amd/agesa/family15/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family15_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 96cfca2..253ae1c 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -40,9 +40,7 @@ #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> #include "agesawrapper.h" -#include "root_complex/chip.h" #include "northbridge.h" -#include "chip.h" #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) diff --git a/src/northbridge/amd/agesa/family15/root_complex/chip.h b/src/northbridge/amd/agesa/family15/root_complex/chip.h deleted file mode 100644 index 8f670f6..0000000 --- a/src/northbridge/amd/agesa/family15/root_complex/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family15_root_complex_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family15tn/chip.h b/src/northbridge/amd/agesa/family15tn/chip.h deleted file mode 100644 index 091de82..0000000 --- a/src/northbridge/amd/agesa/family15tn/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family15tn_config -{ -}; - diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index fb30277..67550eb 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -40,9 +40,7 @@ #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> #include "agesawrapper.h" -#include "root_complex/chip.h" #include "northbridge.h" -#include "chip.h" #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) diff --git a/src/northbridge/amd/agesa/family15tn/root_complex/chip.h b/src/northbridge/amd/agesa/family15tn/root_complex/chip.h deleted file mode 100644 index 0306fdd..0000000 --- a/src/northbridge/amd/agesa/family15tn/root_complex/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_agesa_family15tn_root_complex_config -{ -}; - diff --git a/src/northbridge/amd/amdfam10/chip.h b/src/northbridge/amd/amdfam10/chip.h deleted file mode 100644 index a8161cb..0000000 --- a/src/northbridge/amd/amdfam10/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_amdfam10_config -{ -}; - diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 865a3bc..101ce6e 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -37,7 +37,6 @@ #include <pc80/mc146818rtc.h> #endif -#include "chip.h" #include "root_complex/chip.h" #include "northbridge.h" diff --git a/src/northbridge/amd/amdfam10/root_complex/chip.h b/src/northbridge/amd/amdfam10/root_complex/chip.h deleted file mode 100644 index 8c93020..0000000 --- a/src/northbridge/amd/amdfam10/root_complex/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_amdfam10_root_complex_config -{ -}; - diff --git a/src/northbridge/amd/amdk8/chip.h b/src/northbridge/amd/amdk8/chip.h deleted file mode 100644 index a2331f4..0000000 --- a/src/northbridge/amd/amdk8/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -struct northbridge_amd_amdk8_config -{ -}; - diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index d94ee9a..5713ccb 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -25,7 +25,6 @@ #include <pc80/mc146818rtc.h> #endif -#include "chip.h" #include "root_complex/chip.h" #include "northbridge.h" diff --git a/src/northbridge/amd/amdk8/root_complex/chip.h b/src/northbridge/amd/amdk8/root_complex/chip.h deleted file mode 100644 index a9b6b5b..0000000 --- a/src/northbridge/amd/amdk8/root_complex/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -struct northbridge_amd_amdk8_root_complex_config -{ -}; - diff --git a/src/northbridge/amd/gx1/chip.h b/src/northbridge/amd/gx1/chip.h deleted file mode 100644 index 0378b61..0000000 --- a/src/northbridge/amd/gx1/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -struct northbridge_amd_gx1_config -{ -}; - diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index 5c59f73..fbea3b5 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -7,7 +7,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include "northbridge.h" #include <cpu/amd/gx1def.h> #include <cpu/x86/cache.h> diff --git a/src/northbridge/amd/gx2/chip.h b/src/northbridge/amd/gx2/chip.h deleted file mode 100644 index 1e266c6..0000000 --- a/src/northbridge/amd/gx2/chip.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_gx2_config -{ - -}; - diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index 8da37b4..12096d8 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include "northbridge.h" #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index 37fcf7e..f51bcc6 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include "northbridge.h" #include <cpu/amd/gx2def.h> #include <cpu/x86/msr.h> diff --git a/src/northbridge/amd/lx/chip.h b/src/northbridge/amd/lx/chip.h deleted file mode 100644 index 12b50fb..0000000 --- a/src/northbridge/amd/lx/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_amd_lx_config { -}; - diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 9ceceb8..5f98b40 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -33,7 +33,6 @@ #include <cpu/x86/cache.h> #include <cpu/amd/vr.h> #include <cpu/cpu.h> -#include "chip.h" #include "northbridge.h" #include "../../../southbridge/amd/cs5536/cs5536.h" diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 54cc057..6288608 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include "northbridge.h" #include <cpu/amd/lxdef.h> #include <cpu/x86/msr.h> diff --git a/src/northbridge/intel/e7501/chip.h b/src/northbridge/intel/e7501/chip.h deleted file mode 100644 index 112c03c..0000000 --- a/src/northbridge/intel/e7501/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -struct northbridge_intel_e7501_config -{ -}; - diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 1fa77d7..c70f032 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -7,7 +7,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> diff --git a/src/northbridge/intel/e7505/chip.h b/src/northbridge/intel/e7505/chip.h deleted file mode 100644 index 8fd3cdc..0000000 --- a/src/northbridge/intel/e7505/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -struct northbridge_intel_e7505_config -{ -}; - diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 9046f43..b6d24fa 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -7,7 +7,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include "e7505.h" #if CONFIG_WRITE_HIGH_TABLES diff --git a/src/northbridge/intel/i440bx/chip.h b/src/northbridge/intel/i440bx/chip.h deleted file mode 100644 index 15ecb4d..0000000 --- a/src/northbridge/intel/i440bx/chip.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_i440bx_config -{ -}; - diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 18e5716..39bd6b9 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -9,7 +9,6 @@ #include <bitops.h> #include <cpu/cpu.h> #include <pc80/keyboard.h> -#include "chip.h" #include "northbridge.h" #include "i440bx.h" diff --git a/src/northbridge/intel/i440lx/chip.h b/src/northbridge/intel/i440lx/chip.h deleted file mode 100644 index 19a9b26..0000000 --- a/src/northbridge/intel/i440lx/chip.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Maciej Pijanka <maciej.pijanka(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_i440lx_config -{ -}; - diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index f34b5ab..57fcfcb 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -30,7 +30,6 @@ #include <bitops.h> #include <cpu/cpu.h> #include <pc80/keyboard.h> -#include "chip.h" #include "northbridge.h" #include "i440lx.h" diff --git a/src/northbridge/intel/i5000/chip.h b/src/northbridge/intel/i5000/chip.h deleted file mode 100644 index 214ffcf..0000000 --- a/src/northbridge/intel/i5000/chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_i5000_config { -}; - diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index ea3665c..1548f19 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -29,7 +29,6 @@ #include <cpu/cpu.h> #include <arch/acpi.h> #include <cbmem.h> -#include "chip.h" #if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif diff --git a/src/northbridge/intel/i82810/chip.h b/src/northbridge/intel/i82810/chip.h deleted file mode 100644 index c571677..0000000 --- a/src/northbridge/intel/i82810/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_i82810_config { -}; - diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 5c51b9a..4c09d44 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -29,7 +29,6 @@ #include <string.h> #include <bitops.h> #include <cpu/cpu.h> -#include "chip.h" #include "northbridge.h" #include "i82810.h" diff --git a/src/northbridge/intel/i82830/chip.h b/src/northbridge/intel/i82830/chip.h deleted file mode 100644 index d0360fe..0000000 --- a/src/northbridge/intel/i82830/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Joseph Smith <joe(a)smittys.pointclark.net> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_i82830_config { -}; - diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index f3341d4..95ac2ed 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -28,7 +28,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include "i82830.h" static void northbridge_init(device_t dev) diff --git a/src/northbridge/intel/i855/chip.h b/src/northbridge/intel/i855/chip.h deleted file mode 100644 index 40b1d38..0000000 --- a/src/northbridge/intel/i855/chip.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Jon Dufresne <jon.dufresne(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_i855_config -{ -}; - diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index b59ba50..74e2c76 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -31,7 +31,6 @@ #include <bitops.h> #include <cpu/x86/cache.h> #include <cpu/cpu.h> -#include "chip.h" static void northbridge_init(device_t dev) { diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h deleted file mode 100644 index 2deb985..0000000 --- a/src/northbridge/intel/i945/chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_i945_config { -}; - diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 41b15cf..684bb71 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -29,7 +29,6 @@ #include <bitops.h> #include <cpu/cpu.h> #include <arch/acpi.h> -#include "chip.h" #include "i945.h" static int get_pcie_bar(u32 *base, u32 *len) diff --git a/src/northbridge/intel/sch/chip.h b/src/northbridge/intel/sch/chip.h deleted file mode 100644 index b3aebd3..0000000 --- a/src/northbridge/intel/sch/chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_intel_sch_config { -}; - diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 48556e2..16ada2f 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -29,7 +29,6 @@ #include <bitops.h> #include <cpu/cpu.h> #include <arch/acpi.h> -#include "chip.h" #include "sch.h" static int get_pcie_bar(u32 *base, u32 *len) diff --git a/src/northbridge/rdc/r8610/chip.h b/src/northbridge/rdc/r8610/chip.h deleted file mode 100644 index 150f032..0000000 --- a/src/northbridge/rdc/r8610/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_rdc_r8610_config { -}; - diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index 250ace0..65fd5eb 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -30,7 +30,6 @@ #include <string.h> #include <bitops.h> #include <smbios.h> -#include "chip.h" #if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> diff --git a/src/northbridge/via/cn400/agp.c b/src/northbridge/via/cn400/agp.c index a302759..f6dbc69 100644 --- a/src/northbridge/via/cn400/agp.c +++ b/src/northbridge/via/cn400/agp.c @@ -24,7 +24,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "chip.h" #include "northbridge.h" #include "cn400.h" diff --git a/src/northbridge/via/cn400/chip.h b/src/northbridge/via/cn400/chip.h deleted file mode 100644 index e403d35..0000000 --- a/src/northbridge/via/cn400/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_via_cn400_config { -}; - diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index 74e0edf..61d7345 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -30,7 +30,6 @@ #include <string.h> #include <bitops.h> #include <cpu/cpu.h> -#include "chip.h" #include "northbridge.h" #include "cn400.h" diff --git a/src/northbridge/via/cn400/vga.c b/src/northbridge/via/cn400/vga.c index 7641a81..8c75a4f 100644 --- a/src/northbridge/via/cn400/vga.c +++ b/src/northbridge/via/cn400/vga.c @@ -34,7 +34,6 @@ #include <bitops.h> #include <cpu/cpu.h> #include <arch/interrupt.h> -#include "chip.h" #include "northbridge.h" #include "cn400.h" diff --git a/src/northbridge/via/cn400/vlink.c b/src/northbridge/via/cn400/vlink.c index dc574c1..85a0fc6 100644 --- a/src/northbridge/via/cn400/vlink.c +++ b/src/northbridge/via/cn400/vlink.c @@ -22,7 +22,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "chip.h" #include "northbridge.h" #include "cn400.h" diff --git a/src/northbridge/via/cn700/agp.c b/src/northbridge/via/cn700/agp.c index 327fac4..ba84f79 100644 --- a/src/northbridge/via/cn700/agp.c +++ b/src/northbridge/via/cn700/agp.c @@ -24,7 +24,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "chip.h" #include "northbridge.h" #include "cn700.h" diff --git a/src/northbridge/via/cn700/chip.h b/src/northbridge/via/cn700/chip.h deleted file mode 100644 index 5b1515d..0000000 --- a/src/northbridge/via/cn700/chip.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_via_cn700_config { -}; - diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index ced4c2f..837ec85 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -30,7 +30,6 @@ #include <string.h> #include <bitops.h> #include <cpu/cpu.h> -#include "chip.h" #include "northbridge.h" #include "cn700.h" diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c index 33d1fe0..d184644 100644 --- a/src/northbridge/via/cn700/vga.c +++ b/src/northbridge/via/cn700/vga.c @@ -34,7 +34,6 @@ #include <bitops.h> #include <cpu/cpu.h> #include <arch/interrupt.h> -#include "chip.h" #include "northbridge.h" #include "cn700.h" diff --git a/src/northbridge/via/cx700/chip.h b/src/northbridge/via/cx700/chip.h deleted file mode 100644 index 0e8491b..0000000 --- a/src/northbridge/via/cx700/chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_via_cx700_config { -}; - diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index 4fca723..1df9ce0 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -29,7 +29,6 @@ #include <bitops.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include "chip.h" #include "northbridge.h" #if CONFIG_WRITE_HIGH_TABLES diff --git a/src/northbridge/via/cx700/vga.c b/src/northbridge/via/cx700/vga.c index 91dd864..821edc4 100644 --- a/src/northbridge/via/cx700/vga.c +++ b/src/northbridge/via/cx700/vga.c @@ -31,7 +31,6 @@ #include <cpu/x86/msr.h> #include <arch/interrupt.h> #include "registers.h" -#include "chip.h" #include "northbridge.h" /* PCI Domain 1 Device 0 Function 0 */ diff --git a/src/northbridge/via/vt8601/chip.h b/src/northbridge/via/vt8601/chip.h deleted file mode 100644 index c65e12e..0000000 --- a/src/northbridge/via/vt8601/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -struct northbridge_via_vt8601_config -{ -}; - diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 92adf32..f5f084c 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -9,7 +9,6 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> -#include "chip.h" #include "northbridge.h" /* diff --git a/src/northbridge/via/vt8623/chip.h b/src/northbridge/via/vt8623/chip.h deleted file mode 100644 index 5fb3f80..0000000 --- a/src/northbridge/via/vt8623/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -struct northbridge_via_vt8623_config -{ -}; - diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 5ea2212..76cd7a0 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -11,7 +11,6 @@ #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> -#include "chip.h" #include "northbridge.h" /* diff --git a/src/northbridge/via/vt8623/vga.c b/src/northbridge/via/vt8623/vga.c index 933c733..20857a6 100644 --- a/src/northbridge/via/vt8623/vga.c +++ b/src/northbridge/via/vt8623/vga.c @@ -30,7 +30,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <arch/interrupt.h> -#include "chip.h" #include "northbridge.h" static int via_vt8623_int15_handler(struct eregs *regs) diff --git a/src/northbridge/via/vx800/chip.h b/src/northbridge/via/vx800/chip.h deleted file mode 100644 index 64df31a..0000000 --- a/src/northbridge/via/vx800/chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -struct northbridge_via_vx800_config { -}; - diff --git a/src/northbridge/via/vx800/ide.c b/src/northbridge/via/vx800/ide.c index 9fa8f35..4ed4879 100644 --- a/src/northbridge/via/vx800/ide.c +++ b/src/northbridge/via/vx800/ide.c @@ -22,7 +22,6 @@ #include <device/pci_ops.h> #include <device/pci_ids.h> #include <console/console.h> -#include "chip.h" #include <arch/io.h> #include "vx800.h" @@ -191,10 +190,6 @@ static void ide_init(struct device *dev) pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); #if 0 - - struct southbridge_via_vt8237r_config *sb = - (struct southbridge_via_vt8237r_config *)dev->chip_info; - u8 enables; u32 cablesel; diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index b9941d1..b5cd5a3 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -28,7 +28,6 @@ #include <pc80/keyboard.h> #include <pc80/i8259.h> #include "vx800.h" -#include "chip.h" static const unsigned char pciIrqs[4] = { 0xa, 0x9, 0xb, 0xa }; diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index f3cfa41..6274e23 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -31,7 +31,6 @@ #include <string.h> #include <bitops.h> #include <cpu/cpu.h> -#include "chip.h" #include "northbridge.h" #include "vx800.h" diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index e438012..bb7de9e 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -33,7 +33,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <arch/interrupt.h> -#include "chip.h" #include "northbridge.h" /* PCI Domain 1 Device 0 Function 0 */ diff --git a/src/southbridge/amd/cimx/sb700/chip_name.c b/src/southbridge/amd/cimx/sb700/chip_name.c deleted file mode 100644 index 13d2276..0000000 --- a/src/southbridge/amd/cimx/sb700/chip_name.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include "chip.h" - -struct chip_operations southbridge_amd_cimx_sb700_ops = { - CHIP_NAME("AMD South Bridge SB700") -}; diff --git a/src/southbridge/amd/cimx/sb800/chip_name.c b/src/southbridge/amd/cimx/sb800/chip_name.c deleted file mode 100644 index 9ce89d6..0000000 --- a/src/southbridge/amd/cimx/sb800/chip_name.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include "chip.h" - -struct chip_operations southbridge_amd_cimx_sb800_ops = { - CHIP_NAME("AMD South Bridge SB800") -}; diff --git a/src/southbridge/amd/cimx/sb900/chip_name.c b/src/southbridge/amd/cimx/sb900/chip_name.c deleted file mode 100644 index dd875dc..0000000 --- a/src/southbridge/amd/cimx/sb900/chip_name.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include "chip.h" - -struct chip_operations southbridge_amd_cimx_sb900_ops = { - CHIP_NAME("AMD South Bridge SB900") -}; diff --git a/src/southbridge/intel/i82801cx/chip.h b/src/southbridge/intel/i82801cx/chip.h deleted file mode 100644 index 5618521..0000000 --- a/src/southbridge/intel/i82801cx/chip.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef I82801CX_CHIP_H -#define I82801CX_CHIP_H - -struct southbridge_intel_i82801cx_config -{ -}; - -#endif /* I82801CX_CHIP_H */ diff --git a/src/southbridge/intel/i82801cx/i82801cx.h b/src/southbridge/intel/i82801cx/i82801cx.h index da518a3..2842883 100644 --- a/src/southbridge/intel/i82801cx/i82801cx.h +++ b/src/southbridge/intel/i82801cx/i82801cx.h @@ -3,7 +3,6 @@ #if !defined(__PRE_RAM__) #include <device/device.h> -#include "chip.h" void i82801cx_enable(device_t dev); void i82801cx_hard_reset(void); #endif diff --git a/src/southbridge/intel/pxhd/chip.h b/src/southbridge/intel/pxhd/chip.h deleted file mode 100644 index 27d88a8..0000000 --- a/src/southbridge/intel/pxhd/chip.h +++ /dev/null @@ -1,5 +0,0 @@ -struct southbridge_intel_pxhd_config -{ - /* nothing */ -}; - diff --git a/src/southbridge/intel/pxhd/pxhd.h b/src/southbridge/intel/pxhd/pxhd.h index c3e6ce5..b0e8cdb 100644 --- a/src/southbridge/intel/pxhd/pxhd.h +++ b/src/southbridge/intel/pxhd/pxhd.h @@ -1,6 +1,5 @@ #ifndef PXHD_H #define PXHD_H -#include "chip.h" #endif /* PXHD_H */ diff --git a/src/southbridge/ti/pcixx12/chip.h b/src/southbridge/ti/pcixx12/chip.h deleted file mode 100644 index 03151a8..0000000 --- a/src/southbridge/ti/pcixx12/chip.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _SOUTHBRIDGE_TI_PCIXX12 -#define _SOUTHBRIDGE_TI_PCIXX12 - -struct southbridge_ti_pcixx12_config { - int dummy; - -}; - -#endif /* _SOUTHBRIDGE_TI_PCIXX12 */ diff --git a/src/southbridge/ti/pcixx12/pcixx12.c b/src/southbridge/ti/pcixx12/pcixx12.c index 0ea3b11..5e62292 100644 --- a/src/southbridge/ti/pcixx12/pcixx12.c +++ b/src/southbridge/ti/pcixx12/pcixx12.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <console/console.h> #include <device/cardbus.h> -#include "chip.h" static void pcixx12_init(device_t dev) { @@ -62,7 +61,6 @@ static const struct pci_driver ti_pcixx12_driver __pci_driver = { static void southbridge_init(device_t dev) { - // struct southbridge_ti_pcixx12_config *config = dev->chip_info; } struct chip_operations southbridge_ti_pcixx12_ops = { diff --git a/src/superio/fintek/f71805f/chip.h b/src/superio/fintek/f71805f/chip.h deleted file mode 100644 index 603dbee..0000000 --- a/src/superio/fintek/f71805f/chip.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_FINTEK_F71805F_CHIP_H -#define SUPERIO_FINTEK_F71805F_CHIP_H - -#include <device/device.h> -#include <uart8250.h> - -/* This chip doesn't have keyboard and mouse support. */ - -struct superio_fintek_f71805f_config { - -}; - -#endif diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c index 5f17946..afe5b8c 100644 --- a/src/superio/fintek/f71805f/superio.c +++ b/src/superio/fintek/f71805f/superio.c @@ -24,7 +24,6 @@ #include <console/console.h> #include <stdlib.h> #include <uart8250.h> -#include "chip.h" #include "f71805f.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f71859/chip.h b/src/superio/fintek/f71859/chip.h deleted file mode 100644 index bd45ac0..0000000 --- a/src/superio/fintek/f71859/chip.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Marc Jones <marcj303(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_FINTEK_F71859_CHIP_H -#define SUPERIO_FINTEK_F71859_CHIP_H - -#include <device/device.h> -#include <uart8250.h> - -struct superio_fintek_f71859_config { - -}; - -#endif diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index 809140b..a0158ba 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -25,7 +25,6 @@ #include <console/console.h> #include <stdlib.h> #include <uart8250.h> -#include "chip.h" #include "f71859.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/intel/i3100/chip.h b/src/superio/intel/i3100/chip.h deleted file mode 100644 index 05e2f45..0000000 --- a/src/superio/intel/i3100/chip.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_INTEL_I3100_CHIP_H -#define SUPERIO_INTEL_I3100_CHIP_H - -#include <device/device.h> -#include <uart8250.h> - -struct superio_intel_i3100_config { -}; - -#endif diff --git a/src/superio/intel/i3100/superio.c b/src/superio/intel/i3100/superio.c index 74862eb..b8c107d 100644 --- a/src/superio/intel/i3100/superio.c +++ b/src/superio/intel/i3100/superio.c @@ -22,7 +22,6 @@ #include <device/device.h> #include <device/pnp.h> #include <uart8250.h> -#include "chip.h" #include "i3100.h" #include <arch/io.h> diff --git a/src/superio/ite/it8661f/chip.h b/src/superio/ite/it8661f/chip.h deleted file mode 100644 index 1d9d1f9..0000000 --- a/src/superio/ite/it8661f/chip.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_ITE_IT8661F_CHIP_H -#define SUPERIO_ITE_IT8661F_CHIP_H - -/* This chip doesn't have keyboard and mouse support. */ - -#include <device/device.h> -#include <uart8250.h> - -struct superio_ite_it8661f_config { - -}; - -#endif diff --git a/src/superio/ite/it8661f/superio.c b/src/superio/ite/it8661f/superio.c index fcf54e7..a348a7f 100644 --- a/src/superio/ite/it8661f/superio.c +++ b/src/superio/ite/it8661f/superio.c @@ -22,7 +22,6 @@ #include <device/pnp.h> #include <uart8250.h> #include <stdlib.h> -#include "chip.h" #include "it8661f.h" /* TODO: Add pnp_enter_ext_func_mode() etc. and wrap functions. */ diff --git a/src/superio/ite/it8705f/chip.h b/src/superio/ite/it8705f/chip.h deleted file mode 100644 index ac2ba77..0000000 --- a/src/superio/ite/it8705f/chip.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_ITE_IT8705F_CHIP_H -#define SUPERIO_ITE_IT8705F_CHIP_H - -/* This chip doesn't have keyboard and mouse support. */ - -#include <device/device.h> -#include <uart8250.h> - -struct superio_ite_it8705f_config { - -}; - -#endif diff --git a/src/superio/ite/it8705f/superio.c b/src/superio/ite/it8705f/superio.c index 8f14a34..8992ea2 100644 --- a/src/superio/ite/it8705f/superio.c +++ b/src/superio/ite/it8705f/superio.c @@ -22,13 +22,10 @@ #include <device/pnp.h> #include <uart8250.h> #include <stdlib.h> -#include "chip.h" #include "it8705f.h" static void init(device_t dev) { - struct superio_ite_it8705f_config *conf = dev->chip_info; - if (!dev->enabled) return; diff --git a/src/superio/nsc/pc87382/chip.h b/src/superio/nsc/pc87382/chip.h deleted file mode 100644 index a9f0200..0000000 --- a/src/superio/nsc/pc87382/chip.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_NSC_PC87382_CHIP_H -#define SUPERIO_NSC_PC87382_CHIP_H - -#include <uart8250.h> - -struct superio_nsc_pc87382_config { - -}; - -#endif diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 7f4afe3..9d4bee0 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -27,7 +27,6 @@ #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "chip.h" #include "pc87382.h" static void init(device_t dev) diff --git a/src/superio/nsc/pc87384/chip.h b/src/superio/nsc/pc87384/chip.h deleted file mode 100644 index 1c49725..0000000 --- a/src/superio/nsc/pc87384/chip.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_NSC_PC87384_CHIP_H -#define SUPERIO_NSC_PC87384_CHIP_H - -#include <uart8250.h> - -struct superio_nsc_pc87384_config { - -}; - -#endif diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c index 11ddc82..39177fd 100644 --- a/src/superio/nsc/pc87384/superio.c +++ b/src/superio/nsc/pc87384/superio.c @@ -27,7 +27,6 @@ #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "chip.h" #include "pc87384.h" static struct device_operations ops = { diff --git a/src/superio/nsc/pc87392/chip.h b/src/superio/nsc/pc87392/chip.h deleted file mode 100644 index a6ebf1b..0000000 --- a/src/superio/nsc/pc87392/chip.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_NSC_PC87392_CHIP_H -#define SUPERIO_NSC_PC87392_CHIP_H - -#include <uart8250.h> - -struct superio_nsc_pc87392_config { - -}; - -#endif diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index 1b527ad..81c679c 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -26,7 +26,6 @@ #include <bitops.h> #include <uart8250.h> #include <stdlib.h> -#include "chip.h" #include "pc87392.h" static void init(device_t dev) diff --git a/src/superio/smsc/lpc47n217/chip.h b/src/superio/smsc/lpc47n217/chip.h deleted file mode 100644 index b0fbe8c..0000000 --- a/src/superio/smsc/lpc47n217/chip.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_SMSC_LPC47N217_CHIP_H -#define SUPERIO_SMSC_LPC47N217_CHIP_H - -#include <uart8250.h> - -struct superio_smsc_lpc47n217_config { - -}; - -#endif diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index 01c96b1..2658831 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -33,7 +33,6 @@ #include <uart8250.h> #include <assert.h> #include <stdlib.h> -#include "chip.h" #include "lpc47n217.h" /* Forward declarations */ @@ -133,9 +132,6 @@ static void lpc47n217_pnp_enable(device_t dev) */ static void lpc47n217_init(device_t dev) { - /* TODO: Reserved for future. */ - /* struct superio_smsc_lpc47n217_config* conf = dev->chip_info; */ - if (!dev->enabled) return; } diff --git a/src/superio/via/vt1211/chip.h b/src/superio/via/vt1211/chip.h deleted file mode 100644 index 89d64cd..0000000 --- a/src/superio/via/vt1211/chip.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Nick Barker <nick.barker9(a)btinternet.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_VIA_VT1211_CHIP_H -#define SUPERIO_VIA_VT1211_CHIP_H - -#include <uart8250.h> - -struct superio_via_vt1211_config { - -}; - -#endif diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index e681d6e..abcae77 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -26,7 +26,6 @@ #include <uart8250.h> #include <stdlib.h> #include "vt1211.h" -#include "chip.h" static u8 hwm_io_regs[] = { 0x10,0x03, 0x11,0x10, 0x12,0x0d, 0x13,0x7f, diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 3aa57f9..f066d7b 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -179,25 +179,24 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) { } void add_header(struct device *dev) { - if ((dev->chiph_exists) || (scan_mode == KCONFIG_MODE)){ - int include_exists = 0; - struct header *h = &headers; - while (h->next) { - int result = strcmp(dev->name, h->next->name); - if (result == 0) { - include_exists = 1; - break; - } - if (result < 0) break; - h = h->next; - } - if (!include_exists) { - struct header *tmp = h->next; - h->next = malloc(sizeof(struct header)); - memset(h->next, 0, sizeof(struct header)); - h->next->name = dev->name; - h->next->next = tmp; + int include_exists = 0; + struct header *h = &headers; + while (h->next) { + int result = strcmp(dev->name, h->next->name); + if (result == 0) { + include_exists = 1; + break; } + if (result < 0) break; + h = h->next; + } + if (!include_exists) { + struct header *tmp = h->next; + h->next = malloc(sizeof(struct header)); + memset(h->next, 0, sizeof(struct header)); + h->next->chiph_exists = dev->chiph_exists; + h->next->name = dev->name; + h->next->next = tmp; } } @@ -617,8 +616,10 @@ int main(int argc, char** argv) { h = &headers; while (h->next) { h = h->next; - fprintf(autogen, "#include \"%s/chip.h\"\n", h->name); + if (h->chiph_exists) + fprintf(autogen, "#include \"%s/chip.h\"\n", h->name); } + fprintf(autogen, "\n#ifndef __PRE_RAM__\n"); h = &headers; while (h->next) { h = h->next; @@ -627,6 +628,7 @@ int main(int argc, char** argv) { fprintf(autogen, "extern struct chip_operations %s_ops;\n", name_underscore); free(name_underscore); } + fprintf(autogen, "#endif\n"); walk_device_tree(autogen, &root, inherit_subsystem_ids, NULL); fprintf(autogen, "\n/* pass 0 */\n"); diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index 1576600..b8a231a 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -86,6 +86,7 @@ struct device *head; struct header; struct header { char *name; + int chiph_exists; struct header *next; };

1 0

Moving gerrit to an separate mailing list
by Alex G. 27 Aug '12

27 Aug '12

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 I've brought this up today on IRC. My main argument is that the coreboot mailing list should be a place for discussion, for newcomers asking for help, talking about the future of the project, etc. Definitely more for discussion and less for patch review. We have gerrit for patch review. Some (actually, a lot) of people prefer to do their reviews by replying to the gerrit emails. It's awesome to have this option. The more the merrier, right? Right. Back in the days -- I mean waaaay back, think patchwork and svn -- doing patch review on the list, with some deficiencies, worked fine. We switched to git and gerrit. We eventually got to the problem that gerrit traffic accounts for most of the traffic on the mailing list. It makes the list irritatingly clobbered for some people, to the point they just stop using it. The argument from the "I like gerrit in the mailinglist" camp is "setting up your own filter to keep out gerrit message is easy". We can't really force people to do this. They (myself included) would rather stoThp using the mailing list. All I've said and refuted above are arguments and rants we like to use to tease each other. I strongly believe that it makes sense, now more than ever, to separate development and discussion traffic into two separate lists. I hope you all agree. Alex -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQIcBAEBAgAGBQJQItoNAAoJEL0kPHNPXJJK+UIP/2yVfa/UziIDeQRJdhhUOs1C UlGji9eLHw4rPxm9NS+3n+s3bmQDdnOMZkOZ0mbXCO/ufTCZurbZ7uOlDQasTYtt rPyU5GeMnILhH159ZIAo8KBI53HrBH+RdxOyxY0gVvSw5Vb2Ye4LVCTvrfDIZJo3 p+h7aPeAaR8mApwo24PAqJX9NDYZjytfuOFZ91Jw8YS5BXykH8oa8Xj32ezqt7fV lxOqew7UjNdVT26aCuHnTqlPYUw/Nl97iluWrebd8Rre6PLai03dxXqVlvgHHVXJ UzJFflwAn4gEjnYrOfd4qu/sCkWJkCQDfYx/DAiJtkPjUeY1FNw1Dnibsi6mP+F3 IleLl/SWxv21UnZM6OJ999CxYTdXD2sNytlM65d67UniGfeN6v1ARPZG0l2FzsRC PfUhrcPKryAsVCf4otWI64QUT0r0KgxU6qUdX6ZOvFerKcE+ono8ERJCL4v9TBB+ DVJGV2Dil+67FPzPriRhcLufPfQ14+B8BRNcFYbYOkmgjBtRmrZk/WvaEU5uVvII sbXbEzfSKrCKGr/K00XPRti0CRg7wn6MVeVsLTxvA5HMIkuGxd9FfmG9EPrC0JXZ tljwICM4AJkbQ6EkDg2Z66SUWnPBtfiCLNyPs8IfK5rfYkhkreqnWRtwxl8Ua7SE Lk13bwHJ/Jyf5r3RDAJU =543W -----END PGP SIGNATURE-----

4 3

Patch set updated for coreboot: 24661ea pirq_routing: Allow routing with more than 4 PIRQ links
by Alexandru Gagniuc 25 Aug '12

25 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1482 -gerrit commit 24661ea7f2e5b1c34daeb56abd3398d9aa903d0e Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Aug 23 02:32:58 2012 -0500 pirq_routing: Allow routing with more than 4 PIRQ links pirq_routing_irqs assumed that only four links are available for PIRQ routing, INTA to INTD. Some chipsets provide more, up to INTH. When pirq_routing_irqs found a link number greater than 4 in the pirq table, it would not assign that IRQ. This is a shame, as it limits the flexibility of routing IRQs. Make the maximum number of links a Kconfig variable, and modify the code to respect it. This works beatifully on the VX900, which provides 8 routable interrupts. While we're at it, also refactor pirq_routing_irqs, and add some much needed comments. The copyrights added were determined from git log filename. Change-Id: I4b565315404c65b871406f616474e2cc9e6e013e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/Kconfig | 12 ++++ src/arch/x86/boot/pirq_routing.c | 94 ++++++++++++++++++++++---------- src/arch/x86/include/arch/pirq_routing.h | 29 ++++++++++ 3 files changed, 107 insertions(+), 28 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 469266d..bff8751 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1,6 +1,7 @@ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> ## Copyright (C) 2009-2010 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify @@ -374,6 +375,17 @@ config HAVE_PIRQ_TABLE Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE. +config MAX_PIRQ_LINKS + int + default 4 + help + This variable specifies the number of PIRQ interrupt links which are + routable. On most chipsets, this is 4, INTA through INTD. Some + chipsets offer more than four links, commonly up to INTH. They may + also have a separate link for ATA or IOAPIC interrupts. When the PIRQ + table specifies links greater than 4, pirq_routing_irqs will not + function properly, unless this variable is correctly set. + #These Options are here to avoid "undefined" warnings. #The actual selection and help texts are in the following menu. diff --git a/src/arch/x86/boot/pirq_routing.c b/src/arch/x86/boot/pirq_routing.c index bb8a7b6..3316707 100644 --- a/src/arch/x86/boot/pirq_routing.c +++ b/src/arch/x86/boot/pirq_routing.c @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2010 Stefan Reinauer <stepan(a)coreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ #include <console/console.h> #include <arch/pirq_routing.h> #include <string.h> @@ -97,13 +116,45 @@ unsigned long copy_pirq_routing_table(unsigned long addr) } #if CONFIG_PIRQ_ROUTE +static u8 pirq_get_next_free_irq(u8* pirq, u16 bitmap) +{ + int i, link; + u8 irq = 0; + for (i = 2; i <= 15; i++) + { + /* Can we assign this IRQ ? */ + if (!((bitmap >> i) & 1)) + continue; + /* We can, Now let's assume we can use this IRQ */ + irq = i; + /* And assume we have not yet routed it */ + int already_routed = 0; + /* Have we already routed it ? */ + for(link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) { + if (pirq[link] == irq) { + already_routed = 1; + break; + } + } + /* If it's not yet routed, use it */ + if(!already_routed) + break; + /* But if it was already routed, try the next one */ + continue; + } + /* Now we got our IRQ */ + return irq; +} + void pirq_routing_irqs(unsigned long addr) { - int i, j, k, num_entries; - unsigned char irq_slot[4]; - unsigned char pirq[4] = {0, 0, 0, 0}; + int i, intx, num_entries; + unsigned char irq_slot[MAX_INTX_ENTRIES]; + unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]; struct irq_routing_table *pirq_tbl; + memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS); + pirq_tbl = (struct irq_routing_table *)(addr); num_entries = (pirq_tbl->size - 32) / 16; @@ -113,37 +164,26 @@ void pirq_routing_irqs(unsigned long addr) printk(BIOS_DEBUG, "PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn >> 3, pirq_tbl->slots[i].slot); - for (j = 0; j < 4; j++) { + for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) { - int link = pirq_tbl->slots[i].irq[j].link; - int bitmap = pirq_tbl->slots[i].irq[j].bitmap; + int link = pirq_tbl->slots[i].irq[intx].link; + int bitmap = pirq_tbl->slots[i].irq[intx].bitmap; int irq = 0; printk(BIOS_DEBUG, "INT: %c link: %x bitmap: %x ", - 'A' + j, link, bitmap); + 'A' + intx, link, bitmap); - if (!bitmap|| !link || link > 4) { + if (!bitmap|| !link || link > CONFIG_MAX_PIRQ_LINKS) { printk(BIOS_DEBUG, "not routed\n"); - irq_slot[j] = irq; + irq_slot[intx] = irq; continue; } /* yet not routed */ - if (!pirq[link - 1]) { - - for (k = 2; k <= 15; k++) { - - if (!((bitmap >> k) & 1)) - continue; - - irq = k; - - /* yet not routed */ - if (pirq[0] != irq && pirq[1] != irq && pirq[2] != irq && pirq[3] != irq) - break; - } - + if (!pirq[link - 1]) + { + irq = pirq_get_next_free_irq(pirq, bitmap); if (irq) pirq[link - 1] = irq; } @@ -151,7 +191,7 @@ void pirq_routing_irqs(unsigned long addr) irq = pirq[link - 1]; printk(BIOS_DEBUG, "IRQ: %d\n", irq); - irq_slot[j] = irq; + irq_slot[intx] = irq; } /* Bus, device, slots IRQs for {A,B,C,D}. */ @@ -159,10 +199,8 @@ void pirq_routing_irqs(unsigned long addr) pirq_tbl->slots[i].devfn >> 3, irq_slot); } - printk(BIOS_DEBUG, "PIRQ1: %d\n", pirq[0]); - printk(BIOS_DEBUG, "PIRQ2: %d\n", pirq[1]); - printk(BIOS_DEBUG, "PIRQ3: %d\n", pirq[2]); - printk(BIOS_DEBUG, "PIRQ4: %d\n", pirq[3]); + for(i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) + printk(BIOS_DEBUG, "PIRQ%u: %d\n", i+1, pirq[i]); pirq_assign_irqs(pirq); } diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h index 08ba535..a1c7b96 100644 --- a/src/arch/x86/include/arch/pirq_routing.h +++ b/src/arch/x86/include/arch/pirq_routing.h @@ -1,6 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2012 Patrick Georgi <patrick(a)georgi-clan.de> + * Copyright (C) 2010 Stefan Reinauer <stepan(a)coreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ #ifndef ARCH_PIRQ_ROUTING_H #define ARCH_PIRQ_ROUTING_H +/* This is the maximum number on interrupt entries that a PCI device may have. + * This is NOT the number of slots or devices in the system + * This is NOT the number of entries in the PIRQ table + * This tells us that in the PIRQ table, we are going to have 4 link-bitmap + * entries per PCI device + * It is fixed at 4: INTA, INTB, INTC, and INTD + * CAUTION: If you change this, pirq_routing will not work correctly*/ +#define MAX_INTX_ENTRIES 4 + #if CONFIG_GENERATE_PIRQ_TABLE #include <stdint.h>

1 0

Patch set updated for coreboot: cdd72d0 pirq_routing: Allow routing with more than 4 PIRQ links
by Alexandru Gagniuc 25 Aug '12

25 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1482 -gerrit commit cdd72d018bbc755078a090242447a9cef1a546bb Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Aug 23 02:32:58 2012 -0500 pirq_routing: Allow routing with more than 4 PIRQ links pirq_routing_irqs assumed that only four links are available for PIRQ routing, INTA to INTD. Some chipsets provide more, up to INTH. When pirq_routing_irqs found a link number greater than 4 in the pirq table, it would not assign that IRQ. This is a shame, as it limits the flexibility of routing IRQs. Make the maximum number of links a Kconfig variable, and modify the code to respect it. This works beatifully on the VX900, which provides 8 routable interrupts. While we're at it, also refactor pirq_routing_irqs, and add some much needed comments. The copyrights added were determined from git log filename. Change-Id: I4b565315404c65b871406f616474e2cc9e6e013e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/Kconfig | 12 ++++ src/arch/x86/boot/pirq_routing.c | 94 ++++++++++++++++++++++---------- src/arch/x86/include/arch/pirq_routing.h | 29 ++++++++++ 3 files changed, 107 insertions(+), 28 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index ccf8665..4ff078a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1,6 +1,7 @@ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> ## Copyright (C) 2009-2010 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify @@ -374,6 +375,17 @@ config HAVE_PIRQ_TABLE Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE. +config MAX_PIRQ_LINKS + int + default 4 + help + This variable specifies the number of PIRQ interrupt links which are + routable. On most chipsets, this is 4, INTA through INTD. Some + chipsets offer more than four links, commonly up to INTH. They may + also have a separate link for ATA or IOAPIC interrupts. When the PIRQ + table specifies links greater than 4, pirq_routing_irqs will not + function properly, unless this variable is correctly set. + #These Options are here to avoid "undefined" warnings. #The actual selection and help texts are in the following menu. diff --git a/src/arch/x86/boot/pirq_routing.c b/src/arch/x86/boot/pirq_routing.c index bb8a7b6..3316707 100644 --- a/src/arch/x86/boot/pirq_routing.c +++ b/src/arch/x86/boot/pirq_routing.c @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2010 Stefan Reinauer <stepan(a)coreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ #include <console/console.h> #include <arch/pirq_routing.h> #include <string.h> @@ -97,13 +116,45 @@ unsigned long copy_pirq_routing_table(unsigned long addr) } #if CONFIG_PIRQ_ROUTE +static u8 pirq_get_next_free_irq(u8* pirq, u16 bitmap) +{ + int i, link; + u8 irq = 0; + for (i = 2; i <= 15; i++) + { + /* Can we assign this IRQ ? */ + if (!((bitmap >> i) & 1)) + continue; + /* We can, Now let's assume we can use this IRQ */ + irq = i; + /* And assume we have not yet routed it */ + int already_routed = 0; + /* Have we already routed it ? */ + for(link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) { + if (pirq[link] == irq) { + already_routed = 1; + break; + } + } + /* If it's not yet routed, use it */ + if(!already_routed) + break; + /* But if it was already routed, try the next one */ + continue; + } + /* Now we got our IRQ */ + return irq; +} + void pirq_routing_irqs(unsigned long addr) { - int i, j, k, num_entries; - unsigned char irq_slot[4]; - unsigned char pirq[4] = {0, 0, 0, 0}; + int i, intx, num_entries; + unsigned char irq_slot[MAX_INTX_ENTRIES]; + unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]; struct irq_routing_table *pirq_tbl; + memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS); + pirq_tbl = (struct irq_routing_table *)(addr); num_entries = (pirq_tbl->size - 32) / 16; @@ -113,37 +164,26 @@ void pirq_routing_irqs(unsigned long addr) printk(BIOS_DEBUG, "PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn >> 3, pirq_tbl->slots[i].slot); - for (j = 0; j < 4; j++) { + for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) { - int link = pirq_tbl->slots[i].irq[j].link; - int bitmap = pirq_tbl->slots[i].irq[j].bitmap; + int link = pirq_tbl->slots[i].irq[intx].link; + int bitmap = pirq_tbl->slots[i].irq[intx].bitmap; int irq = 0; printk(BIOS_DEBUG, "INT: %c link: %x bitmap: %x ", - 'A' + j, link, bitmap); + 'A' + intx, link, bitmap); - if (!bitmap|| !link || link > 4) { + if (!bitmap|| !link || link > CONFIG_MAX_PIRQ_LINKS) { printk(BIOS_DEBUG, "not routed\n"); - irq_slot[j] = irq; + irq_slot[intx] = irq; continue; } /* yet not routed */ - if (!pirq[link - 1]) { - - for (k = 2; k <= 15; k++) { - - if (!((bitmap >> k) & 1)) - continue; - - irq = k; - - /* yet not routed */ - if (pirq[0] != irq && pirq[1] != irq && pirq[2] != irq && pirq[3] != irq) - break; - } - + if (!pirq[link - 1]) + { + irq = pirq_get_next_free_irq(pirq, bitmap); if (irq) pirq[link - 1] = irq; } @@ -151,7 +191,7 @@ void pirq_routing_irqs(unsigned long addr) irq = pirq[link - 1]; printk(BIOS_DEBUG, "IRQ: %d\n", irq); - irq_slot[j] = irq; + irq_slot[intx] = irq; } /* Bus, device, slots IRQs for {A,B,C,D}. */ @@ -159,10 +199,8 @@ void pirq_routing_irqs(unsigned long addr) pirq_tbl->slots[i].devfn >> 3, irq_slot); } - printk(BIOS_DEBUG, "PIRQ1: %d\n", pirq[0]); - printk(BIOS_DEBUG, "PIRQ2: %d\n", pirq[1]); - printk(BIOS_DEBUG, "PIRQ3: %d\n", pirq[2]); - printk(BIOS_DEBUG, "PIRQ4: %d\n", pirq[3]); + for(i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) + printk(BIOS_DEBUG, "PIRQ%u: %d\n", i+1, pirq[i]); pirq_assign_irqs(pirq); } diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h index 08ba535..a1c7b96 100644 --- a/src/arch/x86/include/arch/pirq_routing.h +++ b/src/arch/x86/include/arch/pirq_routing.h @@ -1,6 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2012 Patrick Georgi <patrick(a)georgi-clan.de> + * Copyright (C) 2010 Stefan Reinauer <stepan(a)coreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ #ifndef ARCH_PIRQ_ROUTING_H #define ARCH_PIRQ_ROUTING_H +/* This is the maximum number on interrupt entries that a PCI device may have. + * This is NOT the number of slots or devices in the system + * This is NOT the number of entries in the PIRQ table + * This tells us that in the PIRQ table, we are going to have 4 link-bitmap + * entries per PCI device + * It is fixed at 4: INTA, INTB, INTC, and INTD + * CAUTION: If you change this, pirq_routing will not work correctly*/ +#define MAX_INTX_ENTRIES 4 + #if CONFIG_GENERATE_PIRQ_TABLE #include <stdint.h>

1 0

Patch set updated for coreboot: abaf1ea pirq_routing: Allow routing with more than 4 PIRQ links
by Alexandru Gagniuc 25 Aug '12

25 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1482 -gerrit commit abaf1ea00ca838d17869311f07b95b0ab002a4e5 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Aug 23 02:32:58 2012 -0500 pirq_routing: Allow routing with more than 4 PIRQ links pirq_routing_irqs assumed that only for links are available for PIRQ routing, INTA to INTD. Some chipsets provide more, up to INTH. When pirq_routing_irqs found a link number greater than 4 in the pirq table, it would not assign that IRQ. This is a shame, as it limits the flexibility of routing IRQs. Make the maximum number of links a Kconfig variable, and modify the code to respect it. This works beatifully on the VX900, which provides 8 routable interrupts. While we're at it, also refactor pirq_routing_irqs, and add some much needed comments. The copyrights added were determined from git log filename. Change-Id: I4b565315404c65b871406f616474e2cc9e6e013e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/Kconfig | 12 ++++ src/arch/x86/boot/pirq_routing.c | 94 ++++++++++++++++++++++---------- src/arch/x86/include/arch/pirq_routing.h | 29 ++++++++++ 3 files changed, 107 insertions(+), 28 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index ccf8665..4ff078a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1,6 +1,7 @@ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> ## Copyright (C) 2009-2010 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify @@ -374,6 +375,17 @@ config HAVE_PIRQ_TABLE Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE. +config MAX_PIRQ_LINKS + int + default 4 + help + This variable specifies the number of PIRQ interrupt links which are + routable. On most chipsets, this is 4, INTA through INTD. Some + chipsets offer more than four links, commonly up to INTH. They may + also have a separate link for ATA or IOAPIC interrupts. When the PIRQ + table specifies links greater than 4, pirq_routing_irqs will not + function properly, unless this variable is correctly set. + #These Options are here to avoid "undefined" warnings. #The actual selection and help texts are in the following menu. diff --git a/src/arch/x86/boot/pirq_routing.c b/src/arch/x86/boot/pirq_routing.c index bb8a7b6..3316707 100644 --- a/src/arch/x86/boot/pirq_routing.c +++ b/src/arch/x86/boot/pirq_routing.c @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2010 Stefan Reinauer <stepan(a)coreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ #include <console/console.h> #include <arch/pirq_routing.h> #include <string.h> @@ -97,13 +116,45 @@ unsigned long copy_pirq_routing_table(unsigned long addr) } #if CONFIG_PIRQ_ROUTE +static u8 pirq_get_next_free_irq(u8* pirq, u16 bitmap) +{ + int i, link; + u8 irq = 0; + for (i = 2; i <= 15; i++) + { + /* Can we assign this IRQ ? */ + if (!((bitmap >> i) & 1)) + continue; + /* We can, Now let's assume we can use this IRQ */ + irq = i; + /* And assume we have not yet routed it */ + int already_routed = 0; + /* Have we already routed it ? */ + for(link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) { + if (pirq[link] == irq) { + already_routed = 1; + break; + } + } + /* If it's not yet routed, use it */ + if(!already_routed) + break; + /* But if it was already routed, try the next one */ + continue; + } + /* Now we got our IRQ */ + return irq; +} + void pirq_routing_irqs(unsigned long addr) { - int i, j, k, num_entries; - unsigned char irq_slot[4]; - unsigned char pirq[4] = {0, 0, 0, 0}; + int i, intx, num_entries; + unsigned char irq_slot[MAX_INTX_ENTRIES]; + unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]; struct irq_routing_table *pirq_tbl; + memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS); + pirq_tbl = (struct irq_routing_table *)(addr); num_entries = (pirq_tbl->size - 32) / 16; @@ -113,37 +164,26 @@ void pirq_routing_irqs(unsigned long addr) printk(BIOS_DEBUG, "PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn >> 3, pirq_tbl->slots[i].slot); - for (j = 0; j < 4; j++) { + for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) { - int link = pirq_tbl->slots[i].irq[j].link; - int bitmap = pirq_tbl->slots[i].irq[j].bitmap; + int link = pirq_tbl->slots[i].irq[intx].link; + int bitmap = pirq_tbl->slots[i].irq[intx].bitmap; int irq = 0; printk(BIOS_DEBUG, "INT: %c link: %x bitmap: %x ", - 'A' + j, link, bitmap); + 'A' + intx, link, bitmap); - if (!bitmap|| !link || link > 4) { + if (!bitmap|| !link || link > CONFIG_MAX_PIRQ_LINKS) { printk(BIOS_DEBUG, "not routed\n"); - irq_slot[j] = irq; + irq_slot[intx] = irq; continue; } /* yet not routed */ - if (!pirq[link - 1]) { - - for (k = 2; k <= 15; k++) { - - if (!((bitmap >> k) & 1)) - continue; - - irq = k; - - /* yet not routed */ - if (pirq[0] != irq && pirq[1] != irq && pirq[2] != irq && pirq[3] != irq) - break; - } - + if (!pirq[link - 1]) + { + irq = pirq_get_next_free_irq(pirq, bitmap); if (irq) pirq[link - 1] = irq; } @@ -151,7 +191,7 @@ void pirq_routing_irqs(unsigned long addr) irq = pirq[link - 1]; printk(BIOS_DEBUG, "IRQ: %d\n", irq); - irq_slot[j] = irq; + irq_slot[intx] = irq; } /* Bus, device, slots IRQs for {A,B,C,D}. */ @@ -159,10 +199,8 @@ void pirq_routing_irqs(unsigned long addr) pirq_tbl->slots[i].devfn >> 3, irq_slot); } - printk(BIOS_DEBUG, "PIRQ1: %d\n", pirq[0]); - printk(BIOS_DEBUG, "PIRQ2: %d\n", pirq[1]); - printk(BIOS_DEBUG, "PIRQ3: %d\n", pirq[2]); - printk(BIOS_DEBUG, "PIRQ4: %d\n", pirq[3]); + for(i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) + printk(BIOS_DEBUG, "PIRQ%u: %d\n", i+1, pirq[i]); pirq_assign_irqs(pirq); } diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h index 08ba535..a1c7b96 100644 --- a/src/arch/x86/include/arch/pirq_routing.h +++ b/src/arch/x86/include/arch/pirq_routing.h @@ -1,6 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2012 Patrick Georgi <patrick(a)georgi-clan.de> + * Copyright (C) 2010 Stefan Reinauer <stepan(a)coreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ #ifndef ARCH_PIRQ_ROUTING_H #define ARCH_PIRQ_ROUTING_H +/* This is the maximum number on interrupt entries that a PCI device may have. + * This is NOT the number of slots or devices in the system + * This is NOT the number of entries in the PIRQ table + * This tells us that in the PIRQ table, we are going to have 4 link-bitmap + * entries per PCI device + * It is fixed at 4: INTA, INTB, INTC, and INTD + * CAUTION: If you change this, pirq_routing will not work correctly*/ +#define MAX_INTX_ENTRIES 4 + #if CONFIG_GENERATE_PIRQ_TABLE #include <stdint.h>

1 0

Support for IBM/Lenovo Thinkpad T60 Flash
by Joerg Mayer 25 Aug '12

25 Aug '12

Hello, some time (> 1 year?) ago I asked on flashrom about support for the T60 and the attached patch was sent as part of the answer. The other part of the answer was that whoever sent this patch was not happy with it. Unfortunately I didn't keep the mail(s) and have forgotten the reason for this. Google also didn't really help. What I found was a similar but not identical mail on coreboot: http://www.coreboot.org/pipermail/coreboot/2010-December/062303.html As the T60 is one of the few Laptop models that are supported by coreboot and I'd like to update to it I have two requests: 1) would someone be willing to update the patch to the current flashrom codebase (I tried this and was able to read, but I don't trust it as the change was done without understanding what the changes did). 2) if possible integrate this into flashrom to make using coreboot easier. 3) (of 2) would it be useful to integrate bucts into flashrom or move it to coreboot/utils/? Thanks Jörg -- Joerg Mayer <jmayer(a)loplof.de> We are stuck with technology when what we really want is just stuff that works. Some say that should read Microsoft instead of technology.

2 1

← Newer
1
2
3
4
5
6
7
8
...
33
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot August 2012