coreboot August 2012

coreboot@coreboot.org

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Patch set updated for coreboot: 2bc6e8c Every chip must have chip_operations
by Kyösti Mälkki 27 Aug '12

27 Aug '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1472 -gerrit commit 2bc6e8cdd7910e2c0a1593370fe9839ca023400a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Aug 21 17:54:26 2012 +0300 Every chip must have chip_operations Forcing this rule, chip_ops can be added in the static devicetree regardless of the existence of the chip.h files. Take care of NULL .name case in dummy chip_operations. Fix typo in mPGA603 socket. Change-Id: Iec1c23484e85cab3f80a34f2b082088f38ac4de9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/smbios.c | 3 +- .../intel/socket_mPGA603/socket_mPGA603_400Mhz.c | 2 +- src/devices/Makefile.inc | 3 ++ src/devices/dummy_chip_ops.c | 30 ++++++++++++ util/sconfig/main.c | 53 ++++++++++------------ util/sconfig/sconfig.h | 1 + 6 files changed, 62 insertions(+), 30 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 8877f60..a171707 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -278,7 +278,8 @@ static int smbios_walk_device_tree(device_t tree, int *handle, unsigned long *cu int len = 0; for(dev = tree; dev; dev = dev->next) { - printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), dev->chip_ops ? dev->chip_ops->name : ""); + printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), + (dev->chip_ops && dev->chip_ops->name) ? dev->chip_ops->name : ""); if (dev->ops && dev->ops->get_smbios_data) len += dev->ops->get_smbios_data(dev, handle, current); diff --git a/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c b/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c index 9154608..2436f96 100644 --- a/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c +++ b/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c @@ -2,6 +2,6 @@ #include "chip.h" -struct chip_opertations cpu_intel_socket_mPGA603_ops = { +struct chip_operations cpu_intel_socket_mPGA603_ops = { CHIP_NAME("Socket mPGA603 400Mhz CPU") }; diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 9a2f71e..cde8b3f 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -11,6 +11,9 @@ ramstage-y += pnp_device.c ramstage-y += pci_ops.c ramstage-y += smbus_ops.c +# Work-around for chip.h removal +ramstage-y += dummy_chip_ops.c + romstage-y+= device_romstage.c subdirs-y += oprom diff --git a/src/devices/dummy_chip_ops.c b/src/devices/dummy_chip_ops.c new file mode 100644 index 0000000..a2fc999 --- /dev/null +++ b/src/devices/dummy_chip_ops.c @@ -0,0 +1,30 @@ +#include <device/device.h> + +/* Dummy chip_operations, so every chip has one for sure. + * Temporary work-around before total chip.h removal. + */ + +struct chip_operations cpu_via_c3_ops = {}; +struct chip_operations cpu_via_c7_ops = {}; +struct chip_operations cpu_amd_geode_lx_ops = {}; +struct chip_operations cpu_amd_geode_gx1_ops = {}; +struct chip_operations cpu_amd_geode_gx2_ops = {}; +struct chip_operations drivers_ati_ragexl_ops = {}; +struct chip_operations drivers_dec_21143_ops = {}; +struct chip_operations drivers_generic_generic_ops = {}; +struct chip_operations drivers_oxford_oxpcie_ops = {}; +struct chip_operations drivers_realtek_ops = {}; +struct chip_operations drivers_sil_3114_ops = {}; +struct chip_operations drivers_trident_blade3d_ops = {}; +struct chip_operations southbridge_amd_amd8131_ops = {}; +struct chip_operations southbridge_amd_amd8132_ops = {}; +struct chip_operations southbridge_amd_amd8151_ops = {}; +struct chip_operations southbridge_broadcom_bcm21000_ops = {}; +struct chip_operations southbridge_broadcom_bcm5780_ops = {}; +struct chip_operations southbridge_intel_i82870_ops = {}; +struct chip_operations southbridge_rdc_r8610_ops = {}; +struct chip_operations southbridge_via_k8t890_ops = {}; +struct chip_operations superio_serverengines_pilot_ops = {}; +struct chip_operations superio_smsc_lpc47n207_ops = {}; +struct chip_operations superio_smsc_sio1007_ops = {}; + diff --git a/util/sconfig/main.c b/util/sconfig/main.c index fe4c3b8..f066d7b 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -179,25 +179,24 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) { } void add_header(struct device *dev) { - if ((dev->chiph_exists) || (scan_mode == KCONFIG_MODE)){ - int include_exists = 0; - struct header *h = &headers; - while (h->next) { - int result = strcmp(dev->name, h->next->name); - if (result == 0) { - include_exists = 1; - break; - } - if (result < 0) break; - h = h->next; - } - if (!include_exists) { - struct header *tmp = h->next; - h->next = malloc(sizeof(struct header)); - memset(h->next, 0, sizeof(struct header)); - h->next->name = dev->name; - h->next->next = tmp; + int include_exists = 0; + struct header *h = &headers; + while (h->next) { + int result = strcmp(dev->name, h->next->name); + if (result == 0) { + include_exists = 1; + break; } + if (result < 0) break; + h = h->next; + } + if (!include_exists) { + struct header *tmp = h->next; + h->next = malloc(sizeof(struct header)); + memset(h->next, 0, sizeof(struct header)); + h->next->chiph_exists = dev->chiph_exists; + h->next->name = dev->name; + h->next->next = tmp; } } @@ -418,16 +417,11 @@ static void pass1(FILE *fil, struct device *ptr) fprintf(fil, "\t.link_list = NULL,\n"); if (ptr->sibling) fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); - if (ptr->chip->chiph_exists) { - fprintf(fil, "#ifndef __PRE_RAM__\n"); - fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); - fprintf(fil, "#endif\n"); + fprintf(fil, "#ifndef __PRE_RAM__\n"); + fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); + fprintf(fil, "#endif\n"); + if (ptr->chip->chiph_exists) fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id); - } else if (ptr->chip->chip == &mainboard) { - fprintf(fil, "#ifndef __PRE_RAM__\n"); - fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore); - fprintf(fil, "#endif\n"); - } if (ptr->nextdev) fprintf(fil, "\t.next=&%s\n", ptr->nextdev->name); fprintf(fil, "};\n"); @@ -622,8 +616,10 @@ int main(int argc, char** argv) { h = &headers; while (h->next) { h = h->next; - fprintf(autogen, "#include \"%s/chip.h\"\n", h->name); + if (h->chiph_exists) + fprintf(autogen, "#include \"%s/chip.h\"\n", h->name); } + fprintf(autogen, "\n#ifndef __PRE_RAM__\n"); h = &headers; while (h->next) { h = h->next; @@ -632,6 +628,7 @@ int main(int argc, char** argv) { fprintf(autogen, "extern struct chip_operations %s_ops;\n", name_underscore); free(name_underscore); } + fprintf(autogen, "#endif\n"); walk_device_tree(autogen, &root, inherit_subsystem_ids, NULL); fprintf(autogen, "\n/* pass 0 */\n"); diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index 1576600..b8a231a 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -86,6 +86,7 @@ struct device *head; struct header; struct header { char *name; + int chiph_exists; struct header *next; };

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Patch merged into coreboot/master: f939696 SB700/SP5100: This configures the HPET clock period.
by gerrit＠coreboot.org 27 Aug '12

27 Aug '12

the following patch was just integrated into master: commit f9396968d7dfdd36288fc9eb33e0c97862bd83fc Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Aug 21 16:51:33 2012 -0600 SB700/SP5100: This configures the HPET clock period. Prior to this change the setting would be zeroes and would cause a BSOD in 64 bit versions of Windows. Change-Id: I2d422ef9667457af53f9fd055799e489ed2b25db Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Build-Tested: build bot (Jenkins) at Wed Aug 22 01:12:50 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Mon Aug 27 15:57:18 2012, giving +2 See http://review.coreboot.org/1475 for details. -gerrit

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Patch merged into coreboot/master: 2743368 AMD Hudson: Move the combining firmware from Python to sh.
by gerrit＠coreboot.org 27 Aug '12

27 Aug '12

the following patch was just integrated into master: commit 274336812d4869247574b458c87c468d1fd28822 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Mon Aug 27 18:40:44 2012 +0800 AMD Hudson: Move the combining firmware from Python to sh. Maybe sooner or later python is not a default tools to build coreboot. Most of the work is done by awk now. GNU extension of gawk is not used, isn't? echo, expr, printf, cat, awk, test, mv are the external tools. If XHCI, IMC or GEC firmware is not available and not defined, this script can skip integrating them. Change-Id: I9944b22b0b755672a46d472c355d138abafd6393 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Aug 27 11:02:55 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Mon Aug 27 15:50:19 2012, giving +1 Reviewed-By: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> at Mon Aug 27 15:51:17 2012, giving +2 See http://review.coreboot.org/1417 for details. -gerrit

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Patch merged into coreboot/master: fe4c78e gitconfig: Match the Change-Id line more exactly
by gerrit＠coreboot.org 27 Aug '12

27 Aug '12

the following patch was just integrated into master: commit fe4c78e8c004334f39004df632d29b38549efac1 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Mon Aug 27 16:58:39 2012 +0800 gitconfig: Match the Change-Id line more exactly Change-Id: I5ac267770bc5b43dd1435e75ab0fcbde0d88b664 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Aug 27 09:46:00 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Mon Aug 27 09:15:26 2012, giving +2 See http://review.coreboot.org/1487 for details. -gerrit

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Patch merged into coreboot/master: 2a39261 Intel model_106cx: change CAR to HT-capable
by gerrit＠coreboot.org 27 Aug '12

27 Aug '12

the following patch was just integrated into master: commit 2a39261e25686ae1b3c311262dcedfea754957d3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 31 23:47:09 2012 +0300 Intel model_106cx: change CAR to HT-capable There are hyper-threading Atom CPUs, those would not enable L2 cache with model_6ex CAR code. Switch to code that can handle different number of threads and cores. Change-Id: I57328c231f8998f45f7b0d26c63b24585f8476dd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Jul 31 23:25:40 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Fri Aug 3 12:21:19 2012, giving +1 Reviewed-By: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> at Mon Aug 27 15:39:28 2012, giving +2 See http://review.coreboot.org/1384 for details. -gerrit

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Patch merged into coreboot/master: 2ed8104 AMD northbridges: factor out CPU allocation
by gerrit＠coreboot.org 27 Aug '12

27 Aug '12

the following patch was just integrated into master: commit 2ed8104b9e82e59391138c256b3b2b1b94d802ed Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Aug 7 17:12:11 2012 +0300 AMD northbridges: factor out CPU allocation Factor CPU allocation out of AMD northbridge codes. As CPU topology information is required for generation of certain ACPI tables, make this code globally available. For AMDK8 and AMDFAM10 northbridge, there is a possible case of BSP CPU with lapicid!=0. We do not want to leave the lapic 0 from devicetree unused, so always use that node for BSP CPU. Change-Id: I8b1e73ed5b20b314f71dfd69a7b781ac05aea120 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Aug 7 17:07:05 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Tue Aug 14 15:46:07 2012, giving +1 Reviewed-By: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> at Mon Aug 27 15:36:47 2012, giving +2 See http://review.coreboot.org/1418 for details. -gerrit

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Patch merged into coreboot/master: 07f63f5 AMD northbridges: rewrite CPU allocation
by gerrit＠coreboot.org 27 Aug '12

27 Aug '12

the following patch was just integrated into master: commit 07f63f5bc09b65f36e5b720f2a1b829ec4f6bf00 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 6 19:02:56 2012 +0300 AMD northbridges: rewrite CPU allocation Use of alloc_find_dev() prevents creation of a device duplicates for device_path and is SMP safe. Reduce scope of variables to make the code more readable and in preparation for refactoring the allocation out of northbridge.c. Change-Id: I153dc1a5cab4f2eae4ab3a57af02841cb1a261c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Aug 6 07:46:18 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Tue Aug 14 15:18:08 2012, giving +1 Reviewed-By: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> at Mon Aug 27 15:35:33 2012, giving +2 See http://review.coreboot.org/1186 for details. -gerrit

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Patch set updated for coreboot: 2743368 AMD Hudson: Move the combining firmware from Python to sh.
by Zheng Bao 27 Aug '12

27 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1417 -gerrit commit 274336812d4869247574b458c87c468d1fd28822 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Mon Aug 27 18:40:44 2012 +0800 AMD Hudson: Move the combining firmware from Python to sh. Maybe sooner or later python is not a default tools to build coreboot. Most of the work is done by awk now. GNU extension of gawk is not used, isn't? echo, expr, printf, cat, awk, test, mv are the external tools. If XHCI, IMC or GEC firmware is not available and not defined, this script can skip integrating them. Change-Id: I9944b22b0b755672a46d472c355d138abafd6393 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 73 ++++++++++++++++++++++++-- src/southbridge/amd/agesa/hudson/hudson_fwm.py | 64 ---------------------- 2 files changed, 69 insertions(+), 68 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 19ffae1..ff0662d 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -14,16 +14,81 @@ romstage-y += early_setup.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c -$(obj)/hudson.bin: - python $(src)/southbridge/amd/agesa/hudson/hudson_fwm.py $(CONFIG_HUDSON_FWM_POSITION) $@ $(CONFIG_HUDSON_XHCI_FWM_FILE) $(CONFIG_HUDSON_IMC_FWM_FILE) "" +# ROMSIG At ROMBASE + 0x20000: +# +-----------+---------------+----------------+------------+ +# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# +-----------+---------------+----------------+------------+ +# EC ROM should be 64K aligned. +HUDSON_FWM_POSITION=$(shell printf %d $(CONFIG_HUDSON_FWM_POSITION)) + +#assume the cbfs header is less than 128 bytes. +ROMSIG_SIZE=16 +ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) +HUDSON_XHCI_POSITION=$(shell expr $(HUDSON_FWM_POSITION) + $(ROMSIG_SIZE) + 128) +XHCI_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_XHCI_FWM_FILE))) +else +HUDSON_XHCI_POSITION=0 +XHCI_FWM_SIZE=0 +endif + +ifeq ($(CONFIG_HUDSON_GEC_FWM), y) +HUDSON_GEC_POSITION=$(shell expr $(HUDSON_FWM_POSITION) + $(ROMSIG_SIZE) + 128 \ + + $(XHCI_FWM_SIZE) + 128) +GEC_FWM_SIZE=$(word 5,$(shell ls -l $(CONFIG_HUDSON_GEC_FWM_FILE))) +else +HUDSON_GEC_POSITION=0 +GEC_FWM_SIZE=0 +endif + +ifeq ($(CONFIG_HUDSON_IMC_FWM), y) +HUDSON_IMC_POSITION_UNALIGN=$(shell expr $(HUDSON_FWM_POSITION) + $(ROMSIG_SIZE) + 128 \ + + $(XHCI_FWM_SIZE) + 128 \ + + $(GEC_FWM_SIZE) + 128 + 65535) +HUDSON_IMC_POSITION=$(shell expr $(HUDSON_IMC_POSITION_UNALIGN) - $(HUDSON_IMC_POSITION_UNALIGN) % 65536) +else +HUDSON_IMC_POSITION=0 +endif + +$(obj)/hudson_romsig.bin: #$(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ + $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ + $(obj)/config.h + echo " Hudson FW $@" + for fwm in 1437226410 \ + $(HUDSON_IMC_POSITION) \ + $(HUDSON_GEC_POSITION) \ + $(HUDSON_XHCI_POSITION) ; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 0x100, $$1/0x100 % 0x100, $$1/0x10000 % 0x100, $$1/0x1000000);}'; \ + done > $@ ifeq ($(CONFIG_HUDSON_FWM), y) cbfs-files-y += hudson/fwm -hudson/fwm-file := $(obj)/hudson.bin -hudson/fwm-position := $(CONFIG_HUDSON_FWM_POSITION) +hudson/fwm-file := $(obj)/hudson_romsig.bin +hudson/fwm-position := $(HUDSON_FWM_POSITION) hudson/fwm-type := raw endif +ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) +cbfs-files-y += hudson/xhci +hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) +hudson/xhci-position := $(HUDSON_XHCI_POSITION) +hudson/xhci-type := raw +endif + +ifeq ($(CONFIG_HUDSON_IMC_FWM), y) +cbfs-files-y += hudson/imc +hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) +hudson/imc-position := $(HUDSON_IMC_POSITION) +hudson/imc-type := raw +endif + +ifeq ($(CONFIG_HUDSON_GEC_FWM), y) +cbfs-files-y += hudson/gec +hudson/gec-file := $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) +hudson/gec-position := $(HUDSON_GEC_POSITION) +hudson/gec-type := raw +endif + #ifeq ($(CONFIG_HUDSON_SATA_AHCI), y) ifdef CONFIG_HUDSON_AHCI_ROM stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) diff --git a/src/southbridge/amd/agesa/hudson/hudson_fwm.py b/src/southbridge/amd/agesa/hudson/hudson_fwm.py deleted file mode 100644 index ad60b3b..0000000 --- a/src/southbridge/amd/agesa/hudson/hudson_fwm.py +++ /dev/null @@ -1,64 +0,0 @@ -import sys, os, re -import struct -from Queue import Queue - -def main(start_addr, file_name, xhci_name, imc_name, gec_name): - fwm_sig = 0x55AA55AA # Hudson-2/3/4 firmware signature - fwm_header_len = 0x10 # 55AA55AA, imc_off, gec_off, xhci_off - - if not os.path.exists(xhci_name): - print "XHCI firmware %s does not exist\n" % xhci_name - sys.exit(1) - if not os.path.exists(imc_name): - print "IMC firmware %s does not exist\n" % imc_name - sys.exit(1) - - f = open(file_name, "w") - print "write to file " + file_name - - imc_offset = 0x10000 # 64K Bytes offset, hardcoded - imc_addr = start_addr + imc_offset; #startaddr + 0x10000 - gec_offset = 0 #TODO - gec_addr = 0 #TODO - xhci_addr = start_addr + fwm_header_len #ROMSIG take 0x10 bytes - - format="I" # one unsigned integer - data=struct.pack(format, fwm_sig) - f.write(data) - data=struct.pack(format, imc_addr) - f.write(data) - data=struct.pack(format, gec_addr) - f.write(data) - data=struct.pack(format, xhci_addr) - f.write(data) - - fwm_content = open(xhci_name).read() - f.write(fwm_content) - - imc_content = open(imc_name).read() - f.seek(0) - f.seek(imc_offset) - f.write(imc_content) -# if os.path.exists(gec_name): -# gec_conent = open(gec_name).read() -# f.seek(0) -# f.seek(gec_offset) -# f.write(gec_content) - - f.close() - print "done\n" - - -if __name__ == '__main__': - if (len(sys.argv) < 6): - print "\nUsage: %s <rom_addr> <rom_file> <xhci_rom> <imc_rom> <gec_rom>\n" % sys.argv[0] - print "Example: %s 0xFFF20000 hudson.bin xhci.bin imc.bin gec.bin\n" % sys.argv[0] - sys.exit(1) - rom_addr = int(sys.argv[1], 16) - rom_file = sys.argv[2] - xhci_file = sys.argv[3] - imc_file = sys.argv[4] - gec_file = sys.argv[5] - print "%x %s %s %s %s" % (rom_addr, rom_file, xhci_file, imc_file, gec_file) - - main(rom_addr, rom_file, xhci_file, imc_file, gec_file)

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Patch set updated for coreboot: 77106f0 AMD S3: The offset of the nv storage depends on config.h
by Zheng Bao 27 Aug '12

27 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1485 -gerrit commit 77106f04978c27afd8feea6a9dccd4f79da1b605 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Mon Aug 27 17:45:01 2012 +0800 AMD S3: The offset of the nv storage depends on config.h Change-Id: Ic8410fb706dce677c7218d19030d84b64cda7b7f Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zheng Bao <fishbaozi(a)gmail.com> --- src/southbridge/amd/Kconfig | 5 ----- src/southbridge/amd/Makefile.inc | 2 +- src/southbridge/amd/agesa/hudson/Kconfig | 8 ++++++++ src/southbridge/amd/cimx/sb700/Kconfig | 9 +++++++++ src/southbridge/amd/cimx/sb800/Kconfig | 8 ++++++++ src/southbridge/amd/cimx/sb900/Kconfig | 9 +++++++++ 6 files changed, 35 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 23f6c06..867afca 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -14,8 +14,3 @@ source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig - -# This can be overriden by mainboard/Kconfig -config S3_VOLATILE_POS - hex - default 0xFFFF0000 diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index d2b9b65..1e3309a 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -19,7 +19,7 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) ifeq ($(CONFIG_CPU_AMD_AGESA), y) -$(obj)/s3.rom: +$(obj)/s3.rom: $(obj)/config.h echo " S3 NVRAM $(CONFIG_S3_VOLATILE_POS) (S3 storage area)" # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index e3fc8c7..f58f920 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -205,4 +205,12 @@ config RAID_MISC_ROM_POSITION The CONFIG_ROM_SIZE must larger than 0x100000. endif +config S3_VOLATILE_POS + hex "S3 volatile storage position" + default 0xFFFF0000 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volitile storage at cold boot stage. + endif diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index 27338fc..f139450 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -59,5 +59,14 @@ config REDIRECT_SBCIMX_TRACE_TO_SERIAL debug information to the serial console. Warning: Only enable this option when debuging or tracing AMD CIMX code. + +config S3_VOLATILE_POS + hex "S3 volatile storage position" + default 0xFFFF0000 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volitile storage at cold boot stage. + endif #SOUTHBRIDGE_AMD_CIMX_SB700 diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 79624e0..4ac2094 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -122,5 +122,13 @@ config RAID_MISC_ROM_POSITION endif +config S3_VOLATILE_POS + hex "S3 volatile storage position" + default 0xFFFF0000 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volitile storage at cold boot stage. + endif #SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index 253d73f..acc369e 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -52,5 +52,14 @@ config ACPI_SCI_IRQ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb900/bootblock.c" + +config S3_VOLATILE_POS + hex "S3 volatile storage position" + default 0xFFFF0000 + depends on HAVE_ACPI_RESUME + help + For a system with S3 feature, the BIOS needs to save some data to + non-volitile storage at cold boot stage. + endif #SOUTHBRIDGE_AMD_CIMX_SB900

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New patch to review for coreboot: fe4c78e gitconfig: Match the Change-Id line more exactly
by Zheng Bao 27 Aug '12

27 Aug '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1487 -gerrit commit fe4c78e8c004334f39004df632d29b38549efac1 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Mon Aug 27 16:58:39 2012 +0800 gitconfig: Match the Change-Id line more exactly Change-Id: I5ac267770bc5b43dd1435e75ab0fcbde0d88b664 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/gitconfig/commit-msg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/gitconfig/commit-msg b/util/gitconfig/commit-msg index 212ffb1..82f0581 100755 --- a/util/gitconfig/commit-msg +++ b/util/gitconfig/commit-msg @@ -37,7 +37,7 @@ add_ChangeId() { fi # Does Change-Id: already exist? if so, exit (no change). - if grep -i '^Change-Id:' "$MSG" >/dev/null + if grep -i '^Change-Id: I[0-9a-f]\{40\}$' "$MSG" >/dev/null then return fi

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coreboot August 2012