coreboot August 2012

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Patch merged into coreboot/master: 5ff70e8 MPTABLE: check for fixed IRQ entries on all pins
by gerrit＠coreboot.org 25 Aug '12

25 Aug '12

the following patch was just integrated into master: commit 5ff70e835e2d52a08f072972bc2ba576fa067174 Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Aug 20 11:19:00 2012 +0200 MPTABLE: check for fixed IRQ entries on all pins Don't derive the IRQ pin from the function number. Especially onboard chipset devices don't follow that rule. Instead check and add all fixed IRQ entries. Change-Id: I46c88bad39104c1d9b4154f180f8b3c42df28262 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Sat Aug 25 03:07:29 2012, giving +1 Reviewed-By: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> at Sat Aug 25 05:15:50 2012, giving +2 See http://review.coreboot.org/1461 for details. -gerrit

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Patch set updated for coreboot: 1ad7fac bd82x6x: remove ioapic initialization
by Alexandru Gagniuc 25 Aug '12

25 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1463 -gerrit commit 1ad7faced8828af71149311519ae174598445587 Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Aug 20 11:22:37 2012 +0200 bd82x6x: remove ioapic initialization This now done by the generic ioapic driver. Change-Id: Iea648158c429ee5b053c7b3f3cdfcfaecb4eb4c3 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/bd82x6x/lpc.c | 49 ++----------------------------------- 1 file changed, 2 insertions(+), 47 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 592f5de..3a6140f 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -26,7 +26,6 @@ #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> -#include <arch/ioapic.h> #include <arch/acpi.h> #include <cpu/cpu.h> #include <elog.h> @@ -39,45 +38,6 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static void pch_enable_apic(struct device *dev) -{ - int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } - - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ -} - static void pch_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit for one frame. */ @@ -537,8 +497,8 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - pch_enable_apic(dev); + /* enable ACPI */ + pci_write_config8(dev, ACPI_CNTL, 0x80); pch_enable_serial_irqs(dev); @@ -612,11 +572,6 @@ static void pch_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - /* Set PCH IO decode ranges if required.*/ if ((config->gen1_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));

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Patch set updated for coreboot: 5ff70e8 MPTABLE: check for fixed IRQ entries on all pins
by Alexandru Gagniuc 25 Aug '12

25 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1461 -gerrit commit 5ff70e835e2d52a08f072972bc2ba576fa067174 Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Aug 20 11:19:00 2012 +0200 MPTABLE: check for fixed IRQ entries on all pins Don't derive the IRQ pin from the function number. Especially onboard chipset devices don't follow that rule. Instead check and add all fixed IRQ entries. Change-Id: I46c88bad39104c1d9b4154f180f8b3c42df28262 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/boot/mpspec.c | 89 ++++++++++++++++++++++++---------------------- 1 file changed, 47 insertions(+), 42 deletions(-) diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index 78996c7..cf346a5 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -419,7 +419,7 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) int isa_bus, pin, parentpin; device_t dev, parent, oldparent; void *tmp, *v; - int isaioapic = -1; + int isaioapic = -1, have_fixed_entries; v = smp_write_floating_table(addr, 0); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -461,48 +461,53 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) if (dev->path.type != DEVICE_PATH_PCI || !dev->enabled) continue; - pin = (dev->path.pci.devfn & 7) % 4; - - if (dev->pci_irq_info[pin].ioapic_dst_id) { - printk(BIOS_DEBUG, "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev), - pin + 'A', - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - dev->pci_irq_info[pin].ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) >> 1) | pin, - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - } else { - oldparent = parent = dev; - while((parent = parent->bus->dev)) { - parentpin = (oldparent->path.pci.devfn >> 3) + (oldparent->path.pci.devfn & 7); - parentpin += dev->path.pci.devfn & 7; - parentpin += dev->path.pci.devfn >> 3; - parentpin %= 4; - - if (parent->pci_irq_info[parentpin].ioapic_dst_id) { - printk(BIOS_DEBUG, "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n", - dev_path(dev), pin + 'A', - parent->pci_irq_info[parentpin].ioapic_dst_id, - parent->pci_irq_info[parentpin].ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - parent->pci_irq_info[parentpin].ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) >> 1) | pin, - parent->pci_irq_info[parentpin].ioapic_dst_id, - parent->pci_irq_info[parentpin].ioapic_irq_pin); - - break; - } - - if (parent->path.type == DEVICE_PATH_PCI_DOMAIN) { - printk(BIOS_WARNING, "no IRQ found for %s\n", dev_path(dev)); - break; - } - oldparent = parent; + have_fixed_entries = 0; + for (pin = 0; pin < 4; pin++) { + if (dev->pci_irq_info[pin].ioapic_dst_id) { + printk(BIOS_DEBUG, "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev), + pin + 'A', + dev->pci_irq_info[pin].ioapic_dst_id, + dev->pci_irq_info[pin].ioapic_irq_pin); + smp_write_intsrc(mc, mp_INT, + dev->pci_irq_info[pin].ioapic_flags, + dev->bus->secondary, + ((dev->path.pci.devfn & 0xf8) >> 1) | pin, + dev->pci_irq_info[pin].ioapic_dst_id, + dev->pci_irq_info[pin].ioapic_irq_pin); + have_fixed_entries = 1; + } + } + + if (!have_fixed_entries) { + pin = (dev->path.pci.devfn & 7) % 4; + oldparent = parent = dev; + while((parent = parent->bus->dev)) { + parentpin = (oldparent->path.pci.devfn >> 3) + (oldparent->path.pci.devfn & 7); + parentpin += dev->path.pci.devfn & 7; + parentpin += dev->path.pci.devfn >> 3; + parentpin %= 4; + + if (parent->pci_irq_info[parentpin].ioapic_dst_id) { + printk(BIOS_DEBUG, "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n", + dev_path(dev), pin + 'A', + parent->pci_irq_info[parentpin].ioapic_dst_id, + parent->pci_irq_info[parentpin].ioapic_irq_pin); + smp_write_intsrc(mc, mp_INT, + parent->pci_irq_info[parentpin].ioapic_flags, + dev->bus->secondary, + ((dev->path.pci.devfn & 0xf8) >> 1) | pin, + parent->pci_irq_info[parentpin].ioapic_dst_id, + parent->pci_irq_info[parentpin].ioapic_irq_pin); + + break; } + + if (parent->path.type == DEVICE_PATH_PCI_DOMAIN) { + printk(BIOS_WARNING, "no IRQ found for %s\n", dev_path(dev)); + break; + } + oldparent = parent; + } } }

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Patch set updated for coreboot: a9e23fc IEI/KINO: Fixes an apparent ACPI VGA resource collision.
by Alexandru Gagniuc 25 Aug '12

25 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1480 -gerrit commit a9e23fc50614a8e5fb8cdedc32530471372e8902 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Aug 22 11:10:41 2012 -0600 IEI/KINO: Fixes an apparent ACPI VGA resource collision. Without this change 64 bit versions of Windows will BSOD. Change-Id: Ica4b79d798a269399341868b1c793ce745aa93fc Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/mainboard/iei/kino-780am2-fam10/dsdt.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl index 66f8254..1501731 100644 --- a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl +++ b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl @@ -1545,9 +1545,9 @@ DefinitionBlock ( 0xF300 /* length */ ) - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ #if 0 + Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */

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Patch set updated for coreboot: 200dd80 Add possibility to patch VGA oprom
by Alexandru Gagniuc 25 Aug '12

25 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1478 -gerrit commit 200dd809f040c5ef34c4faf1c478e751fe620897 Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Wed Aug 22 16:59:02 2012 +0200 Add possibility to patch VGA oprom In some rare cases it could be useful to patch a VGA oprom in order to fix some stuff. In later patches this will be used to add EDID information to SeaVIDEOBIOS in oder to support some flat panels. Change-Id: Ic1005053265505a65b6fd99bc3c6c9cfcbffee43 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- src/devices/pci_rom.c | 7 +++++++ src/include/device/pci_rom.h | 3 +++ 2 files changed, 10 insertions(+) diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c index fe67515..1135d94 100644 --- a/src/devices/pci_rom.c +++ b/src/devices/pci_rom.c @@ -162,6 +162,13 @@ struct rom_header *pci_rom_load(struct device *dev, memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size); } + + /* In some cases it is useful to patch an pci vga oprom. A good example + * is adding/changing some EDID information stored in the VGA option rom. + */ + if (pci_vga_rom_patch) + pci_vga_rom_patch(rom_data, (void *)PCI_VGA_RAM_IMAGE_START); + return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START); } diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index fe77276..690e304 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -37,4 +37,7 @@ struct rom_header *pci_rom_probe(struct device *dev); struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); u32 __attribute__((weak)) map_oprom_vendev(u32 vendev); +void __attribute__((weak)) +pci_vga_rom_patch(struct pci_data *rom_data, void *pci_vga_ram_image_start); + #endif

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Patch set updated for coreboot: c4a3b62 AMD S3: The offset of the nv storage depends on config.h
by Alexandru Gagniuc 25 Aug '12

25 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1485 -gerrit commit c4a3b62b426c8a843c3cc533ab983ba7b5dd8476 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Fri Aug 24 23:18:28 2012 +0800 AMD S3: The offset of the nv storage depends on config.h Change-Id: Ic8410fb706dce677c7218d19030d84b64cda7b7f Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zheng Bao <fishbaozi(a)gmail.com> --- src/southbridge/amd/Kconfig | 11 ++++++++++- src/southbridge/amd/Makefile.inc | 2 +- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 23f6c06..d2bf958 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -17,5 +17,14 @@ source src/southbridge/amd/sr5650/Kconfig # This can be overriden by mainboard/Kconfig config S3_VOLATILE_POS - hex + hex "s3 volatile position" default 0xFFFF0000 + depends on (HAVE_ACPI_RESUME \ + && (SOUTHBRIDGE_AMD_AGESA_HUDSON \ + || SOUTHBRIDGE_AMD_CIMX_SB700 \ + || SOUTHBRIDGE_AMD_CIMX_SB800 \ + || SOUTHBRIDGE_AMD_CIMX_SB900 \ + || SOUTHBRIDGE_AMD_SB800 \ + || SOUTHBRIDGE_AMD_SB700 \ + || SOUTHBRIDGE_AMD_SB600)) + diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index d2b9b65..1e3309a 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -19,7 +19,7 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) ifeq ($(CONFIG_CPU_AMD_AGESA), y) -$(obj)/s3.rom: +$(obj)/s3.rom: $(obj)/config.h echo " S3 NVRAM $(CONFIG_S3_VOLATILE_POS) (S3 storage area)" # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) LC_ALL=C awk 'BEGIN {for (i=0; i<32768; i++) {printf "%c", 255}}' > $@.tmp

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Patch set updated for coreboot: 3bcbfa3 pirq_routing: Allow routing with more than 4 PIRQ links
by Alexandru Gagniuc 25 Aug '12

25 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1482 -gerrit commit 3bcbfa3d58496480434c6d9fa4eefcc667365f81 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Aug 23 02:32:58 2012 -0500 pirq_routing: Allow routing with more than 4 PIRQ links pirq_routing_irqs assumed that only for links are available for PIRQ routing, INTA to INTD. Some chipsets provide more, up to INTH. When pirq_routing_irqs found a link number greater than 4in the pirq table, it would not assign that IRQ. This is a shame, as it limits the flexibility of routing IRQs. Make the maximum number of links a Kconfig variable, and modify the code to respect it. This works beatifully on the VX900, which provides 8 routable interrupts. While we're at it, also refactor pirq_routing_irqs, and add some much needed comments. Change-Id: I4b565315404c65b871406f616474e2cc9e6e013e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/Kconfig | 11 ++++++ src/arch/x86/boot/pirq_routing.c | 77 +++++++++++++++++++++++++--------------- 2 files changed, 60 insertions(+), 28 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 469266d..6da906d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -374,6 +374,17 @@ config HAVE_PIRQ_TABLE Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE. +config MAX_PIRQ_LINKS + int + default 4 + help + This variable specifies the number of PIRQ interrupt links which are + routable. On most chipsets, this is 4, INTA through INTD. Some + chipsets offer more than four links, commonly up to INTH. They may + also have a separate link for ATA or IOAPIC interrupts. When the PIRQ + table specifies links greater than 4, pirq_routing_irqs will not + function properly, unless this variable is correctly set. + #These Options are here to avoid "undefined" warnings. #The actual selection and help texts are in the following menu. diff --git a/src/arch/x86/boot/pirq_routing.c b/src/arch/x86/boot/pirq_routing.c index bb8a7b6..dd147c6 100644 --- a/src/arch/x86/boot/pirq_routing.c +++ b/src/arch/x86/boot/pirq_routing.c @@ -97,13 +97,47 @@ unsigned long copy_pirq_routing_table(unsigned long addr) } #if CONFIG_PIRQ_ROUTE + +#define MAX_INTX_ENTRIES 4 +static u8 pirq_get_next_free_irq(u8* pirq, u16 bitmap) +{ + int i, link; + u8 irq = 0; + for (i = 2; i <= 15; i++) + { + /* Can we assign this IRQ ? */ + if (!((bitmap >> i) & 1)) + continue; + /* We can, Now let's assume we can use this IRQ */ + irq = i; + /* And assume we have not yet routed it */ + int already_routed = 0; + /* Have we already routed it ? */ + for(link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) { + if (pirq[link] == irq) { + already_routed = 1; + break; + } + } + /* If it's not yet routed, use it */ + if(!already_routed) + break; + /* But if it was already routed, try the next one */ + continue; + } + /* Now we got our IRQ */ + return irq; +} + void pirq_routing_irqs(unsigned long addr) { - int i, j, k, num_entries; - unsigned char irq_slot[4]; - unsigned char pirq[4] = {0, 0, 0, 0}; + int i, intx, num_entries; + unsigned char irq_slot[MAX_INTX_ENTRIES]; + unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]; struct irq_routing_table *pirq_tbl; + memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS); + pirq_tbl = (struct irq_routing_table *)(addr); num_entries = (pirq_tbl->size - 32) / 16; @@ -113,37 +147,26 @@ void pirq_routing_irqs(unsigned long addr) printk(BIOS_DEBUG, "PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn >> 3, pirq_tbl->slots[i].slot); - for (j = 0; j < 4; j++) { + for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) { - int link = pirq_tbl->slots[i].irq[j].link; - int bitmap = pirq_tbl->slots[i].irq[j].bitmap; + int link = pirq_tbl->slots[i].irq[intx].link; + int bitmap = pirq_tbl->slots[i].irq[intx].bitmap; int irq = 0; printk(BIOS_DEBUG, "INT: %c link: %x bitmap: %x ", - 'A' + j, link, bitmap); + 'A' + intx, link, bitmap); - if (!bitmap|| !link || link > 4) { + if (!bitmap|| !link || link > CONFIG_MAX_PIRQ_LINKS) { printk(BIOS_DEBUG, "not routed\n"); - irq_slot[j] = irq; + irq_slot[intx] = irq; continue; } /* yet not routed */ - if (!pirq[link - 1]) { - - for (k = 2; k <= 15; k++) { - - if (!((bitmap >> k) & 1)) - continue; - - irq = k; - - /* yet not routed */ - if (pirq[0] != irq && pirq[1] != irq && pirq[2] != irq && pirq[3] != irq) - break; - } - + if (!pirq[link - 1]) + { + irq = pirq_get_next_free_irq(pirq, bitmap); if (irq) pirq[link - 1] = irq; } @@ -151,7 +174,7 @@ void pirq_routing_irqs(unsigned long addr) irq = pirq[link - 1]; printk(BIOS_DEBUG, "IRQ: %d\n", irq); - irq_slot[j] = irq; + irq_slot[intx] = irq; } /* Bus, device, slots IRQs for {A,B,C,D}. */ @@ -159,10 +182,8 @@ void pirq_routing_irqs(unsigned long addr) pirq_tbl->slots[i].devfn >> 3, irq_slot); } - printk(BIOS_DEBUG, "PIRQ1: %d\n", pirq[0]); - printk(BIOS_DEBUG, "PIRQ2: %d\n", pirq[1]); - printk(BIOS_DEBUG, "PIRQ3: %d\n", pirq[2]); - printk(BIOS_DEBUG, "PIRQ4: %d\n", pirq[3]); + for(i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) + printk(BIOS_DEBUG, "PIRQ%u: %d\n", i+1, pirq[i]); pirq_assign_irqs(pirq); }

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Patch set updated for coreboot: b52a318 ioapic driver: typedef the ioapic_config struct (TRIVIAL)
by Alexandru Gagniuc 25 Aug '12

25 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1481 -gerrit commit b52a318592af96e41b1c2d40e8755e6274e41cb9 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Aug 22 19:12:49 2012 -0500 ioapic driver: typedef the ioapic_config struct (TRIVIAL) I use the ioapic_config in my VX900 branch. Typing: struct drivers_generic_ioapic_config *config = (struct drivers_generic_ioapic_config *)dev->chip_info; is clumsy at best, so just create a typedef to mahe this more elegant: ioapic_config_t config = (ioapic_config_t*)ioapic->chip_info; Change-Id: I407899845cfbd847ba6309dd0cf9ef836a607c8e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/generic/ioapic/chip.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/drivers/generic/ioapic/chip.h b/src/drivers/generic/ioapic/chip.h index ad6ff0b..0936d63 100644 --- a/src/drivers/generic/ioapic/chip.h +++ b/src/drivers/generic/ioapic/chip.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,12 +21,13 @@ #ifndef DRIVERS_GENERIC_IOAPIC_CHIP_H #define DRIVERS_GENERIC_IOAPIC_CHIP_H -struct drivers_generic_ioapic_config { +typedef struct drivers_generic_ioapic_config { u32 version; u8 apicid; u8 irq_on_fsb; u8 enable_virtual_wire; u8 have_isa_interrupts; u32 base; -}; +} ioapic_config_t; + #endif

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Patch set updated for coreboot: 30ef834 bd82x6x: remove ioapic initialization
by Alexandru Gagniuc 25 Aug '12

25 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1463 -gerrit commit 30ef834524e55122067eafa377d5eadafc8bca82 Author: Sven Schnelle <svens(a)stackframe.org> Date: Mon Aug 20 11:22:37 2012 +0200 bd82x6x: remove ioapic initialization This now done by the generic ioapic driver. Change-Id: Iea648158c429ee5b053c7b3f3cdfcfaecb4eb4c3 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/bd82x6x/lpc.c | 49 ++----------------------------------- 1 file changed, 2 insertions(+), 47 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 592f5de..3a6140f 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -26,7 +26,6 @@ #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> -#include <arch/ioapic.h> #include <arch/acpi.h> #include <cpu/cpu.h> #include <elog.h> @@ -39,45 +38,6 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static void pch_enable_apic(struct device *dev) -{ - int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } - - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ -} - static void pch_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit for one frame. */ @@ -537,8 +497,8 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - pch_enable_apic(dev); + /* enable ACPI */ + pci_write_config8(dev, ACPI_CNTL, 0x80); pch_enable_serial_irqs(dev); @@ -612,11 +572,6 @@ static void pch_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - /* Set PCH IO decode ranges if required.*/ if ((config->gen1_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));

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Patch merged into coreboot/master: cf86e09 Fix mptable build troubles
by gerrit＠coreboot.org 25 Aug '12

25 Aug '12

the following patch was just integrated into master: commit cf86e09ebfae2cf65beade47ba5da925617a86e2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Aug 25 00:21:44 2012 +0300 Fix mptable build troubles A missing mptable.c file got passed jenkins, got merged and broke the build. Hopefully finally fix this. Deletes unused files: src/mainboard/asus/dsbf/mptable.c src/mainboard/supermicro/x7db8/mptable.c Change-Id: Ie81f5a6c4c69ab381f86a243bc8874395e69ee26 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Aug 24 23:35:41 2012, giving +1 Reviewed-By: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> at Fri Aug 24 23:36:06 2012, giving +2 See http://review.coreboot.org/1486 for details. -gerrit

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coreboot August 2012