coreboot August 2012

coreboot@coreboot.org

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Coreboot with a Linux kernel and initramfs as payload.
by Hoàng Tùng 30 Aug '12

30 Aug '12

Hi all, I'm trying to build Coreboot with a Linux kernel and initramfs as payload. Here is my step to do it 1. Download souce code Coreboot , linux-2.6.34.13 , busybox-1.20.2 2. Build busybox and make rootfs ( i build static ) $ cd busybox-1.20.2 $ make menuconfig $ make $ mkdir _install $ make install $ cd _install $ find . | cpio -o --format=newc > ../rootfs.img $ cd .. $ gzip -c rootfs.img > rootfs.img.gz 3. Compile a minimal linux kernel $ cd linux-2.6.34.13 $ make menuconfig $ make 4. Convert the kernel image and rootfs to ELF $ mkelfImage --kernel=bzImage --ramdisk=rootfs.img --output=payload.elf 5. Compile Coreboot for qemu using this payload.elf as payload 6. Start qemu using Coreboot.rom $ qemu -bios coreboot/build/coreboot.rom -hda disk.img -nographic But result is failed. QEMU hang out and can't continue Below is qemu log. Could you give me some advice ?? Thanks ------------------------------------------------------------------------- qemu log ------------------------------------------------------------------------ open /dev/kvm: No such file or directory Could not initialize KVM, will disable KVM support qemu: pci_add_option_rom: failed to find romfile "pxe-rtl8139.bin" coreboot-4.0-2732-g0db6820-dirty Thu Aug 30 11:34:32 ICT 2012 starting... Loading image. CBFS: Looking for 'fallback/coreboot_ram' CBFS: found. CBFS: loading stage fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000 Jumping to image. coreboot-4.0-2732-g0db6820-dirty Thu Aug 30 11:34:32 ICT 2012 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 Compare with tree... Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 scan_static_bus for Root Device PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1237] ops PCI: 00:00.0 [8086/1237] enabled PCI: 00:01.0 [8086/7000] bus ops PCI: 00:01.0 [8086/7000] enabled PCI: 00:01.1 [8086/7010] ops PCI: 00:01.1 [8086/7010] enabled PCI: 00:01.3 [8086/7113] bus ops pwrmgt_enable: gpo default missing in devicetree.cb! PCI: 00:01.3 [8086/7113] enabled PCI: 00:02.0 [1013/00b8] ops PCI: 00:02.0 [1013/00b8] enabled PCI: 00:03.0 [10ec/8139] enabled scan_static_bus for PCI: 00:01.0 scan_static_bus for PCI: 00:01.0 done scan_static_bus for PCI: 00:01.3 scan_static_bus for PCI: 00:01.3 done PCI: pci_scan_bus returning with max=000 scan_static_bus for Root Device done done found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:01.3 PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 10 PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:03.0 PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:03.0 10 * [0x0 - 0xff] io PCI: 00:01.1 20 * [0x400 - 0x40f] io PCI_DOMAIN: 0000 compute_resources_io: base: 410 size: 410 align: 8 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.0 10 * [0x0 - 0x1ffffff] prefmem PCI: 00:02.0 30 * [0x2000000 - 0x200ffff] mem PCI: 00:02.0 14 * [0x2010000 - 0x2010fff] mem PCI: 00:03.0 14 * [0x2011000 - 0x20110ff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 2011100 size: 2011100 align: 25 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 00:01.1 constrain_resources: PCI: 00:01.3 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:03.0 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000e3ff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:410 align:8 gran:0 limit:e3ff Assigned: PCI: 00:03.0 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:01.1 20 * [0x1400 - 0x140f] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1410 size: 410 align: 8 gran: 0 done PCI_DOMAIN: 0000 allocate_resources_mem: base:fc000000 size:2011100 align:25 gran:0 limit:febfffff Assigned: PCI: 00:02.0 10 * [0xfc000000 - 0xfdffffff] prefmem Assigned: PCI: 00:02.0 30 * [0xfe000000 - 0xfe00ffff] mem Assigned: PCI: 00:02.0 14 * [0xfe010000 - 0xfe010fff] mem Assigned: PCI: 00:03.0 14 * [0xfe011000 - 0xfe0110ff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fe011100 size: 2011100 align: 25 gran: 0 done Root Device assign_resources, bus 0 link: 0 Detected 393216 Kbytes (384 MiB) RAM. PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.1 20 <- [0x0000001400 - 0x000000140f] size 0x00000010 gran 0x04 io PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 prefmem PCI: 00:02.0 14 <- [0x00fe010000 - 0x00fe010fff] size 0x00001000 gran 0x0c mem PCI: 00:02.0 30 <- [0x00fe000000 - 0x00fe00ffff] size 0x00010000 gran 0x10 romem PCI: 00:03.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:03.0 14 <- [0x00fe011000 - 0x00fe0110ff] size 0x00000100 gran 0x08 mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 410 align 8 gran 0 limit e3ff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base fc000000 size 2011100 align 25 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI_DOMAIN: 0000 resource base c0000 size 17f40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:00.0 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PCI: 00:01.1 PCI: 00:01.1 resource base 1400 size 10 align 4 gran 4 limit e3ff flags 60000100 index 20 PCI: 00:01.3 PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:02.0 PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit febfffff flags 60001200 index 10 PCI: 00:02.0 resource base fe010000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 14 PCI: 00:02.0 resource base fe000000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 PCI: 00:03.0 PCI: 00:03.0 resource base 1000 size 100 align 8 gran 8 limit e3ff flags 60000100 index 10 PCI: 00:03.0 resource base fe011000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14 Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 00 PCI: 00:01.0 cmd <- 00 PCI: 00:01.1 cmd <- 01 PCI: 00:01.3 cmd <- 00 PCI: 00:02.0 cmd <- 03 PCI: 00:03.0 cmd <- 03 done. Initializing devices... Root Device init PCI: 00:00.0 init Keyboard init... setting ethernet Assigning IRQ 11 to 0:3.0 i8259_configure_irq_trigger: current interrupts are 0x0 i8259_configure_irq_trigger: try to set interrupts 0x800 PCI: 00:01.0 init RTC Init PCI: 00:01.1 init IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: off PCI: 00:02.0 init CBFS: Looking for 'pci1013,00b8.rom' CBFS: Could not find file 'pci1013,00b8.rom'. Option ROM address for PCI: 00:02.0 = fe000000 PCI expansion ROM, signature 0xaa55, INIT size 0x8c00, data ptr 0x010f PCI ROM image, vendor ID 1013, device ID 00b8, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from fe000000 to 0xc0000, 0x8c00 bytes Real mode stub @00000600: 867 bytes Calling Option ROM... ... Option ROM returned. PCI: 00:03.0 init CBFS: Looking for 'pci10ec,8139.rom' CBFS: Could not find file 'pci10ec,8139.rom'. Devices initialized Show all devs...After init. Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:01.3: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 Re-Initializing CBMEM area to 0x17fe0000 Initializing CBMEM area to 0x17fe0000 (131072 bytes) Adding CBMEM entry as no. 1 Moving GDT to 17fe0200...ok High Tables Base is 17fe0000. Copying Interrupt Routing Table to 0x000f0000... done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x17fe0400... done. PIRQ table: 128 bytes. Adding CBMEM entry as no. 3 smbios_write_tables: 17fe1400 Root Device (QEMU Mainboard) PCI_DOMAIN: 0000 (QEMU Northbridge) PCI: 00:00.0 (QEMU Northbridge) PCI: 00:01.0 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PCI: 00:01.1 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PCI: 00:01.3 () PCI: 00:02.0 () PCI: 00:03.0 () SMBIOS tables: 377 bytes. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum cbe0 New low_table_end: 0x00000528 Now going to write high coreboot table at 0x17fe1c00 rom_table_end = 0x17fe1c00 Adjust low_table_end from 0x00000528 to 0x00001000 Adjust rom_table_end from 0x17fe1c00 to 0x17ff0000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-0000000017fdffff: RAM 3. 0000000017fe0000-0000000017ffffff: CONFIGURATION TABLES 4. 00000000ff800000-00000000ffffffff: RESERVED Wrote coreboot table at: 17fe1c00, 0x1f0 bytes, checksum 2ae5 coreboot table: 520 bytes. Multiboot Information structure has been written. 0. FREE SPACE 17fe9c00 00016400 1. GDT 17fe0200 00000200 2. IRQ TABLE 17fe0400 00001000 3. SMBIOS 17fe1400 00000800 4. COREBOOT 17fe1c00 00008000 Lam den day thoiCBFS: Looking for 'fallback/payload' CBFS: found. Got a payload CPU0: stack from 00118000 to 00120000:Lowest stack address 0011fbb8 Loading segment from rom address 0xff809bb8 code (compression=1) New segment dstaddr 0x10000 memsize 0x13224 srcaddr 0xff809c44 filesize 0x1003 (cleaned up) New segment addr 0x10000 size 0x13224 offset 0xff809c44 filesize 0x1003 Loading segment from rom address 0xff809bd4 BSS 0x00020000 (4208 byte) Loading segment from rom address 0xff809bf0 code (compression=0) New segment dstaddr 0x100000 memsize 0x700000 srcaddr 0xff80ac47 filesize 0xe0680 (cleaned up) New segment addr 0x100000 size 0x700000 offset 0xff80ac47 filesize 0xe0680 Loading segment from rom address 0xff809c0c code (compression=0) New segment dstaddr 0x800000 memsize 0xdc459 srcaddr 0xff8eb2c7 filesize 0xdc459 (cleaned up) New segment addr 0x800000 size 0xdc459 offset 0xff8eb2c7 filesize 0xdc459 Loading segment from rom address 0xff809c28 Entry Point 0x00000000 Loading Segment: addr: 0x0000000000020000 memsz: 0x0000000000001070 filesz: 0x0000000000000000 lb: [0x0000000000100000, 0x0000000000124000) Post relocation: addr: 0x0000000000020000 memsz: 0x0000000000001070 filesz: 0x0000000000000000 Loading Segment: addr: 0x0000000000010000 memsz: 0x0000000000013224 filesz: 0x0000000000001003 lb: [0x0000000000100000, 0x0000000000124000) Post relocation: addr: 0x0000000000010000 memsz: 0x0000000000013224 filesz: 0x0000000000001003 using LZMA [ 0x00010000, 0001199c, 0x00023224) <- ff809c44 Clearing Segment: addr: 0x000000000001199c memsz: 0x0000000000011888 dest 00010000, end 00023224, bouncebuffer 178bc000 Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000700000 filesz: 0x00000000000e0680 lb: [0x0000000000100000, 0x0000000000124000) segment: [0x0000000000100000, 0x00000000001e0680, 0x0000000000800000) late: [0x0000000000124000, 0x00000000001e0680, 0x0000000000800000) bounce: [0x00000000178bc000, 0x00000000178e0000, 0x00000000178e0000) Post relocation: addr: 0x00000000178bc000 memsz: 0x0000000000024000 filesz: 0x0000000000024000 it's not compressed! [ 0x178bc000, 178e0000, 0x178e0000) <- ff80ac47 dest 178bc000, end 178e0000, bouncebuffer 178bc000 Loading Segment: addr: 0x0000000000124000 memsz: 0x00000000006dc000 filesz: 0x00000000000bc680 lb: [0x0000000000100000, 0x0000000000124000) Post relocation: addr: 0x0000000000124000 memsz: 0x00000000006dc000 filesz: 0x00000000000bc680 it's not compressed! [ 0x00124000, 001e0680, 0x00800000) <- ff82ec47 Clearing Segment: addr: 0x00000000001e0680 memsz: 0x000000000061f980 dest 00124000, end 00800000, bouncebuffer 178bc000 Loading Segment: addr: 0x0000000000800000 memsz: 0x00000000000dc459 filesz: 0x00000000000dc459 lb: [0x0000000000100000, 0x0000000000124000) Post relocation: addr: 0x0000000000800000 memsz: 0x00000000000dc459 filesz: 0x00000000000dc459 it's not compressed! [ 0x00800000, 008dc459, 0x008dc459) <- ff8eb2c7 dest 00800000, end 008dc459, bouncebuffer 178bc000 Loaded segments Jumping to boot code at 10000 entry = 0x00010000 lb_start = 0x00100000 lb_size = 0x00024000 adjust = 0x17ebc000 buffer = 0x178bc000 elf_boot_notes = 0x0010d364 adjusted_boot_notes = 0x17fc9364 Firmware type: LinuxBIOS

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Patch merged into coreboot/master: 77106f0 AMD S3: The offset of the nv storage depends on config.h
by gerrit＠coreboot.org 30 Aug '12

30 Aug '12

the following patch was just integrated into master: commit 77106f04978c27afd8feea6a9dccd4f79da1b605 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Mon Aug 27 17:45:01 2012 +0800 AMD S3: The offset of the nv storage depends on config.h Change-Id: Ic8410fb706dce677c7218d19030d84b64cda7b7f Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zheng Bao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Aug 27 10:08:00 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Tue Aug 28 11:58:45 2012, giving +1 Reviewed-By: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> at Tue Aug 28 23:34:55 2012, giving +2 See http://review.coreboot.org/1485 for details. -gerrit

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Patch merged into coreboot/master: b52a318 ioapic driver: typedef the ioapic_config struct (TRIVIAL)
by gerrit＠coreboot.org 30 Aug '12

30 Aug '12

the following patch was just integrated into master: commit b52a318592af96e41b1c2d40e8755e6274e41cb9 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Aug 22 19:12:49 2012 -0500 ioapic driver: typedef the ioapic_config struct (TRIVIAL) I use the ioapic_config in my VX900 branch. Typing: struct drivers_generic_ioapic_config *config = (struct drivers_generic_ioapic_config *)dev->chip_info; is clumsy at best, so just create a typedef to mahe this more elegant: ioapic_config_t config = (ioapic_config_t*)ioapic->chip_info; Change-Id: I407899845cfbd847ba6309dd0cf9ef836a607c8e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Aug 25 01:47:45 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Tue Aug 28 12:00:45 2012, giving +2 Reviewed-By: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> at Sat Aug 25 05:18:55 2012, giving +1 See http://review.coreboot.org/1481 for details. -gerrit

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Patch set updated for coreboot: 3253dd3 pirq_routing: Allow routing with more than 4 PIRQ links
by Alexandru Gagniuc 29 Aug '12

29 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1482 -gerrit commit 3253dd3ea4ad85111d609d1a685c3f8c6eee91ef Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Aug 23 02:32:58 2012 -0500 pirq_routing: Allow routing with more than 4 PIRQ links pirq_routing_irqs assumed that only four links are available for PIRQ routing, INTA to INTD. Some chipsets provide more, up to INTH. When pirq_routing_irqs found a link number greater than 4 in the pirq table, it would not assign that IRQ. This is a shame, as it limits the flexibility of routing IRQs. Make the maximum number of links a Kconfig variable, and modify the code to respect it. This works beatifully on the VX900, which provides 8 routable interrupts. While we're at it, also refactor pirq_routing_irqs, and add some much needed comments. Rename pirq_routing_irqs to pirq_route_irqs to demistify the role of this function. The copyrights added were determined from git log filename. Change-Id: I4b565315404c65b871406f616474e2cc9e6e013e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/Kconfig | 12 ++++ src/arch/x86/boot/pirq_routing.c | 98 ++++++++++++++++++++++---------- src/arch/x86/include/arch/pirq_routing.h | 35 +++++++++++- 3 files changed, 112 insertions(+), 33 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 469266d..e0062dd 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1,6 +1,7 @@ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> ## Copyright (C) 2009-2010 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify @@ -374,6 +375,17 @@ config HAVE_PIRQ_TABLE Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE. +config MAX_PIRQ_LINKS + int + default 4 + help + This variable specifies the number of PIRQ interrupt links which are + routable. On most chipsets, this is 4, INTA through INTD. Some + chipsets offer more than four links, commonly up to INTH. They may + also have a separate link for ATA or IOAPIC interrupts. When the PIRQ + table specifies links greater than 4, pirq_route_irqs will not + function properly, unless this variable is correctly set. + #These Options are here to avoid "undefined" warnings. #The actual selection and help texts are in the following menu. diff --git a/src/arch/x86/boot/pirq_routing.c b/src/arch/x86/boot/pirq_routing.c index bb8a7b6..357500c 100644 --- a/src/arch/x86/boot/pirq_routing.c +++ b/src/arch/x86/boot/pirq_routing.c @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2010 Stefan Reinauer <stepan(a)coreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ #include <console/console.h> #include <arch/pirq_routing.h> #include <string.h> @@ -92,18 +111,50 @@ unsigned long copy_pirq_routing_table(unsigned long addr) #if CONFIG_DEBUG_PIRQ verify_copy_pirq_routing_table(addr); #endif - pirq_routing_irqs(addr); + pirq_route_irqs(addr); return addr + intel_irq_routing_table.size; } #if CONFIG_PIRQ_ROUTE -void pirq_routing_irqs(unsigned long addr) +static u8 pirq_get_next_free_irq(u8* pirq, u16 bitmap) { - int i, j, k, num_entries; - unsigned char irq_slot[4]; - unsigned char pirq[4] = {0, 0, 0, 0}; + int i, link; + u8 irq = 0; + for (i = 2; i <= 15; i++) + { + /* Can we assign this IRQ ? */ + if (!((bitmap >> i) & 1)) + continue; + /* We can, Now let's assume we can use this IRQ */ + irq = i; + /* And assume we have not yet routed it */ + int already_routed = 0; + /* Have we already routed it ? */ + for(link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) { + if (pirq[link] == irq) { + already_routed = 1; + break; + } + } + /* If it's not yet routed, use it */ + if(!already_routed) + break; + /* But if it was already routed, try the next one */ + continue; + } + /* Now we got our IRQ */ + return irq; +} + +void pirq_route_irqs(unsigned long addr) +{ + int i, intx, num_entries; + unsigned char irq_slot[MAX_INTX_ENTRIES]; + unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]; struct irq_routing_table *pirq_tbl; + memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS); + pirq_tbl = (struct irq_routing_table *)(addr); num_entries = (pirq_tbl->size - 32) / 16; @@ -113,37 +164,26 @@ void pirq_routing_irqs(unsigned long addr) printk(BIOS_DEBUG, "PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn >> 3, pirq_tbl->slots[i].slot); - for (j = 0; j < 4; j++) { + for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) { - int link = pirq_tbl->slots[i].irq[j].link; - int bitmap = pirq_tbl->slots[i].irq[j].bitmap; + int link = pirq_tbl->slots[i].irq[intx].link; + int bitmap = pirq_tbl->slots[i].irq[intx].bitmap; int irq = 0; printk(BIOS_DEBUG, "INT: %c link: %x bitmap: %x ", - 'A' + j, link, bitmap); + 'A' + intx, link, bitmap); - if (!bitmap|| !link || link > 4) { + if (!bitmap|| !link || link > CONFIG_MAX_PIRQ_LINKS) { printk(BIOS_DEBUG, "not routed\n"); - irq_slot[j] = irq; + irq_slot[intx] = irq; continue; } /* yet not routed */ - if (!pirq[link - 1]) { - - for (k = 2; k <= 15; k++) { - - if (!((bitmap >> k) & 1)) - continue; - - irq = k; - - /* yet not routed */ - if (pirq[0] != irq && pirq[1] != irq && pirq[2] != irq && pirq[3] != irq) - break; - } - + if (!pirq[link - 1]) + { + irq = pirq_get_next_free_irq(pirq, bitmap); if (irq) pirq[link - 1] = irq; } @@ -151,7 +191,7 @@ void pirq_routing_irqs(unsigned long addr) irq = pirq[link - 1]; printk(BIOS_DEBUG, "IRQ: %d\n", irq); - irq_slot[j] = irq; + irq_slot[intx] = irq; } /* Bus, device, slots IRQs for {A,B,C,D}. */ @@ -159,10 +199,8 @@ void pirq_routing_irqs(unsigned long addr) pirq_tbl->slots[i].devfn >> 3, irq_slot); } - printk(BIOS_DEBUG, "PIRQ1: %d\n", pirq[0]); - printk(BIOS_DEBUG, "PIRQ2: %d\n", pirq[1]); - printk(BIOS_DEBUG, "PIRQ3: %d\n", pirq[2]); - printk(BIOS_DEBUG, "PIRQ4: %d\n", pirq[3]); + for(i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) + printk(BIOS_DEBUG, "PIRQ%c: %d\n", i + 'A', pirq[i]); pirq_assign_irqs(pirq); } diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h index 08ba535..c5be5f4 100644 --- a/src/arch/x86/include/arch/pirq_routing.h +++ b/src/arch/x86/include/arch/pirq_routing.h @@ -1,6 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2012 Patrick Georgi <patrick(a)georgi-clan.de> + * Copyright (C) 2010 Stefan Reinauer <stepan(a)coreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ #ifndef ARCH_PIRQ_ROUTING_H #define ARCH_PIRQ_ROUTING_H +/* This is the maximum number on interrupt entries that a PCI device may have. + * This is NOT the number of slots or devices in the system + * This is NOT the number of entries in the PIRQ table + * This tells us that in the PIRQ table, we are going to have 4 link-bitmap + * entries per PCI device + * It is fixed at 4: INTA, INTB, INTC, and INTD + * CAUTION: If you change this, pirq_routing will not work correctly*/ +#define MAX_INTX_ENTRIES 4 + #if CONFIG_GENERATE_PIRQ_TABLE #include <stdint.h> @@ -40,10 +69,10 @@ unsigned long copy_pirq_routing_table(unsigned long start); unsigned long write_pirq_routing_table(unsigned long start); #if CONFIG_PIRQ_ROUTE -void pirq_routing_irqs(unsigned long start); -void pirq_assign_irqs(const unsigned char pIntAtoD[4]); +void pirq_route_irqs(unsigned long start); +void pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]); #else -#define pirq_routing_irqs(start) {} +#define pirq_route_irqs(start) {} #endif #else

1 0

drivers/generic/ioapic enable_dev not called
by Rudolf Marek 29 Aug '12

29 Aug '12

Hi all, I'm working on ioapic_irq support on M2V-MX SE. While at it, I wanted to factor out SB and NB ioapic initialization and use the generic ioapic driver. However I never see that code from drivers/generic/ioapic.c is called. I tried various devicetree combinations, but nothing works. I'm out of ideas, possibly this has to do something that I do this on AMD system. My first question is what is the difference between .enable and .enable_dev anyway? I'm pasting here my "simple" devicetree.cb, the commented version does not work either and I get complains that it is left over static device and no PCI device. I think in both cases I got IOAPIC: 09 missing read_resources And enable_dev is never called. I put there a printk. Please can someone sched some light? Thanks Rudolf chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # APIC cluster chip cpu/amd/socket_AM2 # CPU device lapic 0 on end # APIC end end device pci_domain 0 on # PCI domain subsystemid 0x1043 0 inherit chip northbridge/amd/amdk8 # mc0 device pci 18.0 on # Northbridge # Devices on link 0, link 0 == LDT 0 chip southbridge/via/k8t890 # "Southbridge" K8M890 device pci 0.0 on end # HT device pci 0.5 on chip drivers/generic/ioapic register "irq_on_fsb" = "1" register "base" = "0xfecc0000" device ioapic 9 on end end end end #end NB chip end #end LDT0 device pci 18.0 on end #LDT1 device pci 18.0 on end #LDT2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end #mc0 # chip drivers/generic/ioapic # register "irq_on_fsb" = "1" # register "base" = "0xfecc0000" # device ioapic 9 on end # end end #pci_domain end #root complex

2 6

Failed flash recovery & dual BIOS support
by Fred . 29 Aug '12

29 Aug '12

Add support for "dual BIOS" and failed flash recovery. Many motherboards have 2 firmware ICs. Motherboard manufacturers tend to market this as "dual BIOS". It checks the integrity of the BIOS and if it fails the test, then it boots using the other firmware image on the other circuit.

1 0

Patch set updated for coreboot: 92ddf01 pirq_routing: Allow routing with more than 4 PIRQ links
by Alexandru Gagniuc 29 Aug '12

29 Aug '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1482 -gerrit commit 92ddf0152c2b1386f0b18a876728e8bd7106cc9b Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Aug 23 02:32:58 2012 -0500 pirq_routing: Allow routing with more than 4 PIRQ links pirq_routing_irqs assumed that only four links are available for PIRQ routing, INTA to INTD. Some chipsets provide more, up to INTH. When pirq_routing_irqs found a link number greater than 4 in the pirq table, it would not assign that IRQ. This is a shame, as it limits the flexibility of routing IRQs. Make the maximum number of links a Kconfig variable, and modify the code to respect it. This works beatifully on the VX900, which provides 8 routable interrupts. While we're at it, also refactor pirq_routing_irqs, and add some much needed comments. The copyrights added were determined from git log filename. Change-Id: I4b565315404c65b871406f616474e2cc9e6e013e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/Kconfig | 12 ++++ src/arch/x86/boot/pirq_routing.c | 98 ++++++++++++++++++++++---------- src/arch/x86/include/arch/pirq_routing.h | 35 +++++++++++- 3 files changed, 112 insertions(+), 33 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 469266d..e0062dd 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1,6 +1,7 @@ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> ## Copyright (C) 2009-2010 coresystems GmbH ## ## This program is free software; you can redistribute it and/or modify @@ -374,6 +375,17 @@ config HAVE_PIRQ_TABLE Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE. +config MAX_PIRQ_LINKS + int + default 4 + help + This variable specifies the number of PIRQ interrupt links which are + routable. On most chipsets, this is 4, INTA through INTD. Some + chipsets offer more than four links, commonly up to INTH. They may + also have a separate link for ATA or IOAPIC interrupts. When the PIRQ + table specifies links greater than 4, pirq_route_irqs will not + function properly, unless this variable is correctly set. + #These Options are here to avoid "undefined" warnings. #The actual selection and help texts are in the following menu. diff --git a/src/arch/x86/boot/pirq_routing.c b/src/arch/x86/boot/pirq_routing.c index bb8a7b6..5b0a9da 100644 --- a/src/arch/x86/boot/pirq_routing.c +++ b/src/arch/x86/boot/pirq_routing.c @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2010 Stefan Reinauer <stepan(a)coreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ #include <console/console.h> #include <arch/pirq_routing.h> #include <string.h> @@ -92,18 +111,50 @@ unsigned long copy_pirq_routing_table(unsigned long addr) #if CONFIG_DEBUG_PIRQ verify_copy_pirq_routing_table(addr); #endif - pirq_routing_irqs(addr); + pirq_route_irqs(addr); return addr + intel_irq_routing_table.size; } #if CONFIG_PIRQ_ROUTE -void pirq_routing_irqs(unsigned long addr) +static u8 pirq_get_next_free_irq(u8* pirq, u16 bitmap) { - int i, j, k, num_entries; - unsigned char irq_slot[4]; - unsigned char pirq[4] = {0, 0, 0, 0}; + int i, link; + u8 irq = 0; + for (i = 2; i <= 15; i++) + { + /* Can we assign this IRQ ? */ + if (!((bitmap >> i) & 1)) + continue; + /* We can, Now let's assume we can use this IRQ */ + irq = i; + /* And assume we have not yet routed it */ + int already_routed = 0; + /* Have we already routed it ? */ + for(link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) { + if (pirq[link] == irq) { + already_routed = 1; + break; + } + } + /* If it's not yet routed, use it */ + if(!already_routed) + break; + /* But if it was already routed, try the next one */ + continue; + } + /* Now we got our IRQ */ + return irq; +} + +void pirq_route_irqs(unsigned long addr) +{ + int i, intx, num_entries; + unsigned char irq_slot[MAX_INTX_ENTRIES]; + unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]; struct irq_routing_table *pirq_tbl; + memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS); + pirq_tbl = (struct irq_routing_table *)(addr); num_entries = (pirq_tbl->size - 32) / 16; @@ -113,37 +164,26 @@ void pirq_routing_irqs(unsigned long addr) printk(BIOS_DEBUG, "PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn >> 3, pirq_tbl->slots[i].slot); - for (j = 0; j < 4; j++) { + for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) { - int link = pirq_tbl->slots[i].irq[j].link; - int bitmap = pirq_tbl->slots[i].irq[j].bitmap; + int link = pirq_tbl->slots[i].irq[intx].link; + int bitmap = pirq_tbl->slots[i].irq[intx].bitmap; int irq = 0; printk(BIOS_DEBUG, "INT: %c link: %x bitmap: %x ", - 'A' + j, link, bitmap); + 'A' + intx, link, bitmap); - if (!bitmap|| !link || link > 4) { + if (!bitmap|| !link || link > CONFIG_MAX_PIRQ_LINKS) { printk(BIOS_DEBUG, "not routed\n"); - irq_slot[j] = irq; + irq_slot[intx] = irq; continue; } /* yet not routed */ - if (!pirq[link - 1]) { - - for (k = 2; k <= 15; k++) { - - if (!((bitmap >> k) & 1)) - continue; - - irq = k; - - /* yet not routed */ - if (pirq[0] != irq && pirq[1] != irq && pirq[2] != irq && pirq[3] != irq) - break; - } - + if (!pirq[link - 1]) + { + irq = pirq_get_next_free_irq(pirq, bitmap); if (irq) pirq[link - 1] = irq; } @@ -151,7 +191,7 @@ void pirq_routing_irqs(unsigned long addr) irq = pirq[link - 1]; printk(BIOS_DEBUG, "IRQ: %d\n", irq); - irq_slot[j] = irq; + irq_slot[intx] = irq; } /* Bus, device, slots IRQs for {A,B,C,D}. */ @@ -159,10 +199,8 @@ void pirq_routing_irqs(unsigned long addr) pirq_tbl->slots[i].devfn >> 3, irq_slot); } - printk(BIOS_DEBUG, "PIRQ1: %d\n", pirq[0]); - printk(BIOS_DEBUG, "PIRQ2: %d\n", pirq[1]); - printk(BIOS_DEBUG, "PIRQ3: %d\n", pirq[2]); - printk(BIOS_DEBUG, "PIRQ4: %d\n", pirq[3]); + for(i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) + printk(BIOS_DEBUG, "PIRQ%u: %d\n", i + 'A', pirq[i]); pirq_assign_irqs(pirq); } diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h index 08ba535..c5be5f4 100644 --- a/src/arch/x86/include/arch/pirq_routing.h +++ b/src/arch/x86/include/arch/pirq_routing.h @@ -1,6 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2012 Patrick Georgi <patrick(a)georgi-clan.de> + * Copyright (C) 2010 Stefan Reinauer <stepan(a)coreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ #ifndef ARCH_PIRQ_ROUTING_H #define ARCH_PIRQ_ROUTING_H +/* This is the maximum number on interrupt entries that a PCI device may have. + * This is NOT the number of slots or devices in the system + * This is NOT the number of entries in the PIRQ table + * This tells us that in the PIRQ table, we are going to have 4 link-bitmap + * entries per PCI device + * It is fixed at 4: INTA, INTB, INTC, and INTD + * CAUTION: If you change this, pirq_routing will not work correctly*/ +#define MAX_INTX_ENTRIES 4 + #if CONFIG_GENERATE_PIRQ_TABLE #include <stdint.h> @@ -40,10 +69,10 @@ unsigned long copy_pirq_routing_table(unsigned long start); unsigned long write_pirq_routing_table(unsigned long start); #if CONFIG_PIRQ_ROUTE -void pirq_routing_irqs(unsigned long start); -void pirq_assign_irqs(const unsigned char pIntAtoD[4]); +void pirq_route_irqs(unsigned long start); +void pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]); #else -#define pirq_routing_irqs(start) {} +#define pirq_route_irqs(start) {} #endif #else

1 0

Patch merged into coreboot/master: 23204c0 Fix AMD UMA for RS780
by gerrit＠coreboot.org 28 Aug '12

28 Aug '12

the following patch was just integrated into master: commit 23204c0f9fcf0467eca018a63a040aa924eb0453 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Aug 27 20:00:33 2012 +0300 Fix AMD UMA for RS780 In commit 6b5eb1cc2d1702ff10cd02249d3d861c094f9118 setup of UMA memory region was moved to happen at a later state and this broke UMA with RS780 southbridge. Share the TOP_MEM and UMA settings before any of the PCI or CPU scanning takes place. Change-Id: I9cae1fc2948cbccede58d099faf1dfe49e9df303 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Aug 28 08:20:38 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Tue Aug 28 15:38:32 2012, giving +2 Reviewed-By: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> at Tue Aug 28 14:32:52 2012, giving +2 See http://review.coreboot.org/1488 for details. -gerrit

1 0

(help me to get better) flashrom support for thinkpads with locked down opcodes
by Stefan Tauner 28 Aug '12

28 Aug '12

Hi there! As you probably all know the procedure to relieve the coreboot- supported thinkpads from their proprietary firmware is not completely trivial[1]. The main problem is that the vendor has locked down the available SPI opcodes that we are allowed to use and this hinders current flashrom to identify the flash chip. Carl-Daniel has started to work on a patch that allows flashrom to use a lower-quality identifying opcode (RES) on such locked down computers without spoiling flashrom use on other devices. I have continued that and we now have a patch that allows probing and reading on the thinkpads. Erase (and hence write in practice) does not work yet, because the available erase opcodes are also limited, but that will be dealt with shortly(-ish :). The current version of the patch can be found here: http://patchwork.coreboot.org/patch/3726/ I would like to request the help of at least one volunteer who is able to recover from failed flash attempts and is willing to revert to the vendor firmware temporarily and spend some time testing patches we sent him. This will of course not make the coreboot conversion foolproof and is quite late... but i am pretty sure it will still be welcomed by newbies :) Also, i would like to see a flashrom -V log of any affected machine that is not a T60 (2007-GCG)[2] and is running the vendor firmware. [1]: http://www.coreboot.org/Lenovo_x60x [2]: http://paste.flashrom.org/view.php?id=635 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

3 3

Patch merged into coreboot/master: a44ddea AMD hudson: Complete the missing rule
by gerrit＠coreboot.org 28 Aug '12

28 Aug '12

the following patch was just integrated into master: commit a44ddea8b7bf3e78be7a216128ba7bdc9fad0d8c Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Aug 28 12:02:26 2012 +0800 AMD hudson: Complete the missing rule Forgot to change the code back after debugging. Change-Id: Iaf58d65c14d53ca77958080faf6ab85d60992226 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Aug 28 04:37:44 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Tue Aug 28 11:55:31 2012, giving +2 See http://review.coreboot.org/1491 for details. -gerrit

1 0

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coreboot August 2012