coreboot May 2012

coreboot@coreboot.org

31 participants
287 discussions

New patch to review for coreboot: ff0cffa Some more #if cleanup
by Patrick Georgi 05 May '12

05 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1006 -gerrit commit ff0cffa20e8bca8a17ca5ceb283066ade2517732 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat May 5 15:50:17 2012 +0200 Some more #if cleanup Replace #elif (CONFIG_FOO==1) with #elif CONFIG_FOO find src -type f -exec sed -i "s,$#.*$($CONFIG_[A-Z0-9_]*$[[:space:]]*==[[:space:]]1),\1\2,g" {} + (manual tweak since it hit a false positive) Replace #elif (CONFIG_FOO==0) with #elif !CONFIG_FOO find src -type f -exec sed -i "s,$#.*$($CONFIG_[A-Z0-9_]*$[[:space:]]*==[[:space:]]0),\1\!\2,g" {} + Change-Id: I8f4ebf609740dfc53e79d5f1e60f9446364bb07d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/cpu/amd/model_10xxx/init_cpus.c | 6 +++--- src/cpu/amd/model_fxx/init_cpus.c | 2 +- src/cpu/x86/mtrr/earlymtrr.c | 2 +- src/cpu/x86/mtrr/mtrr.c | 2 +- src/northbridge/amd/amdfam10/northbridge.c | 2 +- src/northbridge/amd/amdk8/coherent_ht.c | 10 +++++----- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 10 +++++----- src/southbridge/amd/rs780/gfx.c | 4 ++-- src/southbridge/amd/sr5650/early_setup.c | 6 +++--- 9 files changed, 22 insertions(+), 22 deletions(-) diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index edc016a..e2a4a64 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -111,7 +111,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, i * (nb_cfg_54 ? (siblings + 1) : 1) + j * (nb_cfg_54 ? 1 : 64); -#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0) +#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0) #if !CONFIG_LIFT_BSP_APIC_ID if ((i != 0) || (j != 0)) /* except bsp */ #endif @@ -274,7 +274,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) enable_lapic(); -#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0) +#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0) u32 initial_apicid = get_initial_apicid(); #if !CONFIG_LIFT_BSP_APIC_ID @@ -331,7 +331,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) cpuSetAMDMSR(); #if CONFIG_SET_FIDVID -#if (CONFIG_LOGICAL_CPUS == 1) && CONFIG_SET_FIDVID_CORE0_ONLY +#if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY // Run on all AP for proper FID/VID setup. if (id.coreid == 0) // only need set fid for core0 #endif diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index ed1c830..333f331 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -276,7 +276,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) u32 loop = 100; #if CONFIG_SET_FIDVID -#if (CONFIG_LOGICAL_CPUS == 1) && CONFIG_SET_FIDVID_CORE0_ONLY +#if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY if (id.coreid == 0) // only need set fid for core0 #endif init_fidvid_ap(bsp_apicid, apicid); diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index f8119d3..7a1f51d 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -20,7 +20,7 @@ static void set_var_mtrr( wrmsr(MTRRphysMask_MSR(reg), maskm); } -#if !defined(CONFIG_CACHE_AS_RAM) || (CONFIG_CACHE_AS_RAM == 0) +#if !defined(CONFIG_CACHE_AS_RAM) || !CONFIG_CACHE_AS_RAM static void cache_lbmem(int type) { /* Enable caching for 0 - 1MB using variable mtrr */ diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index c310905..cce526a 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -464,7 +464,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_var_mtrr_resource, &var_state); -#if (CONFIG_GFXUMA == 1) /* UMA or SP. */ +#if CONFIG_GFXUMA /* UMA or SP. */ /* For now we assume the UMA space is at the end of memory below 4GB */ if (var_state.hole_startk || var_state.hole_sizek) { printk(BIOS_DEBUG, "Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n"); diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 0e80c71..3b20684 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1425,7 +1425,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if (cpu) { cpu->path.apic.node_id = i; cpu->path.apic.core_id = j; - #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET>0) + #if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0) if(sysconf.enabled_apic_ext_id) { if(sysconf.lift_bsp_apicid) { cpu->path.apic.apic_id += sysconf.apicid_offset; diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 636114d..9ad3423 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -394,7 +394,7 @@ static uint8_t get_linkn_last(uint8_t byte) } #endif -#if (CONFIG_MAX_PHYSICAL_CPUS > 2) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) +#if (CONFIG_MAX_PHYSICAL_CPUS > 2) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED static uint8_t get_linkn_last_count(uint8_t byte) { byte &= 0x0f; @@ -563,7 +563,7 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif if(diff && (val_s!=(val&0xff)) ) { /* use another connect as response*/ val_s -= val & 0xff; -#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) +#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED uint8_t byte; /* Some node have two links left * don't worry we only have (2, (3 as source need to handle @@ -722,7 +722,7 @@ static unsigned setup_smp2(void) setup_row_local(7,1); setup_remote_row_direct(1, 0, byte); -#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) +#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED val = get_row(7,1); byte = (val>>16) & 0xfe; byte = get_linkn_last_count(byte); @@ -848,7 +848,7 @@ static unsigned setup_smp4(void) setup_temp_row(2,3); verify_connection(7); /* to 3*/ -#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) +#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED /* We need to find out which link is to node3 */ if((byte>>2)==2) { /* one to node3, one to node0, one to node4*/ val = get_row(7,3); @@ -869,7 +869,7 @@ static unsigned setup_smp4(void) print_linkn("(3,2) link=", byte); setup_remote_row_direct(3,2, byte); -#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) +#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED /* set link from 3 to 5 before enable it*/ val = get_row(7,3); byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1); diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 00b1555..2440d2e 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -66,14 +66,14 @@ static u16 mctGet_NVbits(u8 index) case NV_BYPMAX: #if !CONFIG_GFXUMA val = 4; -#elif (CONFIG_GFXUMA == 1) +#elif CONFIG_GFXUMA val = 7; #endif break; case NV_RDWRQBYP: #if !CONFIG_GFXUMA val = 2; -#elif (CONFIG_GFXUMA == 1) +#elif CONFIG_GFXUMA val = 3; #endif break; @@ -115,7 +115,7 @@ static u16 mctGet_NVbits(u8 index) case NV_BurstLen32: #if !CONFIG_GFXUMA val = 0; /* 64 byte mode */ -#elif (CONFIG_GFXUMA == 1) +#elif CONFIG_GFXUMA val = 1; /* 32 byte mode */ #endif break; @@ -134,14 +134,14 @@ static u16 mctGet_NVbits(u8 index) case NV_BottomIO: #if !CONFIG_GFXUMA val = 0xE0; /* address bits [31:24] */ -#elif (CONFIG_GFXUMA == 1) +#elif CONFIG_GFXUMA val = 0xC0; /* address bits [31:24] */ #endif break; case NV_BottomUMA: #if !CONFIG_GFXUMA val = 0xE0; /* address bits [31:24] */ -#elif (CONFIG_GFXUMA == 1) +#elif CONFIG_GFXUMA val = 0xC0; /* address bits [31:24] */ #endif break; diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index e8d4596..e07aa10 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -411,7 +411,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* GFX_InitFBAccess finished. */ -#if (CONFIG_GFXUMA == 1) /* for UMA mode. */ +#if CONFIG_GFXUMA /* for UMA mode. */ /* GFX_StartMC. */ set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000); set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001); @@ -473,7 +473,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) vgainfo.sHeader.ucTableFormatRevision = 1; vgainfo.sHeader.ucTableContentRevision = 2; -#if (CONFIG_GFXUMA == 0) /* SP mode. */ +#if !CONFIG_GFXUMA /* SP mode. */ // Side port support is incomplete, do not use it // These parameters must match the motherboard vgainfo.ulBootUpSidePortClock = 667*100; diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 32bdd7f..0f54ba3 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -51,7 +51,7 @@ static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val) /* family 10 only, for reg > 0xFF */ -#if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1) +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask, u32 val) { @@ -220,7 +220,7 @@ void sr5650_htinit(void) /* Enable Protocol checker */ set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC); -#if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1) /* save some spaces */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 /* save some spaces */ /* HT3 mode, RPR 5.4.3 */ set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0); @@ -270,7 +270,7 @@ void sr5650_htinit(void) } } -#if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1) /* save some spaces */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 /* save some spaces */ void fam10_optimization(void) { device_t cpu_f0, cpu_f2, cpu_f3;

1 0

New patch to review for coreboot: 334222b Add config_enabled() from Linux
by Patrick Georgi 05 May '12

05 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1005 -gerrit commit 334222b6a3e066265c01d00589394efd16ae0f4b Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat May 5 15:11:22 2012 +0200 Add config_enabled() from Linux This change is taken from Linux. It allows to check for Kconfig definitions in the preprocessor and source code using the same idiom. Long term plan is to remove our Kconfig hack to #define values to 0, and this helps. This includes a tiny modification to the macros to fix romcc support. Change-Id: I0fddbea8c8ca215cf226acf39cb329b0ba0445a5 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile.inc | 4 ++-- src/include/kconfig.h | 21 +++++++++++++++++++++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 534b985..01fb41f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -91,7 +91,7 @@ romstage-c-deps:=$$(OPTION_TABLE_H) define ramstage-objs_asl_template $(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" - $(CC) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-y)/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$(a)).asl + $(CC) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-y)/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$(a)).asl cd $$(dir $$@); $(IASL) -p $$(notdir $$@) -tc $$(notdir $$(basename $$(a))).asl mv $$(basename $$(a)).hex $$(basename $$(a)).c $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$(a)).c @@ -154,7 +154,7 @@ endif INCLUDES := -Isrc -Isrc/include -I$(obj) -Isrc/arch/$(ARCHDIR-y)/include INCLUDES += -Isrc/devices/oprom/include # abspath is a workaround for romcc -INCLUDES += -include $(abspath $(obj)/config.h) +INCLUDES += -include $(src)/include/kconfig.h CFLAGS = $(INCLUDES) -Os -pipe -g -nostdinc CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes diff --git a/src/include/kconfig.h b/src/include/kconfig.h new file mode 100644 index 0000000..73106e9 --- /dev/null +++ b/src/include/kconfig.h @@ -0,0 +1,21 @@ +#ifndef __KCONFIG_H__ +#define __KCONFIG_H__ + +#include <config.h> + +/* + * Getting something that works in C and CPP for an arg that may or may + * not be defined is tricky. Here, if we have "#define CONFIG_BOOGER 1" + * we match on the placeholder define, insert the "0," for arg1 and generate + * the triplet (0, 1, 0). Then the last step cherry picks the 2nd arg (a one). + * When CONFIG_BOOGER is not defined, we generate a (... 1, 0) pair, and when + * the last step cherry picks the 2nd arg, we get a zero. + */ +#define __ARG_PLACEHOLDER_1 0, +#define config_enabled(cfg) _config_enabled(cfg) +#define _config_enabled(value) __config_enabled(__ARG_PLACEHOLDER_##value) +#define __config_enabled(arg1_or_junk) ___config_enabled(arg1_or_junk 1, 0, 0) +#define ___config_enabled(__ignored, val, ...) val + +#define IS_ENABLED(option) config_enabled(option) +#endif

1 0

New patch to review for coreboot: a683bce Clean up #ifs
by Patrick Georgi 05 May '12

05 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1004 -gerrit commit a683bce1f9db7f5fc57daf613572a73d80412cc3 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat May 5 15:29:32 2012 +0200 Clean up #ifs Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*$CONFIG_[A-Z0-9_]*$[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*($CONFIG_[A-Z0-9_]*$[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*$CONFIG_[A-Z0-9_]*$[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*($CONFIG_[A-Z0-9_]*$[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/boot/acpi.c | 2 +- src/arch/x86/boot/coreboot_table.c | 2 +- src/arch/x86/boot/tables.c | 6 +- src/arch/x86/include/arch/acpi.h | 2 +- src/arch/x86/include/arch/pci_ops.h | 2 +- src/arch/x86/include/arch/pciconf.h | 2 +- src/arch/x86/include/arch/pirq_routing.h | 4 +- src/arch/x86/include/arch/romcc_io.h | 12 ++-- src/arch/x86/lib/cbfs_and_run.c | 2 +- src/arch/x86/lib/exception.c | 2 +- src/arch/x86/lib/pci_ops_conf1.c | 2 +- src/boot/hardwaremain.c | 4 +- src/cpu/amd/agesa/family10/model_10_init.c | 4 +- src/cpu/amd/agesa/family12/model_12_init.c | 4 +- src/cpu/amd/agesa/family14/model_14_init.c | 6 +- src/cpu/amd/agesa/family15/model_15_init.c | 4 +- src/cpu/amd/car/post_cache_as_ram.c | 12 ++-- src/cpu/amd/dualcore/dualcore.c | 2 +- src/cpu/amd/model_10xxx/init_cpus.c | 10 ++-- src/cpu/amd/model_10xxx/model_10xxx_init.c | 4 +- src/cpu/amd/model_fxx/init_cpus.c | 16 +++--- src/cpu/amd/model_fxx/model_fxx_init.c | 22 ++++---- src/cpu/amd/model_fxx/model_fxx_update_microcode.c | 8 ++-- src/cpu/amd/model_fxx/powernow_acpi.c | 2 +- src/cpu/amd/model_fxx/processor_name.c | 12 ++-- src/cpu/amd/mtrr/amd_mtrr.c | 4 +- src/cpu/intel/hyperthreading/intel_sibling.c | 2 +- src/cpu/x86/lapic/lapic_cpu_init.c | 26 +++++----- src/devices/device.c | 8 ++-- src/devices/hypertransport.c | 6 +- src/devices/pci_device.c | 26 +++++----- src/devices/pci_rom.c | 2 +- src/drivers/ati/ragexl/atyfb.h | 6 +- src/drivers/ati/ragexl/mach64_ct.c | 2 +- src/drivers/ati/ragexl/xlinit.c | 18 +++--- src/include/cpu/amd/model_fxx_rev.h | 4 +- src/include/cpu/x86/lapic.h | 2 +- src/include/delay.h | 2 +- src/include/reset.h | 2 +- src/include/smp/atomic.h | 2 +- src/include/smp/spinlock.h | 2 +- src/include/watchdog.h | 2 +- src/mainboard/advansus/a785e-i/acpi_tables.c | 2 +- src/mainboard/advansus/a785e-i/get_bus_conf.c | 4 +- src/mainboard/advansus/a785e-i/mainboard.c | 4 +- src/mainboard/advansus/a785e-i/mptable.c | 2 +- src/mainboard/advansus/a785e-i/platform_cfg.h | 2 +- src/mainboard/advansus/a785e-i/romstage.c | 4 +- src/mainboard/amd/bimini_fam10/get_bus_conf.c | 4 +- src/mainboard/amd/bimini_fam10/mainboard.c | 4 +- src/mainboard/amd/bimini_fam10/mptable.c | 2 +- src/mainboard/amd/bimini_fam10/romstage.c | 2 +- src/mainboard/amd/dbm690t/get_bus_conf.c | 4 +- src/mainboard/amd/dbm690t/mainboard.c | 4 +- src/mainboard/amd/dbm690t/mptable.c | 2 +- src/mainboard/amd/dbm690t/romstage.c | 2 +- src/mainboard/amd/dinar/mainboard.c | 4 +- src/mainboard/amd/dinar/rd890_cfg.h | 4 +- src/mainboard/amd/dinar/sb700_cfg.h | 2 +- src/mainboard/amd/inagua/mainboard.c | 4 +- src/mainboard/amd/inagua/mptable.c | 2 +- src/mainboard/amd/inagua/platform_cfg.h | 2 +- src/mainboard/amd/mahogany/get_bus_conf.c | 4 +- src/mainboard/amd/mahogany/mainboard.c | 4 +- src/mainboard/amd/mahogany/mptable.c | 2 +- src/mainboard/amd/mahogany/romstage.c | 2 +- src/mainboard/amd/mahogany_fam10/get_bus_conf.c | 4 +- src/mainboard/amd/mahogany_fam10/mainboard.c | 4 +- src/mainboard/amd/mahogany_fam10/mptable.c | 2 +- src/mainboard/amd/mahogany_fam10/romstage.c | 2 +- src/mainboard/amd/persimmon/agesawrapper.c | 2 +- src/mainboard/amd/persimmon/get_bus_conf.c | 4 +- src/mainboard/amd/persimmon/mainboard.c | 6 +- src/mainboard/amd/persimmon/mptable.c | 2 +- src/mainboard/amd/persimmon/platform_cfg.h | 2 +- src/mainboard/amd/persimmon/romstage.c | 6 +- src/mainboard/amd/pistachio/get_bus_conf.c | 4 +- src/mainboard/amd/pistachio/mainboard.c | 4 +- src/mainboard/amd/pistachio/mptable.c | 2 +- src/mainboard/amd/pistachio/romstage.c | 2 +- src/mainboard/amd/serengeti_cheetah/get_bus_conf.c | 4 +- src/mainboard/amd/serengeti_cheetah/mptable.c | 2 +- src/mainboard/amd/serengeti_cheetah/romstage.c | 6 +- .../amd/serengeti_cheetah_fam10/get_bus_conf.c | 2 +- .../amd/serengeti_cheetah_fam10/mptable.c | 2 +- .../amd/serengeti_cheetah_fam10/romstage.c | 2 +- src/mainboard/amd/south_station/mainboard.c | 4 +- src/mainboard/amd/south_station/mptable.c | 2 +- src/mainboard/amd/south_station/platform_cfg.h | 2 +- src/mainboard/amd/tilapia_fam10/get_bus_conf.c | 4 +- src/mainboard/amd/tilapia_fam10/mainboard.c | 4 +- src/mainboard/amd/tilapia_fam10/mptable.c | 2 +- src/mainboard/amd/tilapia_fam10/romstage.c | 2 +- src/mainboard/amd/torpedo/Oem.h | 2 +- src/mainboard/amd/torpedo/mainboard.c | 4 +- src/mainboard/amd/torpedo/mptable.c | 2 +- src/mainboard/amd/torpedo/platform_cfg.h | 6 +- src/mainboard/amd/union_station/mainboard.c | 4 +- src/mainboard/amd/union_station/mptable.c | 2 +- src/mainboard/amd/union_station/platform_cfg.h | 2 +- src/mainboard/arima/hdama/romstage.c | 2 +- src/mainboard/asrock/939a785gmh/get_bus_conf.c | 4 +- src/mainboard/asrock/939a785gmh/mainboard.c | 4 +- src/mainboard/asrock/939a785gmh/mptable.c | 2 +- src/mainboard/asrock/939a785gmh/romstage.c | 2 +- src/mainboard/asrock/e350m1/mainboard.c | 4 +- src/mainboard/asrock/e350m1/mptable.c | 2 +- src/mainboard/asrock/e350m1/platform_cfg.h | 2 +- src/mainboard/asus/a8n_e/get_bus_conf.c | 4 +- src/mainboard/asus/a8n_e/romstage.c | 2 +- src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +- src/mainboard/asus/a8v-e_se/romstage.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 2 +- src/mainboard/asus/m2n-e/get_bus_conf.c | 4 +- src/mainboard/asus/m2n-e/romstage.c | 6 +- src/mainboard/asus/m2v-mx_se/mainboard.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 4 +- src/mainboard/asus/m2v/romstage.c | 4 +- src/mainboard/asus/m4a78-em/get_bus_conf.c | 4 +- src/mainboard/asus/m4a78-em/mainboard.c | 2 +- src/mainboard/asus/m4a78-em/mptable.c | 2 +- src/mainboard/asus/m4a78-em/romstage.c | 2 +- src/mainboard/asus/m4a785-m/get_bus_conf.c | 4 +- src/mainboard/asus/m4a785-m/mainboard.c | 2 +- src/mainboard/asus/m4a785-m/mptable.c | 2 +- src/mainboard/asus/m4a785-m/romstage.c | 2 +- src/mainboard/asus/m5a88-v/acpi_tables.c | 2 +- src/mainboard/asus/m5a88-v/get_bus_conf.c | 4 +- src/mainboard/asus/m5a88-v/mainboard.c | 4 +- src/mainboard/asus/m5a88-v/mptable.c | 2 +- src/mainboard/asus/m5a88-v/platform_cfg.h | 2 +- src/mainboard/asus/m5a88-v/romstage.c | 4 +- src/mainboard/avalue/eax-785e/acpi_tables.c | 2 +- src/mainboard/avalue/eax-785e/get_bus_conf.c | 8 ++-- src/mainboard/avalue/eax-785e/mainboard.c | 4 +- src/mainboard/avalue/eax-785e/mptable.c | 2 +- src/mainboard/avalue/eax-785e/platform_cfg.h | 2 +- src/mainboard/avalue/eax-785e/romstage.c | 4 +- src/mainboard/broadcom/blast/get_bus_conf.c | 4 +- src/mainboard/broadcom/blast/mptable.c | 2 +- src/mainboard/broadcom/blast/romstage.c | 2 +- src/mainboard/emulation/qemu-x86/northbridge.c | 4 +- src/mainboard/getac/p470/romstage.c | 2 +- src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c | 4 +- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 6 +- src/mainboard/gigabyte/m57sli/get_bus_conf.c | 4 +- src/mainboard/gigabyte/m57sli/romstage.c | 6 +- src/mainboard/gigabyte/ma785gm/get_bus_conf.c | 4 +- src/mainboard/gigabyte/ma785gm/mainboard.c | 4 +- src/mainboard/gigabyte/ma785gm/mptable.c | 2 +- src/mainboard/gigabyte/ma785gm/romstage.c | 2 +- src/mainboard/gigabyte/ma785gmt/get_bus_conf.c | 4 +- src/mainboard/gigabyte/ma785gmt/mainboard.c | 4 +- src/mainboard/gigabyte/ma785gmt/mptable.c | 2 +- src/mainboard/gigabyte/ma785gmt/romstage.c | 2 +- src/mainboard/gigabyte/ma78gm/get_bus_conf.c | 4 +- src/mainboard/gigabyte/ma78gm/mainboard.c | 4 +- src/mainboard/gigabyte/ma78gm/mptable.c | 2 +- src/mainboard/gigabyte/ma78gm/romstage.c | 2 +- src/mainboard/hp/dl145_g1/get_bus_conf.c | 4 +- src/mainboard/hp/dl145_g1/romstage.c | 4 +- src/mainboard/hp/dl145_g3/get_bus_conf.c | 4 +- src/mainboard/hp/dl145_g3/mptable.c | 2 +- src/mainboard/hp/dl145_g3/romstage.c | 6 +- src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c | 2 +- src/mainboard/hp/dl165_g6_fam10/mptable.c | 2 +- src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +- src/mainboard/ibm/e325/romstage.c | 2 +- src/mainboard/ibm/e326/romstage.c | 2 +- src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c | 4 +- src/mainboard/iei/kino-780am2-fam10/mainboard.c | 4 +- src/mainboard/iei/kino-780am2-fam10/mptable.c | 2 +- src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 +- src/mainboard/intel/eagleheights/fadt.c | 2 +- src/mainboard/iwill/dk8_htx/get_bus_conf.c | 4 +- src/mainboard/iwill/dk8_htx/mptable.c | 2 +- src/mainboard/iwill/dk8_htx/romstage.c | 6 +- src/mainboard/iwill/dk8s2/romstage.c | 6 +- src/mainboard/iwill/dk8x/romstage.c | 6 +- src/mainboard/jetway/pa78vm5/get_bus_conf.c | 4 +- src/mainboard/jetway/pa78vm5/mainboard.c | 4 +- src/mainboard/jetway/pa78vm5/mptable.c | 2 +- src/mainboard/jetway/pa78vm5/romstage.c | 2 +- src/mainboard/kontron/kt690/get_bus_conf.c | 4 +- src/mainboard/kontron/kt690/mainboard.c | 4 +- src/mainboard/kontron/kt690/mptable.c | 2 +- src/mainboard/kontron/kt690/romstage.c | 2 +- src/mainboard/msi/ms7135/get_bus_conf.c | 4 +- src/mainboard/msi/ms7135/romstage.c | 2 +- src/mainboard/msi/ms7260/get_bus_conf.c | 4 +- src/mainboard/msi/ms7260/romstage.c | 6 +- src/mainboard/msi/ms9185/get_bus_conf.c | 4 +- src/mainboard/msi/ms9185/mptable.c | 2 +- src/mainboard/msi/ms9185/romstage.c | 2 +- src/mainboard/msi/ms9282/get_bus_conf.c | 4 +- src/mainboard/msi/ms9282/romstage.c | 2 +- src/mainboard/msi/ms9652_fam10/get_bus_conf.c | 4 +- src/mainboard/msi/ms9652_fam10/romstage.c | 2 +- src/mainboard/newisys/khepri/romstage.c | 2 +- src/mainboard/nvidia/l1_2pvv/get_bus_conf.c | 4 +- src/mainboard/nvidia/l1_2pvv/romstage.c | 6 +- src/mainboard/siemens/sitemp_g1p1/acpi_tables.c | 2 +- src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c | 4 +- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 8 ++-- src/mainboard/siemens/sitemp_g1p1/romstage.c | 2 +- src/mainboard/sunw/ultra40/get_bus_conf.c | 4 +- src/mainboard/sunw/ultra40/romstage.c | 2 +- src/mainboard/supermicro/h8dme/get_bus_conf.c | 4 +- src/mainboard/supermicro/h8dme/romstage.c | 6 +- src/mainboard/supermicro/h8dmr/get_bus_conf.c | 4 +- src/mainboard/supermicro/h8dmr/romstage.c | 6 +- .../supermicro/h8dmr_fam10/get_bus_conf.c | 4 +- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 +- src/mainboard/supermicro/h8qgi/buildOpts.c | 6 +- src/mainboard/supermicro/h8qgi/mainboard.c | 2 +- src/mainboard/supermicro/h8qgi/rd890_cfg.h | 4 +- src/mainboard/supermicro/h8qgi/sb700_cfg.h | 2 +- .../supermicro/h8qme_fam10/get_bus_conf.c | 4 +- src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 +- .../supermicro/h8scm_fam10/get_bus_conf.c | 4 +- src/mainboard/supermicro/h8scm_fam10/mainboard.c | 2 +- src/mainboard/supermicro/h8scm_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 +- src/mainboard/technexion/tim5690/get_bus_conf.c | 4 +- src/mainboard/technexion/tim5690/mainboard.c | 4 +- src/mainboard/technexion/tim5690/mptable.c | 2 +- src/mainboard/technexion/tim5690/romstage.c | 2 +- src/mainboard/technexion/tim8690/get_bus_conf.c | 4 +- src/mainboard/technexion/tim8690/mainboard.c | 4 +- src/mainboard/technexion/tim8690/mptable.c | 2 +- src/mainboard/technexion/tim8690/romstage.c | 2 +- src/mainboard/tyan/s2850/mptable.c | 4 +- src/mainboard/tyan/s2850/romstage.c | 2 +- src/mainboard/tyan/s2875/mptable.c | 4 +- src/mainboard/tyan/s2875/romstage.c | 2 +- src/mainboard/tyan/s2880/mptable.c | 4 +- src/mainboard/tyan/s2880/romstage.c | 2 +- src/mainboard/tyan/s2881/get_bus_conf.c | 4 +- src/mainboard/tyan/s2881/romstage.c | 2 +- src/mainboard/tyan/s2882/mptable.c | 4 +- src/mainboard/tyan/s2882/romstage.c | 2 +- src/mainboard/tyan/s2885/get_bus_conf.c | 4 +- src/mainboard/tyan/s2885/romstage.c | 2 +- src/mainboard/tyan/s2891/get_bus_conf.c | 4 +- src/mainboard/tyan/s2891/romstage.c | 2 +- src/mainboard/tyan/s2892/get_bus_conf.c | 4 +- src/mainboard/tyan/s2892/romstage.c | 2 +- src/mainboard/tyan/s2895/get_bus_conf.c | 4 +- src/mainboard/tyan/s2912/get_bus_conf.c | 4 +- src/mainboard/tyan/s2912/romstage.c | 6 +- src/mainboard/tyan/s2912_fam10/get_bus_conf.c | 4 +- src/mainboard/tyan/s2912_fam10/romstage.c | 2 +- src/mainboard/tyan/s4880/mptable.c | 4 +- src/mainboard/tyan/s4880/romstage.c | 2 +- src/mainboard/tyan/s4882/mptable.c | 4 +- src/mainboard/tyan/s4882/romstage.c | 2 +- src/mainboard/via/epia-n/mainboard.c | 2 +- src/northbridge/amd/agesa/family10/northbridge.c | 38 +++++++------- src/northbridge/amd/agesa/family12/northbridge.c | 24 ++++---- src/northbridge/amd/agesa/family14/northbridge.c | 24 ++++---- src/northbridge/amd/agesa/family15/northbridge.c | 24 ++++---- src/northbridge/amd/amdfam10/amdfam10.h | 8 ++-- src/northbridge/amd/amdfam10/conf.c | 10 ++-- src/northbridge/amd/amdfam10/debug.c | 2 +- src/northbridge/amd/amdfam10/early_ht.c | 4 +- src/northbridge/amd/amdfam10/northbridge.c | 54 ++++++++++---------- src/northbridge/amd/amdfam10/reset_test.c | 2 +- src/northbridge/amd/amdht/ht_wrapper.c | 2 +- src/northbridge/amd/amdk8/amdk8.h | 2 +- src/northbridge/amd/amdk8/coherent_ht.c | 24 ++++---- src/northbridge/amd/amdk8/debug.c | 2 +- src/northbridge/amd/amdk8/incoherent_ht.c | 12 ++-- src/northbridge/amd/amdk8/misc_control.c | 2 +- src/northbridge/amd/amdk8/northbridge.c | 42 ++++++++-------- src/northbridge/amd/amdk8/raminit.c | 4 +- src/northbridge/amd/amdk8/raminit_f.c | 10 ++-- src/northbridge/amd/amdk8/raminit_f_dqs.c | 22 ++++---- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 10 ++-- src/northbridge/amd/gx1/northbridge.c | 4 +- src/northbridge/amd/gx2/northbridge.c | 4 +- src/northbridge/amd/lx/northbridge.c | 4 +- src/northbridge/intel/e7501/northbridge.c | 4 +- src/northbridge/intel/e7505/northbridge.c | 4 +- src/northbridge/intel/e7520/northbridge.c | 4 +- src/northbridge/intel/e7525/northbridge.c | 4 +- src/northbridge/intel/i3100/northbridge.c | 4 +- src/northbridge/intel/i3100/raminit.c | 2 +- src/northbridge/intel/i440bx/northbridge.c | 4 +- src/northbridge/intel/i440lx/northbridge.c | 4 +- src/northbridge/intel/i82810/northbridge.c | 4 +- src/northbridge/intel/i82830/northbridge.c | 4 +- src/northbridge/intel/i855/northbridge.c | 4 +- src/northbridge/intel/i945/northbridge.c | 4 +- src/northbridge/intel/sandybridge/northbridge.c | 4 +- src/northbridge/intel/sch/northbridge.c | 4 +- src/northbridge/rdc/r8610/northbridge.c | 4 +- src/northbridge/via/cn400/northbridge.c | 4 +- src/northbridge/via/cn700/northbridge.c | 4 +- src/northbridge/via/cx700/northbridge.c | 4 +- src/northbridge/via/vt8601/northbridge.c | 4 +- src/northbridge/via/vt8623/northbridge.c | 4 +- src/northbridge/via/vx800/examples/chipset_init.c | 4 +- src/southbridge/amd/amd8111/acpi.c | 4 +- src/southbridge/amd/cimx/sb700/bootblock.c | 2 +- src/southbridge/amd/cimx/sb700/early.c | 2 +- src/southbridge/amd/cimx/sb700/sb_cimx.h | 2 +- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 2 +- src/southbridge/amd/cimx/sb800/cfg.c | 4 +- src/southbridge/amd/cimx/sb800/early.c | 4 +- src/southbridge/amd/cimx/sb800/late.c | 4 +- src/southbridge/amd/cimx/sb800/sb_cimx.h | 2 +- src/southbridge/amd/cimx/sb900/bootblock.c | 2 +- src/southbridge/amd/cs5530/vga.c | 4 +- src/southbridge/amd/rs690/ht.c | 6 +- src/southbridge/amd/rs780/early_setup.c | 2 +- src/southbridge/amd/rs780/gfx.c | 6 +- src/southbridge/amd/rs780/rs780.c | 2 +- src/southbridge/amd/sb600/ide.c | 2 +- src/southbridge/amd/sb700/early_setup.c | 2 +- src/southbridge/amd/sb700/ide.c | 2 +- src/southbridge/amd/sb700/lpc.c | 2 +- src/southbridge/amd/sb700/sb700.h | 2 +- src/southbridge/amd/sb800/early_setup.c | 2 +- src/southbridge/amd/sb800/ide.c | 2 +- src/southbridge/broadcom/bcm5780/nic.c | 2 +- src/southbridge/intel/i82371eb/smbus.c | 4 +- src/southbridge/nvidia/ck804/early_setup.c | 2 +- src/southbridge/nvidia/ck804/early_setup_car.c | 2 +- src/southbridge/nvidia/ck804/ide.c | 2 +- src/southbridge/nvidia/ck804/nic.c | 2 +- src/southbridge/nvidia/mcp55/ide.c | 2 +- src/southbridge/nvidia/mcp55/nic.c | 2 +- src/southbridge/nvidia/mcp55/smbus.c | 4 +- src/southbridge/sis/sis966/ide.c | 2 +- src/southbridge/via/vt8237r/early_smbus.c | 2 +- src/southbridge/via/vt8237r/lpc.c | 2 +- src/superio/via/vt1211/vt1211.c | 2 +- 337 files changed, 729 insertions(+), 729 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 010ba9f..6932208 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -550,7 +550,7 @@ void acpi_write_hest(acpi_hest_t *hest) header->checksum = acpi_checksum((void *)hest, header->length); } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME void suspend_resume(void) { void *wake_vec; diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index 9ceca45..5b5834a 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -324,7 +324,7 @@ static void lb_strings(struct lb_header *header) } -#if CONFIG_WRITE_HIGH_TABLES == 1 +#if CONFIG_WRITE_HIGH_TABLES static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) { struct lb_record *rec; diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 4fefc7d..72aa979 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -71,7 +71,7 @@ struct lb_memory *write_tables(void) low_table_start = 0; low_table_end = 0x500; -#if CONFIG_GENERATE_PIRQ_TABLE == 1 +#if CONFIG_GENERATE_PIRQ_TABLE #define MAX_PIRQ_TABLE_SIZE (4 * 1024) post_code(0x9a); @@ -97,7 +97,7 @@ struct lb_memory *write_tables(void) #endif -#if CONFIG_GENERATE_MP_TABLE == 1 +#if CONFIG_GENERATE_MP_TABLE #define MAX_MP_TABLE_SIZE (4 * 1024) post_code(0x9b); @@ -120,7 +120,7 @@ struct lb_memory *write_tables(void) } #endif /* CONFIG_GENERATE_MP_TABLE */ -#if CONFIG_GENERATE_ACPI_TABLES == 1 +#if CONFIG_GENERATE_ACPI_TABLES #define MAX_ACPI_SIZE (45 * 1024) post_code(0x9c); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index be62008..9f790cc 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -27,7 +27,7 @@ #ifndef __ASM_ACPI_H #define __ASM_ACPI_H -#if CONFIG_GENERATE_ACPI_TABLES==1 +#if CONFIG_GENERATE_ACPI_TABLES #include <stdint.h> diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index 9c4e029..955ccd3 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -4,7 +4,7 @@ extern const struct pci_bus_operations pci_cf8_conf1; extern const struct pci_bus_operations pci_cf8_conf2; -#if CONFIG_MMCONF_SUPPORT==1 +#if CONFIG_MMCONF_SUPPORT extern const struct pci_bus_operations pci_ops_mmconf; #endif diff --git a/src/arch/x86/include/arch/pciconf.h b/src/arch/x86/include/arch/pciconf.h index a356935..df21817 100644 --- a/src/arch/x86/include/arch/pciconf.h +++ b/src/arch/x86/include/arch/pciconf.h @@ -5,7 +5,7 @@ #define PCI_CONF_REG_INDEX 0xcf8 #define PCI_CONF_REG_DATA 0xcfc -#if CONFIG_PCI_IO_CFG_EXT == 0 +#if !CONFIG_PCI_IO_CFG_EXT #define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where)) #else #define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where & 0xff) | ((where & 0xf00)<<16) ) diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h index 0b65eac..08ba535 100644 --- a/src/arch/x86/include/arch/pirq_routing.h +++ b/src/arch/x86/include/arch/pirq_routing.h @@ -1,7 +1,7 @@ #ifndef ARCH_PIRQ_ROUTING_H #define ARCH_PIRQ_ROUTING_H -#if CONFIG_GENERATE_PIRQ_TABLE==1 +#if CONFIG_GENERATE_PIRQ_TABLE #include <stdint.h> #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) @@ -39,7 +39,7 @@ extern const struct irq_routing_table intel_irq_routing_table; unsigned long copy_pirq_routing_table(unsigned long start); unsigned long write_pirq_routing_table(unsigned long start); -#if CONFIG_PIRQ_ROUTE==1 +#if CONFIG_PIRQ_ROUTE void pirq_routing_irqs(unsigned long start); void pirq_assign_irqs(const unsigned char pIntAtoD[4]); #else diff --git a/src/arch/x86/include/arch/romcc_io.h b/src/arch/x86/include/arch/romcc_io.h index b0c8f65..37fb7ab 100644 --- a/src/arch/x86/include/arch/romcc_io.h +++ b/src/arch/x86/include/arch/romcc_io.h @@ -65,7 +65,7 @@ typedef unsigned device_t; /* pci and pci_mmio need to have different ways to ha static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where) { unsigned addr; -#if CONFIG_PCI_IO_CFG_EXT == 0 +#if !CONFIG_PCI_IO_CFG_EXT addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 @@ -94,7 +94,7 @@ static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t d static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where) { unsigned addr; -#if CONFIG_PCI_IO_CFG_EXT == 0 +#if !CONFIG_PCI_IO_CFG_EXT addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); @@ -125,7 +125,7 @@ static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where) { unsigned addr; -#if CONFIG_PCI_IO_CFG_EXT == 0 +#if !CONFIG_PCI_IO_CFG_EXT addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); @@ -155,7 +155,7 @@ static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) { unsigned addr; -#if CONFIG_PCI_IO_CFG_EXT == 0 +#if !CONFIG_PCI_IO_CFG_EXT addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); @@ -186,7 +186,7 @@ static inline __attribute__((always_inline)) void pci_write_config8(device_t dev static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) { unsigned addr; -#if CONFIG_PCI_IO_CFG_EXT == 0 +#if !CONFIG_PCI_IO_CFG_EXT addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); @@ -217,7 +217,7 @@ static inline __attribute__((always_inline)) void pci_write_config16(device_t de static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) { unsigned addr; -#if CONFIG_PCI_IO_CFG_EXT == 0 +#if !CONFIG_PCI_IO_CFG_EXT addr = (dev>>4) | where; #else addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index 53f06ee..62b2789 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -50,7 +50,7 @@ void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset) cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset); } -#if CONFIG_AP_CODE_IN_CAR == 1 +#if CONFIG_AP_CODE_IN_CAR void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr) { cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ap", ret_addr); diff --git a/src/arch/x86/lib/exception.c b/src/arch/x86/lib/exception.c index 91525d5..4721bc8 100644 --- a/src/arch/x86/lib/exception.c +++ b/src/arch/x86/lib/exception.c @@ -365,7 +365,7 @@ void x86_exception(struct eregs *info); void x86_exception(struct eregs *info) { -#if CONFIG_GDB_STUB == 1 +#if CONFIG_GDB_STUB int signo; memcpy(gdb_stub_registers, info, 8*sizeof(uint32_t)); gdb_stub_registers[PC] = info->eip; diff --git a/src/arch/x86/lib/pci_ops_conf1.c b/src/arch/x86/lib/pci_ops_conf1.c index 266a9cc..77df4b3 100644 --- a/src/arch/x86/lib/pci_ops_conf1.c +++ b/src/arch/x86/lib/pci_ops_conf1.c @@ -8,7 +8,7 @@ * Functions for accessing PCI configuration space with type 1 accesses */ -#if CONFIG_PCI_IO_CFG_EXT == 0 +#if !CONFIG_PCI_IO_CFG_EXT #define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | \ (devfn << 8) | (where & ~3)) #else diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 532135f..f0853ec 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -113,13 +113,13 @@ void hardwaremain(int boot_complete) timestamps[5] = rdtsc(); #endif -#if CONFIG_WRITE_HIGH_TABLES == 1 +#if CONFIG_WRITE_HIGH_TABLES cbmem_initialize(); #if CONFIG_CONSOLE_CBMEM cbmemc_reinit(); #endif #endif -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME suspend_resume(); post_code(0x8a); #endif diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c index 8c1cfad..c216a81 100644 --- a/src/cpu/amd/agesa/family10/model_10_init.c +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -61,7 +61,7 @@ static void model_10_init(device_t dev) u8 i; msr_t msr; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS u32 siblings; #endif @@ -88,7 +88,7 @@ static void model_10_init(device_t dev) // init_processor_name(); -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 3a12db3..4ed477c 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -63,7 +63,7 @@ static void model_12_init(device_t dev) u8 i; msr_t msr; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS u32 siblings; #endif @@ -94,7 +94,7 @@ static void model_12_init(device_t dev) // init_processor_name(); -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index d90695a..9cc36e2 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -61,7 +61,7 @@ static void model_14_init(device_t dev) { u32 i; msr_t msr; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS u32 siblings; #endif printk(BIOS_DEBUG, "Model 14 Init.\n"); @@ -94,7 +94,7 @@ static void model_14_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME if (acpi_slp_type == 3) restore_mtrr(); #endif @@ -112,7 +112,7 @@ static void model_14_init(device_t dev) /* Enable the local cpu apics */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c index d100338..39775ba 100644 --- a/src/cpu/amd/agesa/family15/model_15_init.c +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -59,7 +59,7 @@ static void model_15_init(device_t dev) u8 i; msr_t msr; int msrno; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS u32 siblings; #endif @@ -95,7 +95,7 @@ static void model_15_init(device_t dev) /* Enable the local cpu apics */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 270c542..d99be48 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -29,7 +29,7 @@ static void inline __attribute__((always_inline)) memcopy(void *dest, const voi : "memory", "cc"); } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME static inline void *backup_resume(void) { unsigned long high_ram_base; @@ -83,7 +83,7 @@ static void vErrata343(void) static void post_cache_as_ram(void) { -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif #if 1 @@ -108,7 +108,7 @@ static void post_cache_as_ram(void) #error "You need to set CONFIG_RAMTOP greater than 1M" #endif -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME resume_backup_memory = backup_resume(); #endif @@ -142,7 +142,7 @@ static void post_cache_as_ram(void) set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME /* now copy the rest of the area, using the WB method because we already run normal RAM */ if (resume_backup_memory) { @@ -154,7 +154,7 @@ static void post_cache_as_ram(void) print_debug("Clearing initial memory region: "); -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); #else @@ -164,7 +164,7 @@ static void post_cache_as_ram(void) set_sysinfo_in_ram(1); // So other core0 could start to train mem -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ // struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // wait for ap memory to trained diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 9c2583f..69ce56a 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -17,7 +17,7 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid) static inline uint8_t set_apicid_cpuid_lo(void) { -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set #endif diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index e0538af..edc016a 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -33,7 +33,7 @@ static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); void cpuSetAMDMSR(void); -#if CONFIG_PCI_IO_CFG_EXT == 1 +#if CONFIG_PCI_IO_CFG_EXT static void set_EnableCf8ExtCfg(void) { // set the NB_CFG[46]=1; @@ -112,7 +112,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, j * (nb_cfg_54 ? 1 : 64); #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0) -#if CONFIG_LIFT_BSP_APIC_ID == 0 +#if !CONFIG_LIFT_BSP_APIC_ID if ((i != 0) || (j != 0)) /* except bsp */ #endif ap_apicid += CONFIG_APIC_ID_OFFSET; @@ -267,7 +267,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) if (id.coreid == 0) { set_apicid_cpuid_lo(); /* only set it on core0 */ set_EnableCf8ExtCfg(); /* only set it on core0 */ -#if (CONFIG_ENABLE_APIC_EXT_ID == 1) +#if CONFIG_ENABLE_APIC_EXT_ID enable_apic_ext_id(id.nodeid); #endif } @@ -277,7 +277,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0) u32 initial_apicid = get_initial_apicid(); -#if CONFIG_LIFT_BSP_APIC_ID == 0 +#if !CONFIG_LIFT_BSP_APIC_ID if (initial_apicid != 0) // other than bsp #endif { @@ -289,7 +289,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) lapic_write(LAPIC_ID, dword); } -#if CONFIG_LIFT_BSP_APIC_ID == 1 +#if CONFIG_LIFT_BSP_APIC_ID bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index cf11135..27f56c2 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -63,7 +63,7 @@ static void model_10xxx_init(device_t dev) u8 i; msr_t msr; struct node_core_id id; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS u32 siblings; #endif @@ -92,7 +92,7 @@ static void model_10xxx_init(device_t dev) /* Set the processor name string */ init_processor_name(); -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 0036277..ed1c830 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -40,7 +40,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, 3); if (nb_cfg_54) { if (j == 0) { // if it is single core, we need to increase siblings for apic calculation -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT e0_later_single_core = is_e0_later_in_bsp(i); // single core #else e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 @@ -72,8 +72,8 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, i * (nb_cfg_54 ? (siblings + 1) : 1) + j * (nb_cfg_54 ? 1 : 8); -#if (CONFIG_ENABLE_APIC_EXT_ID == 1) -#if CONFIG_LIFT_BSP_APIC_ID == 0 +#if CONFIG_ENABLE_APIC_EXT_ID +#if !CONFIG_LIFT_BSP_APIC_ID if ((i != 0) || (j != 0)) /* except bsp */ #endif ap_apicid += CONFIG_APIC_ID_OFFSET; @@ -215,7 +215,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) core0 is done at first --- use wait_all_core0_started */ if (id.coreid == 0) { set_apicid_cpuid_lo(); /* only set it on core0 */ -#if (CONFIG_ENABLE_APIC_EXT_ID == 1) +#if CONFIG_ENABLE_APIC_EXT_ID enable_apic_ext_id(id.nodeid); #endif } @@ -223,10 +223,10 @@ static u32 init_cpus(u32 cpu_init_detectedx) enable_lapic(); // init_timer(); // We need TMICT to pass msg for FID/VID change -#if (CONFIG_ENABLE_APIC_EXT_ID == 1) +#if CONFIG_ENABLE_APIC_EXT_ID u32 initial_apicid = get_initial_apicid(); -#if CONFIG_LIFT_BSP_APIC_ID == 0 +#if !CONFIG_LIFT_BSP_APIC_ID if (initial_apicid != 0) // other than bsp #endif { @@ -238,7 +238,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) lapic_write(LAPIC_ID, dword); } -#if CONFIG_LIFT_BSP_APIC_ID == 1 +#if CONFIG_LIFT_BSP_APIC_ID bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif @@ -293,7 +293,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) } lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ train_ram_on_node(id.nodeid, id.coreid, sysinfo, (unsigned)STOP_CAR_AND_CPU); #endif diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index ae5429d..7084606 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -31,7 +31,7 @@ #if CONFIG_WAIT_BEFORE_CPUS_INIT void cpus_ready_for_init(void) { -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // wait for ap memory to trained wait_all_core0_mem_trained(sysinfox); @@ -39,7 +39,7 @@ void cpus_ready_for_init(void) } #endif -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT int is_e0_later_in_bsp(int nodeid) { uint32_t val; @@ -67,7 +67,7 @@ int is_e0_later_in_bsp(int nodeid) } #endif -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; @@ -298,7 +298,7 @@ static void init_ecc_memory(unsigned node_id) #if CONFIG_HW_MEM_HOLE_SIZEK != 0 unsigned long hole_startk = 0; -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT if (!is_cpu_pre_e0()) { #endif @@ -307,7 +307,7 @@ static void init_ecc_memory(unsigned node_id) if (val & 1) { hole_startk = ((val & (0xff << 24)) >> 10); } -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT } #endif #endif @@ -370,7 +370,7 @@ static void init_ecc_memory(unsigned node_id) static inline void k8_errata(void) { msr_t msr; -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT if (is_cpu_pre_c0()) { /* Erratum 63... */ msr = rdmsr(HWCR_MSR); @@ -437,14 +437,14 @@ static inline void k8_errata(void) #endif -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT /* I can't touch this msr on early buggy cpus */ if (!is_cpu_pre_b3()) #endif { msr = rdmsr(NB_CFG_MSR); -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT if (!is_cpu_pre_c0() && is_cpu_pre_d0()) { /* D0 later don't need it */ /* Erratum 86 Disable data masking on C0 and @@ -523,7 +523,7 @@ static void model_fxx_init(device_t dev) /* Enable the local cpu apics */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS u32 siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { @@ -570,7 +570,7 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT { X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */ { X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */ { X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */ @@ -612,7 +612,7 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */ #endif -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT /* * AMD F0 support. * diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c index 5cc0fba..69769c9 100644 --- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c +++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c @@ -27,13 +27,13 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT #include "microcode_rev_c.h" #include "microcode_rev_d.h" #include "microcode_rev_e.h" #endif -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT // #include "microcode_rev_f.h" #endif /* Dummy terminator */ @@ -45,7 +45,7 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { static unsigned id_mapping_table[] = { - #if CONFIG_K8_REV_F_SUPPORT == 0 + #if !CONFIG_K8_REV_F_SUPPORT 0x0f48, 0x0048, 0x0f58, 0x0048, @@ -68,7 +68,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { 0x20fb1, 0x0210, #endif - #if CONFIG_K8_REV_F_SUPPORT == 1 + #if CONFIG_K8_REV_F_SUPPORT #endif diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index 83d34f1..81b1067 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -632,7 +632,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) return 0; } -#if CONFIG_MAX_PHYSICAL_CPUS==1 +#if CONFIG_MAX_PHYSICAL_CPUS /* IRT 80us RVO = 50mV PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */ control = (3 << 30) | (2 << 28) | (2 << 20) | (0 << 18) | (5 << 11); #else diff --git a/src/cpu/amd/model_fxx/processor_name.c b/src/cpu/amd/model_fxx/processor_name.c index 3f3d973..6f45b0f 100644 --- a/src/cpu/amd/model_fxx/processor_name.c +++ b/src/cpu/amd/model_fxx/processor_name.c @@ -42,7 +42,7 @@ * your mainboard will not be posted on the AMD Recommended Motherboard Website */ -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT static const char *processor_names[]={ /* 0x00 */ "AMD Engineering Sample", /* 0x01-0x03 */ NULL, NULL, NULL, @@ -113,7 +113,7 @@ static inline void wrmsr_amd(unsigned index, msr_t msr) int init_processor_name(void) { -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT u32 EightBitBrandId; #endif u32 BrandId; @@ -127,7 +127,7 @@ int init_processor_name(void) char program_string[48]; unsigned int *program_values = (unsigned int *)program_string; -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT /* Find out which CPU brand it is */ EightBitBrandId = cpuid_ebx(0x00000001) & 0xff; BrandId = cpuid_ebx(0x80000001) & 0xffff; @@ -151,7 +151,7 @@ int init_processor_name(void) processor_name_string = "AMD Processor model unknown"; #endif -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT u32 Socket; u32 CmpCap; u32 PwrLmt; @@ -407,7 +407,7 @@ int init_processor_name(void) for (i=0; i<47; i++) { // 48 -1 if(program_string[i] == program_string[i+1]) { switch (program_string[i]) { -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT case 'X': ModelNumber = 22+ NN; break; case 'Y': ModelNumber = 38 + (2*NN); break; case 'Z': @@ -416,7 +416,7 @@ int init_processor_name(void) case 'V': ModelNumber = 9 + NN; break; #endif -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT case 'R': ModelNumber = NN - 1; break; case 'P': ModelNumber = 26 + NN; break; case 'T': ModelNumber = 15 + (CmpCap * 10) + NN; break; diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 54a70e2..5c48cfd 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -6,7 +6,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA extern uint64_t uma_memory_size; #endif @@ -163,7 +163,7 @@ void amd_setup_mtrrs(void) * has been deducted from the size of memory below 4GB. * When setting TOM, include UMA DRAM */ - #if CONFIG_GFXUMA == 1 + #if CONFIG_GFXUMA msr.lo += uma_memory_size; #endif wrmsr(TOP_MEM, msr); diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index e988664..2d2e105 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -7,7 +7,7 @@ #include <smp/spinlock.h> #include <assert.h> -#if CONFIG_SERIAL_CPU_INIT==0 +#if !CONFIG_SERIAL_CPU_INIT #error Intel hyper-threading requires serialized cpu init #endif diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index f823981..e491d46 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -16,7 +16,7 @@ #include <cpu/cpu.h> #include <cpu/intel/speedstep.h> -#if CONFIG_SMP == 1 +#if CONFIG_SMP /* This is a lot more paranoid now, since Linux can NOT handle * being told there is a CPU when none exists. So any errors * will return 0, meaning no CPU. @@ -29,7 +29,7 @@ static unsigned long get_valid_start_eip(unsigned long orig_start_eip) return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000 } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME char *lowmem_backup; char *lowmem_backup_ptr; int lowmem_backup_size; @@ -49,7 +49,7 @@ static void copy_secondary_start_to_1m_below(void) start_eip = get_valid_start_eip((unsigned long)_secondary_start); code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME /* need to save it for RAM resume */ lowmem_backup_size = code_size; lowmem_backup = malloc(code_size); @@ -277,7 +277,7 @@ int start_cpu(device_t cpu) return result; } -#if CONFIG_AP_IN_SIPI_WAIT == 1 +#if CONFIG_AP_IN_SIPI_WAIT /** * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of delay. @@ -384,7 +384,7 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat void secondary_cpu_init(void) { atomic_inc(&active_cpus); -#if CONFIG_SERIAL_CPU_INIT == 1 +#if CONFIG_SERIAL_CPU_INIT spin_lock(&start_cpu_lock); #endif @@ -399,7 +399,7 @@ void secondary_cpu_init(void) writecr4(cr4_val); #endif cpu_initialize(); -#if CONFIG_SERIAL_CPU_INIT == 1 +#if CONFIG_SERIAL_CPU_INIT spin_unlock(&start_cpu_lock); #endif @@ -417,7 +417,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) if (cpu->path.type != DEVICE_PATH_APIC) { continue; } - #if CONFIG_SERIAL_CPU_INIT == 0 + #if !CONFIG_SERIAL_CPU_INIT if(cpu==bsp_cpu) { continue; } @@ -436,7 +436,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) printk(BIOS_ERR, "CPU 0x%02x would not start!\n", cpu->path.apic.apic_id); } -#if CONFIG_SERIAL_CPU_INIT == 1 +#if CONFIG_SERIAL_CPU_INIT udelay(10); #endif } @@ -502,7 +502,7 @@ void initialize_cpus(struct bus *cpu_bus) /* Find the device structure for the boot cpu */ info->cpu = alloc_find_dev(cpu_bus, &cpu_path); -#if CONFIG_SMP == 1 +#if CONFIG_SMP copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif @@ -512,8 +512,8 @@ void initialize_cpus(struct bus *cpu_bus) cpus_ready_for_init(); -#if CONFIG_SMP == 1 - #if CONFIG_SERIAL_CPU_INIT == 0 +#if CONFIG_SMP + #if !CONFIG_SERIAL_CPU_INIT /* start all aps at first, so we can init ECC all together */ start_other_cpus(cpu_bus, info->cpu); #endif @@ -522,8 +522,8 @@ void initialize_cpus(struct bus *cpu_bus) /* Initialize the bootstrap processor */ cpu_initialize(); -#if CONFIG_SMP == 1 - #if CONFIG_SERIAL_CPU_INIT == 1 +#if CONFIG_SMP + #if CONFIG_SERIAL_CPU_INIT start_other_cpus(cpu_bus, info->cpu); #endif diff --git a/src/devices/device.c b/src/devices/device.c index 0e9c39e..ebac1a0 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -536,7 +536,7 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, } } -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM #define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM) #else #define MEM_MASK (IORESOURCE_MEM) @@ -676,7 +676,7 @@ static void avoid_fixed_resources(struct device *dev) } } -#if CONFIG_VGA_BRIDGE_SETUP == 1 +#if CONFIG_VGA_BRIDGE_SETUP device_t vga_pri = 0; static void set_vga_bridge_bits(void) { @@ -725,7 +725,7 @@ static void set_vga_bridge_bits(void) if (!vga) vga = vga_first; -#if CONFIG_ONBOARD_VGA_IS_PRIMARY == 1 +#if CONFIG_ONBOARD_VGA_IS_PRIMARY if (vga_onboard) /* Will use onboard VGA as primary. */ #else if (!vga) /* Will use last add-on adapter as primary. */ @@ -935,7 +935,7 @@ void dev_configure(void) struct device *root; struct device *child; -#if CONFIG_VGA_BRIDGE_SETUP == 1 +#if CONFIG_VGA_BRIDGE_SETUP set_vga_bridge_bits(); #endif diff --git a/src/devices/hypertransport.c b/src/devices/hypertransport.c index 9267291..420054e 100644 --- a/src/devices/hypertransport.c +++ b/src/devices/hypertransport.c @@ -103,9 +103,9 @@ static unsigned ht_read_freq_cap(device_t dev, unsigned pos) /* AMD K8 unsupported 1GHz? */ if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) { -#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 +#if CONFIG_K8_HT_FREQ_1G_SUPPORT -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT /* Only e0 later suupport 1GHz HT. */ if (is_cpu_pre_e0()) freq_cap &= ~(1 << HT_FREQ_1000Mhz); @@ -351,7 +351,7 @@ static void ht_collapse_early_enumeration(struct bus *bus, } while ((ctrl & (1 << 5)) == 0); /* Actually, only for one HT device HT chain, and unitid is 0. */ -#if CONFIG_HT_CHAIN_UNITID_BASE == 0 +#if !CONFIG_HT_CHAIN_UNITID_BASE if (offset_unitid) return; #endif diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index c9af7c4..7fa7384 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -33,22 +33,22 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <delay.h> -#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1 +#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT #include <device/hypertransport.h> #endif -#if CONFIG_PCIX_PLUGIN_SUPPORT == 1 +#if CONFIG_PCIX_PLUGIN_SUPPORT #include <device/pcix.h> #endif -#if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1 +#if CONFIG_PCIEXP_PLUGIN_SUPPORT #include <device/pciexp.h> #endif -#if CONFIG_AGP_PLUGIN_SUPPORT == 1 +#if CONFIG_AGP_PLUGIN_SUPPORT #include <device/agp.h> #endif -#if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1 +#if CONFIG_CARDBUS_PLUGIN_SUPPORT #include <device/cardbus.h> #endif -#if CONFIG_PC80_SYSTEM == 1 +#if CONFIG_PC80_SYSTEM #include <pc80/i8259.h> #endif #if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN @@ -748,17 +748,17 @@ static struct device_operations *get_pci_bridge_ops(device_t dev) { unsigned int pos; -#if CONFIG_PCIX_PLUGIN_SUPPORT == 1 +#if CONFIG_PCIX_PLUGIN_SUPPORT pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); if (pos) { printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev)); return &default_pcix_ops_bus; } #endif -#if CONFIG_AGP_PLUGIN_SUPPORT == 1 +#if CONFIG_AGP_PLUGIN_SUPPORT /* How do I detect a PCI to AGP bridge? */ #endif -#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1 +#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT pos = 0; while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) { u16 flags; @@ -771,7 +771,7 @@ static struct device_operations *get_pci_bridge_ops(device_t dev) } } #endif -#if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1 +#if CONFIG_PCIEXP_PLUGIN_SUPPORT pos = pci_find_capability(dev, PCI_CAP_ID_PCIE); if (pos) { u16 flags; @@ -860,7 +860,7 @@ static void set_pci_ops(struct device *dev) goto bad; dev->ops = get_pci_bridge_ops(dev); break; -#if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1 +#if CONFIG_CARDBUS_PLUGIN_SUPPORT case PCI_HEADER_TYPE_CARDBUS: dev->ops = &default_cardbus_ops_bus; break; @@ -1256,7 +1256,7 @@ unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) return max; } -#if CONFIG_PC80_SYSTEM == 1 +#if CONFIG_PC80_SYSTEM /** * Assign IRQ numbers. * @@ -1305,7 +1305,7 @@ void pci_assign_irqs(unsigned bus, unsigned slot, printk(BIOS_DEBUG, " Readback = %d\n", irq); #endif -#if CONFIG_PC80_SYSTEM == 1 +#if CONFIG_PC80_SYSTEM /* Change to level triggered. */ i8259_configure_irq_trigger(pIntAtoD[line - 1], IRQ_LEVEL_TRIGGERED); diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c index e7933eb..fe67515 100644 --- a/src/devices/pci_rom.c +++ b/src/devices/pci_rom.c @@ -151,7 +151,7 @@ struct rom_header *pci_rom_load(struct device *dev, * devices have a mismatch between the hardware and the ROM. */ if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS == 0 +#if !CONFIG_MULTIPLE_VGA_ADAPTERS extern device_t vga_pri; /* Primary VGA device (device.c). */ if (dev != vga_pri) return NULL; /* Only one VGA supported. */ #endif diff --git a/src/drivers/ati/ragexl/atyfb.h b/src/drivers/ati/ragexl/atyfb.h index 99a87b3..557ead7 100644 --- a/src/drivers/ati/ragexl/atyfb.h +++ b/src/drivers/ati/ragexl/atyfb.h @@ -8,7 +8,7 @@ #define max(x,y) (x>=y)?x:y -#if CONFIG_CONSOLE_BTEXT==1 +#if CONFIG_CONSOLE_BTEXT /* * Elements of the hardware specific atyfb_par structure */ @@ -73,7 +73,7 @@ union aty_pll { * The hardware parameters for each card */ struct atyfb_par { -#if CONFIG_CONSOLE_BTEXT==1 +#if CONFIG_CONSOLE_BTEXT struct crtc crtc; #endif union aty_pll pll; @@ -97,7 +97,7 @@ struct aty_cursor { }; #endif struct fb_info_aty { -#if CONFIG_CONSOLE_BTEXT==1 +#if CONFIG_CONSOLE_BTEXT #if PLL_CRTC_DECODE==1 struct fb_info fb_info; #endif diff --git a/src/drivers/ati/ragexl/mach64_ct.c b/src/drivers/ati/ragexl/mach64_ct.c index b34be82..9b45f2a 100644 --- a/src/drivers/ati/ragexl/mach64_ct.c +++ b/src/drivers/ati/ragexl/mach64_ct.c @@ -284,7 +284,7 @@ int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per, aty_calc_pll_ct(info, &pll->ct); return 0; } -#if CONFIG_CONSOLE_BTEXT==1 +#if CONFIG_CONSOLE_BTEXT #if PLL_CRTC_DECODE==1 u32 aty_pll_ct_to_var(const struct fb_info_aty *info, const union aty_pll *pll) diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c index 747b343..36a0619 100644 --- a/src/drivers/ati/ragexl/xlinit.c +++ b/src/drivers/ati/ragexl/xlinit.c @@ -28,7 +28,7 @@ // Hence do only remove this if you fix the code. #define CONFIG_CONSOLE_BTEXT 0 -#if CONFIG_CONSOLE_BTEXT==1 +#if CONFIG_CONSOLE_BTEXT #define PLL_CRTC_DECODE 0 #define SUPPORT_8_BPP_ABOVE 0 @@ -393,7 +393,7 @@ static char m64n_xl_33[] = "3D RAGE (XL PCI-33MHz)"; static char m64n_xl_66[] = "3D RAGE (XL PCI-66MHz)"; -#if CONFIG_CONSOLE_BTEXT==1 +#if CONFIG_CONSOLE_BTEXT static void aty_set_crtc(const struct fb_info_aty *info, const struct crtc *crtc); static int aty_var_to_crtc(const struct fb_info_aty *info, @@ -455,7 +455,7 @@ static struct { /* 3D RAGE XL PCI-33/BGA */ { 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 }, }; -#if CONFIG_CONSOLE_BTEXT==1 +#if CONFIG_CONSOLE_BTEXT static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk) { int i, size; @@ -502,7 +502,7 @@ static void ati_ragexl_init(device_t dev) #endif int pll, mclk, xclk; -#if CONFIG_CONSOLE_BTEXT==1 +#if CONFIG_CONSOLE_BTEXT #if 0 int gtb_memsize, k; @@ -532,7 +532,7 @@ static void ati_ragexl_init(device_t dev) res = res->next; } -#if CONFIG_CONSOLE_BTEXT==1 +#if CONFIG_CONSOLE_BTEXT info->frame_buffer = res->base; #endif /* CONFIG_CONSOLE_BTEXT */ @@ -548,7 +548,7 @@ static void ati_ragexl_init(device_t dev) #endif -#if CONFIG_CONSOLE_BTEXT==1 +#if CONFIG_CONSOLE_BTEXT info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0); #endif @@ -581,7 +581,7 @@ found: mclk = 63; } #endif -#if CONFIG_CONSOLE_BTEXT==1 +#if CONFIG_CONSOLE_BTEXT aty_calc_mem_refresh(info, type, xclk); #endif /* CONFIG_CONSOLE_BTEXT */ @@ -596,7 +596,7 @@ found: atyfb_xl_init(info); -#if CONFIG_CONSOLE_BTEXT==1 +#if CONFIG_CONSOLE_BTEXT info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07); @@ -803,7 +803,7 @@ found: } -#if CONFIG_CONSOLE_BTEXT==1 +#if CONFIG_CONSOLE_BTEXT static int atyfb_decode_var(const struct fb_var_screeninfo *var, struct atyfb_par *par, diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index 56381e3..1e85596 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -2,7 +2,7 @@ int init_processor_name(void); -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT static inline int is_cpu_rev_a0(void) { return (cpuid_eax(1) & 0xfffef) == 0x0f00; @@ -79,7 +79,7 @@ int is_e0_later_in_bsp(int nodeid); //defined model_fxx_init.c #endif -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT //AMD_F0_SUPPORT static inline int is_cpu_pre_f0(void) { diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 2215ec7..078f2a7 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -147,7 +147,7 @@ static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue) void setup_lapic(void); -#if CONFIG_SMP == 1 +#if CONFIG_SMP struct device; int start_cpu(struct device *cpu); #endif /* CONFIG_SMP */ diff --git a/src/include/delay.h b/src/include/delay.h index 5d0dc01..0333879 100644 --- a/src/include/delay.h +++ b/src/include/delay.h @@ -3,7 +3,7 @@ #if !defined( __ROMCC__) -#if CONFIG_HAVE_INIT_TIMER == 1 +#if CONFIG_HAVE_INIT_TIMER void init_timer(void); #else #define init_timer() do{} while(0) diff --git a/src/include/reset.h b/src/include/reset.h index 3d72a8c..79bf6d5 100644 --- a/src/include/reset.h +++ b/src/include/reset.h @@ -4,7 +4,7 @@ #if !defined( __ROMCC__ ) /* ROMCC can't do function prototypes... */ -#if CONFIG_HAVE_HARD_RESET == 1 +#if CONFIG_HAVE_HARD_RESET void hard_reset(void); #else #define hard_reset() do {} while(0) diff --git a/src/include/smp/atomic.h b/src/include/smp/atomic.h index 8da08a2..44be4c5 100644 --- a/src/include/smp/atomic.h +++ b/src/include/smp/atomic.h @@ -1,7 +1,7 @@ #ifndef SMP_ATOMIC_H #define SMP_ATOMIC_H -#if CONFIG_SMP == 1 +#if CONFIG_SMP #include <arch/smp/atomic.h> #else diff --git a/src/include/smp/spinlock.h b/src/include/smp/spinlock.h index 1b0b4fd..87298b1 100644 --- a/src/include/smp/spinlock.h +++ b/src/include/smp/spinlock.h @@ -1,7 +1,7 @@ #ifndef SMP_SPINLOCK_H #define SMP_SPINLOCK_H -#if CONFIG_SMP == 1 +#if CONFIG_SMP #include <arch/smp/spinlock.h> #else /* !CONFIG_SMP */ diff --git a/src/include/watchdog.h b/src/include/watchdog.h index 98d6d51..d626737 100644 --- a/src/include/watchdog.h +++ b/src/include/watchdog.h @@ -1,7 +1,7 @@ #ifndef WATCHDOG_H #define WATCHDOG_H -#if CONFIG_USE_WATCHDOG_ON_BOOT == 1 +#if CONFIG_USE_WATCHDOG_ON_BOOT void watchdog_off(void); #else #define watchdog_off() diff --git a/src/mainboard/advansus/a785e-i/acpi_tables.c b/src/mainboard/advansus/a785e-i/acpi_tables.c index 9642bb4..fa93842 100644 --- a/src/mainboard/advansus/a785e-i/acpi_tables.c +++ b/src/mainboard/advansus/a785e-i/acpi_tables.c @@ -236,7 +236,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_create_facs(facs); /* FDAT */ -#if CONFIG_BOARD_HAS_FADT == 1 +#if CONFIG_BOARD_HAS_FADT current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c index 5c21e09..fcf0bd9 100644 --- a/src/mainboard/advansus/a785e-i/get_bus_conf.c +++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdfam10_sysconf.h> @@ -141,7 +141,7 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index ff2d395..afa82f3 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -84,7 +84,7 @@ static void a785e_i_enable(device_t dev) printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -133,7 +133,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c index 8643320..818d4be 100644 --- a/src/mainboard/advansus/a785e-i/mptable.c +++ b/src/mainboard/advansus/a785e-i/mptable.c @@ -79,7 +79,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h index 5fd49d6..98e2c94 100644 --- a/src/mainboard/advansus/a785e-i/platform_cfg.h +++ b/src/mainboard/advansus/a785e-i/platform_cfg.h @@ -36,7 +36,7 @@ * bigger than 1M you have to set the ROM size outside CIMx module and * before AGESA module get call. */ -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 #define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 #define BIOS_SIZE BIOS_SIZE_2M diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 3a33b5f..dcc3ba5 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -160,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); @@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* run _early_setup before soft-reset. */ rs780_early_setup(); -#if CONFIG_SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); post_code(0x39); diff --git a/src/mainboard/amd/bimini_fam10/get_bus_conf.c b/src/mainboard/amd/bimini_fam10/get_bus_conf.c index e53aef5..41a2fe7 100644 --- a/src/mainboard/amd/bimini_fam10/get_bus_conf.c +++ b/src/mainboard/amd/bimini_fam10/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdfam10_sysconf.h> @@ -138,7 +138,7 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index 1fd0eeb..241d905 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -134,7 +134,7 @@ static void bimini_enable(device_t dev) printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -184,7 +184,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c index ae81411..ec60b35 100644 --- a/src/mainboard/amd/bimini_fam10/mptable.c +++ b/src/mainboard/amd/bimini_fam10/mptable.c @@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 732e033..5980ca2 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/amd/dbm690t/get_bus_conf.c b/src/mainboard/amd/dbm690t/get_bus_conf.c index 2b0fca7..d4152a1 100644 --- a/src/mainboard/amd/dbm690t/get_bus_conf.c +++ b/src/mainboard/amd/dbm690t/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c index 2f54bfd..8841291 100644 --- a/src/mainboard/amd/dbm690t/mainboard.c +++ b/src/mainboard/amd/dbm690t/mainboard.c @@ -187,7 +187,7 @@ static void dbm690t_enable(device_t dev) { printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -238,7 +238,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c index cf98ae3..f34918f 100644 --- a/src/mainboard/amd/dbm690t/mptable.c +++ b/src/mainboard/amd/dbm690t/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 66637a8..459aa47 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index 9d10390..360e1df 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -75,7 +75,7 @@ uint64_t uma_memory_base, uma_memory_size; static void dinar_enable(device_t dev) { printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; uint32_t sys_mem; @@ -124,7 +124,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h index a4f4e1a..aaab1f3 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.h +++ b/src/mainboard/amd/dinar/rd890_cfg.h @@ -32,10 +32,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1 +#if CONFIG_CPU_AMD_AGESA_FAMILY10 #define DEFAULT_HT_PATH {0x0, 0x3} #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1 +#if CONFIG_CPU_AMD_AGESA_FAMILY15 #define DEFAULT_HT_PATH {0x0, 0x1} #endif #endif diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h index b405f0e..038e7e7 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.h +++ b/src/mainboard/amd/dinar/sb700_cfg.h @@ -40,7 +40,7 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 #define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 #define BIOS_SIZE BIOS_SIZE_2M diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 17c985d..d35b175 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -80,7 +80,7 @@ static void inagua_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; uint32_t sys_mem; @@ -128,7 +128,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index b5a507f..393eb9e 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -87,7 +87,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index 2a3342c..dd0251f 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -37,7 +37,7 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 #define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 #define BIOS_SIZE BIOS_SIZE_2M diff --git a/src/mainboard/amd/mahogany/get_bus_conf.c b/src/mainboard/amd/mahogany/get_bus_conf.c index bed7606..149e163 100644 --- a/src/mainboard/amd/mahogany/get_bus_conf.c +++ b/src/mainboard/amd/mahogany/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 0ccef10..989070c 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -105,7 +105,7 @@ static void mahogany_enable(device_t dev) { printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -154,7 +154,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c index dabd2ed..376e043 100644 --- a/src/mainboard/amd/mahogany/mptable.c +++ b/src/mainboard/amd/mahogany/mptable.c @@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 104652a..9d913e9 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c index b169775..563a87e 100644 --- a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c +++ b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index 2cbeaf1..1f1941b 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -106,7 +106,7 @@ static void mahogany_enable(device_t dev) { printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -155,7 +155,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c index c56952e..d69c7b7 100644 --- a/src/mainboard/amd/mahogany_fam10/mptable.c +++ b/src/mainboard/amd/mahogany_fam10/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index dce9baa..d48b69d 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS==1 + #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index e60673e..0d63abb 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -515,7 +515,7 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME UINT32 agesawrapper_amdinitresume ( VOID diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 4c094ae..1d5842a 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -51,7 +51,7 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME extern u8 acpi_slp_type; #endif @@ -83,7 +83,7 @@ void get_bus_conf(void) * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME if (acpi_slp_type != 3) { status = agesawrapper_amdinitlate(); if(status) diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 9a8428e..76a9ae6 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -63,11 +63,11 @@ static void persimmon_enable(device_t dev) * The mainboard is the first place that we get control in ramstage. Check * for S3 resume and call the approriate AGESA/CIMx resume functions. */ -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); #endif -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; uint32_t sys_mem; @@ -113,7 +113,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 61ddef1..d0c31f0 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 97aa47e..db3fc15 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -37,7 +37,7 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 #define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 #define BIOS_SIZE BIOS_SIZE_2M diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 55d0516..56a6788 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -51,7 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif @@ -107,7 +107,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ #endif post_code(0x40); @@ -126,7 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); diff --git a/src/mainboard/amd/pistachio/get_bus_conf.c b/src/mainboard/amd/pistachio/get_bus_conf.c index 2b0fca7..d4152a1 100644 --- a/src/mainboard/amd/pistachio/get_bus_conf.c +++ b/src/mainboard/amd/pistachio/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c index d1d9a84..e5d0efa 100644 --- a/src/mainboard/amd/pistachio/mainboard.c +++ b/src/mainboard/amd/pistachio/mainboard.c @@ -257,7 +257,7 @@ static void pistachio_enable(device_t dev) { printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -308,7 +308,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c index cf98ae3..f34918f 100644 --- a/src/mainboard/amd/pistachio/mptable.c +++ b/src/mainboard/amd/pistachio/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 5d6e7a8..45c94c8 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -101,7 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c index 36b5776..d4f44c0 100644 --- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c @@ -3,7 +3,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -192,7 +192,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index 4214408..866875d 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -4,7 +4,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 8378ca4..7378130 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -1,4 +1,4 @@ -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -139,13 +139,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index b595473..da7efe6 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -22,7 +22,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index e90b348..d19b3c6 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -23,7 +23,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 29b00b2..09447a6 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -255,7 +255,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS==1 + #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index 990c8b9..ed65b34 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -82,7 +82,7 @@ static void southstation_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; uint32_t sys_mem; @@ -129,7 +129,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index 99004b3..ba73ce0 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index 66aab8b..1c8506b 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -37,7 +37,7 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 #define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 #define BIOS_SIZE BIOS_SIZE_2M diff --git a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c index b169775..563a87e 100644 --- a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c +++ b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 357bdac..e2ef3f9 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -281,7 +281,7 @@ static void tilapia_enable(device_t dev) { printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -331,7 +331,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c index 4a276fb..d7951cf 100644 --- a/src/mainboard/amd/tilapia_fam10/mptable.c +++ b/src/mainboard/amd/tilapia_fam10/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index f316395..9919cce 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h index 037ce94..4acc136 100644 --- a/src/mainboard/amd/torpedo/Oem.h +++ b/src/mainboard/amd/torpedo/Oem.h @@ -20,7 +20,7 @@ #define BIOS_SIZE 0x04 //04 - 1MB #endif #define LEGACY_FREE 0x00 -#if CONFIG_ONBOARD_USB30 == 0 +#if !CONFIG_ONBOARD_USB30 #define XHCI_SUPPORT 0x01 #endif diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 2152153..7248bfb 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -58,7 +58,7 @@ uint64_t uma_memory_base, uma_memory_size; static void torpedo_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; uint32_t sys_mem; @@ -107,7 +107,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 936a417..9513741 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -164,7 +164,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin)) #else diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index cf31c6a..a6d02e8 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -39,7 +39,7 @@ #define BIOS_SIZE_4M 3 #define BIOS_SIZE_8M 7 -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 #define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 #define BIOS_SIZE BIOS_SIZE_2M @@ -311,7 +311,7 @@ #define INCHIP_USB_CINFIG 0x7F #define INCHIP_USB_OHCI1_CINFIG 0x01 #define INCHIP_USB_OHCI2_CINFIG 0x01 -#if CONFIG_ONBOARD_USB30 == 1 +#if CONFIG_ONBOARD_USB30 #define INCHIP_USB_OHCI3_CINFIG 0x00 #else #define INCHIP_USB_OHCI3_CINFIG 0x01 @@ -985,7 +985,7 @@ * @li <b>0</b> - Disable * @li <b>1</b> - Enable */ -#if CONFIG_ONBOARD_USB30 == 1 +#if CONFIG_ONBOARD_USB30 #define SB_XHCI_SWITCH 0 #else #define SB_XHCI_SWITCH 1 diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 800d64d..c5b481d 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -56,7 +56,7 @@ static void unionstation_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; uint32_t sys_mem; @@ -103,7 +103,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index 99004b3..ba73ce0 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index 66aab8b..1c8506b 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -37,7 +37,7 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 #define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 #define BIOS_SIZE BIOS_SIZE_2M diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index c334fa5..cd08389 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -93,7 +93,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/asrock/939a785gmh/get_bus_conf.c b/src/mainboard/asrock/939a785gmh/get_bus_conf.c index bed7606..149e163 100644 --- a/src/mainboard/asrock/939a785gmh/get_bus_conf.c +++ b/src/mainboard/asrock/939a785gmh/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c index 945a19f..0b566e4 100644 --- a/src/mainboard/asrock/939a785gmh/mainboard.c +++ b/src/mainboard/asrock/939a785gmh/mainboard.c @@ -103,7 +103,7 @@ static void mb_enable(device_t dev) { printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -152,7 +152,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c index c0ca550..5b73b20 100644 --- a/src/mainboard/asrock/939a785gmh/mptable.c +++ b/src/mainboard/asrock/939a785gmh/mptable.c @@ -99,7 +99,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 4a1b1c3..51b7519 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -169,7 +169,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index 4e58324..8642e28 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -54,7 +54,7 @@ uint64_t uma_memory_base, uma_memory_size; static void e350m1_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; uint32_t sys_mem; @@ -101,7 +101,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 7e8c947..81fe0bd 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 6aa31d2..7fa9c23 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -37,7 +37,7 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE - #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 + #if CONFIG_COREBOOT_ROMSIZE_KB_1024 #define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 #define BIOS_SIZE BIOS_SIZE_2M diff --git a/src/mainboard/asus/a8n_e/get_bus_conf.c b/src/mainboard/asus/a8n_e/get_bus_conf.c index 75741fd..ce1448d 100644 --- a/src/mainboard/asus/a8n_e/get_bus_conf.c +++ b/src/mainboard/asus/a8n_e/get_bus_conf.c @@ -27,7 +27,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> @@ -114,7 +114,7 @@ void get_bus_conf(void) } } -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index b3e85b7..fcbe86d 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -121,7 +121,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 47a0e65..53a1fbc 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -190,7 +190,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_info("now booting... Core0 started\n"); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 4193452..7539a80 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -192,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_info("now booting... Core0 started\n"); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index f24c4d4..82b0636 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_info("now booting... Core0 started\n"); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/asus/m2n-e/get_bus_conf.c b/src/mainboard/asus/m2n-e/get_bus_conf.c index a39ac22..031b673 100644 --- a/src/mainboard/asus/m2n-e/get_bus_conf.c +++ b/src/mainboard/asus/m2n-e/get_bus_conf.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> @@ -112,7 +112,7 @@ void get_bus_conf(void) bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index e820a79..8f9089d 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -20,7 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -126,7 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1); printk(BIOS_DEBUG, "bsp_apicid=0x%02x\n", bsp_apicid); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ /* In BSP so could hold all AP until sysinfo is in RAM. */ set_sysinfo_in_ram(0); #endif @@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); /* Routing table and start other core0. */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS /* * It is said that we should start core1 after all core0 launched * becase optimize_link_coherent_ht is moved out from diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c index 614af39..c936fa9 100644 --- a/src/mainboard/asus/m2v-mx_se/mainboard.c +++ b/src/mainboard/asus/m2v-mx_se/mainboard.c @@ -30,7 +30,7 @@ uint64_t uma_memory_base, uma_memory_size; int add_mainboard_resources(struct lb_memory *mem) { -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); #endif diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 9825e2b..ac88f6a 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -24,7 +24,7 @@ unsigned int get_sbdn(unsigned bus); -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_INFO, "now booting... All core 0 started\n"); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 53a3fc3..367ef3b 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -24,7 +24,7 @@ unsigned int get_sbdn(unsigned bus); -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -256,7 +256,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_INFO, "now booting... All core 0 started\n"); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c index b169775..563a87e 100644 --- a/src/mainboard/asus/m4a78-em/get_bus_conf.c +++ b/src/mainboard/asus/m4a78-em/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c index 4854208..10ecb64 100644 --- a/src/mainboard/asus/m4a78-em/mainboard.c +++ b/src/mainboard/asus/m4a78-em/mainboard.c @@ -125,7 +125,7 @@ static void m4a78em_enable(device_t dev) { printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c index 4a276fb..d7951cf 100644 --- a/src/mainboard/asus/m4a78-em/mptable.c +++ b/src/mainboard/asus/m4a78-em/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index a96592d..50bbfca 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS==1 + #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c index b169775..563a87e 100644 --- a/src/mainboard/asus/m4a785-m/get_bus_conf.c +++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index d152f71..3b68143 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -197,7 +197,7 @@ static void m4a785m_enable(device_t dev) { printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c index 4a276fb..d7951cf 100644 --- a/src/mainboard/asus/m4a785-m/mptable.c +++ b/src/mainboard/asus/m4a785-m/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 870af70..f0be2f7 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS==1 + #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/asus/m5a88-v/acpi_tables.c b/src/mainboard/asus/m5a88-v/acpi_tables.c index 9642bb4..fa93842 100644 --- a/src/mainboard/asus/m5a88-v/acpi_tables.c +++ b/src/mainboard/asus/m5a88-v/acpi_tables.c @@ -236,7 +236,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_create_facs(facs); /* FDAT */ -#if CONFIG_BOARD_HAS_FADT == 1 +#if CONFIG_BOARD_HAS_FADT current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c index 5c21e09..fcf0bd9 100644 --- a/src/mainboard/asus/m5a88-v/get_bus_conf.c +++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdfam10_sysconf.h> @@ -141,7 +141,7 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index 7fa4ee7..38b9648 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -81,7 +81,7 @@ static void m5a88pm_v_enable(device_t dev) printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -130,7 +130,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c index ac8ed5e..7daa5d1 100644 --- a/src/mainboard/asus/m5a88-v/mptable.c +++ b/src/mainboard/asus/m5a88-v/mptable.c @@ -79,7 +79,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/asus/m5a88-v/platform_cfg.h b/src/mainboard/asus/m5a88-v/platform_cfg.h index 43573f1..00f9695 100644 --- a/src/mainboard/asus/m5a88-v/platform_cfg.h +++ b/src/mainboard/asus/m5a88-v/platform_cfg.h @@ -36,7 +36,7 @@ * bigger than 1M you have to set the ROM size outside CIMx module and * before AGESA module get call. */ -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 #define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 #define BIOS_SIZE BIOS_SIZE_2M diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 9d8e08a..22d87b3 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -159,7 +159,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); @@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* run _early_setup before soft-reset. */ rs780_early_setup(); -#if CONFIG_SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); post_code(0x39); diff --git a/src/mainboard/avalue/eax-785e/acpi_tables.c b/src/mainboard/avalue/eax-785e/acpi_tables.c index 9642bb4..fa93842 100644 --- a/src/mainboard/avalue/eax-785e/acpi_tables.c +++ b/src/mainboard/avalue/eax-785e/acpi_tables.c @@ -236,7 +236,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_create_facs(facs); /* FDAT */ -#if CONFIG_BOARD_HAS_FADT == 1 +#if CONFIG_BOARD_HAS_FADT current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c index 20a856e..fcf0bd9 100644 --- a/src/mainboard/avalue/eax-785e/get_bus_conf.c +++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c @@ -23,11 +23,11 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdfam10_sysconf.h> -#if CONFIG_AMD_SB_CIMX == 1 +#if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> #endif @@ -141,14 +141,14 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_sb800 = apicid_base + 0; -#if CONFIG_AMD_SB_CIMX == 1 +#if CONFIG_AMD_SB_CIMX sb_Late_Post(); #endif } diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 7f55c03..52befa5 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -84,7 +84,7 @@ static void eax_785e(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -133,7 +133,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c index 6f541a0..bf5a684 100644 --- a/src/mainboard/avalue/eax-785e/mptable.c +++ b/src/mainboard/avalue/eax-785e/mptable.c @@ -80,7 +80,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else diff --git a/src/mainboard/avalue/eax-785e/platform_cfg.h b/src/mainboard/avalue/eax-785e/platform_cfg.h index e503585..1ce1c51 100644 --- a/src/mainboard/avalue/eax-785e/platform_cfg.h +++ b/src/mainboard/avalue/eax-785e/platform_cfg.h @@ -37,7 +37,7 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 #define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 #define BIOS_SIZE BIOS_SIZE_2M diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index beea992..3667235 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); @@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* run _early_setup before soft-reset. */ rs780_early_setup(); -#if CONFIG_SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); post_code(0x39); diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c index 869f049..36959a4 100644 --- a/src/mainboard/broadcom/blast/get_bus_conf.c +++ b/src/mainboard/broadcom/blast/get_bus_conf.c @@ -3,7 +3,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -101,7 +101,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index 5a1bf28..d7ae6b7 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -4,7 +4,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 4dee763..df7b615 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -105,7 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c index b961e8b..f1669bb 100644 --- a/src/mainboard/emulation/qemu-x86/northbridge.c +++ b/src/mainboard/emulation/qemu-x86/northbridge.c @@ -12,7 +12,7 @@ #include <delay.h> #include <smbios.h> -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -54,7 +54,7 @@ static void cpu_pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index afad4bc..90fc25f 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -341,7 +341,7 @@ void main(unsigned long bist) /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(); -#if CONFIG_HAVE_ACPI_RESUME == 0 +#if !CONFIG_HAVE_ACPI_RESUME /* When doing resume, we must not overwrite RAM */ #if CONFIG_DEBUG_RAM_SETUP sdram_dump_mchbar_registers(); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c index 2fda606..c27dd23 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c @@ -26,7 +26,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -119,7 +119,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 0ba4c59..9c7ae9c 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -21,7 +21,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -150,13 +150,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c index 0df65c7..b264170 100644 --- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c +++ b/src/mainboard/gigabyte/m57sli/get_bus_conf.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -117,7 +117,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 16d2453..281c768 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -153,13 +153,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c index b169775..563a87e 100644 --- a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index 989dfb5..254df00 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -142,7 +142,7 @@ static void ma785gm_enable(device_t dev) { printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -191,7 +191,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c index 4a276fb..d7951cf 100644 --- a/src/mainboard/gigabyte/ma785gm/mptable.c +++ b/src/mainboard/gigabyte/ma785gm/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 68f3dcc..f118c3c 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -143,7 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c index b169775..563a87e 100644 --- a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index 5747e62..8d669ba 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -252,7 +252,7 @@ static void ma785gmt_enable(device_t dev) { printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -302,7 +302,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c index 4a276fb..d7951cf 100644 --- a/src/mainboard/gigabyte/ma785gmt/mptable.c +++ b/src/mainboard/gigabyte/ma785gmt/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 68f3dcc..f118c3c 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -143,7 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c index b169775..563a87e 100644 --- a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index 1a00af6..ee353ed 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -79,7 +79,7 @@ static void ma78gm_enable(device_t dev) { printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -128,7 +128,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c index 4a276fb..d7951cf 100644 --- a/src/mainboard/gigabyte/ma78gm/mptable.c +++ b/src/mainboard/gigabyte/ma78gm/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 6c25a9e..4f90823 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c index b7bbaad..9ca5792 100644 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c @@ -3,7 +3,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -100,7 +100,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 6b8972b..88b2133 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -121,12 +121,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_dl145g1_resource_map(); //setup_default_resource_map(); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c index 36852f1..b1d1b22 100644 --- a/src/mainboard/hp/dl145_g3/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c @@ -26,7 +26,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -127,7 +127,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index 609432a..0b6095f 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -33,7 +33,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index a46218a..4945709 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -25,7 +25,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -163,13 +163,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c index 7f4112b..f313ced 100644 --- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index 00234a3..5f77d03 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -33,7 +33,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdfam10_sysconf.h> diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 32a94d4..8235f9c 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -164,7 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index 5208790..b10f693 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); #endif diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index 0cb0cce..93afa39 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); #endif diff --git a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c index b169775..563a87e 100644 --- a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c +++ b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c index 4d0cd09..ef02c89 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c +++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c @@ -61,7 +61,7 @@ static void kino_enable(device_t dev) { printk(BIOS_INFO, "Mainboard Kino Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -110,7 +110,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c index a26fbde..b007969 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mptable.c +++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index f51b3ec..4318831 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS==1 + #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/intel/eagleheights/fadt.c b/src/mainboard/intel/eagleheights/fadt.c index 40be3ea..c584c62 100644 --- a/src/mainboard/intel/eagleheights/fadt.c +++ b/src/mainboard/intel/eagleheights/fadt.c @@ -67,7 +67,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->dsdt = (unsigned long) dsdt; fadt->preferred_pm_profile = 7; /* Performance Server */ fadt->sci_int = 0x9; -#if CONFIG_HAVE_SMI_HANDLER == 1 +#if CONFIG_HAVE_SMI_HANDLER fadt->smi_cmd = APM_CNT; #else fadt->smi_cmd = 0x00; diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c index aa6d21f..4f63ff5 100644 --- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c +++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c @@ -3,7 +3,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -191,7 +191,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c index 3977673..ff6e582 100644 --- a/src/mainboard/iwill/dk8_htx/mptable.c +++ b/src/mainboard/iwill/dk8_htx/mptable.c @@ -4,7 +4,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 5a24447..e75eb8c 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -1,4 +1,4 @@ -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -103,13 +103,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 4125c66..b8cf14f 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -1,4 +1,4 @@ -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -104,13 +104,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 765114c..b0fb299 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -1,4 +1,4 @@ -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -104,13 +104,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, diff --git a/src/mainboard/jetway/pa78vm5/get_bus_conf.c b/src/mainboard/jetway/pa78vm5/get_bus_conf.c index b169775..563a87e 100644 --- a/src/mainboard/jetway/pa78vm5/get_bus_conf.c +++ b/src/mainboard/jetway/pa78vm5/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c index 6d0ceba..e992f74 100644 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ b/src/mainboard/jetway/pa78vm5/mainboard.c @@ -108,7 +108,7 @@ static void pa78vm5_enable(device_t dev) { printk(BIOS_INFO, "Mainboard PA78VM5 Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -157,7 +157,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c index b8caa23..40d2d6b 100644 --- a/src/mainboard/jetway/pa78vm5/mptable.c +++ b/src/mainboard/jetway/pa78vm5/mptable.c @@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index ba3b208..338c7f3 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -154,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS==1 + #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/kontron/kt690/get_bus_conf.c b/src/mainboard/kontron/kt690/get_bus_conf.c index 2b0fca7..d4152a1 100644 --- a/src/mainboard/kontron/kt690/get_bus_conf.c +++ b/src/mainboard/kontron/kt690/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c index 2e0c8e7..c2a401e 100644 --- a/src/mainboard/kontron/kt690/mainboard.c +++ b/src/mainboard/kontron/kt690/mainboard.c @@ -187,7 +187,7 @@ static void kt690_enable(device_t dev) { printk(BIOS_INFO, "Mainboard KT690 Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -238,7 +238,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c index 4ffba6f..bb3232a 100644 --- a/src/mainboard/kontron/kt690/mptable.c +++ b/src/mainboard/kontron/kt690/mptable.c @@ -99,7 +99,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 621c27f..ee17208 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -104,7 +104,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/msi/ms7135/get_bus_conf.c b/src/mainboard/msi/ms7135/get_bus_conf.c index cfcce2f..fe75f78 100644 --- a/src/mainboard/msi/ms7135/get_bus_conf.c +++ b/src/mainboard/msi/ms7135/get_bus_conf.c @@ -27,7 +27,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -98,7 +98,7 @@ void get_bus_conf(void) } /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 773d93e..515f7d7 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/msi/ms7260/get_bus_conf.c b/src/mainboard/msi/ms7260/get_bus_conf.c index fadc3fe..0f053cd 100644 --- a/src/mainboard/msi/ms7260/get_bus_conf.c +++ b/src/mainboard/msi/ms7260/get_bus_conf.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> @@ -117,7 +117,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index b384119..1e05619 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -20,7 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ /* In BSP so could hold all AP until sysinfo is in RAM. */ set_sysinfo_in_ram(0); #endif @@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); /* Routing table and start other core0. */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched * becase optimize_link_coherent_ht is moved out from * setup_coherent_ht_domain, so here need to make sure last core0 is diff --git a/src/mainboard/msi/ms9185/get_bus_conf.c b/src/mainboard/msi/ms9185/get_bus_conf.c index 0e97de6..b20288b 100644 --- a/src/mainboard/msi/ms9185/get_bus_conf.c +++ b/src/mainboard/msi/ms9185/get_bus_conf.c @@ -26,7 +26,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -124,7 +124,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index fe65d7d..c28074c 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -30,7 +30,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index a2505d6..1a72ae0 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -143,7 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, diff --git a/src/mainboard/msi/ms9282/get_bus_conf.c b/src/mainboard/msi/ms9282/get_bus_conf.c index 833b29b..7ce44ab 100644 --- a/src/mainboard/msi/ms9282/get_bus_conf.c +++ b/src/mainboard/msi/ms9282/get_bus_conf.c @@ -27,7 +27,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -118,7 +118,7 @@ void get_bus_conf(void) } /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index e73e5d7..46492a2 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); //wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c index 746abc8..605b70e 100644 --- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c +++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -116,7 +116,7 @@ void get_bus_conf(void) } /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n", apicid_base); #else diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 0bf6d11..3bb436a 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index 83acd52..1098275 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c index 99f8431..b06f758 100644 --- a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c +++ b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -134,7 +134,7 @@ void get_bus_conf(void) } /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(2); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 94aa14a..266e7ac 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -142,13 +142,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c index bae2782..9cdaa64 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c @@ -148,7 +148,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* Write SB600 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); -#if CONFIG_LINT01_CONVERSION == 0 +#if !CONFIG_LINT01_CONVERSION current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c index 2b0fca7..d4152a1 100644 --- a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c +++ b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 76397ab..0d7b8da 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -816,14 +816,14 @@ static void smm_lock( void ) static void init(device_t dev) { -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0 +#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL INT15_function_extensions int15_func; #endif printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n", dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__); -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0 +#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL if( get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") < 0 ) int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO; int15_func.regs.func05_TV_standard = TV_MODE_NO; @@ -853,7 +853,7 @@ static void enable_dev(device_t dev) detect_hw_variant(dev); update_subsystemid(dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA { msr_t msr, msr2; @@ -921,7 +921,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index b570d45..0c61e5d 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -258,7 +258,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c index bd57def..af4d6f0 100644 --- a/src/mainboard/sunw/ultra40/get_bus_conf.c +++ b/src/mainboard/sunw/ultra40/get_bus_conf.c @@ -3,7 +3,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <stdlib.h> @@ -254,7 +254,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(4); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 0bc8de2..1f0a395 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -129,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c index 42c4c46..53dcd72 100644 --- a/src/mainboard/supermicro/h8dme/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dme/get_bus_conf.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -141,7 +141,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 2cdc4c9..53bd7b1 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -16,7 +16,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -210,14 +210,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif /* dump_smbus_registers(); */ setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, diff --git a/src/mainboard/supermicro/h8dmr/get_bus_conf.c b/src/mainboard/supermicro/h8dmr/get_bus_conf.c index 42c4c46..53dcd72 100644 --- a/src/mainboard/supermicro/h8dmr/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr/get_bus_conf.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -141,7 +141,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 38aef5e..bda4ed0 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -137,13 +137,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c index 07350e3..0cb580c 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -115,7 +115,7 @@ void get_bus_conf(void) } /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 4e243c2..ddd0920 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c index 5837349..d73e8ad 100644 --- a/src/mainboard/supermicro/h8qgi/buildOpts.c +++ b/src/mainboard/supermicro/h8qgi/buildOpts.c @@ -202,7 +202,7 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA h8qgi_manual_swaplist[2] = } }; -#if CONFIG_HT3_SUPPORT == 1 +#if CONFIG_HT3_SUPPORT /** * The socket and link match values are platform specific * @@ -439,10 +439,10 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* -#if (CONFIG_CPU_AMD_AGESA_FAMILY15 == 1) +#if CONFIG_CPU_AMD_AGESA_FAMILY15 #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE #endif -#if (CONFIG_CPU_AMD_AGESA_FAMILY10 == 1) +#if CONFIG_CPU_AMD_AGESA_FAMILY10 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE #endif */ diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c index 675c87f..f6d437e 100644 --- a/src/mainboard/supermicro/h8qgi/mainboard.c +++ b/src/mainboard/supermicro/h8qgi/mainboard.c @@ -72,7 +72,7 @@ static void h8qgi_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } -#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1) +#if CONFIG_HAVE_MAINBOARD_RESOURCES int add_mainboard_resources(struct lb_memory *mem) { return 0; diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h index 8f45019..3ba25d5 100644 --- a/src/mainboard/supermicro/h8qgi/rd890_cfg.h +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h @@ -31,10 +31,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1 +#if CONFIG_CPU_AMD_AGESA_FAMILY10 #define DEFAULT_HT_PATH {0x0, 0x3} #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1 +#if CONFIG_CPU_AMD_AGESA_FAMILY15 #define DEFAULT_HT_PATH {0x0, 0x1} #endif #endif diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h index aac61ec..42cd363 100644 --- a/src/mainboard/supermicro/h8qgi/sb700_cfg.h +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h @@ -40,7 +40,7 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 #define BIOS_SIZE BIOS_SIZE_1M #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 #define BIOS_SIZE BIOS_SIZE_2M diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c index f03fb64..a92bf42 100644 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -132,7 +132,7 @@ void get_bus_conf(void) m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index d9d5218..2f5be99 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -226,7 +226,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c index 6a1fd77..fe5fcde 100644 --- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -128,7 +128,7 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c index 90b5335..d0fb541 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c +++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c @@ -97,7 +97,7 @@ static void h8scm_enable(device_t dev) /* get_ide_dma66(); */ } -#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1) +#if CONFIG_HAVE_MAINBOARD_RESOURCES int add_mainboard_resources(struct lb_memory *mem) { return 0; diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c index 0c75d1a..2e50b84 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c @@ -110,7 +110,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sp5100, (pin)) #else diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 70b3a04..6ad1484 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/technexion/tim5690/get_bus_conf.c b/src/mainboard/technexion/tim5690/get_bus_conf.c index 2b0fca7..d4152a1 100644 --- a/src/mainboard/technexion/tim5690/get_bus_conf.c +++ b/src/mainboard/technexion/tim5690/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 924d09e..6350230 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -241,7 +241,7 @@ static void tim5690_enable(device_t dev) vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO; vgabios_init(&vbios_regs); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -290,7 +290,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c index 4ffba6f..bb3232a 100644 --- a/src/mainboard/technexion/tim5690/mptable.c +++ b/src/mainboard/technexion/tim5690/mptable.c @@ -99,7 +99,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 5934938..c24e891 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -108,7 +108,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/technexion/tim8690/get_bus_conf.c b/src/mainboard/technexion/tim8690/get_bus_conf.c index 2b0fca7..d4152a1 100644 --- a/src/mainboard/technexion/tim8690/get_bus_conf.c +++ b/src/mainboard/technexion/tim8690/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 664372d..18abbc9 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -147,7 +147,7 @@ static void tim8690_enable(device_t dev) { printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -197,7 +197,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c index 4ffba6f..bb3232a 100644 --- a/src/mainboard/technexion/tim8690/mptable.c +++ b/src/mainboard/technexion/tim8690/mptable.c @@ -99,7 +99,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 97bc4e1..875321e 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c index 08027f4..371d9a3 100644 --- a/src/mainboard/tyan/s2850/mptable.c +++ b/src/mainboard/tyan/s2850/mptable.c @@ -4,7 +4,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -80,7 +80,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index e990f4e..567b4f1 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -89,7 +89,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); #endif diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c index c3765f2..90299a7 100644 --- a/src/mainboard/tyan/s2875/mptable.c +++ b/src/mainboard/tyan/s2875/mptable.c @@ -4,7 +4,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -98,7 +98,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index 832255c..4b52cd3 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); #endif diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c index 2d34c8b..32fc639 100644 --- a/src/mainboard/tyan/s2880/mptable.c +++ b/src/mainboard/tyan/s2880/mptable.c @@ -4,7 +4,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -109,7 +109,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 6bdb3d0..6dc62af 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); #endif diff --git a/src/mainboard/tyan/s2881/get_bus_conf.c b/src/mainboard/tyan/s2881/get_bus_conf.c index e4721ce..c7b62c7 100644 --- a/src/mainboard/tyan/s2881/get_bus_conf.c +++ b/src/mainboard/tyan/s2881/get_bus_conf.c @@ -3,7 +3,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -106,7 +106,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index bba4c7e..07ac12b 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -92,7 +92,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c index 47c39a7..6c07965 100644 --- a/src/mainboard/tyan/s2882/mptable.c +++ b/src/mainboard/tyan/s2882/mptable.c @@ -5,7 +5,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 6bdb3d0..6dc62af 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); #endif diff --git a/src/mainboard/tyan/s2885/get_bus_conf.c b/src/mainboard/tyan/s2885/get_bus_conf.c index 5cb760d..e390f7c 100644 --- a/src/mainboard/tyan/s2885/get_bus_conf.c +++ b/src/mainboard/tyan/s2885/get_bus_conf.c @@ -3,7 +3,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -119,7 +119,7 @@ void get_bus_conf(void) } /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index d6552ac..5aede1c 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -92,7 +92,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/tyan/s2891/get_bus_conf.c b/src/mainboard/tyan/s2891/get_bus_conf.c index bbb02e9..6be68ad 100644 --- a/src/mainboard/tyan/s2891/get_bus_conf.c +++ b/src/mainboard/tyan/s2891/get_bus_conf.c @@ -3,7 +3,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -153,7 +153,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index 8cdeb85..0936481 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -113,7 +113,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/tyan/s2892/get_bus_conf.c b/src/mainboard/tyan/s2892/get_bus_conf.c index 3a45cfa..174632f 100644 --- a/src/mainboard/tyan/s2892/get_bus_conf.c +++ b/src/mainboard/tyan/s2892/get_bus_conf.c @@ -3,7 +3,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -146,7 +146,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 2b2d6fa..9124b99 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -104,7 +104,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/tyan/s2895/get_bus_conf.c b/src/mainboard/tyan/s2895/get_bus_conf.c index 9de1629..abd6297 100644 --- a/src/mainboard/tyan/s2895/get_bus_conf.c +++ b/src/mainboard/tyan/s2895/get_bus_conf.c @@ -3,7 +3,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -157,7 +157,7 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(4); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/tyan/s2912/get_bus_conf.c b/src/mainboard/tyan/s2912/get_bus_conf.c index d16f4e6..d807358 100644 --- a/src/mainboard/tyan/s2912/get_bus_conf.c +++ b/src/mainboard/tyan/s2912/get_bus_conf.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdk8_sysconf.h> @@ -112,7 +112,7 @@ void get_bus_conf(void) } /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 67ce286..926521d 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -140,13 +140,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c index da0ed54..4137908 100644 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -114,7 +114,7 @@ void get_bus_conf(void) } /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index df571a0..c3017e5 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c index 9111a63..dcc0fd8 100644 --- a/src/mainboard/tyan/s4880/mptable.c +++ b/src/mainboard/tyan/s4880/mptable.c @@ -4,7 +4,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -109,7 +109,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 9348f39..c697670 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); #endif diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c index bca26a0..350b55c 100644 --- a/src/mainboard/tyan/s4882/mptable.c +++ b/src/mainboard/tyan/s4882/mptable.c @@ -4,7 +4,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -109,7 +109,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index c916e4c..56b6325 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); diff --git a/src/mainboard/via/epia-n/mainboard.c b/src/mainboard/via/epia-n/mainboard.c index 6e11a00..cf5ae96 100644 --- a/src/mainboard/via/epia-n/mainboard.c +++ b/src/mainboard/via/epia-n/mainboard.c @@ -30,7 +30,7 @@ int add_mainboard_resources(struct lb_memory *mem) { -#if CONFIG_IOAPIC == 1 +#if CONFIG_IOAPIC lb_add_memory_range(mem, LB_MEM_RESERVED, IO_APIC_ADDR, 0x1000); lb_add_memory_range(mem, LB_MEM_RESERVED, diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index ee02f0d..7b73987 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -31,7 +31,7 @@ #include <cpu/x86/lapic.h> #include <cbmem.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <pc80/mc146818rtc.h> #endif @@ -70,7 +70,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) dram_base_mask_t d; dev = __f1_dev[0]; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT /* I will use ext space only for simple */ pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8] d.mask = pci_read_config32(dev, 0x114); // enable is bit 0 @@ -551,7 +551,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) resource = amdfam10_find_iopair(dev, nodeid, link); if (resource) { u32 align; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT if((resource->index & 0x1fff) == 0x1110) { // ext align = 8; } @@ -577,7 +577,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags |= IORESOURCE_BRIDGE; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT if ((resource->index & 0x1fff) == 0x1110) { // ext normalize_resource(resource); } @@ -594,7 +594,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT if ((resource->index & 0x1fff) == 0x1110) { // ext normalize_resource(resource); } @@ -677,7 +677,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 +#if CONFIG_MULTIPLE_VGA_ADAPTERS extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -806,7 +806,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if CONFIG_PCI_64BIT_PREF_MEM == 0 +#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); #else struct bus *link; @@ -908,7 +908,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; static void add_uma_resource(struct device *dev, int index) @@ -926,7 +926,7 @@ static void add_uma_resource(struct device *dev, int index) static void amdfam10_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; struct resource *res; #endif @@ -939,7 +939,7 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM for (link = dev->link_list; link; link = link->next) { /* Now reallocate the pci resources memory with the @@ -1054,10 +1054,10 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; @@ -1079,19 +1079,19 @@ static void amdfam10_domain_set_resources(device_t dev) } } -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA /* Deduct uma memory before reporting because * this is what the mtrr code expects */ sizek -= uma_memory_size / 1024; #endif ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; @@ -1101,7 +1101,7 @@ static void amdfam10_domain_set_resources(device_t dev) #endif } -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA add_uma_resource(dev, 7); #endif @@ -1121,7 +1121,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) for (reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT // all nodes for (i = 0; i< sysconf.nodes; i++) { int index; @@ -1270,7 +1270,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } disable_siblings = !CONFIG_LOGICAL_CPUS; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS get_option(&disable_siblings, "multi_core"); #endif @@ -1376,7 +1376,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) * otherwise the device under it will not be scanned */ int linknum; -#if CONFIG_HT3_SUPPORT==1 +#if CONFIG_HT3_SUPPORT linknum = 8; #else linknum = 4; diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index a3afecb..efc0a48 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -222,7 +222,7 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) resource = amdfam12_find_iopair(dev, nodeid, link); if (resource) { u32 align; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT if((resource->index & 0x1fff) == 0x1110) { // ext align = 8; } @@ -248,7 +248,7 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags |= IORESOURCE_BRIDGE; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT if((resource->index & 0x1fff) == 0x1110) { // ext normalize_resource(resource); } @@ -265,7 +265,7 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT if((resource->index & 0x1fff) == 0x1110) { // ext normalize_resource(resource); } @@ -338,7 +338,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; static void add_uma_resource(struct device *dev, int index) @@ -525,7 +525,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if CONFIG_PCI_64BIT_PREF_MEM == 0 +#if !CONFIG_PCI_64BIT_PREF_MEM //- pci_domain_read_resources(dev); struct resource *resource; @@ -574,7 +574,7 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " amsr - incoming dev = %08lx\n",dev); -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; struct resource *res; #endif @@ -587,7 +587,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); for(link = dev->link_list; link; link = link->next) { @@ -711,10 +711,10 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas ram_resource(dev, idx, basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; @@ -740,12 +740,12 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas ram_resource(dev, (idx | 0), basek, sizek); idx += 0x10; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, " adsr - uma_memory_base = %x.\n",uma_memory_base); #else @@ -758,7 +758,7 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas printk(BIOS_DEBUG, " adsr - mmio_basek = %x.\n",mmio_basek); printk(BIOS_DEBUG, " adsr - high_tables_size = %x.\n",high_tables_size); -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA printk(BIOS_DEBUG, "adsr - adding uma resource.\n"); add_uma_resource(dev, 7); #endif diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 2647814..f7c3b8e 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -210,7 +210,7 @@ static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link) resource = amdfam14_find_iopair(dev, nodeid, link); if (resource) { u32 align; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT if ((resource->index & 0x1fff) == 0x1110) { // ext align = 8; } else @@ -235,7 +235,7 @@ static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link) resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags |= IORESOURCE_BRIDGE; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT if ((resource->index & 0x1fff) == 0x1110) { // ext normalize_resource(resource); } @@ -252,7 +252,7 @@ static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link) resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT if ((resource->index & 0x1fff) == 0x1110) { // ext normalize_resource(resource); } @@ -326,7 +326,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; static void add_uma_resource(struct device *dev, int index) @@ -508,7 +508,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if CONFIG_PCI_64BIT_PREF_MEM == 0 +#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); #else struct bus *link; @@ -538,7 +538,7 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "\nFam14h - domain_set_resources.\n"); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; struct resource *res; #endif @@ -551,7 +551,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); for (link = dev->link_list; link; link = link->next) { @@ -685,10 +685,10 @@ static void domain_set_resources(device_t dev) pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES if (high_tables_base == 0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; @@ -712,13 +712,13 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | 0), basek, sizek); idx += 0x10; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); if (high_tables_base == 0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base); #else @@ -732,7 +732,7 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n", high_tables_size); -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA printk(BIOS_DEBUG, "adsr - adding uma resource.\n"); add_uma_resource(dev, 7); #endif diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index d1a322c..130086e 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -406,7 +406,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 +#if CONFIG_MULTIPLE_VGA_ADAPTERS extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -540,7 +540,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if CONFIG_PCI_64BIT_PREF_MEM == 0 +#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); @@ -626,7 +626,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; static void add_uma_resource(struct device *dev, int index) { @@ -644,7 +644,7 @@ static void add_uma_resource(struct device *dev, int index) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; struct resource *res; #endif @@ -657,7 +657,7 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM for (link = dev->link_list; link; link = link->next) { /* Now reallocate the pci resources memory with the @@ -773,10 +773,10 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; @@ -798,19 +798,19 @@ static void domain_set_resources(device_t dev) } } -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA /* Deduct uma memory before reporting because * this is what the mtrr code expects */ sizek -= uma_memory_size / 1024; #endif ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; @@ -820,7 +820,7 @@ static void domain_set_resources(device_t dev) #endif } -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA add_uma_resource(dev, 7); #endif @@ -1022,7 +1022,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) * otherwise the device under it will not be scanned */ int linknum; -#if CONFIG_HT3_SUPPORT==1 +#if CONFIG_HT3_SUPPORT linknum = 8; #else linknum = 4; diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 9951806..2bd0411 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -976,7 +976,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #include "raminit.h" -#if CONFIG_AMDMCT == 0 +#if !CONFIG_AMDMCT //struct definitions @@ -1034,12 +1034,12 @@ struct nodes_info_t { } __attribute__((packed)); /* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/ -#if CONFIG_AMDMCT == 0 +#if !CONFIG_AMDMCT //#define MEM_CS_COPY 1 #define MEM_CS_COPY NODE_NUMS -#if CONFIG_MEM_TRAIN_SEQ == 0 +#if !CONFIG_MEM_TRAIN_SEQ #define DQS_DELAY_COPY NODE_NUMS #else // #define DQS_DELAY_COPY 1 @@ -1102,7 +1102,7 @@ struct sys_info { device_t get_node_pci(u32 nodeid, u32 fn); #endif -#if CONFIG_AMDMCT == 0 +#if !CONFIG_AMDMCT #ifdef __PRE_RAM__ static void soft_reset(void); diff --git a/src/northbridge/amd/amdfam10/conf.c b/src/northbridge/amd/amdfam10/conf.c index adfff0f..d8c161f 100644 --- a/src/northbridge/amd/amdfam10/conf.c +++ b/src/northbridge/amd/amdfam10/conf.c @@ -38,7 +38,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) dev = __f1_dev[0]; #endif -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT // I will use ext space only for simple pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8] d.mask = pci_read_config32(dev, 0x114); // enable is bit 0 @@ -61,12 +61,12 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -#if CONFIG_AMDMCT == 0 +#if !CONFIG_AMDMCT static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) { u32 i; device_t dev; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT // I will use ext space only for simple u32 d_base_i, d_base_d, d_mask_i, d_mask_d; d_base_i = nodeid | (0<<28); @@ -95,7 +95,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) dev = __f1_dev[i]; #endif -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT // I will use ext space only for simple pci_write_config32(dev, 0x110, d_base_i); pci_write_config32(dev, 0x114, d_base_d); //[47:27] at [28:8]; @@ -120,7 +120,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) } #endif -#if CONFIG_AMDMCT == 0 +#if !CONFIG_AMDMCT static void set_DctSelBaseAddr(u32 i, u32 sel_m) { device_t dev; diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index 2dc5427..c6f7c78 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -33,7 +33,7 @@ static inline void print_debug_addr(const char *str, void *val) static void print_debug_pci_dev(u32 dev) { -#if CONFIG_PCI_BUS_SEGN_BITS==0 +#if !CONFIG_PCI_BUS_SEGN_BITS printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); #else printk(BIOS_DEBUG, "PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 58f2cdd..bbf6b86 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -21,7 +21,7 @@ // mmconf is not ready yet static void set_bsp_node_CHtExtNodeCfgEn(void) { -#if CONFIG_EXT_RT_TBL_SUPPORT == 1 +#if CONFIG_EXT_RT_TBL_SUPPORT u32 dword; dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68); dword |= (1<<27) | (1<<25); @@ -112,7 +112,7 @@ static void enumerate_ht_chain(void) real_last_pos = pos; ht_dev_num++ ; #endif - #if CONFIG_HT_CHAIN_END_UNITID_BASE == 0 + #if !CONFIG_HT_CHAIN_END_UNITID_BASE if (!next_unitid) goto out; #endif diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 89bd673..0e80c71 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -31,7 +31,7 @@ #include <cpu/x86/lapic.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #include <pc80/mc146818rtc.h> #endif @@ -161,7 +161,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l #endif u32 max_devfn; -#if CONFIG_HT3_SUPPORT==1 +#if CONFIG_HT3_SUPPORT if(is_sublink1) { u32 regpos; u32 reg; @@ -192,7 +192,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l */ ht_c_index = get_ht_c_index(nodeid, link_num, &sysconf); -#if CONFIG_EXT_CONF_SUPPORT == 0 +#if !CONFIG_EXT_CONF_SUPPORT if(ht_c_index>=4) return max; #endif @@ -316,7 +316,7 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) #endif offset_unitid = 0; #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) - #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY if((nodeid == 0) && (sblink == link->link_num)) #endif offset_unitid = 1; @@ -434,7 +434,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) resource = amdfam10_find_iopair(dev, nodeid, link); if (resource) { u32 align; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT if((resource->index & 0x1fff) == 0x1110) { // ext align = 8; } @@ -460,7 +460,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags |= IORESOURCE_BRIDGE; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT if((resource->index & 0x1fff) == 0x1110) { // ext normalize_resource(resource); } @@ -477,7 +477,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT if((resource->index & 0x1fff) == 0x1110) { // ext normalize_resource(resource); } @@ -560,7 +560,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 +#if CONFIG_MULTIPLE_VGA_ADAPTERS extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -664,7 +664,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if CONFIG_PCI_64BIT_PREF_MEM == 0 +#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); #else struct bus *link; @@ -762,7 +762,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) // WHY this check? CONFIG_AMDMCT is enabled on all Fam10 boards. // Does it make sense not to? -#if CONFIG_AMDMCT == 0 +#if !CONFIG_AMDMCT static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; @@ -843,11 +843,11 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) #endif -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; static void add_uma_resource(struct device *dev, int index) @@ -865,7 +865,7 @@ static void add_uma_resource(struct device *dev, int index) static void amdfam10_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; struct resource *res; #endif @@ -878,7 +878,7 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM for(link = dev->link_list; link; link = link->next) { /* Now reallocate the pci resources memory with the @@ -960,7 +960,7 @@ static void amdfam10_domain_set_resources(device_t dev) reset_memhole = 0; } - #if CONFIG_AMDMCT == 0 + #if !CONFIG_AMDMCT //mmio_basek = 3*1024*1024; // for debug to meet boundary if(reset_memhole) { @@ -975,7 +975,7 @@ static void amdfam10_domain_set_resources(device_t dev) disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); } - #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 + #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC // We need to double check if the mmio_basek is valid for hole // setting, if it is equal to basek, we need to decrease it some resource_t basek_pri; @@ -1031,10 +1031,10 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; @@ -1045,7 +1045,7 @@ static void amdfam10_domain_set_resources(device_t dev) } #endif } - #if CONFIG_AMDMCT == 0 + #if !CONFIG_AMDMCT #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) { struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM @@ -1067,19 +1067,19 @@ static void amdfam10_domain_set_resources(device_t dev) } } -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA /* Deduct uma memory before reporting because * this is what the mtrr code expects */ sizek -= uma_memory_size / 1024; #endif ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; @@ -1089,7 +1089,7 @@ static void amdfam10_domain_set_resources(device_t dev) #endif } -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA add_uma_resource(dev, 7); #endif @@ -1109,7 +1109,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT // all nodes for(i = 0; i< sysconf.nodes; i++) { int index; @@ -1187,7 +1187,7 @@ static void sysconf_init(device_t dev) // first node sysconf.bsp_apicid = lapicid(); sysconf.apicid_offset = sysconf.bsp_apicid; -#if (CONFIG_ENABLE_APIC_EXT_ID == 1) +#if CONFIG_ENABLE_APIC_EXT_ID if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST)) { sysconf.enabled_apic_ext_id = 1; @@ -1265,7 +1265,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } disable_siblings = !CONFIG_LOGICAL_CPUS; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS get_option(&disable_siblings, "multi_core"); #endif @@ -1371,7 +1371,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) * otherwise the device under it will not be scanned */ int linknum; -#if CONFIG_HT3_SUPPORT==1 +#if CONFIG_HT3_SUPPORT linknum = 8; #else linknum = 4; diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index c48fca6..f1f22cb 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -127,7 +127,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b } } -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT // let's check that in extend space // use the nodeid extend space to find out the bus for the linkn u32 tempreg; diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 32908c4..ff444d5 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -28,7 +28,7 @@ */ /* Single CPU system? */ -#if (CONFIG_MAX_PHYSICAL_CPUS == 1) +#if CONFIG_MAX_PHYSICAL_CPUS #define HT_BUILD_NC_ONLY 1 #endif diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index e353edc..5aa3b31 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -2,7 +2,7 @@ #define AMDK8_H -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT #include "f.h" #else #include "pre_f.h" diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index a262686..636114d 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -160,7 +160,7 @@ static void disable_probes(void) #if 0 static void enable_apic_ext_id(u8 node) { -#if CONFIG_ENABLE_APIC_EXT_ID==1 +#if CONFIG_ENABLE_APIC_EXT_ID #warning "FIXME Is the right place to enable apic ext id here?" u32 val; @@ -284,8 +284,8 @@ static uint16_t read_freq_cap(device_t dev, uint8_t pos) freq_cap = pci_read_config16(dev, pos); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ -#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 - #if CONFIG_K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_HT_FREQ_1G_SUPPORT + #if !CONFIG_K8_REV_F_SUPPORT if (!is_cpu_pre_e0()) #endif { @@ -665,7 +665,7 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num) static void setup_uniprocessor(void) { print_spew("Enabling UP settings\n"); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; if (tmp>0) return; #endif @@ -1574,7 +1574,7 @@ static void clear_dead_routes(unsigned nodes) } #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS static unsigned verify_dualcore(unsigned nodes) { unsigned node, totalcpus, tmp; @@ -1593,10 +1593,10 @@ static unsigned verify_dualcore(unsigned nodes) static void coherent_ht_finalize(unsigned nodes) { unsigned node; -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT int rev_a0; #endif -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS unsigned total_cpus; if (read_option(multi_core, 0) == 0) { /* multi_core */ @@ -1614,7 +1614,7 @@ static void coherent_ht_finalize(unsigned nodes) */ print_spew("coherent_ht_finalize\n"); -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT rev_a0 = is_cpu_rev_a0(); #endif for (node = 0; node < nodes; node++) { @@ -1625,7 +1625,7 @@ static void coherent_ht_finalize(unsigned nodes) /* Set the Total CPU and Node count in the system */ val = pci_read_config32(dev, 0x60); val &= (~0x000F0070); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS val |= ((total_cpus-1)<<16)|((nodes-1)<<4); #else val |= ((nodes-1)<<16)|((nodes-1)<<4); @@ -1645,7 +1645,7 @@ static void coherent_ht_finalize(unsigned nodes) (3 << HTTC_HI_PRI_BYP_CNT_SHIFT); pci_write_config32(dev, HT_TRANSACTION_CONTROL, val); -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT if (rev_a0) { pci_write_config32(dev, 0x94, 0); pci_write_config32(dev, 0xb4, 0); @@ -1665,7 +1665,7 @@ static int apply_cpu_errata_fixes(unsigned nodes) device_t dev; uint32_t cmd; dev = NODE_MC(node); -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT if (is_cpu_pre_c0()) { /* Errata 66 @@ -1710,7 +1710,7 @@ static int apply_cpu_errata_fixes(unsigned nodes) #endif -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT /* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */ if (!is_cpu_pre_b3()) #endif diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index fd9fe60..4f9d8ca 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -57,7 +57,7 @@ static void dump_pci_device(unsigned dev) print_debug("\n"); } -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index); static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) { diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index f57eb5b..ee1945a 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -67,7 +67,7 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid device_t dev; //actually, only for one HT device HT chain, and unitid is 0 -#if CONFIG_HT_CHAIN_UNITID_BASE == 0 +#if !CONFIG_HT_CHAIN_UNITID_BASE if(offset_unitid) { return; } @@ -136,8 +136,8 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) /* AMD K8 Unsupported 1Ghz? */ if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { - #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 - #if CONFIG_K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_HT_FREQ_1G_SUPPORT + #if !CONFIG_K8_REV_F_SUPPORT if (is_cpu_pre_e0()) { // only E0 later support 1GHz freq_cap &= ~(1 << HT_FREQ_1000Mhz); } @@ -149,7 +149,7 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap); -#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 == 1 +#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 freq_cap &= 0x3f; printk(BIOS_INFO, "Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed.\n"); #endif @@ -539,7 +539,7 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num) unsigned devn = 1; #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) - #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY if(i==0) // to check if it is sb ht chain #endif devn = CONFIG_HT_CHAIN_UNITID_BASE; @@ -671,7 +671,7 @@ static int ht_setup_chains(uint8_t ht_c_num) #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) - #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY if(i==0) // to check if it is sb ht chain #endif offset_unitid = 1; diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 7ba2b90..cc69883 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -124,7 +124,7 @@ static void misc_control_init(struct device *dev) cmd = pci_read_config32(dev, 0x44); cmd |= (1<<6) | (1<<25); pci_write_config32(dev, 0x44, cmd ); -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT if (is_cpu_pre_c0()) { /* Errata 58 diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 90b4ebf..5eeeda2 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -20,7 +20,7 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/multicore.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <pc80/mc146818rtc.h> #endif @@ -256,7 +256,7 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max) #endif offset_unitid = 0; #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) - #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY if((nodeid == 0) && (sblink == link->link_num)) #endif offset_unitid = 1; @@ -494,7 +494,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 +#if CONFIG_MULTIPLE_VGA_ADAPTERS extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -635,7 +635,7 @@ static void amdk8_domain_read_resources(device_t dev) pci_domain_read_resources(dev); -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM /* Initialize the system wide prefetchable memory resources constraints */ resource = new_resource(dev, 2); resource->limit = 0xfcffffffffULL; @@ -818,11 +818,11 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) } #endif -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; static void add_uma_resource(struct device *dev, int index) @@ -840,7 +840,7 @@ static void add_uma_resource(struct device *dev, int index) static void amdk8_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; struct resource *res; #endif @@ -857,7 +857,7 @@ static void amdk8_domain_set_resources(device_t dev) io = find_resource(dev, 0); io->base = DEVICE_IO_START; #endif -#if CONFIG_PCI_64BIT_PREF_MEM == 1 +#if CONFIG_PCI_64BIT_PREF_MEM /* Now reallocate the pci resources memory with the * highest addresses I can manage. */ @@ -927,7 +927,7 @@ static void amdk8_domain_set_resources(device_t dev) * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. * otherwise We reset the hole to the mmio_basek */ - #if CONFIG_K8_REV_F_SUPPORT == 0 + #if !CONFIG_K8_REV_F_SUPPORT if (!is_cpu_pre_e0()) { #endif @@ -947,7 +947,7 @@ static void amdk8_domain_set_resources(device_t dev) disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); } - #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 + #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some u32 basek_pri; for (i = 0; i < fx_devs; i++) { @@ -968,7 +968,7 @@ static void amdk8_domain_set_resources(device_t dev) #endif } -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT } // is_cpu_pre_e0 #endif @@ -997,7 +997,7 @@ static void amdk8_domain_set_resources(device_t dev) } -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); if ((uma_memory_base >> 10) < mmio_basek) printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i); @@ -1014,10 +1014,10 @@ static void amdk8_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; @@ -1030,7 +1030,7 @@ static void amdk8_domain_set_resources(device_t dev) } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) - #if CONFIG_K8_REV_F_SUPPORT == 0 + #if !CONFIG_K8_REV_F_SUPPORT if(!is_cpu_pre_e0() ) #endif sizek += hoist_memory(mmio_basek,i); @@ -1049,7 +1049,7 @@ static void amdk8_domain_set_resources(device_t dev) /* If sizek == 0, it was split at mmio_basek without a hole. * Don't create an empty ram_resource. */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA /* Deduct uma memory before reporting because * this is what the mtrr code expects */ sizek -= uma_memory_size / 1024; @@ -1057,12 +1057,12 @@ static void amdk8_domain_set_resources(device_t dev) if (sizek) ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; @@ -1072,7 +1072,7 @@ static void amdk8_domain_set_resources(device_t dev) #endif } -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA add_uma_resource(dev, 7); #endif assign_resources(dev->link_list); @@ -1179,7 +1179,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) sysconf.apicid_offset = bsp_apicid; disable_siblings = !CONFIG_LOGICAL_CPUS; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS get_option(&disable_siblings, "multi_core"); #endif @@ -1248,7 +1248,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) // That is the typical case if(j == 0 ){ - #if CONFIG_K8_REV_F_SUPPORT == 0 + #if !CONFIG_K8_REV_F_SUPPORT e0_later_single_core = is_e0_later_in_bsp(i); // single core #else e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 9cb7c60..7db338b 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2289,7 +2289,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK; printk(BIOS_SPEW, "Handling memory hole at 0x%08x (default)\n", hole_startk); -#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 +#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC /* We need to double check if hole_startk is valid. * If it is equal to the dram base address in K (base_k), * we need to decrease it. @@ -2348,7 +2348,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) { int i; u32 whatWait = 0; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME int suspend = acpi_is_wakeup_early(); #else int suspend = 0; diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 33df485..af3a324 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -2965,7 +2965,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK; printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk); -#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 +#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC /* We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some */ uint32_t basek_pri; @@ -3009,7 +3009,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) } #endif -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME #include "exit_from_self.c" #endif @@ -3017,7 +3017,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) { int i; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME int suspend = acpi_is_wakeup_early(); #else int suspend = 0; @@ -3190,7 +3190,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, } -#if CONFIG_MEM_TRAIN_SEQ == 0 +#if !CONFIG_MEM_TRAIN_SEQ #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 dqs_timing(controllers, ctrl, tsc0, sysinfo); #else @@ -3210,7 +3210,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, dqs_timing(i, &ctrl[i], sysinfo, 1); -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ break; // only train the first node with ram #endif } diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 8ddd44f..c7f9e3e 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -1717,7 +1717,7 @@ static unsigned int range_to_mtrr(unsigned int reg, return reg; } -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ static void set_top_mem_ap(unsigned tom_k, unsigned tom2_k) { msr_t msr; @@ -1804,7 +1804,7 @@ static void set_htic_bit(unsigned i, unsigned val, unsigned bit) } -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ static unsigned get_htic_bit(unsigned i, unsigned bit) { uint32_t dword; @@ -1826,9 +1826,9 @@ static void set_sysinfo_in_ram(unsigned val) set_htic_bit(0, val, 9); } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME -#if CONFIG_MEM_TRAIN_SEQ == 0 +#if !CONFIG_MEM_TRAIN_SEQ static int save_index_to_pos(unsigned int dev, int size, int index, int nvram_pos) { u32 dword = pci_read_config32_index_wait(dev, 0x98, index); @@ -1865,7 +1865,7 @@ static int dqs_load_MC_NVRAM_ch(unsigned int dev, int ch, int pos) return pos; } -#if CONFIG_MEM_TRAIN_SEQ == 0 +#if !CONFIG_MEM_TRAIN_SEQ static int dqs_save_MC_NVRAM_ch(unsigned int dev, int ch, int pos) { /* 30 bytes per channel */ @@ -1914,7 +1914,7 @@ static void dqs_restore_MC_NVRAM(unsigned int dev) } #endif -#if CONFIG_MEM_TRAIN_SEQ == 0 +#if !CONFIG_MEM_TRAIN_SEQ #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 static void dqs_timing(int controllers, const struct mem_controller *ctrl, tsc_t *tsc0, struct sys_info *sysinfo) #else @@ -1981,7 +1981,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; printk(BIOS_DEBUG, " done\n"); sysinfo->mem_trained[i]=1; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME dqs_save_MC_NVRAM((ctrl+i)->f2); #endif } @@ -2013,7 +2013,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info if(sysinfo->mem_trained[i] != 0x80) return; -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ //need to enable mtrr, so dqs training could access the test address setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); #endif @@ -2059,7 +2059,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info } out: -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ clear_mtrr_dqs(sysinfo->tom2_k); #endif @@ -2076,7 +2076,7 @@ out: } #endif -#if CONFIG_MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox) { dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the output tidy @@ -2103,7 +2103,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy memcpy(sysinfo, sysinfox, CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); #endif set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's - #if CONFIG_AP_CODE_IN_CAR == 0 + #if !CONFIG_AP_CODE_IN_CAR printk(BIOS_DEBUG, "CODE IN ROM AND RUN ON NODE: %02x\n", nodeid); train_ram(nodeid, sysinfo, sysinfox); #else diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 4af75fd..00b1555 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -64,14 +64,14 @@ static u16 mctGet_NVbits(u8 index) //val = 2; /* S4 (Unbuffered SO-DIMMS) */ break; case NV_BYPMAX: -#if (CONFIG_GFXUMA == 0) +#if !CONFIG_GFXUMA val = 4; #elif (CONFIG_GFXUMA == 1) val = 7; #endif break; case NV_RDWRQBYP: -#if (CONFIG_GFXUMA == 0) +#if !CONFIG_GFXUMA val = 2; #elif (CONFIG_GFXUMA == 1) val = 3; @@ -113,7 +113,7 @@ static u16 mctGet_NVbits(u8 index) //val = 1; /* Enable */ break; case NV_BurstLen32: -#if (CONFIG_GFXUMA == 0) +#if !CONFIG_GFXUMA val = 0; /* 64 byte mode */ #elif (CONFIG_GFXUMA == 1) val = 1; /* 32 byte mode */ @@ -132,14 +132,14 @@ static u16 mctGet_NVbits(u8 index) //val = 1; /* enable */ break; case NV_BottomIO: -#if (CONFIG_GFXUMA == 0) +#if !CONFIG_GFXUMA val = 0xE0; /* address bits [31:24] */ #elif (CONFIG_GFXUMA == 1) val = 0xC0; /* address bits [31:24] */ #endif break; case NV_BottomUMA: -#if (CONFIG_GFXUMA == 0) +#if !CONFIG_GFXUMA val = 0xE0; /* address bits [31:24] */ #elif (CONFIG_GFXUMA == 1) val = 0xC0; /* address bits [31:24] */ diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index abbc855..5c59f73 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -66,7 +66,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER, }; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -113,7 +113,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index f567766..8da37b4 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -273,7 +273,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = PCI_DEVICE_ID_NS_GX2, }; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -294,7 +294,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); /* Systop - 0xc0000 -> KB */ -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 61f3afe..9ceceb8 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -372,7 +372,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = PCI_DEVICE_ID_AMD_LXBRIDGE, }; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -393,7 +393,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); // Systop - 0xc0000 -> KB -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index e6e955f..1fa77d7 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -9,7 +9,7 @@ #include <bitops.h> #include "chip.h" -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -89,7 +89,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 6a533cd..9046f43 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -10,7 +10,7 @@ #include "chip.h" #include "e7505.h" -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -90,7 +90,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index 49c8ba3..3b92aa8 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -16,7 +16,7 @@ static unsigned int max_bus; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -108,7 +108,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 5e9f9c5..ab88899 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -16,7 +16,7 @@ static unsigned int max_bus; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -108,7 +108,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index acd4c3c..db35b85 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -37,7 +37,7 @@ static u32 max_bus; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -129,7 +129,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index 926d5b3..050df95 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -1197,7 +1197,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) pci_write_config16(ctrl->f0, MCHSCRB, data16); /* The memory is now setup, use it */ -#if CONFIG_CACHE_AS_RAM == 0 +#if !CONFIG_CACHE_AS_RAM cache_lbmem(MTRR_TYPE_WRBACK); #endif } diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 136755e..18e5716 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -33,7 +33,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7190, }; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -72,7 +72,7 @@ static void i440bx_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index 73be101..f34b5ab 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -62,7 +62,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7180, }; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -101,7 +101,7 @@ static void i440lx_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 3434c6d..78e3728 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -83,7 +83,7 @@ static int translate_i82810_to_mb[] = { /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, }; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -147,7 +147,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index dea05db..93bdc28 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -64,7 +64,7 @@ int add_northbridge_resources(struct lb_memory *mem) return 0; } -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) @@ -116,7 +116,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index 53f5997..b59ba50 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -53,7 +53,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3580, }; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) @@ -109,7 +109,7 @@ static void pci_domain_set_resources(device_t dev) /* ram_resource(dev, idx++, 1024, tolmk - 1024); */ ram_resource(dev, idx++, 768, tolmk - 768); -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index a10bb4a..40b1aaa 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -93,7 +93,7 @@ static void add_fixed_resources(struct device *dev, int index) } } -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -181,7 +181,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index b1f7c72..b2baaa3 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -143,7 +143,7 @@ static void add_fixed_resources(struct device *dev, int index) } } -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -267,7 +267,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 7b7c67b..57245b6 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -105,7 +105,7 @@ static void add_fixed_resources(struct device *dev, int index) IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -192,7 +192,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables. */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index 48d830c..250ace0 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -32,7 +32,7 @@ #include <smbios.h> #include "chip.h" -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -69,7 +69,7 @@ static void cpu_pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index 2cc331b..74e0edf 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -177,7 +177,7 @@ static void ram_reservation(device_t dev, unsigned long index, } #endif -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -207,7 +207,7 @@ static void cn400_domain_set_resources(device_t dev) tolmk = tomk; } -#if CONFIG_WRITE_HIGH_TABLES == 1 +#if CONFIG_WRITE_HIGH_TABLES /* Locate the High Tables at the Top of Low Memory below the Video RAM */ high_tables_base = ((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index 6400e22..ced4c2f 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -97,7 +97,7 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL, }; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -138,7 +138,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if CONFIG_WRITE_HIGH_TABLES == 1 +#if CONFIG_WRITE_HIGH_TABLES high_tables_base = ((tolmk - CONFIG_VIDEO_MB * 1024) * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index 9e30298..4fca723 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -32,7 +32,7 @@ #include "chip.h" #include "northbridge.h" -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -74,7 +74,7 @@ static void pci_domain_set_resources(device_t dev) tolmk -= 1024; // TOP 1M SM Memory } -#if CONFIG_WRITE_HIGH_TABLES == 1 +#if CONFIG_WRITE_HIGH_TABLES high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 3a7ada5..92adf32 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -45,7 +45,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x0601, /* 0x8601 is the AGP bridge? */ }; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -89,7 +89,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if CONFIG_WRITE_HIGH_TABLES == 1 +#if CONFIG_WRITE_HIGH_TABLES high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 19f14d5..5ea2212 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -105,7 +105,7 @@ static const struct pci_driver agp_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8633_1, }; -#if CONFIG_WRITE_HIGH_TABLES==1 +#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif @@ -149,7 +149,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if CONFIG_WRITE_HIGH_TABLES == 1 +#if CONFIG_WRITE_HIGH_TABLES high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c index 5e82262..f4798c9 100644 --- a/src/northbridge/via/vx800/examples/chipset_init.c +++ b/src/northbridge/via/vx800/examples/chipset_init.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME #include <arch/acpi.h> #endif #include "../vx800.h" @@ -607,7 +607,7 @@ void init_VIA_chipset(void) void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME void *wake_vec; #endif diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index d5b1c18..df57a7e 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -89,7 +89,7 @@ static int lsmbus_block_write(device_t dev, uint8_t cmd, u8 bytes, const u8 *buf } -#if CONFIG_GENERATE_ACPI_TABLES == 1 +#if CONFIG_GENERATE_ACPI_TABLES unsigned pm_base; #endif @@ -162,7 +162,7 @@ static void acpi_init(struct device *dev) (on*12)+(on>>1),(on&1)*5); } -#if CONFIG_GENERATE_ACPI_TABLES == 1 +#if CONFIG_GENERATE_ACPI_TABLES pm_base = pci_read_config16(dev, 0x58) & 0xff00; printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base); #endif diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 401c039..ce7707b 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -22,7 +22,7 @@ #include <arch/romcc_io.h> -#if CONFIG_CONSOLE_POST == 1 +#if CONFIG_CONSOLE_POST /* Data */ #define UART_RBR 0x00 diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index c899320..3f647c8 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -31,7 +31,7 @@ #include "smbus.h" -#if CONFIG_RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO /** * @brief Get SouthBridge device number * @param[in] bus target bus number diff --git a/src/southbridge/amd/cimx/sb700/sb_cimx.h b/src/southbridge/amd/cimx/sb700/sb_cimx.h index 632e4cd..8e62048 100644 --- a/src/southbridge/amd/cimx/sb700/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb700/sb_cimx.h @@ -40,7 +40,7 @@ void sb_Late_Post(void); void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base); void sb7xx_51xx_disable_wideio(u8 wio_index); -#if CONFIG_RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO /** * @brief Get SouthBridge device number, called by finalize_node_setup() * @param[in] bus target bus number diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 7dc752a..22d7724 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -158,7 +158,7 @@ typedef union _PCI_ADDR { #include "vendorcode/amd/cimx/sb800/AMDSBLIB.h" -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME #include "spi.h" #endif diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 2b73155..71fea67 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -26,7 +26,7 @@ #include <arch/io.h> #include <arch/acpi.h> -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME int acpi_get_sleep_type(void) { u16 tmp = inw(PM1_CNT_BLK_ADDRESS); @@ -75,7 +75,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) if (!sb_config) return; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME if (acpi_get_sleep_type() == 3) sb_config->S3Resume = 1; #endif diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index f692897..c0f8533 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -30,7 +30,7 @@ #include "cbmem.h" -#if CONFIG_RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO /** * @brief Get SouthBridge device number * @param[in] bus target bus number @@ -82,7 +82,7 @@ void sb800_clk_output_48Mhz(void) *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME int acpi_is_wakeup_early(void) { return (acpi_get_sleep_type() == 3); diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index c69782b..0ce82b3 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -161,7 +161,7 @@ static const struct pci_driver raid5_driver __pci_driver = { .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5, }; -#if CONFIG_USBDEBUG == 1 +#if CONFIG_USBDEBUG static void usb_set_resources(struct device *dev) { struct resource *res; @@ -480,7 +480,7 @@ static void sb800_enable(device_t dev) /* call the CIMX entry at the last sb800 device, * so make sure the mainboard devicetree is complete */ -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME if (acpi_slp_type != 3) sb_Before_Pci_Init(); else diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h index 5e510de..9916c81 100644 --- a/src/southbridge/amd/cimx/sb800/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h @@ -40,7 +40,7 @@ int acpi_is_wakeup_early(void); */ void sb800_clk_output_48Mhz(void); -#if CONFIG_RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO /** * @brief Get SouthBridge device number, called by finalize_node_setup() * @param[in] bus target bus number diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index e84743b..61c3c3e 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -22,7 +22,7 @@ #include <arch/romcc_io.h> -#if CONFIG_CONSOLE_POST == 1 +#if CONFIG_CONSOLE_POST /* Data */ #define UART_RBR 0x00 diff --git a/src/southbridge/amd/cs5530/vga.c b/src/southbridge/amd/cs5530/vga.c index 4a26251..56bea45 100644 --- a/src/southbridge/amd/cs5530/vga.c +++ b/src/southbridge/amd/cs5530/vga.c @@ -41,7 +41,7 @@ #include <cpu/amd/gx1def.h> #include <delay.h> -#if CONFIG_GX1_VIDEO == 1 +#if CONFIG_GX1_VIDEO /* * Some register descriptions that are no listed in cpu/amd/gx1def.h */ @@ -397,7 +397,7 @@ static void cs5530_activate_video(u32 io_base, const struct video_mode *mode) write32(io_base + CS5530_DISPLAY_CONFIG, val | 0x0020002F); } -#if CONFIG_SPLASH_GRAPHIC == 1 +#if CONFIG_SPLASH_GRAPHIC /* * This bitmap file must provide: diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c index 5d816e5..9eb47bb 100644 --- a/src/southbridge/amd/rs690/ht.c +++ b/src/southbridge/amd/rs690/ht.c @@ -27,7 +27,7 @@ static void ht_dev_set_resources(device_t dev) { -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT unsigned reg; device_t k8_f1; resource_t rbase, rend; @@ -86,7 +86,7 @@ static void ht_dev_set_resources(device_t dev) static void ht_dev_read_resources(device_t dev) { -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT struct resource *res; printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); @@ -95,7 +95,7 @@ static void ht_dev_read_resources(device_t dev) pci_dev_read_resources(dev); -#if CONFIG_EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT /* Add an MMCONFIG resource. */ res = new_resource(dev, 0x1C); res->base = EXT_CONF_BASE_ADDRESS; diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index 8adf1f6..0540823 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -101,7 +101,7 @@ static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, } } /* family 10 only, for reg > 0xFF */ -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask, u32 val) { diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 29a6394..e8d4596 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -659,7 +659,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) pointer = (u32 *)&vgainfo; for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) { -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA *GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i; #else *GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i; @@ -775,7 +775,7 @@ static void rs780_internal_gfx_enable(device_t dev) device_t nb_dev = dev_find_slot(0, 0); msr_t sysmem; -#if (CONFIG_GFXUMA == 0) +#if !CONFIG_GFXUMA u32 FB_Start, FB_End; #endif @@ -818,7 +818,7 @@ static void rs780_internal_gfx_enable(device_t dev) set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f); set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA /* GFX_InitUMA. */ /* Copy CPU DDR Controller to NB MC. */ device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index 717aeab..9b153aa 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -220,7 +220,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) /* Program Straps. */ romstrap2 = 1 << 26; // enables audio function -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA extern uint64_t uma_memory_size; // bits 7-9: aperture size // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g diff --git a/src/southbridge/amd/sb600/ide.c b/src/southbridge/amd/sb600/ide.c index e38e83f..3fa31ea 100644 --- a/src/southbridge/amd/sb600/ide.c +++ b/src/southbridge/amd/sb600/ide.c @@ -45,7 +45,7 @@ static void ide_init(struct device *dev) dword |= 1 << 2; pci_write_config16(dev, 0x4, dword); -#if CONFIG_PCI_ROM_RUN == 1 +#if CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 2dc84d8..c890ad9 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -715,7 +715,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME int acpi_is_wakeup_early(void) { u16 tmp; diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c index 5f415fb..19d4ed5 100644 --- a/src/southbridge/amd/sb700/ide.c +++ b/src/southbridge/amd/sb700/ide.c @@ -60,7 +60,7 @@ static void ide_init(struct device *dev) pci_write_config8(sm_dev, 0xAD, byte); } -#if CONFIG_PCI_ROM_RUN == 1 +#if CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif } diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 5dd7d69..c968927 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -73,7 +73,7 @@ static void lpc_init(device_t dev) /* hack, but the whole sb700 startup lacks any device which is doing the acpi init */ -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME { extern u8 acpi_slp_type; u16 tmp = inw(ACPI_PM1_CNT_BLK); diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index 165c72d..d358ee8 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -75,7 +75,7 @@ void sb7xx_51xx_setup_sata_phys(struct device *dev); #endif -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME int acpi_is_wakeup_early(void); #endif diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 50f4ff7..a85f490 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -665,7 +665,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME static int acpi_is_wakeup_early(void) { u16 tmp; diff --git a/src/southbridge/amd/sb800/ide.c b/src/southbridge/amd/sb800/ide.c index eb287f2..a63878b 100644 --- a/src/southbridge/amd/sb800/ide.c +++ b/src/southbridge/amd/sb800/ide.c @@ -58,7 +58,7 @@ static void ide_init(struct device *dev) pci_write_config8(dev, 0xAD, byte); } -#if CONFIG_PCI_ROM_RUN == 1 +#if CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif } diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c index 387c402..0fa9a4e 100644 --- a/src/southbridge/broadcom/bcm5780/nic.c +++ b/src/southbridge/broadcom/bcm5780/nic.c @@ -26,7 +26,7 @@ static void nic_init(struct device *dev) { -#if CONFIG_PCI_ROM_RUN == 1 +#if CONFIG_PCI_ROM_RUN pci_dev_init(dev);// it will init option rom #endif diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index 65af02a..b4d9493 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -31,7 +31,7 @@ #include "i82371eb.h" #include "smbus.h" -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME extern u8 acpi_slp_type; int acpi_get_sleep_type(void); #endif @@ -92,7 +92,7 @@ static void pwrmgt_enable(struct device *dev) outw(0xffff, DEFAULT_PMBASE + GLBSTS); outl(0xffffffff, DEFAULT_PMBASE + DEVSTS); -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME /* this reads PMCNTRL, so we have to call it before writing the * default value */ acpi_slp_type = acpi_get_sleep_type(); diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index dfe9ff2..505d059 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -82,7 +82,7 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 +#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY #define CK804B_DEVN_BASE 1 #else #define CK804B_DEVN_BASE CK804_DEVN_BASE diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index bb0fd13..efe1b99 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -72,7 +72,7 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 +#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY #define CK804B_DEVN_BASE 1 #else #define CK804B_DEVN_BASE CK804_DEVN_BASE diff --git a/src/southbridge/nvidia/ck804/ide.c b/src/southbridge/nvidia/ck804/ide.c index ac94acb..c7236ec 100644 --- a/src/southbridge/nvidia/ck804/ide.c +++ b/src/southbridge/nvidia/ck804/ide.c @@ -60,7 +60,7 @@ static void ide_init(struct device *dev) dword |= 12; pci_write_config32(dev, 0xf8, dword); -#if CONFIG_PCI_ROM_RUN == 1 +#if CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif } diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c index ca6cd94..c62728a 100644 --- a/src/southbridge/nvidia/ck804/nic.c +++ b/src/southbridge/nvidia/ck804/nic.c @@ -108,7 +108,7 @@ static void nic_init(struct device *dev) nic_index++; -#if CONFIG_PCI_ROM_RUN == 1 +#if CONFIG_PCI_ROM_RUN pci_dev_init(dev); /* It will init Option ROM. */ #endif } diff --git a/src/southbridge/nvidia/mcp55/ide.c b/src/southbridge/nvidia/mcp55/ide.c index 0677a75..6d0cebf 100644 --- a/src/southbridge/nvidia/mcp55/ide.c +++ b/src/southbridge/nvidia/mcp55/ide.c @@ -61,7 +61,7 @@ static void ide_init(struct device *dev) dword = pci_read_config32(dev, 0xf8); dword |= 12; pci_write_config32(dev, 0xf8, dword); -#if CONFIG_PCI_ROM_RUN == 1 +#if CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif } diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c index d74f10d..0521b89 100644 --- a/src/southbridge/nvidia/mcp55/nic.c +++ b/src/southbridge/nvidia/mcp55/nic.c @@ -180,7 +180,7 @@ static void nic_init(struct device *dev) nic_index++; -#if CONFIG_PCI_ROM_RUN == 1 +#if CONFIG_PCI_ROM_RUN pci_dev_init(dev);// it will init option rom #endif diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 3b11dd3..a945f23 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -94,7 +94,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -#if CONFIG_GENERATE_ACPI_TABLES == 1 +#if CONFIG_GENERATE_ACPI_TABLES unsigned pm_base; #endif @@ -113,7 +113,7 @@ static void mcp55_sm_read_resources(device_t dev) static void mcp55_sm_init(device_t dev) { -#if CONFIG_GENERATE_ACPI_TABLES == 1 +#if CONFIG_GENERATE_ACPI_TABLES struct resource *res; res = find_resource(dev, 0x60); diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c index 90ea002..d067b5c 100644 --- a/src/southbridge/sis/sis966/ide.c +++ b/src/southbridge/sis/sis966/ide.c @@ -144,7 +144,7 @@ print_debug("IDE_INIT:---------->\n"); dword = pci_read_config32(dev, 0xf8); dword |= 12; pci_write_config32(dev, 0xf8, dword); -#if CONFIG_PCI_ROM_RUN == 1 +#if CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index e25535b..0c820c0 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -327,7 +327,7 @@ void enable_rom_decode(void) pci_write_config8(dev, 0x41, 0x7f); } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME static int acpi_is_wakeup_early(void) { device_t dev; u16 tmp; diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 7fc5b52..a47ab38 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -244,7 +244,7 @@ static void setup_pm(device_t dev) /* SCI is generated for RTC/pwrBtn/slpBtn. */ tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); #endif diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index 1afa57e..e681d6e 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -131,7 +131,7 @@ static void vt1211_pnp_set_resources(struct device *dev) { struct resource *res; -#if CONFIG_CONSOLE_SERIAL8250 == 1 +#if CONFIG_CONSOLE_SERIAL8250 /* TODO: Do the same for SP2? */ if (dev->path.pnp.device == VT1211_SP1) { for (res = dev->resource_list; res; res = res->next) {

1 0

New patch to review for coreboot: e9bfd63 Add a tool to work on i915 hardware in user mode
by Stefan Reinauer 05 May '12

05 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1003 -gerrit commit e9bfd63e863eb3a57e697e10e84c211a2ee4a7e5 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 4 15:37:18 2012 -0700 Add a tool to work on i915 hardware in user mode This is the beginning of a tool that transforms the i9x5 code to user mode code. Consider this a very early stage although it does produce two programs. Requires spatch 1.0 or greater. To try it out, assuming you have an up-to-date spatch, sh transform make make broken Please don't fall to the temptation to auto-magicize this process. It's primitive for a reason. That said, suggestions welcome of course. Change-Id: I0188e36637b198b06c17f6d3c714d990e88bd57d Signed-off-by: Ronald G. Minnich <rminnich(a)chromium.org> --- util/i915tool/Makefile | 20 + util/i915tool/README | 11 + util/i915tool/main.c | 255 +++++++++++++ util/i915tool/pci.c | 97 +++++ util/i915tool/plusplusplus | 3 + util/i915tool/spatches/deldev.cocci | 29 ++ util/i915tool/spatches/drm_crtc.cocci | 32 ++ util/i915tool/spatches/fixcalls.cocci | 148 ++++++++ util/i915tool/spatches/fx.cocci | 10 + util/i915tool/spatches/getdrmmodefn.cocci | 6 + util/i915tool/spatches/getfn.cocci | 61 +++ util/i915tool/spatches/i915_dma.c.cocci | 3 + util/i915tool/spatches/i915_drv.c.cocci | 8 + util/i915tool/spatches/i915_drv.cocci | 178 +++++++++ util/i915tool/spatches/intel_bios.cocci | 7 + util/i915tool/spatches/intel_display.c.cocci | 507 ++++++++++++++++++++++++++ util/i915tool/spatches/removeinclude.cocci | 6 + util/i915tool/spatches/ringbuffer.cocci | 14 + util/i915tool/transform | 151 ++++++++ util/i915tool/video.h | 133 +++++++ 20 files changed, 1679 insertions(+), 0 deletions(-) diff --git a/util/i915tool/Makefile b/util/i915tool/Makefile new file mode 100644 index 0000000..4cd807a --- /dev/null +++ b/util/i915tool/Makefile @@ -0,0 +1,20 @@ +source=main.c pci.c final/intel_bios.c final/drm_modes.c final/i915_drv.c + +all: probe + +broken: video + +video: $(source) final/intel_display.c + cc -include video.h -Iinputs -static -g -o video $(source) \ + -lpci final/intel_display.c + +probe: $(source) + cc -include video.h -Iinputs -static -g -o probe $(source) -lpci +clean: + rm -f *.o video probe + +moreclean: clean + rm final/* per-file-changes/* tmp/* + +superclean: moreclean + rm inputs/* diff --git a/util/i915tool/README b/util/i915tool/README new file mode 100644 index 0000000..cb5f986 --- /dev/null +++ b/util/i915tool/README @@ -0,0 +1,11 @@ +spatches are the semantic patches +tmp is just tmp +inputs are copied from $LINUX +per-file-changes contain input files that have specific transforms +final contains the final form of the file, with 'global' changes applied (e.g. kzalloc -> calloc) + +transform copies files from $LINUX and then transforms them for use by stand-alone program/coreboot + +The Makefile is simple; this runs 'fast enough' that a complicated Makefile is not worth it. + +There's still some duct tape here but it's getting there. diff --git a/util/i915tool/main.c b/util/i915tool/main.c new file mode 100644 index 0000000..cb828e1 --- /dev/null +++ b/util/i915tool/main.c @@ -0,0 +1,255 @@ +/* + * This file is part of i915tool + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "video.h" + +int verbose = 1; +static unsigned short addrport, dataport; +struct drm_device *i915; +unsigned short vendor=0x8086, device=0x0116; +struct pci_dev fake = {.vendor_id=0x8086, .device_id = 0x0116}; +int dofake = 0; +u8 *bios_image = NULL; +u8 *mmiobase; +u32 mmiophys; +int mmiosize; +size_t bios_image_size; +/* temporary */ +unsigned int i915_lvds_downclock = 0; +int i915_vbt_sdvo_panel_type = -1; + +/* */ + +/* not sure how we want to do this so let's guess */ +/* to make it easy, we start at zero and assume 250 hz. */ +unsigned long msecs(void) +{ + struct timeval start, now; + static int first = 0; + unsigned long j; + if (! first++) + gettimeofday(&start, NULL); + gettimeofday(&now, NULL); + j = (now.tv_sec - start.tv_sec)*1000 + (now.tv_usec-start.tv_usec)/1000; + return j; +} + +void +mdelay(unsigned long ms) +{ + unsigned long start; + start = msecs(); + while (msecs() < (start + ms)) + ; +} + +void +hexdump(u8 *base, int size) +{ + int i, j; + for(i = 0; i < size/sizeof(u32); i += 8) { + printf("%#x: ", i); + for(j = 0; j < 8; j++) + printf("%08x", base[i+j]); + printf("\n"); + } +} +void udelay(int i) +{ + printf("UDELAY!\n"); +} + +unsigned long io_I915_READ(unsigned long addr) +{ + unsigned long val; + if (dofake) + return 0xcafebabe; + outl(addr, addrport); + val = inl(dataport); + if (verbose) + fprintf(stderr, "%s: %x <- %x\n", __func__, val, addr); + return val; +} + +void io_I915_WRITE(unsigned long addr, unsigned long val) +{ + if (dofake) + return; + outl(addr, addrport); + outl(val, dataport); + if (verbose) + fprintf(stderr, "%s: %x -> %x\n", __func__, val, addr); +} + +unsigned long I915_READ(unsigned long addr) +{ + volatile u32 *ptr = (u32 *)(mmiobase + addr); + unsigned long val; + if (dofake) + return 0xcafebabe; + val = *ptr; + if (verbose) + fprintf(stderr, "%s: %x <- %x\n", __func__, val, addr); + return val; +} + +void I915_WRITE(unsigned long addr, unsigned long val) +{ + volatile u32 *ptr = (u32 *)(mmiobase + addr); + if (dofake) + return; + *ptr = val; + if (verbose) + fprintf(stderr, "%s: %x -> %x\n", __func__, val, addr); +} + +u16 I915_READ16(unsigned long addr) +{ + volatile u16 *ptr = (u16 *)(mmiobase + addr); + unsigned long val; + if (dofake) + return 0xbabe; + val = *ptr; + if (verbose) + fprintf(stderr, "%s: %x <- %x\n", __func__, val, addr); + return val; +} + +void I915_WRITE16(unsigned long addr, u16 val) +{ + volatile u16 *ptr = (u16 *)(mmiobase + addr); + if (dofake) + return; + *ptr = val; + if (verbose) + fprintf(stderr, "%s: %x -> %x\n", __func__, val, addr); +} + +#define GTT_RETRY 1000 +static int gtt_poll(u32 reg, u32 mask, u32 value) +{ + unsigned try = GTT_RETRY; + u32 data; + + while (try--) { + data = I915_READ(reg); + if ((data & mask) == value){ + printf("succeeds after %d tries\n", GTT_RETRY-try); + return 1; + } + udelay(10); + } + + fprintf(stderr, "GT init timeout\n"); + return 0; +} +void *pci_map_rom(struct pci_dev *dev, size_t *size) +{ + *size = bios_image_size; + return bios_image; +} + +void *pci_unmap_rom(struct pci_dev *dev, void *bios) +{ + return NULL; +} + +void *dmi_check_system(unsigned long ignore) +{ + return NULL; +} + +void +mapit(void) +{ + int kfd; + kfd = open("/dev/mem", O_RDWR); + if (kfd < 0) + errx(1, "/dev/kmem"); + mmiobase = mmap(NULL, mmiosize, PROT_WRITE|PROT_READ, MAP_SHARED, kfd, + mmiophys); + if ((void *)-1 == mmiobase) + errx(1, "mmap"); +} + +void +devinit() +{ + u32 val; + /* force wake. */ + I915_WRITE(0xa18c, 1); + gtt_poll(0x130090, 1, 1); +} +int main(int argc, char *argv[]) +{ + struct pci_dev *pci_dev_find(struct drm_device *dev); + + for(argc--, argv++; argc; argc--, argv++) { + if (argv[0][0] != '-') + break; + if (!strcmp(argv[0], "-f")) + dofake++; + } + i915 = calloc(1, sizeof(*i915)); + i915->dev_private = calloc(1, sizeof(*i915->dev_private)); + /* until we do a bit more w/ coccinelle */ + i915->dev_private->dev = i915; + + if (dofake) { + i915->pdev = &fake; + if (! find_idlist(i915, vendor, device)) + errx(1, "can't find fake device in pciidlist"); + } else { + if (! pci_dev_find(i915)) + errx(1, "No VGA device of any kind found\n"); + } + + if (argc) { + FILE *fd; + int amt; + /* size it later */ + bios_image = malloc(8*1048576); + fd = fopen(argv[0], "r"); + amt = fread(bios_image, 65536, 128, fd); + if (amt < 1) { + free(bios_image); + } else { + i915->bios_bin = bios_image; + i915->dev_private->opregion.vbt = bios_image; + bios_image_size = amt * 65536; + fclose(fd); + } + } + /* get the base address for the mmio indirection registers -- BAR 2 */ + addrport = i915->pdev->base_addr[4] & ~3; + dataport = addrport + 4; + printf("Addrport is at %x, dataport at %x\n", addrport, dataport); + /* get the base of the mmio space */ + mmiophys = i915->pdev->base_addr[0] & ~0xf; + mmiosize = i915->pdev->size[0]; + printf("phys base is %#x, size %d\n", mmiophys, mmiosize); + mapit(); + devinit(); + //hexdump(mmiobase, mmiosize); + /* we should use ioperm but hey ... it's had troubles */ + iopl(3); + intel_setup_bios(i915); + if (i915->bios_bin) + intel_parse_bios(i915); +} diff --git a/util/i915tool/pci.c b/util/i915tool/pci.c new file mode 100644 index 0000000..ca942dc --- /dev/null +++ b/util/i915tool/pci.c @@ -0,0 +1,97 @@ +/* + * This file is part of i915tool + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "video.h" + +int find_idlist(struct drm_device *dev, u16 vendor, u16 device) +{ + extern const struct pci_device_id pciidlist[]; + int succ = 0; + int i; + for(i = 0; pciidlist[i].vendor && !succ; i++){ + if (vendor == pciidlist[i].vendor && device == + pciidlist[i].device){ + dev->dev_private->info = + (void *)(pciidlist[i].driver_data); + succ = 1; + } + } + return succ; +} + +/* there's only going to be one device ... */ +int pci_dev_find(struct drm_device *dev) +{ + struct pci_access *pacc = NULL; + struct pci_dev *temp; + int succ = 0; + pacc = pci_alloc(); + if (! pacc) + return 0; + pci_init(pacc); + pci_scan_bus(pacc); + + for (temp = pacc->devices; temp && ! dev->pdev; temp = temp->next){ + if ((temp->device_class & 0xff00) == PCI_CLASS_DISPLAY_VGA ) { + pci_fill_info(temp, PCI_FILL_IDENT | + PCI_FILL_BASES | PCI_FILL_CLASS); + dev->pdev = temp; + } + } + + if (dev->pdev) + succ = find_idlist(dev, dev->pdev->vendor_id, + dev->pdev->device_id); + return succ; +} + +/* Support library for kernel style pci functions. We could do a semantic + * patch for it but this is easier to debug as we can fill it with prints + * if we want. And no cpp abuse here. Keep it simple. + */ + +void pci_read_config_byte(struct pci_dev *dev, unsigned long offset, u8 *val) +{ + *val = pci_read_byte(dev, offset); +} + +void pci_write_config_byte(struct pci_dev *dev, unsigned long offset, u8 val) +{ + pci_write_byte(dev, offset, val); +} + +void pci_read_config_word(struct pci_dev *dev, unsigned long offset, u16 *val) +{ + *val = pci_read_word(dev, offset); +} + +void pci_write_config_word(struct pci_dev *dev, unsigned long offset, u16 val) +{ + pci_write_word(dev, offset, val); +} + +void pci_read_config_dword(struct pci_dev *dev, unsigned long offset, u32 *val) +{ + *val = pci_read_long(dev, offset); +} + +void pci_write_config_dword(struct pci_dev *dev, unsigned long offset, u32 val) +{ + pci_write_long(dev, offset, val); +} diff --git a/util/i915tool/plusplusplus b/util/i915tool/plusplusplus new file mode 100644 index 0000000..a5dcd19 --- /dev/null +++ b/util/i915tool/plusplusplus @@ -0,0 +1,3 @@ +#!/bin/bash +sed 's,^\+\+\+.*,+++ '$2',' < $1 > $1.pat + diff --git a/util/i915tool/spatches/deldev.cocci b/util/i915tool/spatches/deldev.cocci new file mode 100644 index 0000000..504dae7 --- /dev/null +++ b/util/i915tool/spatches/deldev.cocci @@ -0,0 +1,29 @@ +@@ +identifier dev; +expression i; +@@ +-struct drm_i915_private *dev = i; ++extern struct drm_device *i915; struct drm_i915_private *dev = i915->dev_private; +@@ +identifier dev; +expression i; +@@ +-struct pci_dev *dev = i; ++extern struct drm_device *i915; struct pci_dev *dev = i915->pdev; +@@ +@@ +-#include "i915_drm.h" +@@ +@@ +-#include "drm.h" +@@ +@@ +-#include "drmP.h" +@@ +@@ +-#include "i915_trace.h" +@@ +identifier d; +@@ +-(d)->pci_device ++(d)->pdev->device_id diff --git a/util/i915tool/spatches/drm_crtc.cocci b/util/i915tool/spatches/drm_crtc.cocci new file mode 100644 index 0000000..662f253 --- /dev/null +++ b/util/i915tool/spatches/drm_crtc.cocci @@ -0,0 +1,32 @@ +@@ +identifier s; +identifier head; +@@ +struct s {... +- struct list_head head; +...}; +@@ +@@ +-#include <...> +@@ +@@ +( +-struct drm_crtc_funcs{...}; +| +-struct drm_crtc{...}; +| +-struct drm_connector_funcs{...}; +| +-struct drm_encoder_funcs{...}; +| +-struct drm_encoder{...}; +| +-struct drm_connector{...}; +| +-struct drm_mode_config_funcs{...}; +| +-struct drm_mode_config{...}; +| +-struct drm_framebuffer_funcs{...}; +) + diff --git a/util/i915tool/spatches/fixcalls.cocci b/util/i915tool/spatches/fixcalls.cocci new file mode 100644 index 0000000..50e6458 --- /dev/null +++ b/util/i915tool/spatches/fixcalls.cocci @@ -0,0 +1,148 @@ +@@ +identifier f; +type T; +@@ +T f(...){<... +-vga_get_uninterruptible(...); +...>} +@@ +identifier f; +type T; +@@ +T f(...){<... +-vga_put(...); +...>} +@@ +identifier f; +type T; +@@ +T f(...){<... +-intel_init_quirks(...); +...>} +@@ +identifier f; +type T; +@@ +T f(...){<... +-drm_mode_config_init(...); +...>} +@@ +identifier f; +type T; +@@ +T f(...){<... +-INIT_WORK(...); +...>} +@@ +identifier f; +type T; +@@ +T f(...){<... +-setup_timer(...); +...>} +@@ +identifier f; +type T; +@@ +T f(...){<... +-DRM_DEBUG_KMS( ++fprintf(stderr, +...); +...>} +@@ +identifier f; +type T; +@@ +T f(...){<... +-DRM_ERROR( ++fprintf(stderr, +...); +...>} +@@ +identifier f; +type T; +@@ +T f(...){<... +-DRM_DEBUG( ++fprintf(stderr, +...); +...>} +@@ +identifier f; +type T; +@@ +T f(...){<... +-DRM_DEBUG_DRIVER( ++fprintf(stderr, +...); +...>} +@@ +identifier f; +type T; +@@ +T f(...){<... +-intel_init_display(...); +...>} +@ rulekz @ +identifier t; +identifier f; +expression E1, E2; +type T; +@@ +T f(...){<... +t = kzalloc(E1, E2); +...>} +@@ +identifier rulekz.f; +expression E1, E2; +@@ + +- kzalloc(E1 ++ calloc(1, E1 +- ,E2 + ) +@@ +identifier d; +@@ +-static +const struct pci_device_id d[] = {...}; +@@ +expression E1; +@@ +-WARN( ++if ( +E1 +-, ++) fprintf(stderr, +...); +@@ +expression E1; +@@ +-BUG_ON( ++assert( +E1); +@@ +@@ +-jiffies ++msecs() +@@ +expression E1; +@@ +-jiffies_to_msecs( +E1 +-) +@@ +expression E1; +@@ +-msecs_to_jiffies( +E1 +-) +@@ +expression E1, E2; +@@ +-time_after( ++( +E1 +-, ++> +E2) diff --git a/util/i915tool/spatches/fx.cocci b/util/i915tool/spatches/fx.cocci new file mode 100644 index 0000000..e47ddca --- /dev/null +++ b/util/i915tool/spatches/fx.cocci @@ -0,0 +1,10 @@ +@@ +identifier f; +type T; +@@ +T f(...){... +-$DRM_DEBUG_KMS|DRM_ERRRO$( ++fprintf(stderr, +...); +...} + diff --git a/util/i915tool/spatches/getdrmmodefn.cocci b/util/i915tool/spatches/getdrmmodefn.cocci new file mode 100644 index 0000000..d5cd17e --- /dev/null +++ b/util/i915tool/spatches/getdrmmodefn.cocci @@ -0,0 +1,6 @@ +@@ +@@ +- drm_mode_set_name(...) {...} +@@ +@@ +- drm_mode_debug_printmodeline(...) {...} diff --git a/util/i915tool/spatches/getfn.cocci b/util/i915tool/spatches/getfn.cocci new file mode 100644 index 0000000..8dea561 --- /dev/null +++ b/util/i915tool/spatches/getfn.cocci @@ -0,0 +1,61 @@ +@@ +@@ +- get_blocksize(...) {...} +@@ +@@ +- lvds_dvo_timing_equal_size(...) {...} +@@ +@@ +- fill_detail_timing_data(...) {...} +@@ +@@ +- intel_setup_bios(...) {...} +@@ +@@ +- intel_parse_bios(...){...} +@@ +@@ +- init_vbt_defaults(...){...} +@@ +@@ +- parse_general_features(...){...} +@@ +@@ +- parse_general_definitions(...){...} +@@ +@@ +- parse_lfp_panel_data(...){...} +@@ +@@ +- parse_sdvo_panel_data(...){...} +@@ +@@ +- parse_sdvo_device_mapping(...){...} +@@ +@@ +- parse_device_mapping(...){...} +@@ +@@ +- parse_driver_features(...){...} +@@ +@@ +- parse_edp(...){...} +@@ +@@ +- find_section(...){...} +@@ +@@ +- get_lvds_dvo_timing(...){...} +@@ +@@ +- intel_bios_ssc_frequency(...){...} +@@ +identifier d; +type T; +@@ +- static T d; +@@ +expression S; +identifier d; +@@ +-#define d S diff --git a/util/i915tool/spatches/i915_dma.c.cocci b/util/i915tool/spatches/i915_dma.c.cocci new file mode 100644 index 0000000..0ae2d55 --- /dev/null +++ b/util/i915tool/spatches/i915_dma.c.cocci @@ -0,0 +1,3 @@ +@@ +@@ +- i915_driver_load(...) {...} diff --git a/util/i915tool/spatches/i915_drv.c.cocci b/util/i915tool/spatches/i915_drv.c.cocci new file mode 100644 index 0000000..0d64d93 --- /dev/null +++ b/util/i915tool/spatches/i915_drv.c.cocci @@ -0,0 +1,8 @@ +@inteldeviceinfo@ +identifier d; +@@ +-const struct intel_device_info d = {...}; +@@ +identifier d; +@@ +-static const struct pci_device_id d[] = {...}; diff --git a/util/i915tool/spatches/i915_drv.cocci b/util/i915tool/spatches/i915_drv.cocci new file mode 100644 index 0000000..633e270 --- /dev/null +++ b/util/i915tool/spatches/i915_drv.cocci @@ -0,0 +1,178 @@ +@@ +identifier d; +@@ +( +-struct drm_i915_fence_reg{...}; +| +-struct drm_i915_error_state{...}; +| +-struct drm_i915_gem_object{...}; +| +-struct drm_i915_display_funcs {...}; +| +-struct drm_i915_gem_phys_object{...}; +| +-struct mem_block{...}; +| +-struct drm_i915_gem_request{...}; +| +-struct drm_i915_file_private{...}; +| +-struct drm_i915_master_private{...}; +| +-struct intel_gmbus{...}; +| +-struct work_struct d; +| +-struct mem_*d; +| +-struct timer_list d; +| +-struct intel_fbc_work *d; +| +-struct drm_i915_error_state *d; +| +-struct i2c_adapter d; +| +-struct i2c_adapter *d; +| +-struct intel_hw_status_page{...}; +| +-struct intel_hw_status_page d; +) +@@ +@@ +-#include<...> +@@ +identifier d; +@@ +struct s {... +- struct drm_i915_display_funcs d; +... +}; +@@ +identifier d; +@@ +struct s {... +-struct notifier_block d; +... +}; +@@ +identifier s; +identifier d; +@@ +struct s {... +-spinlock_t d; +... +}; +@@ +identifier s; +identifier d; +@@ +struct s {... +-atomic_t d; +... +}; +@@ +identifier s; +identifier d; +@@ +struct s {... +-drm_dma_handle_t *d; +... +}; +@@ +identifier s; +identifier d; +@@ +struct s {... +-drm_local_map_t d; +... +}; +@@ +identifier s; +identifier d; +@@ +struct s {... +-spinlock_t *d; +... +}; +@@ +identifier s; +identifier d; +@@ +struct s {... +-struct i2c_adapter d; +... +}; +@@ +identifier s; +identifier d; +@@ +struct s {... +-struct i2c_adapter *d; +... +}; +@@ +identifier s; +identifier d; +@@ +struct s {... +( +-struct inteL_gmbus {...} *d; +| +-struct drm_i915_gem_object *d; +) +... +}; +@@ +identifier s; +identifier d; +@@ +struct s {... +-struct work_struct d; +... +}; +@@ +identifier s; +identifier d; +@@ +struct s {... +-struct resource d; +... +}; +@@ +identifier s; +identifier d; +@@ +struct s {... +-struct timer_list d; +... +}; +@@ +identifier s; +identifier d; +@@ +struct s {... +-wait_queue_head_t d; +... +}; +@@ +identifier s; +identifier d; +constant c; +@@ +struct s {... +-struct intel_ring_buffer d[c]; +... +}; +@@ +identifier s; +identifier d; +constant c; +@@ +struct s {... +-struct drm_i915_fence_reg d[c]; +... +}; + diff --git a/util/i915tool/spatches/intel_bios.cocci b/util/i915tool/spatches/intel_bios.cocci new file mode 100644 index 0000000..2e71363 --- /dev/null +++ b/util/i915tool/spatches/intel_bios.cocci @@ -0,0 +1,7 @@ +@@ +@@ +-#include<...> ++#include "video.h" +@@ +@@ +-#include"..." diff --git a/util/i915tool/spatches/intel_display.c.cocci b/util/i915tool/spatches/intel_display.c.cocci new file mode 100644 index 0000000..d7d87d3 --- /dev/null +++ b/util/i915tool/spatches/intel_display.c.cocci @@ -0,0 +1,507 @@ +@@ +@@ +-struct intel_limit {... }; +@@ +identifier d; +@@ +- intel_limit_t d = {...}; +@@ +@@ +- intel_connector_attach_encoder(...){...} +@@ +@@ +- intel_modeset_cleanup(...){...} +@@ +@@ +- intel_modeset_gem_init(...){...} +@@ +@@ +- intel_modeset_init(...){...} +@@ +@@ +- i915_disable_vga(...){...} +@@ +@@ +- intel_init_quirks(...){...} +@@ +@@ +- quirk_ssc_force_disable(...){...} +@@ +@@ +- quirk_pipea_force (...){...} +@@ +@@ +- intel_init_display(...){...} +@@ +@@ +- intel_init_clock_gating(...){...} +@@ +@@ +- ironlake_enable_rc6(...){...} +@@ +@@ +- ironlake_disable_rc6(...){...} +@@ +@@ +- ironlake_teardown_rc6(...){...} +@@ +@@ +- cpt_init_clock_gating(...){...} +@@ +@@ +- ibx_init_clock_gating(...){...} +@@ +@@ +- i830_init_clock_gating(...){...} +@@ +@@ +- i85x_init_clock_gating(...){...} +@@ +@@ +- gen3_init_clock_gating(...){...} +@@ +@@ +- broadwater_init_clock_gating(...){...} +@@ +@@ +- crestline_init_clock_gating(...){...} +@@ +@@ +- g4x_init_clock_gating(...){...} +@@ +@@ +- ivybridge_init_clock_gating(...){...} +@@ +@@ +- gen6_init_clock_gating(...){...} +@@ +@@ +- ironlake_init_clock_gating(...){...} +@@ +@@ +- gen6_update_ring_freq(...){...} +@@ +@@ +- gen6_enable_rps(...){...} +@@ +@@ +- intel_init_emon(...){...} +@@ +@@ +- gen6_disable_rps(...){...} +@@ +@@ +- gen6_set_rps(...){...} +@@ +@@ +- ironlake_disable_drps(...){...} +@@ +@@ +- ironlake_enable_drps(...){...} +@@ +@@ +- intel_user_framebuffer_destroy(...){...} +@@ +@@ +- intel_setup_outputs(...){...} +@@ +@@ +- intel_crtc_init(...){...} +@@ +@@ +- intel_crtc_reset(...){...} +@@ +@@ +- intel_prepare_page_flip(...){...} +@@ +@@ +- intel_finish_page_flip_plane(...){...} +@@ +@@ +- intel_finish_page_flip(...){...} +@@ +@@ +- intel_unpin_work_fn(...){...} +@@ +@@ +- intel_crtc_destroy(...){...} +@@ +@@ +- intel_mark_busy(...){...} +@@ +@@ +- intel_idle_update(...){...} +@@ +@@ +- intel_decrease_pllclock(...){...} +@@ +@@ +- intel_increase_pllclock(...){...} +@@ +@@ +- intel_crtc_idle_timer(...){...} +@@ +@@ +- intel_gpu_idle_timer(...){...} +@@ +@@ +- ivb_update_cursor(...){...} +@@ +@@ +- i9xx_update_cursor(...){...} +@@ +@@ +- i845_update_cursor(...){...} +@@ +@@ +- intel_crtc_load_lut(...){...} +@@ +@@ +- ironlake_update_pch_refclk(...){...} +@@ +@@ +- intel_update_watermarks(...){...} +@@ +@@ +- sandybridge_update_wm(...){...} +@@ +@@ +- ironlake_update_wm(...){...} +@@ +@@ +- i830_update_wm(...){...} +@@ +@@ +- i9xx_update_wm(...){...} +@@ +@@ +- i965_update_wm(...){...} +@@ +@@ +- g4x_update_wm(...){...} +@@ +@@ +- pineview_update_wm(...){...} +@@ +@@ +- pineview_disable_cxsr(...){...} +@@ +@@ +- intel_encoder_destroy(...){...} +@@ +@@ +- intel_encoder_commit (...){...} +@@ +@@ +- intel_encoder_prepare (...){...} +@@ +@@ +- ironlake_crtc_commit(...){...} +@@ +@@ +- ironlake_crtc_prepare(...){...} +@@ +@@ +- i9xx_crtc_commit(...){...} +@@ +@@ +- i9xx_crtc_prepare(...){...} +@@ +@@ +- intel_crtc_disable(...){...} +@@ +@@ +- intel_crtc_dpms(...){...} +@@ +@@ +- i9xx_crtc_dpms(...){...} +@@ +@@ +- i9xx_crtc_disable(...){...} +@@ +@@ +- i9xx_crtc_enable(...){...} +@@ +@@ +- intel_crtc_dpms_overlay(...){...} +@@ +@@ +- ironlake_crtc_dpms(...){...} +@@ +@@ +- ironlake_crtc_disable(...){...} +@@ +@@ +- ironlake_crtc_enable(...){...} +@@ +@@ +- intel_cpt_verify_modeset(...){...} +@@ +@@ +- ironlake_pch_enable(...){...} +@@ +@@ +- intel_crtc_wait_for_pending_flips(...){...} +@@ +@@ +- intel_clear_scanline_wait(...){...} +@@ +@@ +- ironlake_fdi_disable(...){...} +@@ +@@ +- cpt_phase_pointer_disable(...){...} +@@ +@@ +- ironlake_fdi_pll_enable(...){...} +@@ +@@ +- ivb_manual_fdi_link_train(...){...} +@@ +@@ +- gen6_fdi_link_train(...){...} +@@ +@@ +- ironlake_fdi_link_train(...){...} +@@ +@@ +- cpt_phase_pointer_enable(...){...} +@@ +@@ +- intel_fdi_normal_train(...){...} +@@ +@@ +- ironlake_set_pll_edp(...){...} +@@ +@@ +- intel_update_fbc(...){...} +@@ +@@ +- intel_disable_fbc(...){...} +@@ +@@ +- intel_enable_fbc(...){...} +@@ +@@ +- intel_cancel_fbc_work(...){...} +@@ +@@ +- intel_fbc_work_fn(...){...} +@@ +@@ +- ironlake_disable_fbc(...){...} +@@ +@@ +- ironlake_enable_fbc(...){...} +@@ +@@ +- sandybridge_blit_fbc_update(...){...} +@@ +@@ +- g4x_disable_fbc(...){...} +@@ +@@ +- g4x_enable_fbc(...){...} +@@ +@@ +- i8xx_enable_fbc(...){...} +@@ +@@ +- i8xx_disable_fbc(...){...} +@@ +@@ +- intel_disable_pll(...){...} +@@ +@@ +- intel_enable_pll(...){...} +@@ +@@ +- intel_clock(...){...} +@@ +@@ +- pineview_clock(...){...} +@@ +@@ +- intel_ironlake_limit(...){...} +@@ +@@ +- intel_g4x_limit(...){...} +@@ +@@ +- intel_limit(...){...} +@@ +@@ +- intel_pipe_has_type(...){...} +@@ +@@ +- intel_PLL_is_valid(...){...} +@@ +@@ +- intel_find_best_PLL(...){...} +@@ +@@ +- intel_g4x_find_best_PLL(...){...} +@@ +@@ +- intel_find_pll_ironlake_dp(...){...} +@@ +@@ +- intel_fbc_enabled(...){...} +@@ +@@ +- intel_pin_and_fence_fb_obj(...){...} +@@ +@@ +- i9xx_update_plane(...){...} +@@ +@@ +- ironlake_update_plane(...){...} +@@ +@@ +- intel_pipe_set_base_atomic(...){...} +@@ +@@ +- intel_pipe_set_base(...){...} +@@ +@@ +- intel_crtc_driving_pch(...){...} +@@ +@@ +- intel_crtc_mode_fixup(...){...} +@@ +@@ +- single_enabled_crtc(...){...} +@@ +@@ +- g4x_compute_wm0(...){...} +@@ +@@ +- g4x_compute_srwm(...){...} +@@ +@@ +- ironlake_compute_srwm(...){...} +@@ +@@ +- intel_panel_use_ssc(...){...} +@@ +@@ +- intel_choose_pipe_bpp_dither(...){...} +@@ +@@ +- i9xx_crtc_mode_set(...){...} +@@ +@@ +- ironlake_crtc_mode_set(...){...} +@@ +@@ +- intel_crtc_mode_set(...){...} +@@ +@@ +- intel_crtc_update_cursor(...){...} +@@ +@@ +- intel_crtc_cursor_set(...){...} +@@ +@@ +- intel_crtc_cursor_move(...){...} +@@ +@@ +- intel_crtc_fb_gamma_set(...){...} +@@ +@@ +- intel_crtc_fb_gamma_get(...){...} +@@ +@@ +- intel_crtc_gamma_set(...){...} +@@ +@@ +- intel_framebuffer_create(...){...} +@@ +@@ +- intel_framebuffer_size_for_mode(...){...} +@@ +@@ +- intel_framebuffer_create_for_mode(...){...} +@@ +@@ +- mode_fits_in_fbdev(...){...} +@@ +@@ +- intel_get_load_detect_pipe(...){...} +@@ +@@ +- intel_release_load_detect_pipe(...){...} +@@ +@@ +- intel_crtc_clock_get(...){...} +@@ +@@ +- intel_crtc_mode_get(...){...} +@@ +@@ +- do_intel_finish_page_flip(...){...} +@@ +@@ +- intel_gen2_queue_flip(...){...} +@@ +@@ +- intel_gen3_queue_flip(...){...} +@@ +@@ +- intel_gen4_queue_flip(...){...} +@@ +@@ +- intel_gen6_queue_flip(...){...} +@@ +@@ +- intel_gen7_queue_flip(...){...} +@@ +@@ +- intel_default_queue_flip(...){...} +@@ +@@ +- intel_crtc_page_flip(...){...} +@@ +@@ +- intel_get_pipe_from_crtc_id(...){...} +@@ +@@ +- intel_encoder_clones(...){...} +@@ +@@ +- intel_user_framebuffer_create_handle(...){...} +@@ +@@ +- intel_framebuffer_init(...){...} +@@ +@@ +- intel_user_framebuffer_create(...){...} +@@ +@@ +- intel_alloc_context_page(...){...} +@@ +@@ +- ironlake_setup_rc6(...){...} +@@ +@@ +- intel_best_encoder(...){...} +@@ +identifier d; +@@ +- struct drm_framebuffer_funcs d = {...}; +@@ +identifier d; +@@ +- struct drm_mode_config_funcs d = {...}; +@@ +identifier d; +@@ +-static struct drm_crtc_helper_funcs d = {...}; +@@ +identifier d; +@@ +-static struct drm_crtc_funcs d = {...}; +@@ +identifier d; +@@ +- struct intel_quirk d[] = {...}; diff --git a/util/i915tool/spatches/removeinclude.cocci b/util/i915tool/spatches/removeinclude.cocci new file mode 100644 index 0000000..ff1bfea --- /dev/null +++ b/util/i915tool/spatches/removeinclude.cocci @@ -0,0 +1,6 @@ +@@ +@@ +-#include<...> +@@ +@@ +-#include"..." diff --git a/util/i915tool/spatches/ringbuffer.cocci b/util/i915tool/spatches/ringbuffer.cocci new file mode 100644 index 0000000..68f0c98 --- /dev/null +++ b/util/i915tool/spatches/ringbuffer.cocci @@ -0,0 +1,14 @@ +@@ +identifier d; +type T; +@@ +-T d(...){...} +@@ +identifier d; +type T; +@@ +-T d(...); +@@ +identifier d; +@@ +-struct d{...}; diff --git a/util/i915tool/transform b/util/i915tool/transform new file mode 100644 index 0000000..3e191cb --- /dev/null +++ b/util/i915tool/transform @@ -0,0 +1,151 @@ +#!/bin/bash +# This script has been honed over quite a few iterations. The trick is to make +# it easy for you to see what transformations occur +# without burying you in files. +# Also, coccinelle is not perfect, so we have to help her at times. As she +# gets smarter, we can shrink thigns we do in here. +# So we get input files, then do per-file changes, then do all-file changes +# I've deliberately made this script simple. Please don't decide it needs to +# be automagic. Just let it work in its simple way. Also, if you change even +# one simple thing, ALWAYS rerun this script do make sure you did not make a +# global test. NEVER test one little thing in isolation. That way +# lies madness. +# The only thing you need to set is +# export LINUX=/path/to/your/linux/tree. +# Order in which we do things. +# 1. Get source files into inputs. +# 2. cp them to per-file-changes +# Note that we even copy ones that might not currently need per-file +# changes. Because they may in future and it keeps the script simple. +# We tried both ways and like this best. +# 3. run 'ed' across a few files that need it +# 4. run coccinelle with any per-file changes +# There is some ugliness here as we have to do a reverse patch step. Sorry. +# 5. cp per-file-changes/* to final +# 6. run coccinelle files that apply to more than one file +# it's best to run coccinelle on as many files as possible, she's pretty +# smart about +# certain transformations, e.g. if you remove a function definition she can +# remove all calls to that function (usually) +# +# Now you can +# make (will build all working tools) +# or +# make broken +# for things that don't build yet. + +# Step 1 +rm inputs/* per-file-changes/* final/* tmp/* +cp $LINUX/drivers/gpu/drm/i915/i915_reg.h inputs +cp $LINUX/drivers/gpu/drm/i915/i915_drv.? inputs +cp $LINUX/drivers/gpu/drm/i915/intel_display.c inputs +cp $LINUX/drivers/gpu/drm/i915/intel_bios.c inputs +cp $LINUX/drivers/gpu/drm/i915/intel_bios.h inputs +cp $LINUX/drivers/gpu/drm/i915/intel_ringbuffer.h inputs +cp $LINUX/drivers/gpu/drm/i915/i915_dma.c inputs +cp $LINUX/include/drm/drm_crtc.h inputs +cp $LINUX/include/drm/drm_mode.h inputs +cp $LINUX/include/drm/drm_dp_helper.h inputs +cp $LINUX/drivers/gpu/drm/drm_modes.c inputs + +# Step 2 +cp inputs/* per-file-changes + +# Step 3 +# We tried sed but it had some issues that ed did not +# coccinelle can't handle anonymous structs +# also some stuff is easier with ed. +# also there are bugs spatches/in coccinelle it seems :-( +# the literal deletes below suck and we need to figure +# out wtf went wrong. +ed per-file-changes/i915_drv.h << EOF +/intel_gtt/ +. +?struct *{?,/mm;/d +. +/i915_trace.h/ +. +.,/#define POSTING_READ16/d +/struct *intel_gmbus/ +.,/\*gmb/d +. +g/notifier_block/d +g/struct *drm_i915_display_funcs *display;/d +g/struct *completion *[a-z].*;/d +w +q +EOF + +ed per-file-changes/drm_crtc.h <<EOF +/drm_crtc_init/,/endif/-d +w +q +EOF + +ed per-file-changes/intel_display.c << EOF +g/mode_config.funcs *=/d +g/fb_base/d +g/const/s/// +w +q +EOF + +# Reverse patches. We hope these will go away someday. +>per-file-changes/intel_bios.c +spatch -sp_file spatches/getfn.cocci inputs/intel_bios.c -U 0 > tmp/res +./plusplusplus tmp/res per-file-changes/intel_bios.c +(cd per-file-changes/; patch -p1 -R ) < tmp/res.pat + +>per-file-changes/drm_modes.c +spatch -sp_file spatches/getdrmmodefn.cocci inputs/drm_modes.c -U 0 \ + > tmp/drm_modes +./plusplusplus tmp/drm_modes per-file-changes/drm_modes.c +(cd per-file-changes/; patch -p1 -R ) < tmp/drm_modes.pat + +spatch -sp_file spatches/i915_dma.c.cocci inputs/i915_dma.c -U 0 \ + > tmp/i915_dma.c.patch +./plusplusplus tmp/i915_dma.c.patch per-file-changes/i915_dma.c +# This is the only way I can make sure the right file gets patched! +# someone tell me why. It keeps picking the wrong one. +(cd per-file-changes/; patch -p1 -R ) < tmp/i915_dma.c.patch.pat +spatch --in-place -sp_file spatches/fixcalls.cocci per-file-changes/i915_dma.c +#patch -p0 -R < tmp/i915_dma.c.patch.pat + +#echo '#include "video.h"' +>per-file-changes/i915_drv.c +spatch -sp_file spatches/i915_drv.c.cocci inputs/i915_drv.c -U 0 \ + > tmp/i915_drv.c.patch +./plusplusplus tmp/i915_drv.c.patch per-file-changes/i915_drv.c +# This is the only way I can make sure the right file gets patched! +# someone tell me why. It keeps picking the wrong one. +(cd per-file-changes/; patch -p1 -R ) < tmp/i915_drv.c.patch.pat +spatch --in-place -sp_file spatches/fixcalls.cocci per-file-changes/i915_drv.c + +# Finally, a basic spatch sequence! + +spatch --in-place -sp_file \ + spatches/intel_display.c.cocci per-file-changes/intel_display.c \ + > /dev/null + +spatch --in-place -sp_file spatches/i915_drv.cocci \ + per-file-changes/i915_drv.h >/dev/null + +# Now do the common changes to all files. +cp per-file-changes/* final +spatch --in-place -sp_file spatches/ringbuffer.cocci \ + final/intel_ringbuffer.h >/dev/null +spatch --in-place -sp_file spatches/removeinclude.cocci \ + final/intel_display.c > /dev/null +spatch --in-place -sp_file spatches/fixcalls.cocci final/intel_display.c \ + >/dev/null +spatch --in-place -sp_file spatches/ringbuffer.cocci final/drm_dp_helper.h\ + >/dev/null +spatch --in-place -sp_file spatches/removeinclude.cocci final/drm_dp_helper.h\ + >/dev/null +spatch --in-place -sp_file spatches/i915_drv.cocci final/intel_ringbuffer.h\ + >/dev/null +spatch --in-place -sp_file spatches/deldev.cocci final/intel_bios.c \ + final/intel_bios.h final/i915_drv.h final/intel_ringbuffer.h>/dev/null +spatch --in-place -sp_file spatches/fixcalls.cocci final/intel_bios.c \ + >/dev/null +spatch --in-place -sp_file spatches/drm_crtc.cocci final/drm_crtc.h >/dev/null diff --git a/util/i915tool/video.h b/util/i915tool/video.h new file mode 100644 index 0000000..6919830 --- /dev/null +++ b/util/i915tool/video.h @@ -0,0 +1,133 @@ +/* cocci issues ;-( */ +#ifndef VIDEO_H +#define VIDEO_H 1 +#include <stdio.h> +#include <stdlib.h> +#include <assert.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <sys/mman.h> +#include <fcntl.h> +#include <string.h> +#include <pci/pci.h> +#include <sys/io.h> +#include <sys/time.h> +#include <linux/types.h> +/* stuff we can't get coccinelle to do yet */ +#define __iomem +#define __read_mostly +#define __always_unused +#define module_param_named(a, b, c, d) +#define MODULE_PARM_DESC(a, b) +#define DRM_DEBUG_KMS printf +#define CONFIG_DRM_I915_KMS 1 +#define module_init(x); +#define module_exit(x); + +#define MODULE_AUTHOR(x) +#define MODULE_DESCRIPTION(x) +#define MODULE_LICENSE(a) +#define MODULE_DEVICE_TABLE(a, b) + +/* constants that will never change from linux/vga.h */ +/* Legacy VGA regions */ +#define VGA_RSRC_NONE 0x00 +#define VGA_RSRC_LEGACY_IO 0x01 +#define VGA_RSRC_LEGACY_MEM 0x02 +#define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM) +/* Non-legacy access */ +#define VGA_RSRC_NORMAL_IO 0x04 +#define VGA_RSRC_NORMAL_MEM 0x08 + + +/* define in pci.h! */ +#include <pci/pci.h> +/* idiocy. how many names to we need for a type? */ +typedef u32 uint32_t; +typedef u64 uint64_t; +/* WTF */ +typedef int bool; +enum {false = 0, true}; + +/* we define our own. The kernel one is too full of stuff. */ +struct mode_config { + int num_fb; + int num_connector; + int num_crtc; + int num_encoder; + int min_width, min_height, max_width, max_height; +}; + +struct drm_device { + struct pci_dev *pdev; + u8 *bios_bin; + struct drm_i915_private *dev_private; + struct mode_config mode_config; +}; + +/* we're willing to define our own here because it's relatively unchanging */ +#define PCI_ANY_ID (~0) + +struct pci_device_id { + u32 vendor, device; /* Vendor and device ID or PCI_ANY_ID*/ + u32 subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ + u32 class, class_mask; /* (class,subclass,prog-if) triplet */ + unsigned long driver_data; /* Data private to the driver */ +}; + + +/* per the cocinelle people, they can't handle this. + * It also almost never changes */ +#define INTEL_VGA_DEVICE(id, info) { \ + .class = PCI_CLASS_DISPLAY_VGA << 8, \ + .class_mask = 0xff0000, \ + .vendor = 0x8086, \ + .device = id, \ + .subvendor = PCI_ANY_ID, \ + .subdevice = PCI_ANY_ID, \ + .driver_data = (unsigned long) info } + +#define wait_for(condition, time) (sleep(1+time/50) && (!condition)) + + +/* random crap from kernel.h. + * Kernel.h is a catch-all for all kinds of junk and it's + * not worth using coccinelle (yet) to pull it apart. Maybe later. + * And, yes, gcc still does not have nelem! + */ +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1) +#define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask)) +#define ALIGN(x, a) __ALIGN_KERNEL((x), (a)) +#define __ALIGN_MASK(x, mask) __ALIGN_KERNEL_MASK((x), (mask)) +#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a))) +#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) + + +/* temporary. */ +void *dmi_check_system(unsigned long); + +#include "final/drm_dp_helper.h" +#include "final/i915_reg.h" +#include "final/i915_drv.h" +#include "final/drm_mode.h" +#include "final/drm_crtc.h" + +unsigned long I915_READ(unsigned long addr); +void I915_WRITE(unsigned long addr, unsigned long val); +u16 I915_READ16(unsigned long addr); +void I915_WRITE16(unsigned long addr, u16 val); +unsigned long msecs(void); +void mdelay(unsigned long ms); + +/* these should be the same. */ +#define POSTING_READ I915_READ +#define POSTING_READ16 I915_READ16 + +void *pci_map_rom(struct pci_dev *dev, size_t *size); +void *pci_unmap_rom(struct pci_dev *dev, void *p); +extern unsigned int i915_lvds_downclock; +extern int i915_vbt_sdvo_panel_type; +unsigned long lvds_do_not_use_alternate_frequency; +#endif /* VIDEO_H */

1 0

Patch set updated for coreboot: ce910c0 Add SPI driver
by Stefan Reinauer 04 May '12

04 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/997 -gerrit commit ce910c08abdc68d5e5e3e7e62628ae361b3db83b Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 2 17:07:05 2012 -0700 Add SPI driver This driver is taken from u-boot and adapted to match coreboot. It still contains some hacks and is ICH specific at places. Change-Id: I97dd8096f7db3b62f8f4f4e4d08bdee10d88f689 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/drivers/Kconfig | 1 + src/drivers/Makefile.inc | 1 + src/drivers/spi/Kconfig | 73 +++ src/drivers/spi/Makefile.inc | 12 + src/drivers/spi/eon.c | 161 ++++++ src/drivers/spi/macronix.c | 220 +++++++++ src/drivers/spi/spansion.c | 241 +++++++++ src/drivers/spi/spi_flash.c | 309 ++++++++++++ src/drivers/spi/spi_flash_internal.h | 81 +++ src/drivers/spi/sst.c | 268 ++++++++++ src/drivers/spi/stmicro.c | 250 ++++++++++ src/drivers/spi/winbond.c | 218 ++++++++ src/include/device/pci_ids.h | 4 + src/include/spi.h | 203 ++++++++ src/include/spi_flash.h | 91 ++++ src/northbridge/intel/sandybridge/raminit.c | 1 + src/southbridge/intel/bd82x6x/Kconfig | 1 + src/southbridge/intel/bd82x6x/Makefile.inc | 2 + src/southbridge/intel/bd82x6x/spi.c | 712 +++++++++++++++++++++++++++ 19 files changed, 2849 insertions(+), 0 deletions(-) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 259bc29..60e5b65 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -26,3 +26,4 @@ source src/drivers/oxford/Kconfig source src/drivers/sil/Kconfig source src/drivers/trident/Kconfig source src/drivers/ics/Kconfig +source src/drivers/spi/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 5f6dadf..851a4df 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -26,4 +26,5 @@ subdirs-y += oxford subdirs-y += sil subdirs-y += trident subdirs-y += ics +subdirs-y += spi subdirs-$(CONFIG_ARCH_X86) += pc80 diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig new file mode 100644 index 0000000..849d0ac --- /dev/null +++ b/src/drivers/spi/Kconfig @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The Chromium OS Authors. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SPI + bool + default n + help + Select this option if your chipset driver needs to store certain + data in the SPI flash. + +config SPI_FLASH_EON + bool + default y + depends on SPI + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by EON. + +config SPI_FLASH_MACRONIX + bool + default y + depends on SPI + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by Macronix. + +config SPI_FLASH_SPANSION + bool + default y + depends on SPI + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by Spansion. + +config SPI_FLASH_SST + bool + default y + depends on SPI + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by SST. + +config SPI_FLASH_STMICRO + bool + default y + depends on SPI + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by ST MICRO. + +config SPI_FLASH_WINBOND + bool + default y + depends on SPI + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by Winbond. diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc new file mode 100644 index 0000000..6cdf398 --- /dev/null +++ b/src/drivers/spi/Makefile.inc @@ -0,0 +1,12 @@ +# SPI driver interface +ramstage-$(CONFIG_SPI) += spi_flash.c + +# drivers +ramstage-$(CONFIG_SPI_FLASH_EON) += eon.c +ramstage-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c +ramstage-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c +ramstage-$(CONFIG_SPI_FLASH_SST) += sst.c +ramstage-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c +ramstage-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c +ramstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c + diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c new file mode 100644 index 0000000..4056953 --- /dev/null +++ b/src/drivers/spi/eon.c @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2010, ucRobotics Inc. + * Author: Chong Huang <chuang(a)ucrobotics.com> + * Licensed under the GPL-2 or later. + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* EN25Q128-specific commands */ +#define CMD_EN25Q128_WREN 0x06 /* Write Enable */ +#define CMD_EN25Q128_WRDI 0x04 /* Write Disable */ +#define CMD_EN25Q128_RDSR 0x05 /* Read Status Register */ +#define CMD_EN25Q128_WRSR 0x01 /* Write Status Register */ +#define CMD_EN25Q128_READ 0x03 /* Read Data Bytes */ +#define CMD_EN25Q128_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_EN25Q128_PP 0x02 /* Page Program */ +#define CMD_EN25Q128_SE 0x20 /* Sector Erase */ +#define CMD_EN25Q128_BE 0xd8 /* Block Erase */ +#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */ +#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */ + +#define EON_ID_EN25Q128 0x18 + +struct eon_spi_flash_params { + u8 idcode1; + u16 page_size; + u16 pages_per_sector; + u16 sectors_per_block; + u16 nr_sectors; + const char *name; +}; + +/* spi_flash needs to be first so upper layers can free() it */ +struct eon_spi_flash { + struct spi_flash flash; + const struct eon_spi_flash_params *params; +}; + +static inline struct eon_spi_flash *to_eon_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct eon_spi_flash, flash); +} + +static const struct eon_spi_flash_params eon_spi_flash_table[] = { + { + .idcode1 = EON_ID_EN25Q128, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 4096, + .name = "EN25Q128", + }, +}; + +static int eon_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct eon_spi_flash *eon = to_eon_spi_flash(flash); + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = eon->params->page_size; + page_addr = offset / page_size; + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + ret = 0; + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_EN25Q128_PP; + cmd[1] = page_addr >> 8; + cmd[2] = page_addr; + cmd[3] = byte_addr; + + printk(BIOS_SPEW, + "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + break; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: EON Page Program failed\n"); + break; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + break; + + page_addr++; + byte_addr = 0; + } + + printk(BIOS_INFO, "SF: EON: Successfully programmed %zu bytes @ 0x%x\n", + len, offset); + + spi_release_bus(flash->spi); + return ret; +} + +static int eon_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_EN25Q128_BE, offset, len); +} + +struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) +{ + const struct eon_spi_flash_params *params; + struct eon_spi_flash *eon; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) { + params = &eon_spi_flash_table[i]; + if (params->idcode1 == idcode[2]) + break; + } + + if (i == ARRAY_SIZE(eon_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported EON ID %02x\n", idcode[1]); + return NULL; + } + + eon = malloc(sizeof(*eon)); + if (!eon) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + eon->params = params; + eon->flash.spi = spi; + eon->flash.name = params->name; + + eon->flash.write = eon_write; + eon->flash.erase = eon_erase; + eon->flash.read = spi_flash_cmd_read_fast; + eon->flash.sector_size = params->page_size * params->pages_per_sector + * params->sectors_per_block; + eon->flash.size = params->page_size * params->pages_per_sector + * params->nr_sectors; + + return &eon->flash; +} diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c new file mode 100644 index 0000000..130e746 --- /dev/null +++ b/src/drivers/spi/macronix.c @@ -0,0 +1,220 @@ +/* + * Copyright 2009(C) Marvell International Ltd. and its affiliates + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * Based on drivers/mtd/spi/stmicro.c + * + * Copyright 2008, Network Appliance Inc. + * Jason McMullan <mcmullan(a)netapp.com> + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* MX25xx-specific commands */ +#define CMD_MX25XX_WREN 0x06 /* Write Enable */ +#define CMD_MX25XX_WRDI 0x04 /* Write Disable */ +#define CMD_MX25XX_RDSR 0x05 /* Read Status Register */ +#define CMD_MX25XX_WRSR 0x01 /* Write Status Register */ +#define CMD_MX25XX_READ 0x03 /* Read Data Bytes */ +#define CMD_MX25XX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_MX25XX_PP 0x02 /* Page Program */ +#define CMD_MX25XX_SE 0x20 /* Sector Erase */ +#define CMD_MX25XX_BE 0xD8 /* Block Erase */ +#define CMD_MX25XX_CE 0xc7 /* Chip Erase */ +#define CMD_MX25XX_DP 0xb9 /* Deep Power-down */ +#define CMD_MX25XX_RES 0xab /* Release from DP, and Read Signature */ + +#define MACRONIX_SR_WIP (1 << 0) /* Write-in-Progress */ + +struct macronix_spi_flash_params { + u16 idcode; + u16 page_size; + u16 pages_per_sector; + u16 sectors_per_block; + u16 nr_blocks; + const char *name; +}; + +struct macronix_spi_flash { + struct spi_flash flash; + const struct macronix_spi_flash_params *params; +}; + +static inline struct macronix_spi_flash *to_macronix_spi_flash(struct spi_flash + *flash) +{ + return container_of(flash, struct macronix_spi_flash, flash); +} + +static const struct macronix_spi_flash_params macronix_spi_flash_table[] = { + { + .idcode = 0x2015, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "MX25L1605D", + }, + { + .idcode = 0x2016, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "MX25L3205D", + }, + { + .idcode = 0x2017, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "MX25L6405D", + }, + { + .idcode = 0x2018, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 256, + .name = "MX25L12805D", + }, + { + .idcode = 0x2618, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 256, + .name = "MX25L12855E", + }, +}; + +static int macronix_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct macronix_spi_flash *mcx = to_macronix_spi_flash(flash); + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = min(mcx->params->page_size, CONTROLLER_PAGE_LIMIT); + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + ret = 0; + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_MX25XX_PP; + cmd[1] = (offset >> 16) & 0xff; + cmd[2] = (offset >> 8) & 0xff; + cmd[3] = offset & 0xff; + + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + break; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Macronix Page Program failed\n"); + break; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + break; + + offset += chunk_len; + byte_addr = 0; + } + + printk(BIOS_INFO, "SF: Macronix: Successfully programmed %zu bytes @ 0x%lx\n", + len, offset - len); + + spi_release_bus(flash->spi); + return ret; +} + +static int macronix_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_MX25XX_SE, offset, len); +} + +struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode) +{ + const struct macronix_spi_flash_params *params; + struct macronix_spi_flash *mcx; + unsigned int i; + u16 id = idcode[2] | idcode[1] << 8; + + for (i = 0; i < ARRAY_SIZE(macronix_spi_flash_table); i++) { + params = &macronix_spi_flash_table[i]; + if (params->idcode == id) + break; + } + + if (i == ARRAY_SIZE(macronix_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported Macronix ID %04x\n", id); + return NULL; + } + + mcx = malloc(sizeof(*mcx)); + if (!mcx) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + mcx->params = params; + mcx->flash.spi = spi; + mcx->flash.name = params->name; + + mcx->flash.write = macronix_write; + mcx->flash.erase = macronix_erase; +#ifdef CONFIG_SPI_FLASH_NO_FAST_READ + mcx->flash.read = spi_flash_cmd_read_slow; +#else + mcx->flash.read = spi_flash_cmd_read_fast; +#endif + mcx->flash.sector_size = params->page_size * params->pages_per_sector; + mcx->flash.size = mcx->flash.sector_size * params->sectors_per_block * + params->nr_blocks; + + return &mcx->flash; +} diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c new file mode 100644 index 0000000..a4f370a --- /dev/null +++ b/src/drivers/spi/spansion.c @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2009 Freescale Semiconductor, Inc. + * + * Author: Mingkai Hu (Mingkai.hu(a)freescale.com) + * Based on stmicro.c by Wolfgang Denk (wd(a)denx.de), + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com), + * and Jason McMullan (mcmullan(a)netapp.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* S25FLxx-specific commands */ +#define CMD_S25FLXX_READ 0x03 /* Read Data Bytes */ +#define CMD_S25FLXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_S25FLXX_READID 0x90 /* Read Manufacture ID and Device ID */ +#define CMD_S25FLXX_WREN 0x06 /* Write Enable */ +#define CMD_S25FLXX_WRDI 0x04 /* Write Disable */ +#define CMD_S25FLXX_RDSR 0x05 /* Read Status Register */ +#define CMD_S25FLXX_WRSR 0x01 /* Write Status Register */ +#define CMD_S25FLXX_PP 0x02 /* Page Program */ +#define CMD_S25FLXX_SE 0xd8 /* Sector Erase */ +#define CMD_S25FLXX_BE 0xc7 /* Bulk Erase */ +#define CMD_S25FLXX_DP 0xb9 /* Deep Power-down */ +#define CMD_S25FLXX_RES 0xab /* Release from DP, and Read Signature */ + +#define SPSN_ID_S25FL008A 0x0213 +#define SPSN_ID_S25FL016A 0x0214 +#define SPSN_ID_S25FL032A 0x0215 +#define SPSN_ID_S25FL064A 0x0216 +#define SPSN_ID_S25FL128P 0x2018 +#define SPSN_EXT_ID_S25FL128P_256KB 0x0300 +#define SPSN_EXT_ID_S25FL128P_64KB 0x0301 +#define SPSN_EXT_ID_S25FL032P 0x4d00 + +struct spansion_spi_flash_params { + u16 idcode1; + u16 idcode2; + u16 page_size; + u16 pages_per_sector; + u16 nr_sectors; + const char *name; +}; + +struct spansion_spi_flash { + struct spi_flash flash; + const struct spansion_spi_flash_params *params; +}; + +static inline struct spansion_spi_flash *to_spansion_spi_flash(struct spi_flash + *flash) +{ + return container_of(flash, struct spansion_spi_flash, flash); +} + +static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { + { + .idcode1 = SPSN_ID_S25FL008A, + .idcode2 = 0, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 16, + .name = "S25FL008A", + }, + { + .idcode1 = SPSN_ID_S25FL016A, + .idcode2 = 0, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 32, + .name = "S25FL016A", + }, + { + .idcode1 = SPSN_ID_S25FL032A, + .idcode2 = 0, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 64, + .name = "S25FL032A", + }, + { + .idcode1 = SPSN_ID_S25FL064A, + .idcode2 = 0, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 128, + .name = "S25FL064A", + }, + { + .idcode1 = SPSN_ID_S25FL128P, + .idcode2 = SPSN_EXT_ID_S25FL128P_64KB, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 256, + .name = "S25FL128P_64K", + }, + { + .idcode1 = SPSN_ID_S25FL128P, + .idcode2 = SPSN_EXT_ID_S25FL128P_256KB, + .page_size = 256, + .pages_per_sector = 1024, + .nr_sectors = 64, + .name = "S25FL128P_256K", + }, + { + .idcode1 = SPSN_ID_S25FL032A, + .idcode2 = SPSN_EXT_ID_S25FL032P, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 64, + .name = "S25FL032P", + }, +}; + +static int spansion_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct spansion_spi_flash *spsn = to_spansion_spi_flash(flash); + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = spsn->params->page_size; + page_addr = offset / page_size; + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + ret = 0; + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_S25FLXX_PP; + cmd[1] = page_addr >> 8; + cmd[2] = page_addr; + cmd[3] = byte_addr; + + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + break; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: SPANSION Page Program failed\n"); + break; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + break; + + page_addr++; + byte_addr = 0; + } + + printk(BIOS_INFO, "SF: SPANSION: Successfully programmed %zu bytes @ 0x%x\n", + len, offset); + + spi_release_bus(flash->spi); + return ret; +} + +static int spansion_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_S25FLXX_SE, offset, len); +} + +struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) +{ + const struct spansion_spi_flash_params *params; + struct spansion_spi_flash *spsn; + unsigned int i; + unsigned short jedec, ext_jedec; + + jedec = idcode[1] << 8 | idcode[2]; + ext_jedec = idcode[3] << 8 | idcode[4]; + + for (i = 0; i < ARRAY_SIZE(spansion_spi_flash_table); i++) { + params = &spansion_spi_flash_table[i]; + if (params->idcode1 == jedec) { + if (params->idcode2 == ext_jedec) + break; + } + } + + if (i == ARRAY_SIZE(spansion_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported SPANSION ID %04x %04x\n", jedec, ext_jedec); + return NULL; + } + + spsn = malloc(sizeof(struct spansion_spi_flash)); + if (!spsn) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + spsn->params = params; + spsn->flash.spi = spi; + spsn->flash.name = params->name; + + spsn->flash.write = spansion_write; + spsn->flash.erase = spansion_erase; + spsn->flash.read = spi_flash_cmd_read_fast; + spsn->flash.sector_size = params->page_size * params->pages_per_sector; + spsn->flash.size = spsn->flash.sector_size * params->nr_sectors; + + return &spsn->flash; +} diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c new file mode 100644 index 0000000..33cb4d2 --- /dev/null +++ b/src/drivers/spi/spi_flash.c @@ -0,0 +1,309 @@ +/* + * SPI flash interface + * + * Copyright (C) 2008 Atmel Corporation + * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik + * + * Licensed under the GPL-2 or later. + */ + +#include <stdlib.h> +#include <string.h> +#include <spi.h> +#include <spi_flash.h> +#include <delay.h> +#include "spi_flash_internal.h" + +static void spi_flash_addr(u32 addr, u8 *cmd) +{ + /* cmd[0] is actual command */ + cmd[1] = addr >> 16; + cmd[2] = addr >> 8; + cmd[3] = addr >> 0; +} + +int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len) +{ + int ret = spi_xfer(spi, &cmd, 8, response, len * 8); + if (ret) + printk(BIOS_WARNING, "SF: Failed to send command %02x: %d\n", cmd, ret); + + return ret; +} + +int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len) +{ + int ret = spi_xfer(spi, cmd, cmd_len * 8, data, data_len * 8); + if (ret) { + printk(BIOS_WARNING, "SF: Failed to send read command (%zu bytes): %d\n", + data_len, ret); + } + + return ret; +} + +int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, + const void *data, size_t data_len) +{ + int ret; + u8 buff[cmd_len + data_len]; + memcpy(buff, cmd, cmd_len); + memcpy(buff + cmd_len, data, data_len); + + ret = spi_xfer(spi, buff, (cmd_len + data_len) * 8, NULL, 0); + if (ret) { + printk(BIOS_WARNING, "SF: Failed to send write command (%zu bytes): %d\n", + data_len, ret); + } + + return ret; +} + +int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len) +{ + struct spi_slave *spi = flash->spi; + int ret; + + spi_claim_bus(spi); + ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); + spi_release_bus(spi); + + return ret; +} + +int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, + size_t len, void *data) +{ + struct spi_slave *spi = flash->spi; + u8 cmd[5]; + + cmd[0] = CMD_READ_ARRAY_FAST; + spi_flash_addr(offset, cmd); + cmd[4] = 0x00; + + return spi_flash_cmd_read(spi, cmd, sizeof(cmd), data, len); +} + +int spi_flash_cmd_read_slow(struct spi_flash *flash, u32 offset, + size_t len, void *data) +{ + struct spi_slave *spi = flash->spi; + u8 cmd[4]; + + cmd[0] = CMD_READ_ARRAY_SLOW; + spi_flash_addr(offset, cmd); + + return spi_flash_cmd_read(spi, cmd, sizeof(cmd), data, len); +} + +int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, + u8 cmd, u8 poll_bit) +{ + struct spi_slave *spi = flash->spi; + unsigned long timebase; + int ret; + u8 status; + + timebase = timeout; + do { + ret = spi_flash_cmd_read(spi, &cmd, 1, &status, 1); + if (ret) + return -1; + + if ((status & poll_bit) == 0) + break; + + mdelay(1); + } while (timebase--); + + if ((status & poll_bit) == 0) + return 0; + + /* Timed out */ + printk(BIOS_DEBUG, "SF: time out!\n"); + return -1; +} + +int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) +{ + return spi_flash_cmd_poll_bit(flash, timeout, + CMD_READ_STATUS, STATUS_WIP); +} + +int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd, + u32 offset, size_t len) +{ + u32 start, end, erase_size; + int ret; + u8 cmd[4]; + + erase_size = flash->sector_size; + if (offset % erase_size || len % erase_size) { + printk(BIOS_WARNING, "SF: Erase offset/length not multiple of erase size\n"); + return -1; + } + + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + cmd[0] = erase_cmd; + start = offset; + end = start + len; + + while (offset < end) { + spi_flash_addr(offset, cmd); + offset += erase_size; + + printk(BIOS_SPEW, "SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], + cmd[2], cmd[3], offset); + + ret = spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); + if (ret) + goto out; + + ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0); + if (ret) + goto out; + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT); + if (ret) + goto out; + } + + printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); + + out: + spi_release_bus(flash->spi); + return ret; +} + +/* + * The following table holds all device probe functions + * + * shift: number of continuation bytes before the ID + * idcode: the expected IDCODE or 0xff for non JEDEC devices + * probe: the function to call + * + * Non JEDEC devices should be ordered in the table such that + * the probe functions with best detection algorithms come first. + * + * Several matching entries are permitted, they will be tried + * in sequence until a probe function returns non NULL. + * + * IDCODE_CONT_LEN may be redefined if a device needs to declare a + * larger "shift" value. IDCODE_PART_LEN generally shouldn't be + * changed. This is the max number of bytes probe functions may + * examine when looking up part-specific identification info. + * + * Probe functions will be given the idcode buffer starting at their + * manu id byte (the "idcode" in the table below). In other words, + * all of the continuation bytes will be skipped (the "shift" below). + */ +#define IDCODE_CONT_LEN 0 +#define IDCODE_PART_LEN 5 +static const struct { + const u8 shift; + const u8 idcode; + struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode); +} flashes[] = { + /* Keep it sorted by define name */ +#if CONFIG_SPI_FLASH_EON + { 0, 0x1c, spi_flash_probe_eon, }, +#endif +#if CONFIG_SPI_FLASH_MACRONIX + { 0, 0xc2, spi_flash_probe_macronix, }, +#endif +#if CONFIG_SPI_FLASH_SPANSION + { 0, 0x01, spi_flash_probe_spansion, }, +#endif +#if CONFIG_SPI_FLASH_SST + { 0, 0xbf, spi_flash_probe_sst, }, +#endif +#if CONFIG_SPI_FLASH_STMICRO + { 0, 0x20, spi_flash_probe_stmicro, }, +#endif +#if CONFIG_SPI_FLASH_WINBOND + { 0, 0xef, spi_flash_probe_winbond, }, +#endif + /* Keep it sorted by best detection */ +#if CONFIG_SPI_FLASH_STMICRO + { 0, 0xff, spi_flash_probe_stmicro, }, +#endif +}; +#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) + +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode) +{ + struct spi_slave *spi; + struct spi_flash *flash = NULL; + int ret, i, shift; + u8 idcode[IDCODE_LEN], *idp; + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { + printk(BIOS_WARNING, "SF: Failed to set up slave\n"); + return NULL; + } + + ret = spi_claim_bus(spi); + if (ret) { + printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret); + goto err_claim_bus; + } + + /* Read the ID codes */ + ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); + if (ret) + goto err_read_id; + +#ifdef DEBUG + printk(BIOS_SPEW, "SF: Got idcodes\n"); + print_buffer(0, idcode, 1, sizeof(idcode), 0); +#endif + + /* count the number of continuation bytes */ + for (shift = 0, idp = idcode; + shift < IDCODE_CONT_LEN && *idp == 0x7f; + ++shift, ++idp) + continue; + + /* search the table for matches in shift and id */ + for (i = 0; i < ARRAY_SIZE(flashes); ++i) + if (flashes[i].shift == shift && flashes[i].idcode == *idp) { + /* we have a match, call probe */ + flash = flashes[i].probe(spi, idp); + if (flash) + break; + } + + if (!flash) { + printk(BIOS_WARNING, "SF: Unsupported manufacturer %02x\n", *idp); + goto err_manufacturer_probe; + } + + printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n", + flash->name, flash->sector_size, flash->size); + + spi_release_bus(spi); + + return flash; + +err_manufacturer_probe: +err_read_id: + spi_release_bus(spi); +err_claim_bus: + spi_free_slave(spi); + return NULL; +} + +void spi_flash_free(struct spi_flash *flash) +{ + spi_free_slave(flash->spi); + free(flash); +} diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h new file mode 100644 index 0000000..b895e2b --- /dev/null +++ b/src/drivers/spi/spi_flash_internal.h @@ -0,0 +1,81 @@ +/* + * SPI flash internal definitions + * + * Copyright (C) 2008 Atmel Corporation + */ + +/* Common parameters -- kind of high, but they should only occur when there + * is a problem (and well your system already is broken), so err on the side + * of caution in case we're dealing with slower SPI buses and/or processors. + */ +#define CONFIG_SYS_HZ 100 +#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) +#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) +#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) + +/* Common commands */ +#define CMD_READ_ID 0x9f + +#define CMD_READ_ARRAY_SLOW 0x03 +#define CMD_READ_ARRAY_FAST 0x0b +#define CMD_READ_ARRAY_LEGACY 0xe8 + +#define CMD_READ_STATUS 0x05 +#define CMD_WRITE_ENABLE 0x06 + +/* Common status */ +#define STATUS_WIP 0x01 + +/* Send a single-byte command to the device and read the response */ +int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); + +/* + * Send a multi-byte command to the device and read the response. Used + * for flash array reads, etc. + */ +int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len); + +int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, + size_t len, void *data); + +int spi_flash_cmd_read_slow(struct spi_flash *flash, u32 offset, + size_t len, void *data); + +/* + * Send a multi-byte command to the device followed by (optional) + * data. Used for programming the flash array, etc. + */ +int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, + const void *data, size_t data_len); + +/* + * Same as spi_flash_cmd_read() except it also claims/releases the SPI + * bus. Used as common part of the ->read() operation. + */ +int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len); + +/* Send a command to the device and wait for some bit to clear itself. */ +int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, + u8 cmd, u8 poll_bit); + +/* + * Send the read status command to the device and wait for the wip + * (write-in-progress) bit to clear itself. + */ +int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout); + +/* Erase sectors. */ +int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd, + u32 offset, size_t len); + +/* Manufacturer-specific probe functions */ +struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode); diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c new file mode 100644 index 0000000..56cc851 --- /dev/null +++ b/src/drivers/spi/sst.c @@ -0,0 +1,268 @@ +/* + * Driver for SST serial flashes + * + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * Copyright 2008, Network Appliance Inc. + * Jason McMullan <mcmullan(a)netapp.com> + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * Copyright (c) 2008-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +#define CMD_SST_WREN 0x06 /* Write Enable */ +#define CMD_SST_WRDI 0x04 /* Write Disable */ +#define CMD_SST_RDSR 0x05 /* Read Status Register */ +#define CMD_SST_WRSR 0x01 /* Write Status Register */ +#define CMD_SST_READ 0x03 /* Read Data Bytes */ +#define CMD_SST_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_SST_BP 0x02 /* Byte Program */ +#define CMD_SST_AAI_WP 0xAD /* Auto Address Increment Word Program */ +#define CMD_SST_SE 0x20 /* Sector Erase */ + +#define SST_SR_WIP (1 << 0) /* Write-in-Progress */ +#define SST_SR_WEL (1 << 1) /* Write enable */ +#define SST_SR_BP0 (1 << 2) /* Block Protection 0 */ +#define SST_SR_BP1 (1 << 3) /* Block Protection 1 */ +#define SST_SR_BP2 (1 << 4) /* Block Protection 2 */ +#define SST_SR_AAI (1 << 6) /* Addressing mode */ +#define SST_SR_BPL (1 << 7) /* BP bits lock */ + +struct sst_spi_flash_params { + u8 idcode1; + u16 nr_sectors; + const char *name; +}; + +struct sst_spi_flash { + struct spi_flash flash; + const struct sst_spi_flash_params *params; +}; + +static inline struct sst_spi_flash *to_sst_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct sst_spi_flash, flash); +} + +#define SST_SECTOR_SIZE (4 * 1024) +static const struct sst_spi_flash_params sst_spi_flash_table[] = { + { + .idcode1 = 0x8d, + .nr_sectors = 128, + .name = "SST25VF040B", + },{ + .idcode1 = 0x8e, + .nr_sectors = 256, + .name = "SST25VF080B", + },{ + .idcode1 = 0x41, + .nr_sectors = 512, + .name = "SST25VF016B", + },{ + .idcode1 = 0x4a, + .nr_sectors = 1024, + .name = "SST25VF032B", + },{ + .idcode1 = 0x4b, + .nr_sectors = 2048, + .name = "SST25VF064C", + },{ + .idcode1 = 0x01, + .nr_sectors = 16, + .name = "SST25WF512", + },{ + .idcode1 = 0x02, + .nr_sectors = 32, + .name = "SST25WF010", + },{ + .idcode1 = 0x03, + .nr_sectors = 64, + .name = "SST25WF020", + },{ + .idcode1 = 0x04, + .nr_sectors = 128, + .name = "SST25WF040", + }, +}; + +static int +sst_enable_writing(struct spi_flash *flash) +{ + int ret = spi_flash_cmd(flash->spi, CMD_SST_WREN, NULL, 0); + if (ret) + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + return ret; +} + +static int +sst_disable_writing(struct spi_flash *flash) +{ + int ret = spi_flash_cmd(flash->spi, CMD_SST_WRDI, NULL, 0); + if (ret) + printk(BIOS_WARNING, "SF: Disabling Write failed\n"); + return ret; +} + +static int +sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) +{ + int ret; + u8 cmd[4] = { + CMD_SST_BP, + offset >> 16, + offset >> 8, + offset, + }; + + printk(BIOS_SPEW, "BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", + spi_w8r8(flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); + + ret = sst_enable_writing(flash); + if (ret) + return ret; + + ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1); + if (ret) + return ret; + + return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); +} + +static int +sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) +{ + size_t actual, cmd_len; + int ret; + u8 cmd[4]; + + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + /* If the data is not word aligned, write out leading single byte */ + actual = offset % 2; + if (actual) { + ret = sst_byte_write(flash, offset, buf); + if (ret) + goto done; + } + offset += actual; + + ret = sst_enable_writing(flash); + if (ret) + goto done; + + cmd_len = 4; + cmd[0] = CMD_SST_AAI_WP; + cmd[1] = offset >> 16; + cmd[2] = offset >> 8; + cmd[3] = offset; + + for (; actual < len - 1; actual += 2) { + printk(BIOS_SPEW, "WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", + spi_w8r8(flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], + offset); + + ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, + buf + actual, 2); + if (ret) { + printk(BIOS_WARNING, "SF: SST word program failed\n"); + break; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + break; + + cmd_len = 1; + offset += 2; + } + + if (!ret) + ret = sst_disable_writing(flash); + + /* If there is a single trailing byte, write it out */ + if (!ret && actual != len) + ret = sst_byte_write(flash, offset, buf + actual); + + done: + printk(BIOS_INFO, "SF: SST: program %s %zu bytes @ 0x%lx\n", + ret ? "failure" : "success", len, offset - actual); + + spi_release_bus(flash->spi); + return ret; +} + +static int sst_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_SST_SE, offset, len); +} + +static int +sst_unlock(struct spi_flash *flash) +{ + int ret; + u8 cmd, status; + + ret = sst_enable_writing(flash); + if (ret) + return ret; + + cmd = CMD_SST_WRSR; + status = 0; + ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &status, 1); + if (ret) + printk(BIOS_WARNING, "SF: Unable to set status byte\n"); + + printk(BIOS_INFO, "SF: SST: status = %x\n", spi_w8r8(flash->spi, CMD_SST_RDSR)); + + return ret; +} + +struct spi_flash * +spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode) +{ + const struct sst_spi_flash_params *params; + struct sst_spi_flash *stm; + size_t i; + + for (i = 0; i < ARRAY_SIZE(sst_spi_flash_table); ++i) { + params = &sst_spi_flash_table[i]; + if (params->idcode1 == idcode[2]) + break; + } + + if (i == ARRAY_SIZE(sst_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported SST ID %02x\n", idcode[1]); + return NULL; + } + + stm = malloc(sizeof(*stm)); + if (!stm) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + stm->params = params; + stm->flash.spi = spi; + stm->flash.name = params->name; + + stm->flash.write = sst_write; + stm->flash.erase = sst_erase; + stm->flash.read = spi_flash_cmd_read_fast; + stm->flash.sector_size = SST_SECTOR_SIZE; + stm->flash.size = stm->flash.sector_size * params->nr_sectors; + + /* Flash powers up read-only, so clear BP# bits */ + sst_unlock(&stm->flash); + + return &stm->flash; +} diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c new file mode 100644 index 0000000..8cbdad5 --- /dev/null +++ b/src/drivers/spi/stmicro.c @@ -0,0 +1,250 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * Copyright 2008, Network Appliance Inc. + * Jason McMullan <mcmullan(a)netapp.com> + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* M25Pxx-specific commands */ +#define CMD_M25PXX_WREN 0x06 /* Write Enable */ +#define CMD_M25PXX_WRDI 0x04 /* Write Disable */ +#define CMD_M25PXX_RDSR 0x05 /* Read Status Register */ +#define CMD_M25PXX_WRSR 0x01 /* Write Status Register */ +#define CMD_M25PXX_READ 0x03 /* Read Data Bytes */ +#define CMD_M25PXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_M25PXX_PP 0x02 /* Page Program */ +#define CMD_M25PXX_SE 0xd8 /* Sector Erase */ +#define CMD_M25PXX_BE 0xc7 /* Bulk Erase */ +#define CMD_M25PXX_DP 0xb9 /* Deep Power-down */ +#define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */ + +#define STM_ID_M25P10 0x11 +#define STM_ID_M25P16 0x15 +#define STM_ID_M25P20 0x12 +#define STM_ID_M25P32 0x16 +#define STM_ID_M25P40 0x13 +#define STM_ID_M25P64 0x17 +#define STM_ID_M25P80 0x14 +#define STM_ID_M25P128 0x18 + +struct stmicro_spi_flash_params { + u8 idcode1; + u16 page_size; + u16 pages_per_sector; + u16 nr_sectors; + const char *name; +}; + +/* spi_flash needs to be first so upper layers can free() it */ +struct stmicro_spi_flash { + struct spi_flash flash; + const struct stmicro_spi_flash_params *params; +}; + +static inline struct stmicro_spi_flash *to_stmicro_spi_flash(struct spi_flash + *flash) +{ + return container_of(flash, struct stmicro_spi_flash, flash); +} + +static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = { + { + .idcode1 = STM_ID_M25P10, + .page_size = 256, + .pages_per_sector = 128, + .nr_sectors = 4, + .name = "M25P10", + }, + { + .idcode1 = STM_ID_M25P16, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 32, + .name = "M25P16", + }, + { + .idcode1 = STM_ID_M25P20, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 4, + .name = "M25P20", + }, + { + .idcode1 = STM_ID_M25P32, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 64, + .name = "M25P32", + }, + { + .idcode1 = STM_ID_M25P40, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 8, + .name = "M25P40", + }, + { + .idcode1 = STM_ID_M25P64, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 128, + .name = "M25P64", + }, + { + .idcode1 = STM_ID_M25P80, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 16, + .name = "M25P80", + }, + { + .idcode1 = STM_ID_M25P128, + .page_size = 256, + .pages_per_sector = 1024, + .nr_sectors = 64, + .name = "M25P128", + }, +}; + +static int stmicro_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct stmicro_spi_flash *stm = to_stmicro_spi_flash(flash); + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = stm->params->page_size; + page_addr = offset / page_size; + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + ret = 0; + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_M25PXX_PP; + cmd[1] = page_addr >> 8; + cmd[2] = page_addr; + cmd[3] = byte_addr; + + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + break; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: STMicro Page Program failed\n"); + break; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + break; + + page_addr++; + byte_addr = 0; + } + + printk(BIOS_INFO, "SF: STMicro: Successfully programmed %zu bytes @ 0x%x\n", + len, offset); + + spi_release_bus(flash->spi); + return ret; +} + +static int stmicro_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_M25PXX_SE, offset, len); +} + +struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) +{ + const struct stmicro_spi_flash_params *params; + struct stmicro_spi_flash *stm; + unsigned int i; + + if (idcode[0] == 0xff) { + i = spi_flash_cmd(spi, CMD_M25PXX_RES, + idcode, 4); + if (i) + return NULL; + if ((idcode[3] & 0xf0) == 0x10) { + idcode[0] = 0x20; + idcode[1] = 0x20; + idcode[2] = idcode[3] + 1; + } else + return NULL; + } + + for (i = 0; i < ARRAY_SIZE(stmicro_spi_flash_table); i++) { + params = &stmicro_spi_flash_table[i]; + if (params->idcode1 == idcode[2]) { + break; + } + } + + if (i == ARRAY_SIZE(stmicro_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported STMicro ID %02x\n", idcode[1]); + return NULL; + } + + stm = malloc(sizeof(struct stmicro_spi_flash)); + if (!stm) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + stm->params = params; + stm->flash.spi = spi; + stm->flash.name = params->name; + + stm->flash.write = stmicro_write; + stm->flash.erase = stmicro_erase; + stm->flash.read = spi_flash_cmd_read_fast; + stm->flash.sector_size = params->page_size * params->pages_per_sector; + stm->flash.size = stm->flash.sector_size * params->nr_sectors; + + return &stm->flash; +} diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c new file mode 100644 index 0000000..65818d5 --- /dev/null +++ b/src/drivers/spi/winbond.c @@ -0,0 +1,218 @@ +/* + * Copyright 2008, Network Appliance Inc. + * Author: Jason McMullan <mcmullan <at> netapp.com> + * Licensed under the GPL-2 or later. + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* M25Pxx-specific commands */ +#define CMD_W25_WREN 0x06 /* Write Enable */ +#define CMD_W25_WRDI 0x04 /* Write Disable */ +#define CMD_W25_RDSR 0x05 /* Read Status Register */ +#define CMD_W25_WRSR 0x01 /* Write Status Register */ +#define CMD_W25_READ 0x03 /* Read Data Bytes */ +#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_W25_PP 0x02 /* Page Program */ +#define CMD_W25_SE 0x20 /* Sector (4K) Erase */ +#define CMD_W25_BE 0xd8 /* Block (64K) Erase */ +#define CMD_W25_CE 0xc7 /* Chip Erase */ +#define CMD_W25_DP 0xb9 /* Deep Power-down */ +#define CMD_W25_RES 0xab /* Release from DP, and Read Signature */ + +struct winbond_spi_flash_params { + uint16_t id; + /* Log2 of page size in power-of-two mode */ + uint8_t l2_page_size; + uint16_t pages_per_sector; + uint16_t sectors_per_block; + uint16_t nr_blocks; + const char *name; +}; + +/* spi_flash needs to be first so upper layers can free() it */ +struct winbond_spi_flash { + struct spi_flash flash; + const struct winbond_spi_flash_params *params; +}; + +static inline struct winbond_spi_flash * +to_winbond_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct winbond_spi_flash, flash); +} + +static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { + { + .id = 0x3015, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "W25X16", + }, + { + .id = 0x3016, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "W25X32", + }, + { + .id = 0x3017, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "W25X64", + }, + { + .id = 0x4015, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "W25Q16", + }, + { + .id = 0x4016, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "W25Q32", + }, + { + .id = 0x4017, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "W25Q64", + }, + { + .id = 0x4018, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 256, + .name = "W25Q128", + }, +}; + +static int winbond_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct winbond_spi_flash *stm = to_winbond_spi_flash(flash); + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = min(1 << stm->params->l2_page_size, CONTROLLER_PAGE_LIMIT); + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_W25_PP; + cmd[1] = (offset >> 16) & 0xff; + cmd[2] = (offset >> 8) & 0xff; + cmd[3] = offset & 0xff; + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %ld\n", + buf + actual, + cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + goto out; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Winbond Page Program failed\n"); + goto out; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + goto out; + + offset += chunk_len; + byte_addr = 0; + } + + printk(BIOS_INFO, "SF: Winbond: Successfully programmed %zu bytes @ 0x%lx\n", + len, offset - len); + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +static int winbond_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_W25_SE, offset, len); +} + +struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) +{ + const struct winbond_spi_flash_params *params; + unsigned page_size; + struct winbond_spi_flash *stm; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) { + params = &winbond_spi_flash_table[i]; + if (params->id == ((idcode[1] << 8) | idcode[2])) + break; + } + + if (i == ARRAY_SIZE(winbond_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported Winbond ID %02x%02x\n", + idcode[1], idcode[2]); + return NULL; + } + + stm = malloc(sizeof(struct winbond_spi_flash)); + if (!stm) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + stm->params = params; + stm->flash.spi = spi; + stm->flash.name = params->name; + + /* Assuming power-of-two page size initially. */ + page_size = 1 << params->l2_page_size; + + stm->flash.write = winbond_write; + stm->flash.erase = winbond_erase; +#ifdef CONFIG_SPI_FLASH_NO_FAST_READ + stm->flash.read = spi_flash_cmd_read_slow; +#else + stm->flash.read = spi_flash_cmd_read_fast; +#endif + stm->flash.sector_size = (1 << stm->params->l2_page_size) * + stm->params->pages_per_sector; + stm->flash.size = page_size * params->pages_per_sector + * params->sectors_per_block + * params->nr_blocks; + + return &stm->flash; +} diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index a2d6884..1765293 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2502,6 +2502,10 @@ #define PCI_DEVICE_ID_INTEL_82801IO_LPC 0x2914 #define PCI_DEVICE_ID_INTEL_82801IH_LPC 0x2912 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f +#define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc + /* Intel 82801E (C-ICH) */ #define PCI_DEVICE_ID_INTEL_82801E_LPC 0x2450 #define PCI_DEVICE_ID_INTEL_82801E_USB 0x2452 diff --git a/src/include/spi.h b/src/include/spi.h new file mode 100644 index 0000000..bb84258 --- /dev/null +++ b/src/include/spi.h @@ -0,0 +1,203 @@ +/* + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren(a)cideas.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPI_H_ +#define _SPI_H_ + +#include <stdint.h> + +/* Controller-specific definitions: */ + +/* SPI mode flags */ +#define SPI_CPHA 0x01 /* clock phase */ +#define SPI_CPOL 0x02 /* clock polarity */ +#define SPI_MODE_0 (0|0) /* (original MicroWire) */ +#define SPI_MODE_1 (0|SPI_CPHA) +#define SPI_MODE_2 (SPI_CPOL|0) +#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) +#define SPI_CS_HIGH 0x04 /* CS active high */ +#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ +#define SPI_3WIRE 0x10 /* SI/SO signals shared */ +#define SPI_LOOP 0x20 /* loopback mode */ + +/* SPI transfer flags */ +#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ +#define SPI_XFER_END 0x02 /* Deassert CS after transfer */ + +/*----------------------------------------------------------------------- + * Representation of a SPI slave, i.e. what we're communicating with. + * + * Drivers are expected to extend this with controller-specific data. + * + * bus: ID of the bus that the slave is attached to. + * cs: ID of the chip select connected to the slave. + */ +struct spi_slave { + unsigned int bus; + unsigned int cs; +}; + +/*----------------------------------------------------------------------- + * Initialization, must be called once on start up. + * + * TODO: I don't think we really need this. + */ +void spi_init(void); + +/*----------------------------------------------------------------------- + * Set up communications parameters for a SPI slave. + * + * This must be called once for each slave. Note that this function + * usually doesn't touch any actual hardware, it only initializes the + * contents of spi_slave so that the hardware can be easily + * initialized later. + * + * bus: Bus ID of the slave chip. + * cs: Chip select ID of the slave chip on the specified bus. + * max_hz: Maximum SCK rate in Hz. + * mode: Clock polarity, clock phase and other parameters. + * + * Returns: A spi_slave reference that can be used in subsequent SPI + * calls, or NULL if one or more of the parameters are not supported. + */ +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); + +/*----------------------------------------------------------------------- + * Free any memory associated with a SPI slave. + * + * slave: The SPI slave + */ +void spi_free_slave(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * Claim the bus and prepare it for communication with a given slave. + * + * This must be called before doing any transfers with a SPI slave. It + * will enable and initialize any SPI hardware as necessary, and make + * sure that the SCK line is in the correct idle state. It is not + * allowed to claim the same bus for several slaves without releasing + * the bus in between. + * + * slave: The SPI slave + * + * Returns: 0 if the bus was claimed successfully, or a negative value + * if it wasn't. + */ +int spi_claim_bus(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * Release the SPI bus + * + * This must be called once for every call to spi_claim_bus() after + * all transfers have finished. It may disable any SPI hardware as + * appropriate. + * + * slave: The SPI slave + */ +void spi_release_bus(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * SPI transfer + * + * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks + * "bitlen" bits in the SPI MISO port. That's just the way SPI works. + * + * The source of the outgoing bits is the "dout" parameter and the + * destination of the input bits is the "din" parameter. Note that "dout" + * and "din" can point to the same memory location, in which case the + * input data overwrites the output data (since both are buffered by + * temporary variables, this is OK). + * + * spi_xfer() interface: + * slave: The SPI slave which will be sending/receiving the data. + * dout: Pointer to a string of bits to send out. The bits are + * held in a byte array and are sent MSB first. + * bitsout: How many bits to write. + * din: Pointer to a string of bits that will be filled in. + * bitsin: How many bits to read. + * + * Returns: 0 on success, not 0 on failure + */ +int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, + void *din, unsigned int bitsin); + +/*----------------------------------------------------------------------- + * Determine if a SPI chipselect is valid. + * This function is provided by the board if the low-level SPI driver + * needs it to determine if a given chipselect is actually valid. + * + * Returns: 1 if bus:cs identifies a valid chip on this board, 0 + * otherwise. + */ +int spi_cs_is_valid(unsigned int bus, unsigned int cs); + +/*----------------------------------------------------------------------- + * Activate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should activate the chip select + * to the device identified by "slave". + */ +void spi_cs_activate(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * Deactivate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should deactivate the chip + * select to the device identified by "slave". + */ +void spi_cs_deactivate(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * Set transfer speed. + * This sets a new speed to be applied for next spi_xfer(). + * slave: The SPI slave + * hz: The transfer speed + */ +void spi_set_speed(struct spi_slave *slave, uint32_t hz); + +/*----------------------------------------------------------------------- + * Write 8 bits, then read 8 bits. + * slave: The SPI slave we're communicating with + * byte: Byte to be written + * + * Returns: The value that was read, or a negative value on error. + * + * TODO: This function probably shouldn't be inlined. + */ +static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte) +{ + unsigned char dout[2]; + unsigned char din[2]; + int ret; + + dout[0] = byte; + dout[1] = 0; + + ret = spi_xfer(slave, dout, 16, din, 16); + return ret < 0 ? ret : din[1]; +} + +#endif /* _SPI_H_ */ diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h new file mode 100644 index 0000000..2a1dcd4 --- /dev/null +++ b/src/include/spi_flash.h @@ -0,0 +1,91 @@ +/* + * Interface to SPI flash + * + * Copyright (C) 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _SPI_FLASH_H_ +#define _SPI_FLASH_H_ + +#include <stdint.h> +#include <stddef.h> +#include <console/console.h> +#include <spi.h> + +/** + * container_of - cast a member of a structure out to the containing structure + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + +#define min(a, b) ((a)<(b)?(a):(b)) + +#define CONFIG_ICH_SPI +#ifdef CONFIG_ICH_SPI +#define CONTROLLER_PAGE_LIMIT 64 +#else +/* any number larger than 4K would do, actually */ +#define CONTROLLER_PAGE_LIMIT ((int)(~0U>>1)) +#endif + +struct spi_flash { + struct spi_slave *spi; + + const char *name; + + u32 size; + + u32 sector_size; + + int (*read)(struct spi_flash *flash, u32 offset, + size_t len, void *buf); + int (*write)(struct spi_flash *flash, u32 offset, + size_t len, const void *buf); + int (*erase)(struct spi_flash *flash, u32 offset, + size_t len); +}; + +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode); +void spi_flash_free(struct spi_flash *flash); + +static inline int spi_flash_read(struct spi_flash *flash, u32 offset, + size_t len, void *buf) +{ + return flash->read(flash, offset, len, buf); +} + +static inline int spi_flash_write(struct spi_flash *flash, u32 offset, + size_t len, const void *buf) +{ + return flash->write(flash, offset, len, buf); +} + +static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, + size_t len) +{ + return flash->erase(flash, offset, len); +} + +#endif /* _SPI_FLASH_H_ */ diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 8209980..6548b32 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -340,6 +340,7 @@ void sdram_initialize(struct pei_data *pei_data) /* If MRC data is not found we cannot continue S3 resume. */ if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { + printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n"); outb(0x6, 0xcf9); hlt(); } diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 3891be1..f105ee3 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK + select SPI config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 5732254..f086426 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -34,6 +34,8 @@ ramstage-y += me_status.c ramstage-y += reset.c ramstage-y += watchdog.c +ramstage-y += spi.c + ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c $(me-src-y) finalize.c diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c new file mode 100644 index 0000000..c54a325 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -0,0 +1,712 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This file is derived from the flashrom project. */ +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <delay.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +#include <spi.h> + +#define min(a, b) ((a)<(b)?(a):(b)) + +typedef device_t pci_dev_t; +#define pci_read_config_byte(dev, reg, targ) *(targ) = pci_read_config8(dev, reg) +#define pci_read_config_word(dev, reg, targ) *(targ) = pci_read_config16(dev, reg) +#define pci_read_config_dword(dev, reg, targ) *(targ) = pci_read_config32(dev, reg) +#define pci_write_config_byte(dev, reg, val) pci_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val) pci_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val) pci_write_config32(dev, reg, val) + +typedef struct spi_slave ich_spi_slave; + +static int ichspi_lock = 0; + +typedef struct ich7_spi_regs { + uint16_t spis; + uint16_t spic; + uint32_t spia; + uint64_t spid[8]; + uint64_t _pad; + uint32_t bbar; + uint16_t preop; + uint16_t optype; + uint8_t opmenu[8]; +} __attribute__((packed)) ich7_spi_regs; + +typedef struct ich9_spi_regs { + uint32_t bfpr; + uint16_t hsfs; + uint16_t hsfc; + uint32_t faddr; + uint32_t _reserved0; + uint32_t fdata[16]; + uint32_t frap; + uint32_t freg[5]; + uint32_t _reserved1[3]; + uint32_t pr[5]; + uint32_t _reserved2[2]; + uint8_t ssfs; + uint8_t ssfc[3]; + uint16_t preop; + uint16_t optype; + uint8_t opmenu[8]; + uint32_t bbar; + uint8_t _reserved3[12]; + uint32_t fdoc; + uint32_t fdod; + uint8_t _reserved4[8]; + uint32_t afc; + uint32_t lvscc; + uint32_t uvscc; + uint8_t _reserved5[4]; + uint32_t fpb; + uint8_t _reserved6[28]; + uint32_t srdl; + uint32_t srdc; + uint32_t srd; +} __attribute__((packed)) ich9_spi_regs; + +typedef struct ich_spi_controller { + int locked; + + uint8_t *opmenu; + int menubytes; + uint16_t *preop; + uint16_t *optype; + uint32_t *addr; + uint8_t *data; + unsigned databytes; + uint8_t *status; + uint16_t *control; + uint32_t *bbar; +} ich_spi_controller; + +static ich_spi_controller cntlr; + +enum { + SPIS_SCIP = 0x0001, + SPIS_GRANT = 0x0002, + SPIS_CDS = 0x0004, + SPIS_FCERR = 0x0008, + SSFS_AEL = 0x0010, + SPIS_LOCK = 0x8000, + SPIS_RESERVED_MASK = 0x7ff0, + SSFS_RESERVED_MASK = 0x7fe2 +}; + +enum { + SPIC_SCGO = 0x000002, + SPIC_ACS = 0x000004, + SPIC_SPOP = 0x000008, + SPIC_DBC = 0x003f00, + SPIC_DS = 0x004000, + SPIC_SME = 0x008000, + SSFC_SCF_MASK = 0x070000, + SSFC_RESERVED = 0xf80000 +}; + +enum { + HSFS_FDONE = 0x0001, + HSFS_FCERR = 0x0002, + HSFS_AEL = 0x0004, + HSFS_BERASE_MASK = 0x0018, + HSFS_BERASE_SHIFT = 3, + HSFS_SCIP = 0x0020, + HSFS_FDOPSS = 0x2000, + HSFS_FDV = 0x4000, + HSFS_FLOCKDN = 0x8000 +}; + +enum { + HSFC_FGO = 0x0001, + HSFC_FCYCLE_MASK = 0x0006, + HSFC_FCYCLE_SHIFT = 1, + HSFC_FDBC_MASK = 0x3f00, + HSFC_FDBC_SHIFT = 8, + HSFC_FSMIE = 0x8000 +}; + +enum { + SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, + SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, + SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, + SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 +}; + +#ifdef DEBUG + +static u8 readb_(const void *addr) +{ + u8 v = readb(addr); + printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static u16 readw_(const void *addr) +{ + u16 v = readw(addr); + printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static u32 readl_(const void *addr) +{ + u32 v = readl(addr); + printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static void writeb_(u8 b, const void *addr) +{ + writeb(b, addr); + printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +static void writew_(u16 b, const void *addr) +{ + writew(b, addr); + printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +static void writel_(u32 b, const void *addr) +{ + writel(b, addr); + printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +#else /* DEBUG ^^^ defined vvv NOT defined */ + +#define readb_(a) read8((uint32_t)a) +#define readw_(a) read16((uint32_t)a) +#define readl_(a) read32((uint32_t)a) +#define writeb_(val, addr) write8((uint32_t)addr, val) +#define writew_(val, addr) write16((uint32_t)addr, val) +#define writel_(val, addr) write32((uint32_t)addr, val) + +#endif /* DEBUG ^^^ NOT defined */ + +static void write_reg(const void *value, void *dest, uint32_t size) +{ + const uint8_t *bvalue = value; + uint8_t *bdest = dest; + + while (size >= 4) { + writel_(*(const uint32_t *)bvalue, bdest); + bdest += 4; bvalue += 4; size -= 4; + } + while (size) { + writeb_(*bvalue, bdest); + bdest++; bvalue++; size--; + } +} + +static void read_reg(const void *src, void *value, uint32_t size) +{ + const uint8_t *bsrc = src; + uint8_t *bvalue = value; + + while (size >= 4) { + *(uint32_t *)bvalue = readl_(bsrc); + bsrc += 4; bvalue += 4; size -= 4; + } + while (size) { + *bvalue = readb_(bsrc); + bsrc++; bvalue++; size--; + } +} + +static void ich_set_bbar(uint32_t minaddr) +{ + const uint32_t bbar_mask = 0x00ffff00; + uint32_t ichspi_bbar; + + minaddr &= bbar_mask; + ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; + ichspi_bbar |= minaddr; + writel_(ichspi_bbar, cntlr.bbar); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + printk(BIOS_DEBUG, "spi_cs_is_valid used but not implemented\n"); + return 0; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + ich_spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); + return NULL; + } + + memset(slave, 0, sizeof(*slave)); + + slave->bus = bus; + slave->cs = cs; + return slave; +} + +void spi_free_slave(struct spi_slave *_slave) +{ + ich_spi_slave *slave = (ich_spi_slave *)_slave; + free(slave); +} + +static inline int spi_is_cougarpoint_lpc(uint16_t device_id) +{ + return device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && + device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX; +}; + +void spi_init(void) +{ + int ich_version = 0; + + uint8_t *rcrb; /* Root Complex Register Block */ + uint32_t rcba; /* Root Complex Base Address */ + uint8_t bios_cntl; + pci_dev_t dev; + + int bus; + int last_bus = 1; //FIXME: pci_last_busno(); + + if (last_bus == -1) { + printk(BIOS_DEBUG, "No PCI busses?\n"); + return; + } + + for (bus = 0; bus <= last_bus; bus++) { + uint32_t ids; + uint16_t vendor_id, device_id; + + dev = dev_find_slot(bus, PCI_DEVFN(31, 0)); + pci_read_config_dword(dev, 0, &ids); + vendor_id = ids; + device_id = (ids >> 16); + + if (vendor_id != PCI_VENDOR_ID_INTEL) + continue; + + if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) { + ich_version = 7; + break; + } else if (spi_is_cougarpoint_lpc(device_id)) { + ich_version = 9; + break; + } + } + + if (!ich_version) { + printk(BIOS_DEBUG, "ICH SPI: No ICH found.\n"); + return; + } + + pci_read_config_dword(dev, 0xf0, &rcba); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ + rcrb = (uint8_t *)(rcba & 0xffffc000); + switch (ich_version) { + case 7: + { + const uint16_t ich7_spibar_offset = 0x3020; + ich7_spi_regs *ich7_spi = + (ich7_spi_regs *)(rcrb + ich7_spibar_offset); + + ichspi_lock = readw_(&ich7_spi->spis) & SPIS_LOCK; + cntlr.opmenu = ich7_spi->opmenu; + cntlr.menubytes = sizeof(ich7_spi->opmenu); + cntlr.optype = &ich7_spi->optype; + cntlr.addr = &ich7_spi->spia; + cntlr.data = (uint8_t *)ich7_spi->spid; + cntlr.databytes = sizeof(ich7_spi->spid); + cntlr.status = (uint8_t *)&ich7_spi->spis; + cntlr.control = &ich7_spi->spic; + cntlr.bbar = &ich7_spi->bbar; + cntlr.preop = &ich7_spi->preop; + break; + } + case 9: + { + const uint16_t ich9_spibar_offset = 0x3800; + ich9_spi_regs *ich9_spi = + (ich9_spi_regs *)(rcrb + ich9_spibar_offset); + ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; + cntlr.opmenu = ich9_spi->opmenu; + cntlr.menubytes = sizeof(ich9_spi->opmenu); + cntlr.optype = &ich9_spi->optype; + cntlr.addr = &ich9_spi->faddr; + cntlr.data = (uint8_t *)ich9_spi->fdata; + cntlr.databytes = sizeof(ich9_spi->fdata); + cntlr.status = &ich9_spi->ssfs; + cntlr.control = (uint16_t *)ich9_spi->ssfc; + cntlr.bbar = &ich9_spi->bbar; + cntlr.preop = &ich9_spi->preop; + break; + } + default: + printk(BIOS_DEBUG, "ICH SPI: Unrecognized ICH version %d.\n", ich_version); + } + + ich_set_bbar(0); + + /* Disable the BIOS write protect so write commands are allowed. */ + pci_read_config_byte(dev, 0xdc, &bios_cntl); + switch (ich_version) { + case 9: + /* Deassert SMM BIOS Write Protect Disable. */ + bios_cntl &= ~(1 << 5); + break; + + default: + break; + } + pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ +} + +typedef struct spi_transaction { + const uint8_t *out; + uint32_t bytesout; + uint8_t *in; + uint32_t bytesin; + uint8_t type; + uint8_t opcode; + uint32_t offset; +} spi_transaction; + +static inline void spi_use_out(spi_transaction *trans, unsigned bytes) +{ + trans->out += bytes; + trans->bytesout -= bytes; +} + +static inline void spi_use_in(spi_transaction *trans, unsigned bytes) +{ + trans->in += bytes; + trans->bytesin -= bytes; +} + +static void spi_setup_type(spi_transaction *trans) +{ + trans->type = 0xFF; + + /* Try to guess spi type from read/write sizes. */ + if (trans->bytesin == 0) { + if (trans->bytesout > 4) + /* + * If bytesin = 0 and bytesout > 4, we presume this is + * a write data operation, which is accompanied by an + * address. + */ + trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; + else + trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; + return; + } + + if (trans->bytesout == 1) { /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; + return; + } + + if (trans->bytesout == 4) { /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + } +} + +static int spi_setup_opcode(spi_transaction *trans) +{ + uint16_t optypes; + uint8_t opmenu[cntlr.menubytes]; + + trans->opcode = trans->out[0]; + spi_use_out(trans, 1); + if (!ichspi_lock) { + /* The lock is off, so just use index 0. */ + writeb_(trans->opcode, cntlr.opmenu); + optypes = readw_(cntlr.optype); + optypes = (optypes & 0xfffc) | (trans->type & 0x3); + writew_(optypes, cntlr.optype); + return 0; + } else { + /* The lock is on. See if what we need is on the menu. */ + uint8_t optype; + uint16_t opcode_index; + + read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < cntlr.menubytes; + opcode_index++) { + if (opmenu[opcode_index] == trans->opcode) + break; + } + + if (opcode_index == cntlr.menubytes) { + printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", + trans->opcode); + return -1; + } + + optypes = readw_(cntlr.optype); + optype = (optypes >> (opcode_index * 2)) & 0x3; + if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && + optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && + trans->bytesout >= 3) { + /* We guessed wrong earlier. Fix it up. */ + trans->type = optype; + } + if (optype != trans->type) { + printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", + optype); + return -1; + } + return opcode_index; + } +} + +static int spi_setup_offset(spi_transaction *trans) +{ + /* Separate the SPI address and data. */ + switch (trans->type) { + case SPI_OPCODE_TYPE_READ_NO_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: + return 0; + case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: + trans->offset = ((uint32_t)trans->out[0] << 16) | + ((uint32_t)trans->out[1] << 8) | + ((uint32_t)trans->out[2] << 0); + spi_use_out(trans, 3); + return 1; + default: + printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); + return -1; + } +} + +/* + * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set + * below is True) or 0. In case the wait was for the bit(s) to set - write + * those bits back, which would cause resetting them. + * + * Return the last read status value on success or -1 on failure. + */ +static int ich_status_poll(u16 bitmask, int wait_til_set) +{ + int timeout = 6000; /* This will result in 60 ms */ + u16 status = 0; + + while (timeout--) { + status = readw_(cntlr.status); + if (wait_til_set ^ ((status & bitmask) == 0)) { + if (wait_til_set) + writew_((status & bitmask), cntlr.status); + return status; + } + udelay(10); + } + + printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", + status, bitmask); + return -1; +} + +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) +{ + uint16_t control; + int16_t opcode_index; + int with_address; + int status; + + spi_transaction trans = { + dout, bitsout / 8, + din, bitsin / 8, + 0xff, 0xff, 0 + }; + + /* There has to always at least be an opcode. */ + if (!bitsout || !dout) { + printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); + return -1; + } + /* Make sure if we read something we have a place to put it. */ + if (bitsin != 0 && !din) { + printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); + return -1; + } + /* Right now we don't support writing partial bytes. */ + if (bitsout % 8 || bitsin % 8) { + printk(BIOS_DEBUG, "ICH SPI: Accessing partial bytes not supported\n"); + return -1; + } + + if (ich_status_poll(SPIS_SCIP, 0) == -1) + return -1; + + writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); + + spi_setup_type(&trans); + if ((opcode_index = spi_setup_opcode(&trans)) < 0) + return -1; + if ((with_address = spi_setup_offset(&trans)) < 0) + return -1; + + if (!ichspi_lock && trans.opcode == 0x06) { + /* + * Treat Write Enable as Atomic Pre-Op if possible + * in order to prevent the Management Engine from + * issuing a transaction between WREN and DATA. + */ + writew_(trans.opcode, cntlr.preop); + return 0; + } + + /* Preset control fields */ + control = SPIC_SCGO | ((opcode_index & 0x07) << 4); + + /* Issue atomic preop cycle if needed */ + if (readw_(cntlr.preop)) + control |= SPIC_ACS; + + if (!trans.bytesout && !trans.bytesin) { + /* + * This is a 'no data' command (like Write Enable), its + * bitesout size was 1, decremented to zero while executing + * spi_setup_opcode() above. Tell the chip to send the + * command. + */ + writew_(control, cntlr.control); + + /* wait for the result */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); + return -1; + } + + return 0; + } + + /* + * Check if this is a write command atempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (trans.bytesout > cntlr.databytes) { + printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" + " CONTROLLER_PAGE_LIMIT?\n"); + return -1; + } + + /* + * Read or write up to databytes bytes at a time until everything has + * been sent. + */ + while (trans.bytesout || trans.bytesin) { + uint32_t data_length; + + /* SPI addresses are 24 bit only */ + writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + + if (trans.bytesout) + data_length = min(trans.bytesout, cntlr.databytes); + else + data_length = min(trans.bytesin, cntlr.databytes); + + /* Program data into FDATA0 to N */ + if (trans.bytesout) { + write_reg(trans.out, cntlr.data, data_length); + spi_use_out(&trans, data_length); + if (with_address) + trans.offset += data_length; + } + + /* Add proper control fields' values */ + control &= ~((cntlr.databytes - 1) << 8); + control |= SPIC_DS; + control |= (data_length - 1) << 8; + + /* write it */ + writew_(control, cntlr.control); + + /* Wait for Cycle Done Status or Flash Cycle Error. */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); + return -1; + } + + if (trans.bytesin) { + read_reg(cntlr.data, trans.in, data_length); + spi_use_in(&trans, data_length); + if (with_address) + trans.offset += data_length; + } + } + + /* Clear atomic preop now that xfer is done */ + writew_(0, cntlr.preop); + + return 0; +}

1 0

Patch set updated for coreboot: 2635d03 Hook up MRC cache update
by Stefan Reinauer 04 May '12

04 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1002 -gerrit commit 2635d031351d17a21bc37a8e79ed0dbbfae7db15 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 3 16:40:41 2012 -0700 Hook up MRC cache update This one is a WIP: - should not depend on CONFIG_CHROMEOS - There might be a better place for it. Requirements: - must be in ramstage (locking flash while executing code from there might not work) - must be after cbmem is reinitialized (so the mrc cache copy of the current run can be found) Change-Id: I8028fb073349ce2b027ef5f8397dc1a1b8b31c02 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/boot/tables.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 4fefc7d..ff57422 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -53,6 +53,11 @@ struct lb_memory *write_tables(void) */ unsigned long high_table_pointer; +#if CONFIG_CHROMEOS + void update_mrc_cache(void); + update_mrc_cache(); +#endif + if (!high_tables_base) { printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n"); // Are there any boards without?

1 0

Patch set updated for coreboot: 09ccbc4 Rework Sandybridge MRC cache handling
by Stefan Reinauer 04 May '12

04 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1001 -gerrit commit 09ccbc48859f06bcda97e8b04b7c38a6e8b36640 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 3 16:38:09 2012 -0700 Rework Sandybridge MRC cache handling - Separate Sandybridge from ChromeOS a bit The Sandybridge code depends on chromeos features a whole lot. As a first step, provide a code path to look up the MRC cache without depending on u-boot. - Move mrc cache handling to separate file This enables us to handle the MRC cache from ramstage, where we can write the flash safely (eg. to update the cache). Also teach it to lookup the current MRC cache from CBMEM, as the original data block isn't available anymore. After all the preparations, finally write to the SPI as necessary. It's a simple round robin wear levelling that erases the entire MRC cache region when it's full and starts from the beginning. Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/northbridge/intel/sandybridge/Kconfig | 17 ++ src/northbridge/intel/sandybridge/Makefile.inc | 2 + src/northbridge/intel/sandybridge/mrccache.c | 265 +++++++++++++++++++++++ src/northbridge/intel/sandybridge/raminit.c | 123 +---------- src/northbridge/intel/sandybridge/sandybridge.h | 22 ++ 5 files changed, 315 insertions(+), 114 deletions(-) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 8cf0a49..67b3def 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -37,6 +37,23 @@ config CACHE_MRC_SIZE_KB int default 256 +# FIXME: build from rom size +config MRC_CACHE_BASE + hex + default 0xff800000 + +config MRC_CACHE_LOCATION + hex + default 0x1ec000 + +config MRC_CACHE_SIZE + hex + default 0x10000 + +config MRC_CACHE_ALIGNMENT + hex + default 0x1000 + config DCACHE_RAM_BASE hex default 0xff7f0000 diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 87a0b2e..824700e 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -21,9 +21,11 @@ driver-y += northbridge.c driver-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-y += mrccache.c romstage-y += udelay.c romstage-y += raminit.c +romstage-y += mrccache.c romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c new file mode 100644 index 0000000..5c4c382 --- /dev/null +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -0,0 +1,265 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <console/console.h> +#include <cbfs.h> +#include <ip_checksum.h> +#include <device/device.h> +#include <cbmem.h> +#include "pei_data.h" +#include "sandybridge.h" +#include <spi.h> +#include <spi_flash.h> +/* Using the FDT FMAP for finding the MRC cache area requires including FDT + * support in coreboot, which we would like to avoid. There are a number of + * options: + * - Have each mainboard Kconfig supply a hard-coded offset + * - For ChromeOS devices: implement native FMAP + * - For non-ChromeOS devices: use CBFS + * For now let's leave this code in here until the issue is sorted out in + * a way that works for everyone. + */ +#undef USE_FDT_FMAP_FOR_MRC_CACHE +#ifdef USE_FDT_FMAP_FOR_MRC_CACHE +#include <fdt/libfdt.h> +#endif + +struct mrc_data_container *next_mrc_block(struct mrc_data_container *mrc_cache) +{ + /* MRC data blocks are aligned within the region */ + u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; + if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { + mrc_size &= ~(MRC_DATA_ALIGN - 1UL); + mrc_size += MRC_DATA_ALIGN; + } + + u8 *region_ptr = (u8*)mrc_cache; + region_ptr += mrc_size; + return (struct mrc_data_container *)region_ptr; +} + +int is_mrc_cache(struct mrc_data_container *mrc_cache) +{ + return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); +} + +u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) +{ + u8 *mrc_region; + u32 region_size; + u32 *data; +#ifdef USE_FDT_FMAP_FOR_MRC_CACHE + const struct fdt_header *fdt_header; + const struct fdt_property *fdtp; + int offset, len; + const char *compatible = "chromeos,flashmap"; + const char *subnode = "rw-mrc-cache"; + const char *property = "reg"; + u64 flashrom_base = 0; + + fdt_header = cbfs_find_file(CONFIG_FDT_FILE_NAME, CBFS_TYPE_FDT); + + if (!fdt_header) { + printk(BIOS_ERR, "%s: no FDT found!\n", __func__); + return 0; + } + + offset = fdt_node_offset_by_compatible(fdt_header, 0, compatible); + if (offset < 0) { + printk(BIOS_ERR, "%s: no %s node found!\n", + __func__, compatible); + return 0; + } + + if (fdt_get_base_addr(fdt_header, offset, &flashrom_base) < 0) { + printk(BIOS_ERR, "%s: no base address in node name!\n", + __func__); + return 0; + } + + offset = fdt_subnode_offset(fdt_header, offset, subnode); + if (offset < 0) { + printk(BIOS_ERR, "%s: no %s found!\n", __func__, subnode); + return 0; + } + + fdtp = fdt_get_property(fdt_header, offset, property, &len); + if (!fdtp || (len != 8)) { + printk(BIOS_ERR, "%s: property %s at %p, len %d!\n", + __func__, property, fdtp, len); + return 0; + } + + data = (u32 *)fdtp->data; + + // Calculate actual address of the MRC cache in memory + region_size = fdt32_to_cpu(data[1]); + mrc_region = (u8*)((unsigned long)flashrom_base + fdt32_to_cpu(data[0])); +#else + data = (u32 *)((void *)(CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION + 12)); + + region_size = CONFIG_MRC_CACHE_SIZE; + mrc_region = (u8*)(CONFIG_MRC_CACHE_BASE + be32_to_cpu(data[0])); +#endif + + *mrc_region_ptr = (struct mrc_data_container *)mrc_region; + + return region_size; +} + +/* find the first empty field in the MRC cache area. If there's none, return + * the first region. By testing for emptiness caller can detect if flash + * needs to be erased. + * + * FIXME: that interface is crap + */ +struct mrc_data_container *find_next_mrc_cache(void) +{ + u32 entry_id = 0; + struct mrc_data_container *mrc_cache = NULL; + u32 region_size = get_mrc_cache_region(&mrc_cache); + void *mrc_region = (void*)mrc_cache; + + if (mrc_cache == NULL) { + printk(BIOS_ERR, "%s: could not find mrc cache area\n", __func__); + return NULL; + } + + /* Search for the first empty entry in the region */ + while (is_mrc_cache(mrc_cache)) { + entry_id++; + mrc_cache = next_mrc_block(mrc_cache); + /* If we exceed the defined area, move to front */ + if ((void*)mrc_cache >= (void*)(mrc_region + region_size)) { + mrc_cache = (struct mrc_data_container *)mrc_region; + break; + } + } + + printk(BIOS_DEBUG, "picked entry %u from cache block when looking for empty block\n", entry_id); + + return mrc_cache; +} + +struct mrc_data_container *find_current_mrc_cache(void) +{ + u32 entry_id = 0; + struct mrc_data_container *mrc_next, *mrc_cache = NULL; + u32 region_size = get_mrc_cache_region(&mrc_cache); + void *mrc_region = (void*)mrc_cache; + mrc_next = mrc_cache; + + if (mrc_cache == NULL) { + printk(BIOS_ERR, "%s: could not find mrc cache area\n", __func__); + return NULL; + } + + if (mrc_cache->mrc_data_size == -1UL) { + printk(BIOS_ERR, "%s: MRC cache not initialized?\n", __func__); + /* return non-initialized cache, so we can discern this + * from having no cache area at all + */ + return mrc_cache; + } else { + /* Search for the last filled entry in the region */ + while (is_mrc_cache(mrc_next)) { + entry_id++; + mrc_cache = mrc_next; + mrc_next = next_mrc_block(mrc_cache); + /* Stay in the mrcdata region defined in fdt */ + if ((void*)mrc_next >= (void*)(mrc_region + region_size)) + break; + } + entry_id--; + } + + /* Verify checksum */ + if (mrc_cache->mrc_checksum != + compute_ip_checksum(mrc_cache->mrc_data, + mrc_cache->mrc_data_size)) { + printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); + return NULL; + } + + printk(BIOS_DEBUG, "picked entry %u from cache block\n", entry_id); + + return mrc_cache; +} + +/* SPI code needs malloc/free. + * Also unknown if writing flash from XIP-flash code is a good idea + */ +#if !defined(__PRE_RAM__) +void update_mrc_cache(void) +{ + struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); + if (!current) { + printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); + return; + } + if (current->mrc_data_size == -1) { + printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); + return; + } + + /* + * we need to: + */ + // 0. compare MRC data to last mrc-cache block (exit if same) + struct mrc_data_container *cache; + if ((cache = find_current_mrc_cache()) == NULL) { + printk(BIOS_DEBUG, "Failure looking for current last block\n"); + return; + } + + if ((cache->mrc_data_size == current->mrc_data_size) && (memcmp(cache, current, cache->mrc_data_size) == 0)) { + printk(BIOS_DEBUG, "MRC data in flash is up to date. No update.\n"); + return; + } + + // 1. use spi_flash_probe() to find the flash, then + spi_init(); + struct spi_flash *flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + return; + } + + // 2. look up the first unused block + cache = find_next_mrc_cache(); + if (!cache) { + printk(BIOS_DEBUG, "Could not find MRC cache area\n"); + return; + } + + // 3. if no such place exists, erase entire mrc-cache range & use block 0 + if (cache->mrc_data_size != -1) { + printk(BIOS_DEBUG, "We need to erase the MRC cache region\n"); + flash->erase(flash, CONFIG_MRC_CACHE_LOCATION, CONFIG_MRC_CACHE_SIZE); + /* we know we can start at the beginning again */ + get_mrc_cache_region(&cache); + } + // 4. write mrc data with flash->write() + printk(BIOS_DEBUG, "Finally: write MRC cache update to flash\n"); + flash->write(flash, (u32)(((void*)cache)-CONFIG_MRC_CACHE_BASE), current->mrc_data_size + sizeof(*current), current); +} +#endif + diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 6548b32..0df86d6 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -36,9 +36,8 @@ #include "southbridge/intel/bd82x6x/me.h" #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> -#endif -#if 0 -#include <fdt/libfdt.h> +#else +#define recovery_mode_enabled(x) 0 #endif /* @@ -56,17 +55,6 @@ #define CMOS_OFFSET_MRC_SEED_CHK 120 #endif -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - static void save_mrc_data(struct pei_data *pei_data) { u16 c1, c2, checksum; @@ -119,22 +107,10 @@ static void save_mrc_data(struct pei_data *pei_data) cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1); } -#if CONFIG_CHROMEOS static void prepare_mrc_cache(struct pei_data *pei_data) { -#if 0 - const struct fdt_header *fdt_header; - const struct fdt_property *fdtp; - int offset, len; - const char *compatible = "chromeos,flashmap"; - const char *subnode = "rw-mrc-cache"; - const char *property = "reg"; - u32 *data; - struct mrc_data_container *mrc_cache, *mrc_next; - u8 *mrc_region, *region_ptr; + struct mrc_data_container *mrc_cache; u16 c1, c2, checksum, seed_checksum; - u32 region_size, entry_id = 0; - u64 flashrom_base = 0; // preset just in case there is an error pei_data->mrc_input = NULL; @@ -166,96 +142,18 @@ static void prepare_mrc_cache(struct pei_data *pei_data) return; } - fdt_header = cbfs_find_file(CONFIG_FDT_FILE_NAME, CBFS_TYPE_FDT); - - if (!fdt_header) { - printk(BIOS_ERR, "%s: no FDT found!\n", __func__); - return; - } - - offset = fdt_node_offset_by_compatible(fdt_header, 0, compatible); - if (offset < 0) { - printk(BIOS_ERR, "%s: no %s node found!\n", - __func__, compatible); - return; - } - - if (fdt_get_base_addr(fdt_header, offset, &flashrom_base) < 0) { - printk(BIOS_ERR, "%s: no base address in node name!\n", - __func__); - return; - } - - offset = fdt_subnode_offset(fdt_header, offset, subnode); - if (offset < 0) { - printk(BIOS_ERR, "%s: no %s found!\n", __func__, subnode); - return; - } - - fdtp = fdt_get_property(fdt_header, offset, property, &len); - if (!fdtp || (len != 8)) { - printk(BIOS_ERR, "%s: property %s at %p, len %d!\n", - __func__, property, fdtp, len); - return; - } - - data = (u32 *)fdtp->data; - - // Calculate actual address of the MRC cache in memory - region_size = fdt32_to_cpu(data[1]); - mrc_region = region_ptr = (u8*) - ((unsigned long)flashrom_base + fdt32_to_cpu(data[0])); - mrc_cache = mrc_next = (struct mrc_data_container *)mrc_region; - - if (!mrc_cache || mrc_cache->mrc_signature != MRC_DATA_SIGNATURE) { - printk(BIOS_ERR, "%s: invalid MRC data\n", __func__); - return; - } - - if (mrc_cache->mrc_data_size == -1UL) { - printk(BIOS_ERR, "%s: MRC cache not initialized?\n", __func__); - return; - } else { - /* MRC data blocks are aligned within the region */ - u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; - if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { - mrc_size &= ~(MRC_DATA_ALIGN - 1UL); - mrc_size += MRC_DATA_ALIGN; - } - - /* Search for the last filled entry in the region */ - while (mrc_next && - mrc_next->mrc_signature == MRC_DATA_SIGNATURE) { - entry_id++; - mrc_cache = mrc_next; - /* Stay in the mrcdata region defined in fdt */ - if ((entry_id * mrc_size) > region_size) - break; - region_ptr += mrc_size; - mrc_next = (struct mrc_data_container *)region_ptr; - } - entry_id--; - } - - /* Verify checksum */ - if (mrc_cache->mrc_checksum != - compute_ip_checksum(mrc_cache->mrc_data, - mrc_cache->mrc_data_size)) { - printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); + if ((mrc_cache = find_current_mrc_cache()) == NULL) { + /* error message printed in find_current_mrc_cache */ return; } pei_data->mrc_input = mrc_cache->mrc_data; pei_data->mrc_input_len = mrc_cache->mrc_data_size; - printk(BIOS_DEBUG, "%s: at %p, entry %u size %x checksum %04x\n", - __func__, pei_data->mrc_input, entry_id, + printk(BIOS_DEBUG, "%s: at %p, size %x checksum %04x\n", + __func__, pei_data->mrc_input, pei_data->mrc_input_len, mrc_cache->mrc_checksum); -#else - printk(BIOS_ERR, "MRC cache handling code has to be redone.\n"); -#endif } -#endif static const char* ecc_decoder[] = { "inactive", @@ -315,7 +213,6 @@ static void report_memory_config(void) void sdram_initialize(struct pei_data *pei_data) { struct sys_info sysinfo; - const char *target = "mrc.bin"; unsigned long entry; report_platform_info(); @@ -330,7 +227,6 @@ void sdram_initialize(struct pei_data *pei_data) sysinfo.boot_path = pei_data->boot_mode; -#if CONFIG_CHROMEOS /* * Do not pass MRC data in for recovery mode boot, * Always pass it in for S3 resume. @@ -344,17 +240,16 @@ void sdram_initialize(struct pei_data *pei_data) outb(0x6, 0xcf9); hlt(); } -#endif /* Locate and call UEFI System Agent binary. */ - entry = (unsigned long)cbfs_find_file(target, 0xab); + entry = (unsigned long)cbfs_find_file("mrc.bin", 0xab); if (entry) { int rv; asm volatile ( "call *%%ecx\n\t" :"=a" (rv) : "c" (entry), "a" (pei_data)); if (rv) { - printk(BIOS_ERR, "MRC returned %d\n", rv); + printk(BIOS_ERR, "MRC returned %x\n", rv); die("Nonzero MRC return value\n"); } } else { diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index aa62021..7e12416 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -221,6 +221,28 @@ void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ + + +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) + +struct mrc_data_container { + u32 mrc_signature; // "MRCD" + u32 mrc_data_size; // Actual total size of this structure + u32 mrc_checksum; // IP style checksum + u32 reserved; // For header alignment + u8 mrc_data[0]; // Variable size, platform/run time dependent. +} __attribute__ ((packed)); + +struct mrc_data_container *next_mrc_block(struct mrc_data_container *mrc_cache); +int is_mrc_cache(struct mrc_data_container *mrc_cache); +u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr); +struct mrc_data_container *find_next_mrc_cache(void); +struct mrc_data_container *find_current_mrc_cache(void); +#if !defined(__PRE_RAM__) +void update_mrc_cache(void); +#endif + #endif #endif #endif

1 0

Patch set updated for coreboot: ab95893 Add SPI driver
by Stefan Reinauer 04 May '12

04 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/997 -gerrit commit ab95893b42595782c73210c11f8d28f0a6d35c69 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 2 17:07:05 2012 -0700 Add SPI driver This driver is taken from u-boot and adapted to match coreboot. It still contains some hacks and is ICH specific at places. Change-Id: I97dd8096f7db3b62f8f4f4e4d08bdee10d88f689 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/drivers/Kconfig | 1 + src/drivers/Makefile.inc | 1 + src/drivers/spi/Kconfig | 73 +++ src/drivers/spi/Makefile.inc | 12 + src/drivers/spi/eon.c | 161 ++++++ src/drivers/spi/macronix.c | 220 +++++++++ src/drivers/spi/ramtron.c | 315 ++++++++++++ src/drivers/spi/spansion.c | 241 +++++++++ src/drivers/spi/spi_flash.c | 309 ++++++++++++ src/drivers/spi/spi_flash_internal.h | 81 +++ src/drivers/spi/sst.c | 268 ++++++++++ src/drivers/spi/stmicro.c | 250 ++++++++++ src/drivers/spi/winbond.c | 218 ++++++++ src/include/device/pci_ids.h | 4 + src/include/spi.h | 203 ++++++++ src/include/spi_flash.h | 91 ++++ src/northbridge/intel/sandybridge/raminit.c | 1 + src/southbridge/intel/bd82x6x/Kconfig | 1 + src/southbridge/intel/bd82x6x/Makefile.inc | 2 + src/southbridge/intel/bd82x6x/spi.c | 712 +++++++++++++++++++++++++++ 20 files changed, 3164 insertions(+), 0 deletions(-) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 259bc29..60e5b65 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -26,3 +26,4 @@ source src/drivers/oxford/Kconfig source src/drivers/sil/Kconfig source src/drivers/trident/Kconfig source src/drivers/ics/Kconfig +source src/drivers/spi/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 5f6dadf..851a4df 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -26,4 +26,5 @@ subdirs-y += oxford subdirs-y += sil subdirs-y += trident subdirs-y += ics +subdirs-y += spi subdirs-$(CONFIG_ARCH_X86) += pc80 diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig new file mode 100644 index 0000000..849d0ac --- /dev/null +++ b/src/drivers/spi/Kconfig @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 The Chromium OS Authors. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SPI + bool + default n + help + Select this option if your chipset driver needs to store certain + data in the SPI flash. + +config SPI_FLASH_EON + bool + default y + depends on SPI + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by EON. + +config SPI_FLASH_MACRONIX + bool + default y + depends on SPI + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by Macronix. + +config SPI_FLASH_SPANSION + bool + default y + depends on SPI + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by Spansion. + +config SPI_FLASH_SST + bool + default y + depends on SPI + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by SST. + +config SPI_FLASH_STMICRO + bool + default y + depends on SPI + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by ST MICRO. + +config SPI_FLASH_WINBOND + bool + default y + depends on SPI + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by Winbond. diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc new file mode 100644 index 0000000..6cdf398 --- /dev/null +++ b/src/drivers/spi/Makefile.inc @@ -0,0 +1,12 @@ +# SPI driver interface +ramstage-$(CONFIG_SPI) += spi_flash.c + +# drivers +ramstage-$(CONFIG_SPI_FLASH_EON) += eon.c +ramstage-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c +ramstage-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c +ramstage-$(CONFIG_SPI_FLASH_SST) += sst.c +ramstage-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c +ramstage-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c +ramstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c + diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c new file mode 100644 index 0000000..4056953 --- /dev/null +++ b/src/drivers/spi/eon.c @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2010, ucRobotics Inc. + * Author: Chong Huang <chuang(a)ucrobotics.com> + * Licensed under the GPL-2 or later. + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* EN25Q128-specific commands */ +#define CMD_EN25Q128_WREN 0x06 /* Write Enable */ +#define CMD_EN25Q128_WRDI 0x04 /* Write Disable */ +#define CMD_EN25Q128_RDSR 0x05 /* Read Status Register */ +#define CMD_EN25Q128_WRSR 0x01 /* Write Status Register */ +#define CMD_EN25Q128_READ 0x03 /* Read Data Bytes */ +#define CMD_EN25Q128_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_EN25Q128_PP 0x02 /* Page Program */ +#define CMD_EN25Q128_SE 0x20 /* Sector Erase */ +#define CMD_EN25Q128_BE 0xd8 /* Block Erase */ +#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */ +#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */ + +#define EON_ID_EN25Q128 0x18 + +struct eon_spi_flash_params { + u8 idcode1; + u16 page_size; + u16 pages_per_sector; + u16 sectors_per_block; + u16 nr_sectors; + const char *name; +}; + +/* spi_flash needs to be first so upper layers can free() it */ +struct eon_spi_flash { + struct spi_flash flash; + const struct eon_spi_flash_params *params; +}; + +static inline struct eon_spi_flash *to_eon_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct eon_spi_flash, flash); +} + +static const struct eon_spi_flash_params eon_spi_flash_table[] = { + { + .idcode1 = EON_ID_EN25Q128, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 4096, + .name = "EN25Q128", + }, +}; + +static int eon_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct eon_spi_flash *eon = to_eon_spi_flash(flash); + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = eon->params->page_size; + page_addr = offset / page_size; + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + ret = 0; + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_EN25Q128_PP; + cmd[1] = page_addr >> 8; + cmd[2] = page_addr; + cmd[3] = byte_addr; + + printk(BIOS_SPEW, + "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + break; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: EON Page Program failed\n"); + break; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + break; + + page_addr++; + byte_addr = 0; + } + + printk(BIOS_INFO, "SF: EON: Successfully programmed %zu bytes @ 0x%x\n", + len, offset); + + spi_release_bus(flash->spi); + return ret; +} + +static int eon_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_EN25Q128_BE, offset, len); +} + +struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) +{ + const struct eon_spi_flash_params *params; + struct eon_spi_flash *eon; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) { + params = &eon_spi_flash_table[i]; + if (params->idcode1 == idcode[2]) + break; + } + + if (i == ARRAY_SIZE(eon_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported EON ID %02x\n", idcode[1]); + return NULL; + } + + eon = malloc(sizeof(*eon)); + if (!eon) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + eon->params = params; + eon->flash.spi = spi; + eon->flash.name = params->name; + + eon->flash.write = eon_write; + eon->flash.erase = eon_erase; + eon->flash.read = spi_flash_cmd_read_fast; + eon->flash.sector_size = params->page_size * params->pages_per_sector + * params->sectors_per_block; + eon->flash.size = params->page_size * params->pages_per_sector + * params->nr_sectors; + + return &eon->flash; +} diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c new file mode 100644 index 0000000..130e746 --- /dev/null +++ b/src/drivers/spi/macronix.c @@ -0,0 +1,220 @@ +/* + * Copyright 2009(C) Marvell International Ltd. and its affiliates + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * Based on drivers/mtd/spi/stmicro.c + * + * Copyright 2008, Network Appliance Inc. + * Jason McMullan <mcmullan(a)netapp.com> + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* MX25xx-specific commands */ +#define CMD_MX25XX_WREN 0x06 /* Write Enable */ +#define CMD_MX25XX_WRDI 0x04 /* Write Disable */ +#define CMD_MX25XX_RDSR 0x05 /* Read Status Register */ +#define CMD_MX25XX_WRSR 0x01 /* Write Status Register */ +#define CMD_MX25XX_READ 0x03 /* Read Data Bytes */ +#define CMD_MX25XX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_MX25XX_PP 0x02 /* Page Program */ +#define CMD_MX25XX_SE 0x20 /* Sector Erase */ +#define CMD_MX25XX_BE 0xD8 /* Block Erase */ +#define CMD_MX25XX_CE 0xc7 /* Chip Erase */ +#define CMD_MX25XX_DP 0xb9 /* Deep Power-down */ +#define CMD_MX25XX_RES 0xab /* Release from DP, and Read Signature */ + +#define MACRONIX_SR_WIP (1 << 0) /* Write-in-Progress */ + +struct macronix_spi_flash_params { + u16 idcode; + u16 page_size; + u16 pages_per_sector; + u16 sectors_per_block; + u16 nr_blocks; + const char *name; +}; + +struct macronix_spi_flash { + struct spi_flash flash; + const struct macronix_spi_flash_params *params; +}; + +static inline struct macronix_spi_flash *to_macronix_spi_flash(struct spi_flash + *flash) +{ + return container_of(flash, struct macronix_spi_flash, flash); +} + +static const struct macronix_spi_flash_params macronix_spi_flash_table[] = { + { + .idcode = 0x2015, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "MX25L1605D", + }, + { + .idcode = 0x2016, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "MX25L3205D", + }, + { + .idcode = 0x2017, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "MX25L6405D", + }, + { + .idcode = 0x2018, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 256, + .name = "MX25L12805D", + }, + { + .idcode = 0x2618, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 256, + .name = "MX25L12855E", + }, +}; + +static int macronix_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct macronix_spi_flash *mcx = to_macronix_spi_flash(flash); + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = min(mcx->params->page_size, CONTROLLER_PAGE_LIMIT); + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + ret = 0; + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_MX25XX_PP; + cmd[1] = (offset >> 16) & 0xff; + cmd[2] = (offset >> 8) & 0xff; + cmd[3] = offset & 0xff; + + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + break; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Macronix Page Program failed\n"); + break; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + break; + + offset += chunk_len; + byte_addr = 0; + } + + printk(BIOS_INFO, "SF: Macronix: Successfully programmed %zu bytes @ 0x%lx\n", + len, offset - len); + + spi_release_bus(flash->spi); + return ret; +} + +static int macronix_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_MX25XX_SE, offset, len); +} + +struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode) +{ + const struct macronix_spi_flash_params *params; + struct macronix_spi_flash *mcx; + unsigned int i; + u16 id = idcode[2] | idcode[1] << 8; + + for (i = 0; i < ARRAY_SIZE(macronix_spi_flash_table); i++) { + params = &macronix_spi_flash_table[i]; + if (params->idcode == id) + break; + } + + if (i == ARRAY_SIZE(macronix_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported Macronix ID %04x\n", id); + return NULL; + } + + mcx = malloc(sizeof(*mcx)); + if (!mcx) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + mcx->params = params; + mcx->flash.spi = spi; + mcx->flash.name = params->name; + + mcx->flash.write = macronix_write; + mcx->flash.erase = macronix_erase; +#ifdef CONFIG_SPI_FLASH_NO_FAST_READ + mcx->flash.read = spi_flash_cmd_read_slow; +#else + mcx->flash.read = spi_flash_cmd_read_fast; +#endif + mcx->flash.sector_size = params->page_size * params->pages_per_sector; + mcx->flash.size = mcx->flash.sector_size * params->sectors_per_block * + params->nr_blocks; + + return &mcx->flash; +} diff --git a/src/drivers/spi/ramtron.c b/src/drivers/spi/ramtron.c new file mode 100644 index 0000000..2d50b85 --- /dev/null +++ b/src/drivers/spi/ramtron.c @@ -0,0 +1,315 @@ +/* + * (C) Copyright 2010 + * Reinhard Meyer, EMK Elektronik, reinhard.meyer(a)emk-elektronik.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Note: RAMTRON SPI FRAMs are ferroelectric, nonvolatile RAMs + * with an interface identical to SPI flash devices. + * However since they behave like RAM there are no delays or + * busy polls required. They can sustain read or write at the + * allowed SPI bus speed, which can be 40 MHz for some devices. + * + * Unfortunately some RAMTRON devices do not have a means of + * identifying them. They will leave the SO line undriven when + * the READ-ID command is issued. It is therefore mandatory + * that the MISO line has a proper pull-up, so that READ-ID + * will return a row of 0xff. This 0xff pseudo-id will cause + * probes by all vendor specific functions that are designed + * to handle it. If the MISO line is not pulled up, READ-ID + * could return any random noise, even mimicking another + * device. + * + * We use CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC + * to define which device will be assumed after a simple status + * register verify. This method is prone to false positive + * detection and should therefore be the last to be tried. + * Enter it in the last position in the table in spi_flash.c! + * + * The define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC both activates + * compilation of the special handler and defines the device + * to assume. + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* RAMTRON commands common to all devices */ +#define CMD_RAMTRON_WREN 0x06 /* Write Enable */ +#define CMD_RAMTRON_WRDI 0x04 /* Write Disable */ +#define CMD_RAMTRON_RDSR 0x05 /* Read Status Register */ +#define CMD_RAMTRON_WRSR 0x01 /* Write Status Register */ +#define CMD_RAMTRON_READ 0x03 /* Read Data Bytes */ +#define CMD_RAMTRON_WRITE 0x02 /* Write Data Bytes */ +/* not all have those: */ +#define CMD_RAMTRON_FSTRD 0x0b /* Fast Read (for compatibility - not used here) */ +#define CMD_RAMTRON_SLEEP 0xb9 /* Enter Sleep Mode */ +#define CMD_RAMTRON_RDID 0x9f /* Read ID */ +#define CMD_RAMTRON_SNR 0xc3 /* Read Serial Number */ + +/* + * Properties of supported FRAMs + * Note: speed is currently not used because we have no method to deliver that + * value to the upper layers + */ +struct ramtron_spi_fram_params { + u32 size; /* size in bytes */ + u8 addr_len; /* number of address bytes */ + u8 merge_cmd; /* some address bits are in the command byte */ + u8 id1; /* device ID 1 (family, density) */ + u8 id2; /* device ID 2 (sub, rev, rsvd) */ + u32 speed; /* max. SPI clock in Hz */ + const char *name; /* name for display and/or matching */ +}; + +struct ramtron_spi_fram { + struct spi_flash flash; + const struct ramtron_spi_fram_params *params; +}; + +static inline struct ramtron_spi_fram *to_ramtron_spi_fram(struct spi_flash + *flash) +{ + return container_of(flash, struct ramtron_spi_fram, flash); +} + +/* + * table describing supported FRAM chips: + * chips without RDID command must have the values 0xff for id1 and id2 + */ +static const struct ramtron_spi_fram_params ramtron_spi_fram_table[] = { + { + .size = 32*1024, + .addr_len = 2, + .merge_cmd = 0, + .id1 = 0x22, + .id2 = 0x00, + .speed = 40000000, + .name = "FM25V02", + }, + { + .size = 32*1024, + .addr_len = 2, + .merge_cmd = 0, + .id1 = 0x22, + .id2 = 0x01, + .speed = 40000000, + .name = "FM25VN02", + }, + { + .size = 64*1024, + .addr_len = 2, + .merge_cmd = 0, + .id1 = 0x23, + .id2 = 0x00, + .speed = 40000000, + .name = "FM25V05", + }, + { + .size = 64*1024, + .addr_len = 2, + .merge_cmd = 0, + .id1 = 0x23, + .id2 = 0x01, + .speed = 40000000, + .name = "FM25VN05", + }, + { + .size = 128*1024, + .addr_len = 3, + .merge_cmd = 0, + .id1 = 0x24, + .id2 = 0x00, + .speed = 40000000, + .name = "FM25V10", + }, + { + .size = 128*1024, + .addr_len = 3, + .merge_cmd = 0, + .id1 = 0x24, + .id2 = 0x01, + .speed = 40000000, + .name = "FM25VN10", + }, +#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC + { + .size = 256*1024, + .addr_len = 3, + .merge_cmd = 0, + .id1 = 0xff, + .id2 = 0xff, + .speed = 40000000, + .name = "FM25H20", + }, +#endif +}; + +static int ramtron_common(struct spi_flash *flash, + u32 offset, size_t len, void *buf, u8 command) +{ + struct ramtron_spi_fram *sn = to_ramtron_spi_fram(flash); + u8 cmd[4]; + int cmd_len; + int ret; + + if (sn->params->addr_len == 3 && sn->params->merge_cmd == 0) { + cmd[0] = command; + cmd[1] = offset >> 16; + cmd[2] = offset >> 8; + cmd[3] = offset; + cmd_len = 4; + } else if (sn->params->addr_len == 2 && sn->params->merge_cmd == 0) { + cmd[0] = command; + cmd[1] = offset >> 8; + cmd[2] = offset; + cmd_len = 3; + } else { + printk(BIOS_WARNING, "SF: unsupported addr_len or merge_cmd\n"); + return -1; + } + + /* claim the bus */ + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + if (command == CMD_RAMTRON_WRITE) { + /* send WREN */ + ret = spi_flash_cmd(flash->spi, CMD_RAMTRON_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + goto releasebus; + } + } + + /* do the transaction */ + if (command == CMD_RAMTRON_WRITE) + ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, buf, len); + else + ret = spi_flash_cmd_read(flash->spi, cmd, cmd_len, buf, len); + if (ret < 0) + printk(BIOS_WARNING, "SF: Transaction failed\n"); + +releasebus: + /* release the bus */ + spi_release_bus(flash->spi); + return ret; +} + +static int ramtron_read(struct spi_flash *flash, + u32 offset, size_t len, void *buf) +{ + return ramtron_common(flash, offset, len, buf, + CMD_RAMTRON_READ); +} + +static int ramtron_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + return ramtron_common(flash, offset, len, (void *)buf, + CMD_RAMTRON_WRITE); +} + +static int ramtron_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + printk(BIOS_SPEW, "SF: Erase of RAMTRON FRAMs is pointless\n"); + return -1; +} + +/* + * nore: we are called here with idcode pointing to the first non-0x7f byte + * already! + */ +struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode) +{ + const struct ramtron_spi_fram_params *params; + struct ramtron_spi_fram *sn; + unsigned int i; +#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC + int ret; + u8 sr; +#endif + + /* NOTE: the bus has been claimed before this function is called! */ + switch (idcode[0]) { + case 0xc2: + /* JEDEC conformant RAMTRON id */ + for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) { + params = &ramtron_spi_fram_table[i]; + if (idcode[1] == params->id1 && idcode[2] == params->id2) + goto found; + } + break; +#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC + case 0xff: + /* + * probably open MISO line, pulled up. + * We COULD have a non JEDEC conformant FRAM here, + * read the status register to verify + */ + ret = spi_flash_cmd(spi, CMD_RAMTRON_RDSR, &sr, 1); + if (ret) + return NULL; + + /* Bits 5,4,0 are fixed 0 for all devices */ + if ((sr & 0x31) != 0x00) + return NULL; + /* now find the device */ + for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) { + params = &ramtron_spi_fram_table[i]; + if (!strcmp(params->name, CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC)) + goto found; + } + printk(BIOS_WARNING, "SF: Unsupported non-JEDEC RAMTRON device " + CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC "\n"); + break; +#endif + default: + break; + } + + /* arriving here means no method has found a device we can handle */ + printk(BIOS_WARNING, "SF/ramtron: unsupported device id0=%02x id1=%02x id2=%02x\n", + idcode[0], idcode[1], idcode[2]); + return NULL; + +found: + sn = malloc(sizeof(*sn)); + if (!sn) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + sn->params = params; + sn->flash.spi = spi; + sn->flash.name = params->name; + + sn->flash.write = ramtron_write; + sn->flash.read = ramtron_read; + sn->flash.erase = ramtron_erase; + sn->flash.size = params->size; + + return &sn->flash; +} diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c new file mode 100644 index 0000000..a4f370a --- /dev/null +++ b/src/drivers/spi/spansion.c @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2009 Freescale Semiconductor, Inc. + * + * Author: Mingkai Hu (Mingkai.hu(a)freescale.com) + * Based on stmicro.c by Wolfgang Denk (wd(a)denx.de), + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com), + * and Jason McMullan (mcmullan(a)netapp.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* S25FLxx-specific commands */ +#define CMD_S25FLXX_READ 0x03 /* Read Data Bytes */ +#define CMD_S25FLXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_S25FLXX_READID 0x90 /* Read Manufacture ID and Device ID */ +#define CMD_S25FLXX_WREN 0x06 /* Write Enable */ +#define CMD_S25FLXX_WRDI 0x04 /* Write Disable */ +#define CMD_S25FLXX_RDSR 0x05 /* Read Status Register */ +#define CMD_S25FLXX_WRSR 0x01 /* Write Status Register */ +#define CMD_S25FLXX_PP 0x02 /* Page Program */ +#define CMD_S25FLXX_SE 0xd8 /* Sector Erase */ +#define CMD_S25FLXX_BE 0xc7 /* Bulk Erase */ +#define CMD_S25FLXX_DP 0xb9 /* Deep Power-down */ +#define CMD_S25FLXX_RES 0xab /* Release from DP, and Read Signature */ + +#define SPSN_ID_S25FL008A 0x0213 +#define SPSN_ID_S25FL016A 0x0214 +#define SPSN_ID_S25FL032A 0x0215 +#define SPSN_ID_S25FL064A 0x0216 +#define SPSN_ID_S25FL128P 0x2018 +#define SPSN_EXT_ID_S25FL128P_256KB 0x0300 +#define SPSN_EXT_ID_S25FL128P_64KB 0x0301 +#define SPSN_EXT_ID_S25FL032P 0x4d00 + +struct spansion_spi_flash_params { + u16 idcode1; + u16 idcode2; + u16 page_size; + u16 pages_per_sector; + u16 nr_sectors; + const char *name; +}; + +struct spansion_spi_flash { + struct spi_flash flash; + const struct spansion_spi_flash_params *params; +}; + +static inline struct spansion_spi_flash *to_spansion_spi_flash(struct spi_flash + *flash) +{ + return container_of(flash, struct spansion_spi_flash, flash); +} + +static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { + { + .idcode1 = SPSN_ID_S25FL008A, + .idcode2 = 0, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 16, + .name = "S25FL008A", + }, + { + .idcode1 = SPSN_ID_S25FL016A, + .idcode2 = 0, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 32, + .name = "S25FL016A", + }, + { + .idcode1 = SPSN_ID_S25FL032A, + .idcode2 = 0, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 64, + .name = "S25FL032A", + }, + { + .idcode1 = SPSN_ID_S25FL064A, + .idcode2 = 0, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 128, + .name = "S25FL064A", + }, + { + .idcode1 = SPSN_ID_S25FL128P, + .idcode2 = SPSN_EXT_ID_S25FL128P_64KB, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 256, + .name = "S25FL128P_64K", + }, + { + .idcode1 = SPSN_ID_S25FL128P, + .idcode2 = SPSN_EXT_ID_S25FL128P_256KB, + .page_size = 256, + .pages_per_sector = 1024, + .nr_sectors = 64, + .name = "S25FL128P_256K", + }, + { + .idcode1 = SPSN_ID_S25FL032A, + .idcode2 = SPSN_EXT_ID_S25FL032P, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 64, + .name = "S25FL032P", + }, +}; + +static int spansion_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct spansion_spi_flash *spsn = to_spansion_spi_flash(flash); + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = spsn->params->page_size; + page_addr = offset / page_size; + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + ret = 0; + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_S25FLXX_PP; + cmd[1] = page_addr >> 8; + cmd[2] = page_addr; + cmd[3] = byte_addr; + + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + break; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: SPANSION Page Program failed\n"); + break; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + break; + + page_addr++; + byte_addr = 0; + } + + printk(BIOS_INFO, "SF: SPANSION: Successfully programmed %zu bytes @ 0x%x\n", + len, offset); + + spi_release_bus(flash->spi); + return ret; +} + +static int spansion_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_S25FLXX_SE, offset, len); +} + +struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) +{ + const struct spansion_spi_flash_params *params; + struct spansion_spi_flash *spsn; + unsigned int i; + unsigned short jedec, ext_jedec; + + jedec = idcode[1] << 8 | idcode[2]; + ext_jedec = idcode[3] << 8 | idcode[4]; + + for (i = 0; i < ARRAY_SIZE(spansion_spi_flash_table); i++) { + params = &spansion_spi_flash_table[i]; + if (params->idcode1 == jedec) { + if (params->idcode2 == ext_jedec) + break; + } + } + + if (i == ARRAY_SIZE(spansion_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported SPANSION ID %04x %04x\n", jedec, ext_jedec); + return NULL; + } + + spsn = malloc(sizeof(struct spansion_spi_flash)); + if (!spsn) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + spsn->params = params; + spsn->flash.spi = spi; + spsn->flash.name = params->name; + + spsn->flash.write = spansion_write; + spsn->flash.erase = spansion_erase; + spsn->flash.read = spi_flash_cmd_read_fast; + spsn->flash.sector_size = params->page_size * params->pages_per_sector; + spsn->flash.size = spsn->flash.sector_size * params->nr_sectors; + + return &spsn->flash; +} diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c new file mode 100644 index 0000000..33cb4d2 --- /dev/null +++ b/src/drivers/spi/spi_flash.c @@ -0,0 +1,309 @@ +/* + * SPI flash interface + * + * Copyright (C) 2008 Atmel Corporation + * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik + * + * Licensed under the GPL-2 or later. + */ + +#include <stdlib.h> +#include <string.h> +#include <spi.h> +#include <spi_flash.h> +#include <delay.h> +#include "spi_flash_internal.h" + +static void spi_flash_addr(u32 addr, u8 *cmd) +{ + /* cmd[0] is actual command */ + cmd[1] = addr >> 16; + cmd[2] = addr >> 8; + cmd[3] = addr >> 0; +} + +int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len) +{ + int ret = spi_xfer(spi, &cmd, 8, response, len * 8); + if (ret) + printk(BIOS_WARNING, "SF: Failed to send command %02x: %d\n", cmd, ret); + + return ret; +} + +int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len) +{ + int ret = spi_xfer(spi, cmd, cmd_len * 8, data, data_len * 8); + if (ret) { + printk(BIOS_WARNING, "SF: Failed to send read command (%zu bytes): %d\n", + data_len, ret); + } + + return ret; +} + +int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, + const void *data, size_t data_len) +{ + int ret; + u8 buff[cmd_len + data_len]; + memcpy(buff, cmd, cmd_len); + memcpy(buff + cmd_len, data, data_len); + + ret = spi_xfer(spi, buff, (cmd_len + data_len) * 8, NULL, 0); + if (ret) { + printk(BIOS_WARNING, "SF: Failed to send write command (%zu bytes): %d\n", + data_len, ret); + } + + return ret; +} + +int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len) +{ + struct spi_slave *spi = flash->spi; + int ret; + + spi_claim_bus(spi); + ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); + spi_release_bus(spi); + + return ret; +} + +int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, + size_t len, void *data) +{ + struct spi_slave *spi = flash->spi; + u8 cmd[5]; + + cmd[0] = CMD_READ_ARRAY_FAST; + spi_flash_addr(offset, cmd); + cmd[4] = 0x00; + + return spi_flash_cmd_read(spi, cmd, sizeof(cmd), data, len); +} + +int spi_flash_cmd_read_slow(struct spi_flash *flash, u32 offset, + size_t len, void *data) +{ + struct spi_slave *spi = flash->spi; + u8 cmd[4]; + + cmd[0] = CMD_READ_ARRAY_SLOW; + spi_flash_addr(offset, cmd); + + return spi_flash_cmd_read(spi, cmd, sizeof(cmd), data, len); +} + +int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, + u8 cmd, u8 poll_bit) +{ + struct spi_slave *spi = flash->spi; + unsigned long timebase; + int ret; + u8 status; + + timebase = timeout; + do { + ret = spi_flash_cmd_read(spi, &cmd, 1, &status, 1); + if (ret) + return -1; + + if ((status & poll_bit) == 0) + break; + + mdelay(1); + } while (timebase--); + + if ((status & poll_bit) == 0) + return 0; + + /* Timed out */ + printk(BIOS_DEBUG, "SF: time out!\n"); + return -1; +} + +int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) +{ + return spi_flash_cmd_poll_bit(flash, timeout, + CMD_READ_STATUS, STATUS_WIP); +} + +int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd, + u32 offset, size_t len) +{ + u32 start, end, erase_size; + int ret; + u8 cmd[4]; + + erase_size = flash->sector_size; + if (offset % erase_size || len % erase_size) { + printk(BIOS_WARNING, "SF: Erase offset/length not multiple of erase size\n"); + return -1; + } + + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + cmd[0] = erase_cmd; + start = offset; + end = start + len; + + while (offset < end) { + spi_flash_addr(offset, cmd); + offset += erase_size; + + printk(BIOS_SPEW, "SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], + cmd[2], cmd[3], offset); + + ret = spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); + if (ret) + goto out; + + ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0); + if (ret) + goto out; + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT); + if (ret) + goto out; + } + + printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); + + out: + spi_release_bus(flash->spi); + return ret; +} + +/* + * The following table holds all device probe functions + * + * shift: number of continuation bytes before the ID + * idcode: the expected IDCODE or 0xff for non JEDEC devices + * probe: the function to call + * + * Non JEDEC devices should be ordered in the table such that + * the probe functions with best detection algorithms come first. + * + * Several matching entries are permitted, they will be tried + * in sequence until a probe function returns non NULL. + * + * IDCODE_CONT_LEN may be redefined if a device needs to declare a + * larger "shift" value. IDCODE_PART_LEN generally shouldn't be + * changed. This is the max number of bytes probe functions may + * examine when looking up part-specific identification info. + * + * Probe functions will be given the idcode buffer starting at their + * manu id byte (the "idcode" in the table below). In other words, + * all of the continuation bytes will be skipped (the "shift" below). + */ +#define IDCODE_CONT_LEN 0 +#define IDCODE_PART_LEN 5 +static const struct { + const u8 shift; + const u8 idcode; + struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode); +} flashes[] = { + /* Keep it sorted by define name */ +#if CONFIG_SPI_FLASH_EON + { 0, 0x1c, spi_flash_probe_eon, }, +#endif +#if CONFIG_SPI_FLASH_MACRONIX + { 0, 0xc2, spi_flash_probe_macronix, }, +#endif +#if CONFIG_SPI_FLASH_SPANSION + { 0, 0x01, spi_flash_probe_spansion, }, +#endif +#if CONFIG_SPI_FLASH_SST + { 0, 0xbf, spi_flash_probe_sst, }, +#endif +#if CONFIG_SPI_FLASH_STMICRO + { 0, 0x20, spi_flash_probe_stmicro, }, +#endif +#if CONFIG_SPI_FLASH_WINBOND + { 0, 0xef, spi_flash_probe_winbond, }, +#endif + /* Keep it sorted by best detection */ +#if CONFIG_SPI_FLASH_STMICRO + { 0, 0xff, spi_flash_probe_stmicro, }, +#endif +}; +#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) + +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode) +{ + struct spi_slave *spi; + struct spi_flash *flash = NULL; + int ret, i, shift; + u8 idcode[IDCODE_LEN], *idp; + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { + printk(BIOS_WARNING, "SF: Failed to set up slave\n"); + return NULL; + } + + ret = spi_claim_bus(spi); + if (ret) { + printk(BIOS_WARNING, "SF: Failed to claim SPI bus: %d\n", ret); + goto err_claim_bus; + } + + /* Read the ID codes */ + ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); + if (ret) + goto err_read_id; + +#ifdef DEBUG + printk(BIOS_SPEW, "SF: Got idcodes\n"); + print_buffer(0, idcode, 1, sizeof(idcode), 0); +#endif + + /* count the number of continuation bytes */ + for (shift = 0, idp = idcode; + shift < IDCODE_CONT_LEN && *idp == 0x7f; + ++shift, ++idp) + continue; + + /* search the table for matches in shift and id */ + for (i = 0; i < ARRAY_SIZE(flashes); ++i) + if (flashes[i].shift == shift && flashes[i].idcode == *idp) { + /* we have a match, call probe */ + flash = flashes[i].probe(spi, idp); + if (flash) + break; + } + + if (!flash) { + printk(BIOS_WARNING, "SF: Unsupported manufacturer %02x\n", *idp); + goto err_manufacturer_probe; + } + + printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n", + flash->name, flash->sector_size, flash->size); + + spi_release_bus(spi); + + return flash; + +err_manufacturer_probe: +err_read_id: + spi_release_bus(spi); +err_claim_bus: + spi_free_slave(spi); + return NULL; +} + +void spi_flash_free(struct spi_flash *flash) +{ + spi_free_slave(flash->spi); + free(flash); +} diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h new file mode 100644 index 0000000..b895e2b --- /dev/null +++ b/src/drivers/spi/spi_flash_internal.h @@ -0,0 +1,81 @@ +/* + * SPI flash internal definitions + * + * Copyright (C) 2008 Atmel Corporation + */ + +/* Common parameters -- kind of high, but they should only occur when there + * is a problem (and well your system already is broken), so err on the side + * of caution in case we're dealing with slower SPI buses and/or processors. + */ +#define CONFIG_SYS_HZ 100 +#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) +#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) +#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) + +/* Common commands */ +#define CMD_READ_ID 0x9f + +#define CMD_READ_ARRAY_SLOW 0x03 +#define CMD_READ_ARRAY_FAST 0x0b +#define CMD_READ_ARRAY_LEGACY 0xe8 + +#define CMD_READ_STATUS 0x05 +#define CMD_WRITE_ENABLE 0x06 + +/* Common status */ +#define STATUS_WIP 0x01 + +/* Send a single-byte command to the device and read the response */ +int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); + +/* + * Send a multi-byte command to the device and read the response. Used + * for flash array reads, etc. + */ +int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len); + +int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, + size_t len, void *data); + +int spi_flash_cmd_read_slow(struct spi_flash *flash, u32 offset, + size_t len, void *data); + +/* + * Send a multi-byte command to the device followed by (optional) + * data. Used for programming the flash array, etc. + */ +int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, + const void *data, size_t data_len); + +/* + * Same as spi_flash_cmd_read() except it also claims/releases the SPI + * bus. Used as common part of the ->read() operation. + */ +int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, + size_t cmd_len, void *data, size_t data_len); + +/* Send a command to the device and wait for some bit to clear itself. */ +int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, + u8 cmd, u8 poll_bit); + +/* + * Send the read status command to the device and wait for the wip + * (write-in-progress) bit to clear itself. + */ +int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout); + +/* Erase sectors. */ +int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd, + u32 offset, size_t len); + +/* Manufacturer-specific probe functions */ +struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode); diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c new file mode 100644 index 0000000..56cc851 --- /dev/null +++ b/src/drivers/spi/sst.c @@ -0,0 +1,268 @@ +/* + * Driver for SST serial flashes + * + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * Copyright 2008, Network Appliance Inc. + * Jason McMullan <mcmullan(a)netapp.com> + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * Copyright (c) 2008-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +#define CMD_SST_WREN 0x06 /* Write Enable */ +#define CMD_SST_WRDI 0x04 /* Write Disable */ +#define CMD_SST_RDSR 0x05 /* Read Status Register */ +#define CMD_SST_WRSR 0x01 /* Write Status Register */ +#define CMD_SST_READ 0x03 /* Read Data Bytes */ +#define CMD_SST_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_SST_BP 0x02 /* Byte Program */ +#define CMD_SST_AAI_WP 0xAD /* Auto Address Increment Word Program */ +#define CMD_SST_SE 0x20 /* Sector Erase */ + +#define SST_SR_WIP (1 << 0) /* Write-in-Progress */ +#define SST_SR_WEL (1 << 1) /* Write enable */ +#define SST_SR_BP0 (1 << 2) /* Block Protection 0 */ +#define SST_SR_BP1 (1 << 3) /* Block Protection 1 */ +#define SST_SR_BP2 (1 << 4) /* Block Protection 2 */ +#define SST_SR_AAI (1 << 6) /* Addressing mode */ +#define SST_SR_BPL (1 << 7) /* BP bits lock */ + +struct sst_spi_flash_params { + u8 idcode1; + u16 nr_sectors; + const char *name; +}; + +struct sst_spi_flash { + struct spi_flash flash; + const struct sst_spi_flash_params *params; +}; + +static inline struct sst_spi_flash *to_sst_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct sst_spi_flash, flash); +} + +#define SST_SECTOR_SIZE (4 * 1024) +static const struct sst_spi_flash_params sst_spi_flash_table[] = { + { + .idcode1 = 0x8d, + .nr_sectors = 128, + .name = "SST25VF040B", + },{ + .idcode1 = 0x8e, + .nr_sectors = 256, + .name = "SST25VF080B", + },{ + .idcode1 = 0x41, + .nr_sectors = 512, + .name = "SST25VF016B", + },{ + .idcode1 = 0x4a, + .nr_sectors = 1024, + .name = "SST25VF032B", + },{ + .idcode1 = 0x4b, + .nr_sectors = 2048, + .name = "SST25VF064C", + },{ + .idcode1 = 0x01, + .nr_sectors = 16, + .name = "SST25WF512", + },{ + .idcode1 = 0x02, + .nr_sectors = 32, + .name = "SST25WF010", + },{ + .idcode1 = 0x03, + .nr_sectors = 64, + .name = "SST25WF020", + },{ + .idcode1 = 0x04, + .nr_sectors = 128, + .name = "SST25WF040", + }, +}; + +static int +sst_enable_writing(struct spi_flash *flash) +{ + int ret = spi_flash_cmd(flash->spi, CMD_SST_WREN, NULL, 0); + if (ret) + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + return ret; +} + +static int +sst_disable_writing(struct spi_flash *flash) +{ + int ret = spi_flash_cmd(flash->spi, CMD_SST_WRDI, NULL, 0); + if (ret) + printk(BIOS_WARNING, "SF: Disabling Write failed\n"); + return ret; +} + +static int +sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) +{ + int ret; + u8 cmd[4] = { + CMD_SST_BP, + offset >> 16, + offset >> 8, + offset, + }; + + printk(BIOS_SPEW, "BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", + spi_w8r8(flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); + + ret = sst_enable_writing(flash); + if (ret) + return ret; + + ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1); + if (ret) + return ret; + + return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); +} + +static int +sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) +{ + size_t actual, cmd_len; + int ret; + u8 cmd[4]; + + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + /* If the data is not word aligned, write out leading single byte */ + actual = offset % 2; + if (actual) { + ret = sst_byte_write(flash, offset, buf); + if (ret) + goto done; + } + offset += actual; + + ret = sst_enable_writing(flash); + if (ret) + goto done; + + cmd_len = 4; + cmd[0] = CMD_SST_AAI_WP; + cmd[1] = offset >> 16; + cmd[2] = offset >> 8; + cmd[3] = offset; + + for (; actual < len - 1; actual += 2) { + printk(BIOS_SPEW, "WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", + spi_w8r8(flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], + offset); + + ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, + buf + actual, 2); + if (ret) { + printk(BIOS_WARNING, "SF: SST word program failed\n"); + break; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + break; + + cmd_len = 1; + offset += 2; + } + + if (!ret) + ret = sst_disable_writing(flash); + + /* If there is a single trailing byte, write it out */ + if (!ret && actual != len) + ret = sst_byte_write(flash, offset, buf + actual); + + done: + printk(BIOS_INFO, "SF: SST: program %s %zu bytes @ 0x%lx\n", + ret ? "failure" : "success", len, offset - actual); + + spi_release_bus(flash->spi); + return ret; +} + +static int sst_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_SST_SE, offset, len); +} + +static int +sst_unlock(struct spi_flash *flash) +{ + int ret; + u8 cmd, status; + + ret = sst_enable_writing(flash); + if (ret) + return ret; + + cmd = CMD_SST_WRSR; + status = 0; + ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &status, 1); + if (ret) + printk(BIOS_WARNING, "SF: Unable to set status byte\n"); + + printk(BIOS_INFO, "SF: SST: status = %x\n", spi_w8r8(flash->spi, CMD_SST_RDSR)); + + return ret; +} + +struct spi_flash * +spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode) +{ + const struct sst_spi_flash_params *params; + struct sst_spi_flash *stm; + size_t i; + + for (i = 0; i < ARRAY_SIZE(sst_spi_flash_table); ++i) { + params = &sst_spi_flash_table[i]; + if (params->idcode1 == idcode[2]) + break; + } + + if (i == ARRAY_SIZE(sst_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported SST ID %02x\n", idcode[1]); + return NULL; + } + + stm = malloc(sizeof(*stm)); + if (!stm) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + stm->params = params; + stm->flash.spi = spi; + stm->flash.name = params->name; + + stm->flash.write = sst_write; + stm->flash.erase = sst_erase; + stm->flash.read = spi_flash_cmd_read_fast; + stm->flash.sector_size = SST_SECTOR_SIZE; + stm->flash.size = stm->flash.sector_size * params->nr_sectors; + + /* Flash powers up read-only, so clear BP# bits */ + sst_unlock(&stm->flash); + + return &stm->flash; +} diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c new file mode 100644 index 0000000..8cbdad5 --- /dev/null +++ b/src/drivers/spi/stmicro.c @@ -0,0 +1,250 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * Copyright 2008, Network Appliance Inc. + * Jason McMullan <mcmullan(a)netapp.com> + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* M25Pxx-specific commands */ +#define CMD_M25PXX_WREN 0x06 /* Write Enable */ +#define CMD_M25PXX_WRDI 0x04 /* Write Disable */ +#define CMD_M25PXX_RDSR 0x05 /* Read Status Register */ +#define CMD_M25PXX_WRSR 0x01 /* Write Status Register */ +#define CMD_M25PXX_READ 0x03 /* Read Data Bytes */ +#define CMD_M25PXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_M25PXX_PP 0x02 /* Page Program */ +#define CMD_M25PXX_SE 0xd8 /* Sector Erase */ +#define CMD_M25PXX_BE 0xc7 /* Bulk Erase */ +#define CMD_M25PXX_DP 0xb9 /* Deep Power-down */ +#define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */ + +#define STM_ID_M25P10 0x11 +#define STM_ID_M25P16 0x15 +#define STM_ID_M25P20 0x12 +#define STM_ID_M25P32 0x16 +#define STM_ID_M25P40 0x13 +#define STM_ID_M25P64 0x17 +#define STM_ID_M25P80 0x14 +#define STM_ID_M25P128 0x18 + +struct stmicro_spi_flash_params { + u8 idcode1; + u16 page_size; + u16 pages_per_sector; + u16 nr_sectors; + const char *name; +}; + +/* spi_flash needs to be first so upper layers can free() it */ +struct stmicro_spi_flash { + struct spi_flash flash; + const struct stmicro_spi_flash_params *params; +}; + +static inline struct stmicro_spi_flash *to_stmicro_spi_flash(struct spi_flash + *flash) +{ + return container_of(flash, struct stmicro_spi_flash, flash); +} + +static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = { + { + .idcode1 = STM_ID_M25P10, + .page_size = 256, + .pages_per_sector = 128, + .nr_sectors = 4, + .name = "M25P10", + }, + { + .idcode1 = STM_ID_M25P16, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 32, + .name = "M25P16", + }, + { + .idcode1 = STM_ID_M25P20, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 4, + .name = "M25P20", + }, + { + .idcode1 = STM_ID_M25P32, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 64, + .name = "M25P32", + }, + { + .idcode1 = STM_ID_M25P40, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 8, + .name = "M25P40", + }, + { + .idcode1 = STM_ID_M25P64, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 128, + .name = "M25P64", + }, + { + .idcode1 = STM_ID_M25P80, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 16, + .name = "M25P80", + }, + { + .idcode1 = STM_ID_M25P128, + .page_size = 256, + .pages_per_sector = 1024, + .nr_sectors = 64, + .name = "M25P128", + }, +}; + +static int stmicro_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct stmicro_spi_flash *stm = to_stmicro_spi_flash(flash); + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = stm->params->page_size; + page_addr = offset / page_size; + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + ret = 0; + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_M25PXX_PP; + cmd[1] = page_addr >> 8; + cmd[2] = page_addr; + cmd[3] = byte_addr; + + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + break; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: STMicro Page Program failed\n"); + break; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + break; + + page_addr++; + byte_addr = 0; + } + + printk(BIOS_INFO, "SF: STMicro: Successfully programmed %zu bytes @ 0x%x\n", + len, offset); + + spi_release_bus(flash->spi); + return ret; +} + +static int stmicro_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_M25PXX_SE, offset, len); +} + +struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) +{ + const struct stmicro_spi_flash_params *params; + struct stmicro_spi_flash *stm; + unsigned int i; + + if (idcode[0] == 0xff) { + i = spi_flash_cmd(spi, CMD_M25PXX_RES, + idcode, 4); + if (i) + return NULL; + if ((idcode[3] & 0xf0) == 0x10) { + idcode[0] = 0x20; + idcode[1] = 0x20; + idcode[2] = idcode[3] + 1; + } else + return NULL; + } + + for (i = 0; i < ARRAY_SIZE(stmicro_spi_flash_table); i++) { + params = &stmicro_spi_flash_table[i]; + if (params->idcode1 == idcode[2]) { + break; + } + } + + if (i == ARRAY_SIZE(stmicro_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported STMicro ID %02x\n", idcode[1]); + return NULL; + } + + stm = malloc(sizeof(struct stmicro_spi_flash)); + if (!stm) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + stm->params = params; + stm->flash.spi = spi; + stm->flash.name = params->name; + + stm->flash.write = stmicro_write; + stm->flash.erase = stmicro_erase; + stm->flash.read = spi_flash_cmd_read_fast; + stm->flash.sector_size = params->page_size * params->pages_per_sector; + stm->flash.size = stm->flash.sector_size * params->nr_sectors; + + return &stm->flash; +} diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c new file mode 100644 index 0000000..65818d5 --- /dev/null +++ b/src/drivers/spi/winbond.c @@ -0,0 +1,218 @@ +/* + * Copyright 2008, Network Appliance Inc. + * Author: Jason McMullan <mcmullan <at> netapp.com> + * Licensed under the GPL-2 or later. + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* M25Pxx-specific commands */ +#define CMD_W25_WREN 0x06 /* Write Enable */ +#define CMD_W25_WRDI 0x04 /* Write Disable */ +#define CMD_W25_RDSR 0x05 /* Read Status Register */ +#define CMD_W25_WRSR 0x01 /* Write Status Register */ +#define CMD_W25_READ 0x03 /* Read Data Bytes */ +#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_W25_PP 0x02 /* Page Program */ +#define CMD_W25_SE 0x20 /* Sector (4K) Erase */ +#define CMD_W25_BE 0xd8 /* Block (64K) Erase */ +#define CMD_W25_CE 0xc7 /* Chip Erase */ +#define CMD_W25_DP 0xb9 /* Deep Power-down */ +#define CMD_W25_RES 0xab /* Release from DP, and Read Signature */ + +struct winbond_spi_flash_params { + uint16_t id; + /* Log2 of page size in power-of-two mode */ + uint8_t l2_page_size; + uint16_t pages_per_sector; + uint16_t sectors_per_block; + uint16_t nr_blocks; + const char *name; +}; + +/* spi_flash needs to be first so upper layers can free() it */ +struct winbond_spi_flash { + struct spi_flash flash; + const struct winbond_spi_flash_params *params; +}; + +static inline struct winbond_spi_flash * +to_winbond_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct winbond_spi_flash, flash); +} + +static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { + { + .id = 0x3015, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "W25X16", + }, + { + .id = 0x3016, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "W25X32", + }, + { + .id = 0x3017, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "W25X64", + }, + { + .id = 0x4015, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "W25Q16", + }, + { + .id = 0x4016, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "W25Q32", + }, + { + .id = 0x4017, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "W25Q64", + }, + { + .id = 0x4018, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 256, + .name = "W25Q128", + }, +}; + +static int winbond_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct winbond_spi_flash *stm = to_winbond_spi_flash(flash); + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = min(1 << stm->params->l2_page_size, CONTROLLER_PAGE_LIMIT); + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_W25_PP; + cmd[1] = (offset >> 16) & 0xff; + cmd[2] = (offset >> 8) & 0xff; + cmd[3] = offset & 0xff; + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %ld\n", + buf + actual, + cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + goto out; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Winbond Page Program failed\n"); + goto out; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + goto out; + + offset += chunk_len; + byte_addr = 0; + } + + printk(BIOS_INFO, "SF: Winbond: Successfully programmed %zu bytes @ 0x%lx\n", + len, offset - len); + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +static int winbond_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_W25_SE, offset, len); +} + +struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) +{ + const struct winbond_spi_flash_params *params; + unsigned page_size; + struct winbond_spi_flash *stm; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) { + params = &winbond_spi_flash_table[i]; + if (params->id == ((idcode[1] << 8) | idcode[2])) + break; + } + + if (i == ARRAY_SIZE(winbond_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported Winbond ID %02x%02x\n", + idcode[1], idcode[2]); + return NULL; + } + + stm = malloc(sizeof(struct winbond_spi_flash)); + if (!stm) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + stm->params = params; + stm->flash.spi = spi; + stm->flash.name = params->name; + + /* Assuming power-of-two page size initially. */ + page_size = 1 << params->l2_page_size; + + stm->flash.write = winbond_write; + stm->flash.erase = winbond_erase; +#ifdef CONFIG_SPI_FLASH_NO_FAST_READ + stm->flash.read = spi_flash_cmd_read_slow; +#else + stm->flash.read = spi_flash_cmd_read_fast; +#endif + stm->flash.sector_size = (1 << stm->params->l2_page_size) * + stm->params->pages_per_sector; + stm->flash.size = page_size * params->pages_per_sector + * params->sectors_per_block + * params->nr_blocks; + + return &stm->flash; +} diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index a2d6884..1765293 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2502,6 +2502,10 @@ #define PCI_DEVICE_ID_INTEL_82801IO_LPC 0x2914 #define PCI_DEVICE_ID_INTEL_82801IH_LPC 0x2912 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f +#define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc + /* Intel 82801E (C-ICH) */ #define PCI_DEVICE_ID_INTEL_82801E_LPC 0x2450 #define PCI_DEVICE_ID_INTEL_82801E_USB 0x2452 diff --git a/src/include/spi.h b/src/include/spi.h new file mode 100644 index 0000000..bb84258 --- /dev/null +++ b/src/include/spi.h @@ -0,0 +1,203 @@ +/* + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren(a)cideas.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPI_H_ +#define _SPI_H_ + +#include <stdint.h> + +/* Controller-specific definitions: */ + +/* SPI mode flags */ +#define SPI_CPHA 0x01 /* clock phase */ +#define SPI_CPOL 0x02 /* clock polarity */ +#define SPI_MODE_0 (0|0) /* (original MicroWire) */ +#define SPI_MODE_1 (0|SPI_CPHA) +#define SPI_MODE_2 (SPI_CPOL|0) +#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) +#define SPI_CS_HIGH 0x04 /* CS active high */ +#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ +#define SPI_3WIRE 0x10 /* SI/SO signals shared */ +#define SPI_LOOP 0x20 /* loopback mode */ + +/* SPI transfer flags */ +#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */ +#define SPI_XFER_END 0x02 /* Deassert CS after transfer */ + +/*----------------------------------------------------------------------- + * Representation of a SPI slave, i.e. what we're communicating with. + * + * Drivers are expected to extend this with controller-specific data. + * + * bus: ID of the bus that the slave is attached to. + * cs: ID of the chip select connected to the slave. + */ +struct spi_slave { + unsigned int bus; + unsigned int cs; +}; + +/*----------------------------------------------------------------------- + * Initialization, must be called once on start up. + * + * TODO: I don't think we really need this. + */ +void spi_init(void); + +/*----------------------------------------------------------------------- + * Set up communications parameters for a SPI slave. + * + * This must be called once for each slave. Note that this function + * usually doesn't touch any actual hardware, it only initializes the + * contents of spi_slave so that the hardware can be easily + * initialized later. + * + * bus: Bus ID of the slave chip. + * cs: Chip select ID of the slave chip on the specified bus. + * max_hz: Maximum SCK rate in Hz. + * mode: Clock polarity, clock phase and other parameters. + * + * Returns: A spi_slave reference that can be used in subsequent SPI + * calls, or NULL if one or more of the parameters are not supported. + */ +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); + +/*----------------------------------------------------------------------- + * Free any memory associated with a SPI slave. + * + * slave: The SPI slave + */ +void spi_free_slave(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * Claim the bus and prepare it for communication with a given slave. + * + * This must be called before doing any transfers with a SPI slave. It + * will enable and initialize any SPI hardware as necessary, and make + * sure that the SCK line is in the correct idle state. It is not + * allowed to claim the same bus for several slaves without releasing + * the bus in between. + * + * slave: The SPI slave + * + * Returns: 0 if the bus was claimed successfully, or a negative value + * if it wasn't. + */ +int spi_claim_bus(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * Release the SPI bus + * + * This must be called once for every call to spi_claim_bus() after + * all transfers have finished. It may disable any SPI hardware as + * appropriate. + * + * slave: The SPI slave + */ +void spi_release_bus(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * SPI transfer + * + * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks + * "bitlen" bits in the SPI MISO port. That's just the way SPI works. + * + * The source of the outgoing bits is the "dout" parameter and the + * destination of the input bits is the "din" parameter. Note that "dout" + * and "din" can point to the same memory location, in which case the + * input data overwrites the output data (since both are buffered by + * temporary variables, this is OK). + * + * spi_xfer() interface: + * slave: The SPI slave which will be sending/receiving the data. + * dout: Pointer to a string of bits to send out. The bits are + * held in a byte array and are sent MSB first. + * bitsout: How many bits to write. + * din: Pointer to a string of bits that will be filled in. + * bitsin: How many bits to read. + * + * Returns: 0 on success, not 0 on failure + */ +int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, + void *din, unsigned int bitsin); + +/*----------------------------------------------------------------------- + * Determine if a SPI chipselect is valid. + * This function is provided by the board if the low-level SPI driver + * needs it to determine if a given chipselect is actually valid. + * + * Returns: 1 if bus:cs identifies a valid chip on this board, 0 + * otherwise. + */ +int spi_cs_is_valid(unsigned int bus, unsigned int cs); + +/*----------------------------------------------------------------------- + * Activate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should activate the chip select + * to the device identified by "slave". + */ +void spi_cs_activate(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * Deactivate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should deactivate the chip + * select to the device identified by "slave". + */ +void spi_cs_deactivate(struct spi_slave *slave); + +/*----------------------------------------------------------------------- + * Set transfer speed. + * This sets a new speed to be applied for next spi_xfer(). + * slave: The SPI slave + * hz: The transfer speed + */ +void spi_set_speed(struct spi_slave *slave, uint32_t hz); + +/*----------------------------------------------------------------------- + * Write 8 bits, then read 8 bits. + * slave: The SPI slave we're communicating with + * byte: Byte to be written + * + * Returns: The value that was read, or a negative value on error. + * + * TODO: This function probably shouldn't be inlined. + */ +static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte) +{ + unsigned char dout[2]; + unsigned char din[2]; + int ret; + + dout[0] = byte; + dout[1] = 0; + + ret = spi_xfer(slave, dout, 16, din, 16); + return ret < 0 ? ret : din[1]; +} + +#endif /* _SPI_H_ */ diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h new file mode 100644 index 0000000..2a1dcd4 --- /dev/null +++ b/src/include/spi_flash.h @@ -0,0 +1,91 @@ +/* + * Interface to SPI flash + * + * Copyright (C) 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _SPI_FLASH_H_ +#define _SPI_FLASH_H_ + +#include <stdint.h> +#include <stddef.h> +#include <console/console.h> +#include <spi.h> + +/** + * container_of - cast a member of a structure out to the containing structure + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + +#define min(a, b) ((a)<(b)?(a):(b)) + +#define CONFIG_ICH_SPI +#ifdef CONFIG_ICH_SPI +#define CONTROLLER_PAGE_LIMIT 64 +#else +/* any number larger than 4K would do, actually */ +#define CONTROLLER_PAGE_LIMIT ((int)(~0U>>1)) +#endif + +struct spi_flash { + struct spi_slave *spi; + + const char *name; + + u32 size; + + u32 sector_size; + + int (*read)(struct spi_flash *flash, u32 offset, + size_t len, void *buf); + int (*write)(struct spi_flash *flash, u32 offset, + size_t len, const void *buf); + int (*erase)(struct spi_flash *flash, u32 offset, + size_t len); +}; + +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode); +void spi_flash_free(struct spi_flash *flash); + +static inline int spi_flash_read(struct spi_flash *flash, u32 offset, + size_t len, void *buf) +{ + return flash->read(flash, offset, len, buf); +} + +static inline int spi_flash_write(struct spi_flash *flash, u32 offset, + size_t len, const void *buf) +{ + return flash->write(flash, offset, len, buf); +} + +static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, + size_t len) +{ + return flash->erase(flash, offset, len); +} + +#endif /* _SPI_FLASH_H_ */ diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 8209980..6548b32 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -340,6 +340,7 @@ void sdram_initialize(struct pei_data *pei_data) /* If MRC data is not found we cannot continue S3 resume. */ if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { + printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n"); outb(0x6, 0xcf9); hlt(); } diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 3891be1..f105ee3 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK + select SPI config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 5732254..f086426 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -34,6 +34,8 @@ ramstage-y += me_status.c ramstage-y += reset.c ramstage-y += watchdog.c +ramstage-y += spi.c + ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c $(me-src-y) finalize.c diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c new file mode 100644 index 0000000..c54a325 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -0,0 +1,712 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This file is derived from the flashrom project. */ +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <delay.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +#include <spi.h> + +#define min(a, b) ((a)<(b)?(a):(b)) + +typedef device_t pci_dev_t; +#define pci_read_config_byte(dev, reg, targ) *(targ) = pci_read_config8(dev, reg) +#define pci_read_config_word(dev, reg, targ) *(targ) = pci_read_config16(dev, reg) +#define pci_read_config_dword(dev, reg, targ) *(targ) = pci_read_config32(dev, reg) +#define pci_write_config_byte(dev, reg, val) pci_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val) pci_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val) pci_write_config32(dev, reg, val) + +typedef struct spi_slave ich_spi_slave; + +static int ichspi_lock = 0; + +typedef struct ich7_spi_regs { + uint16_t spis; + uint16_t spic; + uint32_t spia; + uint64_t spid[8]; + uint64_t _pad; + uint32_t bbar; + uint16_t preop; + uint16_t optype; + uint8_t opmenu[8]; +} __attribute__((packed)) ich7_spi_regs; + +typedef struct ich9_spi_regs { + uint32_t bfpr; + uint16_t hsfs; + uint16_t hsfc; + uint32_t faddr; + uint32_t _reserved0; + uint32_t fdata[16]; + uint32_t frap; + uint32_t freg[5]; + uint32_t _reserved1[3]; + uint32_t pr[5]; + uint32_t _reserved2[2]; + uint8_t ssfs; + uint8_t ssfc[3]; + uint16_t preop; + uint16_t optype; + uint8_t opmenu[8]; + uint32_t bbar; + uint8_t _reserved3[12]; + uint32_t fdoc; + uint32_t fdod; + uint8_t _reserved4[8]; + uint32_t afc; + uint32_t lvscc; + uint32_t uvscc; + uint8_t _reserved5[4]; + uint32_t fpb; + uint8_t _reserved6[28]; + uint32_t srdl; + uint32_t srdc; + uint32_t srd; +} __attribute__((packed)) ich9_spi_regs; + +typedef struct ich_spi_controller { + int locked; + + uint8_t *opmenu; + int menubytes; + uint16_t *preop; + uint16_t *optype; + uint32_t *addr; + uint8_t *data; + unsigned databytes; + uint8_t *status; + uint16_t *control; + uint32_t *bbar; +} ich_spi_controller; + +static ich_spi_controller cntlr; + +enum { + SPIS_SCIP = 0x0001, + SPIS_GRANT = 0x0002, + SPIS_CDS = 0x0004, + SPIS_FCERR = 0x0008, + SSFS_AEL = 0x0010, + SPIS_LOCK = 0x8000, + SPIS_RESERVED_MASK = 0x7ff0, + SSFS_RESERVED_MASK = 0x7fe2 +}; + +enum { + SPIC_SCGO = 0x000002, + SPIC_ACS = 0x000004, + SPIC_SPOP = 0x000008, + SPIC_DBC = 0x003f00, + SPIC_DS = 0x004000, + SPIC_SME = 0x008000, + SSFC_SCF_MASK = 0x070000, + SSFC_RESERVED = 0xf80000 +}; + +enum { + HSFS_FDONE = 0x0001, + HSFS_FCERR = 0x0002, + HSFS_AEL = 0x0004, + HSFS_BERASE_MASK = 0x0018, + HSFS_BERASE_SHIFT = 3, + HSFS_SCIP = 0x0020, + HSFS_FDOPSS = 0x2000, + HSFS_FDV = 0x4000, + HSFS_FLOCKDN = 0x8000 +}; + +enum { + HSFC_FGO = 0x0001, + HSFC_FCYCLE_MASK = 0x0006, + HSFC_FCYCLE_SHIFT = 1, + HSFC_FDBC_MASK = 0x3f00, + HSFC_FDBC_SHIFT = 8, + HSFC_FSMIE = 0x8000 +}; + +enum { + SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, + SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, + SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, + SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 +}; + +#ifdef DEBUG + +static u8 readb_(const void *addr) +{ + u8 v = readb(addr); + printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static u16 readw_(const void *addr) +{ + u16 v = readw(addr); + printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static u32 readl_(const void *addr) +{ + u32 v = readl(addr); + printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static void writeb_(u8 b, const void *addr) +{ + writeb(b, addr); + printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +static void writew_(u16 b, const void *addr) +{ + writew(b, addr); + printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +static void writel_(u32 b, const void *addr) +{ + writel(b, addr); + printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +#else /* DEBUG ^^^ defined vvv NOT defined */ + +#define readb_(a) read8((uint32_t)a) +#define readw_(a) read16((uint32_t)a) +#define readl_(a) read32((uint32_t)a) +#define writeb_(val, addr) write8((uint32_t)addr, val) +#define writew_(val, addr) write16((uint32_t)addr, val) +#define writel_(val, addr) write32((uint32_t)addr, val) + +#endif /* DEBUG ^^^ NOT defined */ + +static void write_reg(const void *value, void *dest, uint32_t size) +{ + const uint8_t *bvalue = value; + uint8_t *bdest = dest; + + while (size >= 4) { + writel_(*(const uint32_t *)bvalue, bdest); + bdest += 4; bvalue += 4; size -= 4; + } + while (size) { + writeb_(*bvalue, bdest); + bdest++; bvalue++; size--; + } +} + +static void read_reg(const void *src, void *value, uint32_t size) +{ + const uint8_t *bsrc = src; + uint8_t *bvalue = value; + + while (size >= 4) { + *(uint32_t *)bvalue = readl_(bsrc); + bsrc += 4; bvalue += 4; size -= 4; + } + while (size) { + *bvalue = readb_(bsrc); + bsrc++; bvalue++; size--; + } +} + +static void ich_set_bbar(uint32_t minaddr) +{ + const uint32_t bbar_mask = 0x00ffff00; + uint32_t ichspi_bbar; + + minaddr &= bbar_mask; + ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; + ichspi_bbar |= minaddr; + writel_(ichspi_bbar, cntlr.bbar); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + printk(BIOS_DEBUG, "spi_cs_is_valid used but not implemented\n"); + return 0; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + ich_spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); + return NULL; + } + + memset(slave, 0, sizeof(*slave)); + + slave->bus = bus; + slave->cs = cs; + return slave; +} + +void spi_free_slave(struct spi_slave *_slave) +{ + ich_spi_slave *slave = (ich_spi_slave *)_slave; + free(slave); +} + +static inline int spi_is_cougarpoint_lpc(uint16_t device_id) +{ + return device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && + device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX; +}; + +void spi_init(void) +{ + int ich_version = 0; + + uint8_t *rcrb; /* Root Complex Register Block */ + uint32_t rcba; /* Root Complex Base Address */ + uint8_t bios_cntl; + pci_dev_t dev; + + int bus; + int last_bus = 1; //FIXME: pci_last_busno(); + + if (last_bus == -1) { + printk(BIOS_DEBUG, "No PCI busses?\n"); + return; + } + + for (bus = 0; bus <= last_bus; bus++) { + uint32_t ids; + uint16_t vendor_id, device_id; + + dev = dev_find_slot(bus, PCI_DEVFN(31, 0)); + pci_read_config_dword(dev, 0, &ids); + vendor_id = ids; + device_id = (ids >> 16); + + if (vendor_id != PCI_VENDOR_ID_INTEL) + continue; + + if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) { + ich_version = 7; + break; + } else if (spi_is_cougarpoint_lpc(device_id)) { + ich_version = 9; + break; + } + } + + if (!ich_version) { + printk(BIOS_DEBUG, "ICH SPI: No ICH found.\n"); + return; + } + + pci_read_config_dword(dev, 0xf0, &rcba); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ + rcrb = (uint8_t *)(rcba & 0xffffc000); + switch (ich_version) { + case 7: + { + const uint16_t ich7_spibar_offset = 0x3020; + ich7_spi_regs *ich7_spi = + (ich7_spi_regs *)(rcrb + ich7_spibar_offset); + + ichspi_lock = readw_(&ich7_spi->spis) & SPIS_LOCK; + cntlr.opmenu = ich7_spi->opmenu; + cntlr.menubytes = sizeof(ich7_spi->opmenu); + cntlr.optype = &ich7_spi->optype; + cntlr.addr = &ich7_spi->spia; + cntlr.data = (uint8_t *)ich7_spi->spid; + cntlr.databytes = sizeof(ich7_spi->spid); + cntlr.status = (uint8_t *)&ich7_spi->spis; + cntlr.control = &ich7_spi->spic; + cntlr.bbar = &ich7_spi->bbar; + cntlr.preop = &ich7_spi->preop; + break; + } + case 9: + { + const uint16_t ich9_spibar_offset = 0x3800; + ich9_spi_regs *ich9_spi = + (ich9_spi_regs *)(rcrb + ich9_spibar_offset); + ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; + cntlr.opmenu = ich9_spi->opmenu; + cntlr.menubytes = sizeof(ich9_spi->opmenu); + cntlr.optype = &ich9_spi->optype; + cntlr.addr = &ich9_spi->faddr; + cntlr.data = (uint8_t *)ich9_spi->fdata; + cntlr.databytes = sizeof(ich9_spi->fdata); + cntlr.status = &ich9_spi->ssfs; + cntlr.control = (uint16_t *)ich9_spi->ssfc; + cntlr.bbar = &ich9_spi->bbar; + cntlr.preop = &ich9_spi->preop; + break; + } + default: + printk(BIOS_DEBUG, "ICH SPI: Unrecognized ICH version %d.\n", ich_version); + } + + ich_set_bbar(0); + + /* Disable the BIOS write protect so write commands are allowed. */ + pci_read_config_byte(dev, 0xdc, &bios_cntl); + switch (ich_version) { + case 9: + /* Deassert SMM BIOS Write Protect Disable. */ + bios_cntl &= ~(1 << 5); + break; + + default: + break; + } + pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ +} + +typedef struct spi_transaction { + const uint8_t *out; + uint32_t bytesout; + uint8_t *in; + uint32_t bytesin; + uint8_t type; + uint8_t opcode; + uint32_t offset; +} spi_transaction; + +static inline void spi_use_out(spi_transaction *trans, unsigned bytes) +{ + trans->out += bytes; + trans->bytesout -= bytes; +} + +static inline void spi_use_in(spi_transaction *trans, unsigned bytes) +{ + trans->in += bytes; + trans->bytesin -= bytes; +} + +static void spi_setup_type(spi_transaction *trans) +{ + trans->type = 0xFF; + + /* Try to guess spi type from read/write sizes. */ + if (trans->bytesin == 0) { + if (trans->bytesout > 4) + /* + * If bytesin = 0 and bytesout > 4, we presume this is + * a write data operation, which is accompanied by an + * address. + */ + trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; + else + trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; + return; + } + + if (trans->bytesout == 1) { /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; + return; + } + + if (trans->bytesout == 4) { /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + } +} + +static int spi_setup_opcode(spi_transaction *trans) +{ + uint16_t optypes; + uint8_t opmenu[cntlr.menubytes]; + + trans->opcode = trans->out[0]; + spi_use_out(trans, 1); + if (!ichspi_lock) { + /* The lock is off, so just use index 0. */ + writeb_(trans->opcode, cntlr.opmenu); + optypes = readw_(cntlr.optype); + optypes = (optypes & 0xfffc) | (trans->type & 0x3); + writew_(optypes, cntlr.optype); + return 0; + } else { + /* The lock is on. See if what we need is on the menu. */ + uint8_t optype; + uint16_t opcode_index; + + read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < cntlr.menubytes; + opcode_index++) { + if (opmenu[opcode_index] == trans->opcode) + break; + } + + if (opcode_index == cntlr.menubytes) { + printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", + trans->opcode); + return -1; + } + + optypes = readw_(cntlr.optype); + optype = (optypes >> (opcode_index * 2)) & 0x3; + if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && + optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && + trans->bytesout >= 3) { + /* We guessed wrong earlier. Fix it up. */ + trans->type = optype; + } + if (optype != trans->type) { + printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", + optype); + return -1; + } + return opcode_index; + } +} + +static int spi_setup_offset(spi_transaction *trans) +{ + /* Separate the SPI address and data. */ + switch (trans->type) { + case SPI_OPCODE_TYPE_READ_NO_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: + return 0; + case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: + trans->offset = ((uint32_t)trans->out[0] << 16) | + ((uint32_t)trans->out[1] << 8) | + ((uint32_t)trans->out[2] << 0); + spi_use_out(trans, 3); + return 1; + default: + printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); + return -1; + } +} + +/* + * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set + * below is True) or 0. In case the wait was for the bit(s) to set - write + * those bits back, which would cause resetting them. + * + * Return the last read status value on success or -1 on failure. + */ +static int ich_status_poll(u16 bitmask, int wait_til_set) +{ + int timeout = 6000; /* This will result in 60 ms */ + u16 status = 0; + + while (timeout--) { + status = readw_(cntlr.status); + if (wait_til_set ^ ((status & bitmask) == 0)) { + if (wait_til_set) + writew_((status & bitmask), cntlr.status); + return status; + } + udelay(10); + } + + printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", + status, bitmask); + return -1; +} + +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) +{ + uint16_t control; + int16_t opcode_index; + int with_address; + int status; + + spi_transaction trans = { + dout, bitsout / 8, + din, bitsin / 8, + 0xff, 0xff, 0 + }; + + /* There has to always at least be an opcode. */ + if (!bitsout || !dout) { + printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); + return -1; + } + /* Make sure if we read something we have a place to put it. */ + if (bitsin != 0 && !din) { + printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); + return -1; + } + /* Right now we don't support writing partial bytes. */ + if (bitsout % 8 || bitsin % 8) { + printk(BIOS_DEBUG, "ICH SPI: Accessing partial bytes not supported\n"); + return -1; + } + + if (ich_status_poll(SPIS_SCIP, 0) == -1) + return -1; + + writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); + + spi_setup_type(&trans); + if ((opcode_index = spi_setup_opcode(&trans)) < 0) + return -1; + if ((with_address = spi_setup_offset(&trans)) < 0) + return -1; + + if (!ichspi_lock && trans.opcode == 0x06) { + /* + * Treat Write Enable as Atomic Pre-Op if possible + * in order to prevent the Management Engine from + * issuing a transaction between WREN and DATA. + */ + writew_(trans.opcode, cntlr.preop); + return 0; + } + + /* Preset control fields */ + control = SPIC_SCGO | ((opcode_index & 0x07) << 4); + + /* Issue atomic preop cycle if needed */ + if (readw_(cntlr.preop)) + control |= SPIC_ACS; + + if (!trans.bytesout && !trans.bytesin) { + /* + * This is a 'no data' command (like Write Enable), its + * bitesout size was 1, decremented to zero while executing + * spi_setup_opcode() above. Tell the chip to send the + * command. + */ + writew_(control, cntlr.control); + + /* wait for the result */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); + return -1; + } + + return 0; + } + + /* + * Check if this is a write command atempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (trans.bytesout > cntlr.databytes) { + printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" + " CONTROLLER_PAGE_LIMIT?\n"); + return -1; + } + + /* + * Read or write up to databytes bytes at a time until everything has + * been sent. + */ + while (trans.bytesout || trans.bytesin) { + uint32_t data_length; + + /* SPI addresses are 24 bit only */ + writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + + if (trans.bytesout) + data_length = min(trans.bytesout, cntlr.databytes); + else + data_length = min(trans.bytesin, cntlr.databytes); + + /* Program data into FDATA0 to N */ + if (trans.bytesout) { + write_reg(trans.out, cntlr.data, data_length); + spi_use_out(&trans, data_length); + if (with_address) + trans.offset += data_length; + } + + /* Add proper control fields' values */ + control &= ~((cntlr.databytes - 1) << 8); + control |= SPIC_DS; + control |= (data_length - 1) << 8; + + /* write it */ + writew_(control, cntlr.control); + + /* Wait for Cycle Done Status or Flash Cycle Error. */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); + return -1; + } + + if (trans.bytesin) { + read_reg(cntlr.data, trans.in, data_length); + spi_use_in(&trans, data_length); + if (with_address) + trans.offset += data_length; + } + } + + /* Clear atomic preop now that xfer is done */ + writew_(0, cntlr.preop); + + return 0; +}

1 0

Patch set updated for coreboot: 4cbf030 Hook up MRC cache update
by Stefan Reinauer 04 May '12

04 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1002 -gerrit commit 4cbf030d80f801c86949d86dcf781c32d1fb46d9 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 3 16:40:41 2012 -0700 Hook up MRC cache update This one is a WIP: - should not depend on CONFIG_CHROMEOS - There might be a better place for it. Requirements: - must be in ramstage (locking flash while executing code from there might not work) - must be after cbmem is reinitialized (so the mrc cache copy of the current run can be found) Change-Id: I8028fb073349ce2b027ef5f8397dc1a1b8b31c02 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/boot/tables.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 4fefc7d..ff57422 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -53,6 +53,11 @@ struct lb_memory *write_tables(void) */ unsigned long high_table_pointer; +#if CONFIG_CHROMEOS + void update_mrc_cache(void); + update_mrc_cache(); +#endif + if (!high_tables_base) { printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n"); // Are there any boards without?

1 0

Patch set updated for coreboot: d67e4ed Rework Sandybridge MRC cache handling
by Stefan Reinauer 04 May '12

04 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1001 -gerrit commit d67e4edfc60ed59dfd783587daf287ed4420f134 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 3 16:38:09 2012 -0700 Rework Sandybridge MRC cache handling - Separate Sandybridge from ChromeOS a bit The Sandybridge code depends on chromeos features a whole lot. As a first step, provide a code path to look up the MRC cache without depending on u-boot. - Move mrc cache handling to separate file This enables us to handle the MRC cache from ramstage, where we can write the flash safely (eg. to update the cache). Also teach it to lookup the current MRC cache from CBMEM, as the original data block isn't available anymore. After all the preparations, finally write to the SPI as necessary. It's a simple round robin wear levelling that erases the entire MRC cache region when it's full and starts from the beginning. Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/northbridge/intel/sandybridge/Kconfig | 17 ++ src/northbridge/intel/sandybridge/Makefile.inc | 2 + src/northbridge/intel/sandybridge/mrccache.c | 265 +++++++++++++++++++++++ src/northbridge/intel/sandybridge/raminit.c | 123 +---------- src/northbridge/intel/sandybridge/sandybridge.h | 22 ++ 5 files changed, 315 insertions(+), 114 deletions(-) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 8cf0a49..67b3def 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -37,6 +37,23 @@ config CACHE_MRC_SIZE_KB int default 256 +# FIXME: build from rom size +config MRC_CACHE_BASE + hex + default 0xff800000 + +config MRC_CACHE_LOCATION + hex + default 0x1ec000 + +config MRC_CACHE_SIZE + hex + default 0x10000 + +config MRC_CACHE_ALIGNMENT + hex + default 0x1000 + config DCACHE_RAM_BASE hex default 0xff7f0000 diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 87a0b2e..824700e 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -21,9 +21,11 @@ driver-y += northbridge.c driver-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-y += mrccache.c romstage-y += udelay.c romstage-y += raminit.c +romstage-y += mrccache.c romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c new file mode 100644 index 0000000..5c4c382 --- /dev/null +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -0,0 +1,265 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <console/console.h> +#include <cbfs.h> +#include <ip_checksum.h> +#include <device/device.h> +#include <cbmem.h> +#include "pei_data.h" +#include "sandybridge.h" +#include <spi.h> +#include <spi_flash.h> +/* Using the FDT FMAP for finding the MRC cache area requires including FDT + * support in coreboot, which we would like to avoid. There are a number of + * options: + * - Have each mainboard Kconfig supply a hard-coded offset + * - For ChromeOS devices: implement native FMAP + * - For non-ChromeOS devices: use CBFS + * For now let's leave this code in here until the issue is sorted out in + * a way that works for everyone. + */ +#undef USE_FDT_FMAP_FOR_MRC_CACHE +#ifdef USE_FDT_FMAP_FOR_MRC_CACHE +#include <fdt/libfdt.h> +#endif + +struct mrc_data_container *next_mrc_block(struct mrc_data_container *mrc_cache) +{ + /* MRC data blocks are aligned within the region */ + u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; + if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { + mrc_size &= ~(MRC_DATA_ALIGN - 1UL); + mrc_size += MRC_DATA_ALIGN; + } + + u8 *region_ptr = (u8*)mrc_cache; + region_ptr += mrc_size; + return (struct mrc_data_container *)region_ptr; +} + +int is_mrc_cache(struct mrc_data_container *mrc_cache) +{ + return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); +} + +u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) +{ + u8 *mrc_region; + u32 region_size; + u32 *data; +#ifdef USE_FDT_FMAP_FOR_MRC_CACHE + const struct fdt_header *fdt_header; + const struct fdt_property *fdtp; + int offset, len; + const char *compatible = "chromeos,flashmap"; + const char *subnode = "rw-mrc-cache"; + const char *property = "reg"; + u64 flashrom_base = 0; + + fdt_header = cbfs_find_file(CONFIG_FDT_FILE_NAME, CBFS_TYPE_FDT); + + if (!fdt_header) { + printk(BIOS_ERR, "%s: no FDT found!\n", __func__); + return 0; + } + + offset = fdt_node_offset_by_compatible(fdt_header, 0, compatible); + if (offset < 0) { + printk(BIOS_ERR, "%s: no %s node found!\n", + __func__, compatible); + return 0; + } + + if (fdt_get_base_addr(fdt_header, offset, &flashrom_base) < 0) { + printk(BIOS_ERR, "%s: no base address in node name!\n", + __func__); + return 0; + } + + offset = fdt_subnode_offset(fdt_header, offset, subnode); + if (offset < 0) { + printk(BIOS_ERR, "%s: no %s found!\n", __func__, subnode); + return 0; + } + + fdtp = fdt_get_property(fdt_header, offset, property, &len); + if (!fdtp || (len != 8)) { + printk(BIOS_ERR, "%s: property %s at %p, len %d!\n", + __func__, property, fdtp, len); + return 0; + } + + data = (u32 *)fdtp->data; + + // Calculate actual address of the MRC cache in memory + region_size = fdt32_to_cpu(data[1]); + mrc_region = (u8*)((unsigned long)flashrom_base + fdt32_to_cpu(data[0])); +#else + data = (u32 *)((void *)(CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION + 12)); + + region_size = CONFIG_MRC_CACHE_SIZE; + mrc_region = (u8*)(CONFIG_MRC_CACHE_BASE + be32_to_cpu(data[0])); +#endif + + *mrc_region_ptr = (struct mrc_data_container *)mrc_region; + + return region_size; +} + +/* find the first empty field in the MRC cache area. If there's none, return + * the first region. By testing for emptiness caller can detect if flash + * needs to be erased. + * + * FIXME: that interface is crap + */ +struct mrc_data_container *find_next_mrc_cache(void) +{ + u32 entry_id = 0; + struct mrc_data_container *mrc_cache = NULL; + u32 region_size = get_mrc_cache_region(&mrc_cache); + void *mrc_region = (void*)mrc_cache; + + if (mrc_cache == NULL) { + printk(BIOS_ERR, "%s: could not find mrc cache area\n", __func__); + return NULL; + } + + /* Search for the first empty entry in the region */ + while (is_mrc_cache(mrc_cache)) { + entry_id++; + mrc_cache = next_mrc_block(mrc_cache); + /* If we exceed the defined area, move to front */ + if ((void*)mrc_cache >= (void*)(mrc_region + region_size)) { + mrc_cache = (struct mrc_data_container *)mrc_region; + break; + } + } + + printk(BIOS_DEBUG, "picked entry %u from cache block when looking for empty block\n", entry_id); + + return mrc_cache; +} + +struct mrc_data_container *find_current_mrc_cache(void) +{ + u32 entry_id = 0; + struct mrc_data_container *mrc_next, *mrc_cache = NULL; + u32 region_size = get_mrc_cache_region(&mrc_cache); + void *mrc_region = (void*)mrc_cache; + mrc_next = mrc_cache; + + if (mrc_cache == NULL) { + printk(BIOS_ERR, "%s: could not find mrc cache area\n", __func__); + return NULL; + } + + if (mrc_cache->mrc_data_size == -1UL) { + printk(BIOS_ERR, "%s: MRC cache not initialized?\n", __func__); + /* return non-initialized cache, so we can discern this + * from having no cache area at all + */ + return mrc_cache; + } else { + /* Search for the last filled entry in the region */ + while (is_mrc_cache(mrc_next)) { + entry_id++; + mrc_cache = mrc_next; + mrc_next = next_mrc_block(mrc_cache); + /* Stay in the mrcdata region defined in fdt */ + if ((void*)mrc_next >= (void*)(mrc_region + region_size)) + break; + } + entry_id--; + } + + /* Verify checksum */ + if (mrc_cache->mrc_checksum != + compute_ip_checksum(mrc_cache->mrc_data, + mrc_cache->mrc_data_size)) { + printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); + return NULL; + } + + printk(BIOS_DEBUG, "picked entry %u from cache block\n", entry_id); + + return mrc_cache; +} + +/* SPI code needs malloc/free. + * Also unknown if writing flash from XIP-flash code is a good idea + */ +#if !defined(__PRE_RAM__) +void update_mrc_cache(void) +{ + struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); + if (!current) { + printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); + return; + } + if (current->mrc_data_size == -1) { + printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); + return; + } + + /* + * we need to: + */ + // 0. compare MRC data to last mrc-cache block (exit if same) + struct mrc_data_container *cache; + if ((cache = find_current_mrc_cache()) == NULL) { + printk(BIOS_DEBUG, "Failure looking for current last block\n"); + return; + } + + if ((cache->mrc_data_size == current->mrc_data_size) && (memcmp(cache, current, cache->mrc_data_size) == 0)) { + printk(BIOS_DEBUG, "MRC data in flash is up to date. No update.\n"); + return; + } + + // 1. use spi_flash_probe() to find the flash, then + spi_init(); + struct spi_flash *flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + return; + } + + // 2. look up the first unused block + cache = find_next_mrc_cache(); + if (!cache) { + printk(BIOS_DEBUG, "Could not find MRC cache area\n"); + return; + } + + // 3. if no such place exists, erase entire mrc-cache range & use block 0 + if (cache->mrc_data_size != -1) { + printk(BIOS_DEBUG, "We need to erase the MRC cache region\n"); + flash->erase(flash, CONFIG_MRC_CACHE_LOCATION, CONFIG_MRC_CACHE_SIZE); + /* we know we can start at the beginning again */ + get_mrc_cache_region(&cache); + } + // 4. write mrc data with flash->write() + printk(BIOS_DEBUG, "Finally: write MRC cache update to flash\n"); + flash->write(flash, (u32)(((void*)cache)-CONFIG_MRC_CACHE_BASE), current->mrc_data_size + sizeof(*current), current); +} +#endif + diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 6548b32..0df86d6 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -36,9 +36,8 @@ #include "southbridge/intel/bd82x6x/me.h" #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> -#endif -#if 0 -#include <fdt/libfdt.h> +#else +#define recovery_mode_enabled(x) 0 #endif /* @@ -56,17 +55,6 @@ #define CMOS_OFFSET_MRC_SEED_CHK 120 #endif -#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) - -struct mrc_data_container { - u32 mrc_signature; // "MRCD" - u32 mrc_data_size; // Actual total size of this structure - u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment - u8 mrc_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - static void save_mrc_data(struct pei_data *pei_data) { u16 c1, c2, checksum; @@ -119,22 +107,10 @@ static void save_mrc_data(struct pei_data *pei_data) cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1); } -#if CONFIG_CHROMEOS static void prepare_mrc_cache(struct pei_data *pei_data) { -#if 0 - const struct fdt_header *fdt_header; - const struct fdt_property *fdtp; - int offset, len; - const char *compatible = "chromeos,flashmap"; - const char *subnode = "rw-mrc-cache"; - const char *property = "reg"; - u32 *data; - struct mrc_data_container *mrc_cache, *mrc_next; - u8 *mrc_region, *region_ptr; + struct mrc_data_container *mrc_cache; u16 c1, c2, checksum, seed_checksum; - u32 region_size, entry_id = 0; - u64 flashrom_base = 0; // preset just in case there is an error pei_data->mrc_input = NULL; @@ -166,96 +142,18 @@ static void prepare_mrc_cache(struct pei_data *pei_data) return; } - fdt_header = cbfs_find_file(CONFIG_FDT_FILE_NAME, CBFS_TYPE_FDT); - - if (!fdt_header) { - printk(BIOS_ERR, "%s: no FDT found!\n", __func__); - return; - } - - offset = fdt_node_offset_by_compatible(fdt_header, 0, compatible); - if (offset < 0) { - printk(BIOS_ERR, "%s: no %s node found!\n", - __func__, compatible); - return; - } - - if (fdt_get_base_addr(fdt_header, offset, &flashrom_base) < 0) { - printk(BIOS_ERR, "%s: no base address in node name!\n", - __func__); - return; - } - - offset = fdt_subnode_offset(fdt_header, offset, subnode); - if (offset < 0) { - printk(BIOS_ERR, "%s: no %s found!\n", __func__, subnode); - return; - } - - fdtp = fdt_get_property(fdt_header, offset, property, &len); - if (!fdtp || (len != 8)) { - printk(BIOS_ERR, "%s: property %s at %p, len %d!\n", - __func__, property, fdtp, len); - return; - } - - data = (u32 *)fdtp->data; - - // Calculate actual address of the MRC cache in memory - region_size = fdt32_to_cpu(data[1]); - mrc_region = region_ptr = (u8*) - ((unsigned long)flashrom_base + fdt32_to_cpu(data[0])); - mrc_cache = mrc_next = (struct mrc_data_container *)mrc_region; - - if (!mrc_cache || mrc_cache->mrc_signature != MRC_DATA_SIGNATURE) { - printk(BIOS_ERR, "%s: invalid MRC data\n", __func__); - return; - } - - if (mrc_cache->mrc_data_size == -1UL) { - printk(BIOS_ERR, "%s: MRC cache not initialized?\n", __func__); - return; - } else { - /* MRC data blocks are aligned within the region */ - u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size; - if (mrc_size & (MRC_DATA_ALIGN - 1UL)) { - mrc_size &= ~(MRC_DATA_ALIGN - 1UL); - mrc_size += MRC_DATA_ALIGN; - } - - /* Search for the last filled entry in the region */ - while (mrc_next && - mrc_next->mrc_signature == MRC_DATA_SIGNATURE) { - entry_id++; - mrc_cache = mrc_next; - /* Stay in the mrcdata region defined in fdt */ - if ((entry_id * mrc_size) > region_size) - break; - region_ptr += mrc_size; - mrc_next = (struct mrc_data_container *)region_ptr; - } - entry_id--; - } - - /* Verify checksum */ - if (mrc_cache->mrc_checksum != - compute_ip_checksum(mrc_cache->mrc_data, - mrc_cache->mrc_data_size)) { - printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__); + if ((mrc_cache = find_current_mrc_cache()) == NULL) { + /* error message printed in find_current_mrc_cache */ return; } pei_data->mrc_input = mrc_cache->mrc_data; pei_data->mrc_input_len = mrc_cache->mrc_data_size; - printk(BIOS_DEBUG, "%s: at %p, entry %u size %x checksum %04x\n", - __func__, pei_data->mrc_input, entry_id, + printk(BIOS_DEBUG, "%s: at %p, size %x checksum %04x\n", + __func__, pei_data->mrc_input, pei_data->mrc_input_len, mrc_cache->mrc_checksum); -#else - printk(BIOS_ERR, "MRC cache handling code has to be redone.\n"); -#endif } -#endif static const char* ecc_decoder[] = { "inactive", @@ -315,7 +213,6 @@ static void report_memory_config(void) void sdram_initialize(struct pei_data *pei_data) { struct sys_info sysinfo; - const char *target = "mrc.bin"; unsigned long entry; report_platform_info(); @@ -330,7 +227,6 @@ void sdram_initialize(struct pei_data *pei_data) sysinfo.boot_path = pei_data->boot_mode; -#if CONFIG_CHROMEOS /* * Do not pass MRC data in for recovery mode boot, * Always pass it in for S3 resume. @@ -344,17 +240,16 @@ void sdram_initialize(struct pei_data *pei_data) outb(0x6, 0xcf9); hlt(); } -#endif /* Locate and call UEFI System Agent binary. */ - entry = (unsigned long)cbfs_find_file(target, 0xab); + entry = (unsigned long)cbfs_find_file("mrc.bin", 0xab); if (entry) { int rv; asm volatile ( "call *%%ecx\n\t" :"=a" (rv) : "c" (entry), "a" (pei_data)); if (rv) { - printk(BIOS_ERR, "MRC returned %d\n", rv); + printk(BIOS_ERR, "MRC returned %x\n", rv); die("Nonzero MRC return value\n"); } } else { diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index aa62021..7e12416 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -221,6 +221,28 @@ void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ + + +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) + +struct mrc_data_container { + u32 mrc_signature; // "MRCD" + u32 mrc_data_size; // Actual total size of this structure + u32 mrc_checksum; // IP style checksum + u32 reserved; // For header alignment + u8 mrc_data[0]; // Variable size, platform/run time dependent. +} __attribute__ ((packed)); + +struct mrc_data_container *next_mrc_block(struct mrc_data_container *mrc_cache); +int is_mrc_cache(struct mrc_data_container *mrc_cache); +u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr); +struct mrc_data_container *find_next_mrc_cache(void); +struct mrc_data_container *find_current_mrc_cache(void); +#if !defined(__PRE_RAM__) +void update_mrc_cache(void); +#endif + #endif #endif #endif

1 0

← Newer
1
...
18
19
20
21
22
23
24
...
29
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot May 2012