coreboot June 2011

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[commit] r6623 - trunk/src/mainboard/asrock/e350m1
by repository service 04 Jun '11

04 Jun '11

Author: stuge Date: Sat Jun 4 17:43:56 2011 New Revision: 6623 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6623 Log: Port persimmon r6574 to e350m1: MMCONF size Size mmconf according to CONFIG_MMCONF_BUS_NUMBER. Signed-off-by: Marshall Buschman <mbuschman(a)lucidmachines.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asrock/e350m1/agesawrapper.c Modified: trunk/src/mainboard/asrock/e350m1/agesawrapper.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/agesawrapper.c Sat Jun 4 17:43:38 2011 (r6622) +++ trunk/src/mainboard/asrock/e350m1/agesawrapper.c Sat Jun 4 17:43:56 2011 (r6623) @@ -138,7 +138,8 @@ Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Address MSR register. */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1; + + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); /*

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[commit] r6622 - trunk/src/mainboard/asrock/e350m1
by repository service 04 Jun '11

04 Jun '11

Author: stuge Date: Sat Jun 4 17:43:38 2011 New Revision: 6622 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6622 Log: Port persimmon r6573 to e350m1: VGA, PCI MMIO and SB800 legacy 1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support. 2) Extend PCI MMIO limit from dfffffff to fecfffff. 3) Add AMD recommended non-posted mapping for SB800 legacy devices. Signed-off-by: Marshall Buschman <mbuschman(a)lucidmachines.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asrock/e350m1/agesawrapper.c Modified: trunk/src/mainboard/asrock/e350m1/agesawrapper.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/agesawrapper.c Sat Jun 4 17:43:15 2011 (r6621) +++ trunk/src/mainboard/asrock/e350m1/agesawrapper.c Sat Jun 4 17:43:38 2011 (r6622) @@ -85,38 +85,39 @@ PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; - /* Enable MMIO on AMD CPU Address Map Controller */ - - /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */ + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00000B00; + PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 + PciData |= 1 << 7; // set NP (non-posted) bit LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = 0x00000A03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set TOM-DFFFFFFF to Node0 Link0. */ + PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00DFFF00; + PciData = 0x00FECF00; // last address before non-posted range LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC); - PciData = 0x00FFFF00 | 0x80; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8); - PciData = (PCIE_BASE_ADDRESS >> 8) | 03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */ + + /* Send all IO (0000-FFFF) to southbridge. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); PciData = 0x0000F000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000013; + PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); Status = AGESA_SUCCESS; return (UINT32)Status;

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[commit] r6621 - trunk/src/mainboard/asrock/e350m1
by repository service 04 Jun '11

04 Jun '11

Author: stuge Date: Sat Jun 4 17:43:15 2011 New Revision: 6621 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6621 Log: Port persimmon r6572 to e350m1: I/O APIC ID 1) Set I/O APIC ID according to BKDG recommendation 2) Correct I/O APIC ID reported by mptable Signed-off-by: Marshall Buschman <mbuschman(a)lucidmachines.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asrock/e350m1/acpi_tables.c trunk/src/mainboard/asrock/e350m1/get_bus_conf.c trunk/src/mainboard/asrock/e350m1/mptable.c Modified: trunk/src/mainboard/asrock/e350m1/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/acpi_tables.c Sat Jun 4 17:40:12 2011 (r6620) +++ trunk/src/mainboard/asrock/e350m1/acpi_tables.c Sat Jun 4 17:43:15 2011 (r6621) @@ -64,7 +64,7 @@ current = acpi_create_madt_lapics(current); /* Write SB800 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) Modified: trunk/src/mainboard/asrock/e350m1/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/get_bus_conf.c Sat Jun 4 17:40:12 2011 (r6620) +++ trunk/src/mainboard/asrock/e350m1/get_bus_conf.c Sat Jun 4 17:43:15 2011 (r6621) @@ -138,7 +138,7 @@ /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_CPUS; //#if CONFIG_LOGICAL_CPUS==1 // apicid_base = get_apicid_base(1); //#endif Modified: trunk/src/mainboard/asrock/e350m1/mptable.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/mptable.c Sat Jun 4 17:40:12 2011 (r6620) +++ trunk/src/mainboard/asrock/e350m1/mptable.c Sat Jun 4 17:43:15 2011 (r6621) @@ -69,7 +69,7 @@ dword |= (pm_ioread(0x35) & 0xFF) << 8; dword |= (pm_ioread(0x36) & 0xFF) << 16; dword |= (pm_ioread(0x37) & 0xFF) << 24; - smp_write_ioapic(mc, apicid_sb800, 0x11, dword); + smp_write_ioapic(mc, apicid_sb800, 0x21, dword); for (byte = 0x0; byte < sizeof(intr_data); byte ++) { outb(byte | 0x80, 0xC00);

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[commit] r6620 - trunk/src/southbridge/via/vt8237r
by repository service 04 Jun '11

04 Jun '11

Author: stuge Date: Sat Jun 4 17:40:12 2011 New Revision: 6620 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6620 Log: vt8237r: Simplify bootblock init to work around nested if() romcc problem During the hackathon in Prague we discovered that romcc has a problem compiling the previous nested if() statements correctly. This patch makes the code a little simpler, and indeed works around the romcc issue. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/southbridge/via/vt8237r/bootblock.c Modified: trunk/src/southbridge/via/vt8237r/bootblock.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/bootblock.c Fri Jun 3 21:59:52 2011 (r6619) +++ trunk/src/southbridge/via/vt8237r/bootblock.c Sat Jun 4 17:40:12 2011 (r6620) @@ -33,20 +33,23 @@ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); - if (dev == PCI_DEV_INVALID) { - /* Power management controller */ - dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); - - if (dev == PCI_DEV_INVALID) { - /* Power management controller */ - dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); - - if (dev == PCI_DEV_INVALID) - return; - } - } + if (dev != PCI_DEV_INVALID) + goto found; + /* Power management controller */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); + + if (dev != PCI_DEV_INVALID) + goto found; + + /* Power management controller */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); + + if (dev == PCI_DEV_INVALID) + return; + +found: pci_write_config8(dev, 0x41, 0x7f); }

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[patch] ck804 ACPI PIC/APIC interrupt logic
by Jonathan A. Kollasch 04 Jun '11

04 Jun '11

Add ACPI automatic PIC/APIC interrupt routing logic for ck804. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net>

2 4

Wyse S10
by Ansar Mohammed 04 Jun '11

04 Jun '11

Hello All, First off, I have just stumbled onto this project after tearing my hair out with a Wyse S10 and the ultra crappy BIOS it comes with. Thank you for what you do guys.. I have searched the archives of this DL and I see a few people have played with installing coreboot on a Wyse S10. Has anyone gotten it to successfully work?

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Wyse S10
by Ansar Mohammed 04 Jun '11

04 Jun '11

1 0

[patch] update ddr3 max frequency
by Marc Jones 03 Jun '11

03 Jun '11

We found this with some testing at BTDC. This patch sets max freq defaults for ddr2 and ddr3for fam10. It may be overridden by a developer setting it in romstage.c. Signed-off-by: Marc Jones <marcj303(a)gmail.com> -- http://se-eng.com

4 6

[commit] r6619 - in trunk/src/northbridge/amd/amdmct: mct mct_ddr3 wrappers
by repository service 03 Jun '11

03 Jun '11

Author: mjones Date: Fri Jun 3 21:59:52 2011 New Revision: 6619 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6619 Log: This patch sets max freq defaults for ddr2 and ddr3for fam10. Signed-off-by: Marc Jones <marcj303(a)gmail.com> Acked-by: Scott Duplichan <scott(a)notabs.org> Modified: trunk/src/northbridge/amd/amdmct/mct/mct.h trunk/src/northbridge/amd/amdmct/mct/mct_d.h trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h trunk/src/northbridge/amd/amdmct/wrappers/mcti.h trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Modified: trunk/src/northbridge/amd/amdmct/mct/mct.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct.h Fri Jun 3 21:46:25 2011 (r6618) +++ trunk/src/northbridge/amd/amdmct/mct/mct.h Fri Jun 3 21:59:52 2011 (r6619) @@ -496,18 +496,6 @@ 0=disable 1=enable*/ -#ifndef MAX_NODES_SUPPORTED -#define MAX_NODES_SUPPORTED 8 -#endif - -#ifndef MAX_DIMMS_SUPPORTED -#define MAX_DIMMS_SUPPORTED 8 -#endif - -#ifndef MAX_CS_SUPPORTED -#define MAX_CS_SUPPORTED 8 -#endif - /* global function */ u32 NodePresent(u32 Node); Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.h Fri Jun 3 21:46:25 2011 (r6618) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.h Fri Jun 3 21:59:52 2011 (r6619) @@ -667,23 +667,6 @@ yy1b = enable with DctSelIntLvAddr set to yyb */ -#ifndef MAX_NODES_SUPPORTED -#define MAX_NODES_SUPPORTED 8 -#endif - -#ifndef MAX_DIMMS_SUPPORTED -#define MAX_DIMMS_SUPPORTED 8 -#endif - -#ifndef MAX_CS_SUPPORTED -#define MAX_CS_SUPPORTED 8 -#endif - -#ifndef MCT_DIMM_SPARE_NO_WARM -#define MCT_DIMM_SPARE_NO_WARM 0 -#endif - - u32 Get_NB32(u32 dev, u32 reg); void Set_NB32(u32 dev, u32 reg, u32 val); u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index); Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Fri Jun 3 21:46:25 2011 (r6618) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Fri Jun 3 21:59:52 2011 (r6619) @@ -1315,7 +1315,7 @@ u16 word; /* Get CPU Si Revision defined limit (NPT) */ - proposedFreq = 533; /* Rev F0 programmable max memclock is */ + proposedFreq = 800; /* Rev F0 programmable max memclock is */ /*Get User defined limit if "limit" mode */ if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) { Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h Fri Jun 3 21:46:25 2011 (r6618) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h Fri Jun 3 21:59:52 2011 (r6619) @@ -728,22 +728,6 @@ yy1b = enable with DctSelIntLvAddr set to yyb */ -#ifndef MAX_NODES_SUPPORTED -#define MAX_NODES_SUPPORTED 8 -#endif - -#ifndef MAX_DIMMS_SUPPORTED -#define MAX_DIMMS_SUPPORTED 8 -#endif - -#ifndef MAX_CS_SUPPORTED -#define MAX_CS_SUPPORTED 8 -#endif - -#ifndef MCT_DIMM_SPARE_NO_WARM -#define MCT_DIMM_SPARE_NO_WARM 0 -#endif - u32 Get_NB32(u32 dev, u32 reg); void Set_NB32(u32 dev, u32 reg, u32 val); u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index); Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti.h Fri Jun 3 21:46:25 2011 (r6618) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti.h Fri Jun 3 21:59:52 2011 (r6619) @@ -57,6 +57,18 @@ #define MAX_CS_SUPPORTED 8 #endif +#ifndef MCT_DIMM_SPARE_NO_WARM +#define MCT_DIMM_SPARE_NO_WARM 0 +#endif + +#ifndef MEM_MAX_LOAD_FREQ +#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ + #define MEM_MAX_LOAD_FREQ 800 +#else + #define MEM_MAX_LOAD_FREQ 400 +#endif +#endif + #define MCT_TRNG_KEEPOUT_START 0x00000C00 #define MCT_TRNG_KEEPOUT_END 0x00000CFF Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Fri Jun 3 21:46:25 2011 (r6618) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Fri Jun 3 21:59:52 2011 (r6619) @@ -48,7 +48,7 @@ //val = 200; /* 200MHz(DDR400) */ //val = 266; /* 266MHz(DDR533) */ //val = 333; /* 333MHz(DDR667) */ - val = 400; /* 400MHz(DDR800) */ + val = MEM_MAX_LOAD_FREQ;; /* 400MHz(DDR800) */ break; case NV_ECC_CAP: #if SYSTEM_TYPE == SERVER @@ -237,7 +237,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) { - pDCTstat->PresetmaxFreq = 400; + pDCTstat->PresetmaxFreq = MEM_MAX_LOAD_FREQ; } #ifdef UNUSED_CODE

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[PATCH] Correct wrong PCI ID vor VIA K8M890 Chrome
by Alex G. 03 Jun '11

03 Jun '11

before anyone bricks a board Alex.

2 1

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coreboot June 2011