coreboot June 2011

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[commit] r6633 - trunk/src/mainboard/asrock/e350m1
by repository service 04 Jun '11

04 Jun '11

Author: stuge Date: Sat Jun 4 17:47:05 2011 New Revision: 6633 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6633 Log: Port persimmon r6591 to e350m1: ROM cache early Enable rom cache early to reduce boot time. Signed-off-by: Marshall Buschman <mbuschman(a)lucidmachines.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asrock/e350m1/agesawrapper.c trunk/src/mainboard/asrock/e350m1/romstage.c Modified: trunk/src/mainboard/asrock/e350m1/agesawrapper.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/agesawrapper.c Sat Jun 4 17:46:50 2011 (r6632) +++ trunk/src/mainboard/asrock/e350m1/agesawrapper.c Sat Jun 4 17:47:05 2011 (r6633) @@ -157,13 +157,6 @@ PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - Status = AGESA_SUCCESS; return (UINT32)Status; } Modified: trunk/src/mainboard/asrock/e350m1/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/romstage.c Sat Jun 4 17:46:50 2011 (r6632) +++ trunk/src/mainboard/asrock/e350m1/romstage.c Sat Jun 4 17:47:05 2011 (r6633) @@ -47,6 +47,11 @@ u32 val; u8 reg8; + // all cores: allow caching of flash chip code and data + // (there are no cache-as-ram reliability concerns with family 14h) + __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0);

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[commit] r6636 - trunk/src/mainboard/asrock/e350m1
by repository service 04 Jun '11

04 Jun '11

Author: stuge Date: Sat Jun 4 17:48:14 2011 New Revision: 6636 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6636 Log: Port persimmon r6594 to e350m1: Cosmetic cleanup Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Marshall Buschman <mbuschman(a)lucidmachines.com> Modified: trunk/src/mainboard/asrock/e350m1/get_bus_conf.c Modified: trunk/src/mainboard/asrock/e350m1/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/get_bus_conf.c Sat Jun 4 17:47:56 2011 (r6635) +++ trunk/src/mainboard/asrock/e350m1/get_bus_conf.c Sat Jun 4 17:48:14 2011 (r6636) @@ -42,25 +42,12 @@ 0x0000ff0, }; -/* -* HT Chain device num, actually it is unit id base of every ht device in chain, -* assume every chain only have 4 ht device at most -*/ -u32 hcdnx[] = { - 0x20202020, -}; - u32 bus_type[256]; - u32 sbdn_sb800; -//KZ [092110]extern void get_pci1234(void); - static u32 get_bus_conf_done = 0; - - void get_bus_conf(void) { u32 apicid_base; @@ -139,8 +126,5 @@ /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; -//#if CONFIG_LOGICAL_CPUS==1 -// apicid_base = get_apicid_base(1); -//#endif - apicid_sb800 = apicid_base + 0; + apicid_sb800 = apicid_base; }

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[commit] r6635 - trunk/src/mainboard/asrock/e350m1
by repository service 04 Jun '11

04 Jun '11

Author: stuge Date: Sat Jun 4 17:47:56 2011 New Revision: 6635 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6635 Log: Port persimmon r6593 to e350m1: Remove unused Kconfig options Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Marshall Buschman <mbuschman(a)lucidmachines.com> Modified: trunk/src/mainboard/asrock/e350m1/Kconfig Modified: trunk/src/mainboard/asrock/e350m1/Kconfig ============================================================================== --- trunk/src/mainboard/asrock/e350m1/Kconfig Sat Jun 4 17:47:30 2011 (r6634) +++ trunk/src/mainboard/asrock/e350m1/Kconfig Sat Jun 4 17:47:56 2011 (r6635) @@ -22,8 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select DIMM_DDR3 - select DIMM_UNREGISTERED select CPU_AMD_AGESA_WRAPPER_FAMILY14 select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14 @@ -42,7 +40,6 @@ select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 - select ENABLE_APIC_EXT_ID select TINY_BOOTBLOCK select GFXUMA @@ -86,18 +83,6 @@ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - -config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 - -config HT_CHAIN_UNITID_BASE - hex - default 0x0 - config IRQ_SLOT_COUNT int default 11

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[commit] r6634 - trunk/src/mainboard/asrock/e350m1
by repository service 04 Jun '11

04 Jun '11

Author: stuge Date: Sat Jun 4 17:47:30 2011 New Revision: 6634 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6634 Log: Port persimmon r6592 to e350m1: Update GPP port configuration Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Marshall Buschman <mbuschman(a)lucidmachines.com> Modified: trunk/src/mainboard/asrock/e350m1/devicetree.cb Modified: trunk/src/mainboard/asrock/e350m1/devicetree.cb ============================================================================== --- trunk/src/mainboard/asrock/e350m1/devicetree.cb Sat Jun 4 17:47:05 2011 (r6633) +++ trunk/src/mainboard/asrock/e350m1/devicetree.cb Sat Jun 4 17:47:30 2011 (r6634) @@ -99,12 +99,12 @@ end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB - device pci 15.2 on end # PCIe PortC - device pci 15.3 on end # PCIe PortD - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx_wrapper/sb800 # end # device pci 18.0 # These seem unnecessary

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[commit] r6632 - trunk/src/mainboard/asrock/e350m1
by repository service 04 Jun '11

04 Jun '11

Author: stuge Date: Sat Jun 4 17:46:50 2011 New Revision: 6632 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6632 Log: Port persimmon r6590 to e350m1: Work around memory allocation problem Fix memory allocation problem in amdInitLate. Disabled until further debug. Signed-off-by: Marshall Buschman <mbuschman(a)lucidmachines.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asrock/e350m1/agesawrapper.c Modified: trunk/src/mainboard/asrock/e350m1/agesawrapper.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/agesawrapper.c Sat Jun 4 17:46:32 2011 (r6631) +++ trunk/src/mainboard/asrock/e350m1/agesawrapper.c Sat Jun 4 17:46:50 2011 (r6632) @@ -444,33 +444,32 @@ ) { AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AMD_INTERFACE_PARAMS AmdParamStruct = {0}; + AMD_LATE_PARAMS *AmdLateParams; - LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); - - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; + return 0; // this causes bad ACPI SSDT, need to debug - Status = AmdInitLate (&AmdLateParams); + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdCreateStruct (&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; + Status = AmdInitLate (AmdLateParams); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); ASSERT(Status == AGESA_SUCCESS); } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit; + + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib; + AmdReleaseStruct (&AmdParamStruct); return (UINT32)Status; }

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[commit] r6631 - trunk/src/mainboard/asrock/e350m1
by repository service 04 Jun '11

04 Jun '11

Author: stuge Date: Sat Jun 4 17:46:32 2011 New Revision: 6631 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6631 Log: Port persimmon r6589 to e350m1: Strip down AGESA options Remove some non-essential agesa options to reduce boot time. Signed-off-by: Marshall Buschman <mbuschman(a)lucidmachines.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asrock/e350m1/buildOpts.c Modified: trunk/src/mainboard/asrock/e350m1/buildOpts.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/buildOpts.c Sat Jun 4 17:46:13 2011 (r6630) +++ trunk/src/mainboard/asrock/e350m1/buildOpts.c Sat Jun 4 17:46:32 2011 (r6631) @@ -80,16 +80,16 @@ #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE #define BLDOPT_REMOVE_DQS_TRAINING FALSE -//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_ACPI_PSTATES FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE @@ -97,17 +97,17 @@ #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -//#define BLDOPT_REMOVE_SRAT TRUE -//#define BLDOPT_REMOVE_SLIT TRUE -//#define BLDOPT_REMOVE_WHEA TRUE -//#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_HT_ASSIST TRUE -//#define BLDOPT_REMOVE_ATM_MODE TRUE +#define BLDOPT_REMOVE_SRAT TRUE +#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE //#define BLDOPT_REMOVE_C6_STATE TRUE -//#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE /* @@ -123,7 +123,7 @@ #define AGESA_ENTRY_INIT_S3SAVE TRUE #define AGESA_ENTRY_INIT_RESUME TRUE #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE /* * Agesa configuration values selection.

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[commit] r6630 - trunk/src/mainboard/asrock/e350m1
by repository service 04 Jun '11

04 Jun '11

Author: stuge Date: Sat Jun 4 17:46:13 2011 New Revision: 6630 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6630 Log: Port persimmon r6588 to e350m1: VGA framebuffer Declare legacy video frame buffer so that Windows generic VGA driver will work. Signed-off-by: Marshall Buschman <mbuschman(a)lucidmachines.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asrock/e350m1/dsdt.asl Modified: trunk/src/mainboard/asrock/e350m1/dsdt.asl ============================================================================== --- trunk/src/mainboard/asrock/e350m1/dsdt.asl Sat Jun 4 17:45:46 2011 (r6629) +++ trunk/src/mainboard/asrock/e350m1/dsdt.asl Sat Jun 4 17:46:13 2011 (r6630) @@ -1483,9 +1483,8 @@ 0xF300 /* length */ ) -#if 0 - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ +#if 0 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */

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[commit] r6629 - trunk/src/mainboard/asrock/e350m1
by repository service 04 Jun '11

04 Jun '11

Author: stuge Date: Sat Jun 4 17:45:46 2011 New Revision: 6629 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6629 Log: Port persimmon r6587 to e350m1: RTC is not PIIX4 compatible Declare RTC as not PIIX4 compatible to match AMD hardware. Signed-off-by: Marshall Buschman <mbuschman(a)lucidmachines.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asrock/e350m1/dsdt.asl Modified: trunk/src/mainboard/asrock/e350m1/dsdt.asl ============================================================================== --- trunk/src/mainboard/asrock/e350m1/dsdt.asl Sat Jun 4 17:45:29 2011 (r6628) +++ trunk/src/mainboard/asrock/e350m1/dsdt.asl Sat Jun 4 17:45:46 2011 (r6629) @@ -1379,7 +1379,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2)

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[commit] r6628 - trunk/src/mainboard/asrock/e350m1
by repository service 04 Jun '11

04 Jun '11

Author: stuge Date: Sat Jun 4 17:45:29 2011 New Revision: 6628 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6628 Log: Port persimmon r6586 to e350m1: FADT revision Make fadt revision match its length. Solves Windows 7 checked build assert. Signed-off-by: Marshall Buschman <mbuschman(a)lucidmachines.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asrock/e350m1/fadt.c Modified: trunk/src/mainboard/asrock/e350m1/fadt.c ============================================================================== --- trunk/src/mainboard/asrock/e350m1/fadt.c Sat Jun 4 17:45:12 2011 (r6627) +++ trunk/src/mainboard/asrock/e350m1/fadt.c Sat Jun 4 17:45:29 2011 (r6628) @@ -53,7 +53,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4);

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[commit] r6624 - trunk/src/mainboard/asrock/e350m1
by repository service 04 Jun '11

04 Jun '11

Author: stuge Date: Sat Jun 4 17:44:14 2011 New Revision: 6624 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6624 Log: Port persimmon r6578 and r6596 to e350m1: MMCONF base Remove multiple mmconf settings and just use kconfig setting. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asrock/e350m1/dsdt.asl Modified: trunk/src/mainboard/asrock/e350m1/dsdt.asl ============================================================================== --- trunk/src/mainboard/asrock/e350m1/dsdt.asl Sat Jun 4 17:43:56 2011 (r6623) +++ trunk/src/mainboard/asrock/e350m1/dsdt.asl Sat Jun 4 17:44:14 2011 (r6624) @@ -36,7 +36,7 @@ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ Name(PBLN, 0x0) /* Length of BIOS area */ - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */

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coreboot June 2011