coreboot December 2011

coreboot@coreboot.org

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174 discussions

New patch to review for coreboot: b95f3f3 Add rules to pull down and uncompress gpl_vsa_lx_102.bin
by Philip Prindeville 29 Dec '11

29 Dec '11

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/509 -gerrit commit b95f3f353cf61b21bc079566edc100a355757771 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Thu Dec 29 12:21:39 2011 -0700 Add rules to pull down and uncompress gpl_vsa_lx_102.bin These steps are in the Wiki, but they should be automated. Change-Id: I81528dddb47b0cfe4acd33456680f8d3211fabd7 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- src/arch/x86/Makefile.inc | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7bba44e..a95fd62 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -396,3 +396,8 @@ filo: CONFIG_FILO_MASTER=$(CONFIG_FILO_MASTER) \ CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE) +gpl_vsa_lx_102.bin.gz: + @wget -q http://marcjonesconsulting.com/gplvsa/gpl_vsa_lx_102.bin.gz + +gpl_vsa_lx_102.bin: gpl_vsa_lx_102.bin.gz + @gunzip $^

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New patch to review for coreboot: 5fd4844 Set default baudrate on Alix2d to be compatible with factory default
by Philip Prindeville 29 Dec '11

29 Dec '11

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/508 -gerrit commit 5fd4844dce2b414565ad512cbaa930159d00cd5d Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Wed Dec 28 16:32:44 2011 -0700 Set default baudrate on Alix2d to be compatible with factory default Boards shipping from PC Engines with the factory BIOS (tinyBios 0.99) boot up at 38400. In keeping with the principle of least astonishment, boards reflashed with SeaBIOS should probably try to keep compatible with this setting. Change-Id: Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- src/mainboard/pcengines/alix2d/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig index 264f5d9..ea02adf 100644 --- a/src/mainboard/pcengines/alix2d/Kconfig +++ b/src/mainboard/pcengines/alix2d/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_DISABLE + select CONSOLE_SERIAL_38400 config MAINBOARD_DIR string

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Bricked 6F2
by Philip Prindeville 29 Dec '11

29 Dec '11

Ok, I build coreboot's trunk and selected the target Alix2D, but managed to brick the device: coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 starting... MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:0000182e Configuring PLL. coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 starting... MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:07de002e PLL configured. Castle 2.0 BTM periodic sync period. Enable Quack for fewer re-RAS on the MC GLIU port active enable Set the Delay Control in GLCP spd_read_byte dev 50 addr 0d returns 08 spd_read_byte dev 50 addr 05 returns 01 spd_read_byte dev 51 returns 0xff Enable RSDC FPU imprecise exceptions bit Enable Suspend on HLT & PAUSE instructions Enable SUSP and allow TSC to run in Suspend Setup throttling delays to proper mode Done cpuRegInit Ram1.00 Ram2.00 * sdram_set_spd_register spd_read_byte dev 50 addr 15 returns ff * Check DIMM 0 * Check DIMM 1 spd_read_byte dev 51 returns 0xff * Check DDR MAX spd_read_byte dev 50 addr 09 returns 0a spd_read_byte dev 51 returns 0xff * AUTOSIZE DIMM 0 * Check present spd_read_byte dev 50 addr 02 returns 07 * MODBANKS spd_read_byte dev 50 addr 05 returns 01 * FIELDBANKS spd_read_byte dev 50 addr 11 returns 04 * SPDNUMROWS spd_read_byte dev 50 addr 03 returns 03 spd_read_byte dev 50 addr 04 returns 0a * SPDBANKDENSITY spd_read_byte dev 50 addr 1f returns 40 * DIMMSIZE * BEFORT CTZ * TEST DIMM SIZE>8 * PAGESIZE spd_read_byte dev 50 addr 04 returns 0a * MAXCOLADDR * >12address test * RDMSR CF07 * WRMSR CF07 * ALL DONE * AUTOSIZE DIMM 1 * Check present spd_read_byte dev 51 returns 0xff * set cas latency spd_read_byte dev 50 addr 12 returns 10 spd_read_byte dev 50 addr 17 returns 3c spd_read_byte dev 50 addr 19 returns 4b spd_read_byte dev 51 returns 0xff * set all latency spd_read_byte dev 50 addr 1e returns 28 spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 1b returns 0f spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 1d returns 0f spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 1c returns 0a spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 2a returns 46 spd_read_byte dev 51 returns 0xff * set emrs spd_read_byte dev 50 addr 16 returns ff spd_read_byte dev 51 returns 0xff * set ref rate spd_read_byte dev 50 addr 0c returns 3a spd_read_byte dev 51 returns 0xff Ram3 * DRAM controller init done. RAM DLL lock Ram4 POST 02 Past wbinvd Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 booting... clocks_per_usec: 499 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:0f.2: enabled 1 PCI: 00:0f.4: enabled 1 PCI: 00:0f.5: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 Compare with tree... Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:0f.2: enabled 1 PCI: 00:0f.4: enabled 1 PCI: 00:0f.5: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 scan_static_bus for Root Device >> Entering northbridge.c: enable_dev with path 6 >> Entering northbridge.c: pci_domain_enable Enter northbridge_init_early writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0 sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 sizeram: sizem 0x100MB SysmemInit: enable for 256MBytes usable RAM: 268304383 bytes SysmemInit: MSR 0x10000028, val 0x2000000f:0xfdf00100 sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 sizeram: sizem 0x100MB SMMGL0Init: 268304384 bytes SMMGL0Init: offset is 0x80400000 SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0 writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003 writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0 sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 sizeram: sizem 0x100MB SysmemInit: enable for 256MBytes usable RAM: 268304383 bytes SysmemInit: MSR 0x4000002a, val 0x2000000f:0xfdf00100 SMMGL1Init: SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0 writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001 writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0 CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x10FFDF00 CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000 L2 cache enabled Enabling cache GLPCI R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000 GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000 Exit northbridge_init_early Done cpubug fixes Not Doing ChipsetFlashSetup() Preparing for VSA... VSA: Real mode stub @00000600: 862 bytes Searching for vsa Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffd40, attempting to recover by searching for header Could not find file 'vsa'. Failed to load VSA. Graphics init... VRC_VG value: 0xffff Finding PCI configuration type. PCI: Sanity check failed pci_check_direct failed [hang] What am I missing? There doesn't seem to be a default VSA payload for the out-of-the-box default SeaBIOS build, which seems curious... I burned BIOS by doing the following: * boot the box up in linux * scp'd the coreboot.rom file over from my build box * flashrom -w coreboot.rom Those were hopefully the correct steps. -Philip

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Patch set updated for coreboot: a1ce169 Cleanup access to vendor/part # info
by Philip Prindeville 29 Dec '11

29 Dec '11

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/502 -gerrit commit a1ce169728cbae26db404959bc35f4779604d7ad Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Sat Dec 24 22:12:37 2011 -0700 Cleanup access to vendor/part # info Instead of macros to access MAINBOARD record, use convenience functions. Store pointers to MAINBOARD and HEADER for use outside of CB code. Change-Id: I074e3a0df7d25726cbd942538bfdc5a63dd17e12 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- payloads/coreinfo/coreboot_module.c | 4 ++-- payloads/libpayload/arch/i386/coreboot.c | 5 +++++ payloads/libpayload/include/coreboot_tables.h | 16 ++++++++++------ payloads/libpayload/include/sysinfo.h | 3 +++ 4 files changed, 20 insertions(+), 8 deletions(-) diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index 7289366..d33ea9e 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr) { struct cb_mainboard *mb = (struct cb_mainboard *)ptr; - strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31); - strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31); + strncpy(cb_info.vendor, cb_mb_vendor_part(mb), 31); + strncpy(cb_info.part, cb_mb_part_string(mb), 31); } static void parse_strings(unsigned char *ptr) diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c index 135c59c..7fe286e 100644 --- a/payloads/libpayload/arch/i386/coreboot.c +++ b/payloads/libpayload/arch/i386/coreboot.c @@ -137,6 +137,8 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info) header->table_bytes) != header->table_checksum) return -1; + info->header = header; + /* Now, walk the tables. */ ptr += header->header_bytes; @@ -173,6 +175,9 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info) cb_parse_framebuffer(ptr, info); break; #endif + case CB_TAG_MAINBOARD: + info->mainboard = (struct cb_mainboard *)ptr; + break; } ptr += rec->size; diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index e362d06..c68ccc9 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -228,6 +228,16 @@ static inline u16 cb_checksum(const void *ptr, unsigned len) return ipchksum(ptr, len); } +static inline const char *cb_mb_vendor_string(const struct cb_mainboard *cbm) +{ + return (char *)(cbm->strings + cbm->vendor_idx); +} + +static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm) +{ + return (char *)(cbm->strings + cbm->part_number_idx); +} + /* Helpful macros */ #define MEM_RANGE_COUNT(_rec) \ @@ -237,10 +247,4 @@ static inline u16 cb_checksum(const void *ptr, unsigned len) (void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \ + (sizeof((_rec)->map[0]) * (_idx))) -#define MB_VENDOR_STRING(_mb) \ - (((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx) - -#define MB_PART_STRING(_mb) \ - (((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx) - #endif diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index c1d2002..778dfe9 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -56,6 +56,9 @@ struct sysinfo_t { struct cb_framebuffer *framebuffer; unsigned long *mbtable; /** Pointer to the multiboot table */ + + struct cb_header *header; + struct cb_mainboard *mainboard; }; extern struct sysinfo_t lib_sysinfo;

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Patch set updated for coreboot: 24ace2e cb_parse_header() should not assume table in 4K of contiguous memory
by Philip Prindeville 29 Dec '11

29 Dec '11

Philip Prindeville (pprindeville(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/501 -gerrit commit 24ace2ea7da2db5c5f08f813ee6ce8c6147464cb Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Fri Dec 23 18:09:25 2011 -0700 cb_parse_header() should not assume table in 4K of contiguous memory If we have the CB table in E820 memory, we might not have an entire 4K (0x1000) bytes of memory to scan through. Instead, a better strategy is to pass in a pointer to the end of the region or the start + 4K (which ever is lower). This change prepares the cb_parse_header() calling convention for that change. Change-Id: I9257726c6a7065b5596d4c32ab451edd0a3cdc10 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- payloads/libpayload/arch/i386/coreboot.c | 22 ++++++++++++++-------- 1 files changed, 14 insertions(+), 8 deletions(-) diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c index 709f8ae..135c59c 100644 --- a/payloads/libpayload/arch/i386/coreboot.c +++ b/payloads/libpayload/arch/i386/coreboot.c @@ -109,21 +109,21 @@ static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info) } #endif -static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) +static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info) { struct cb_header *header; - unsigned char *ptr = addr; + unsigned char *ptr; void *forward; int i; - for (i = 0; i < len; i += 16, ptr += 16) { + for (ptr = addr; (void *)ptr < end; ptr += 16) { header = (struct cb_header *)ptr; if (!strncmp((const char *)header->signature, "LBIO", 4)) break; } /* We walked the entire space and didn't find anything. */ - if (i >= len) + if ((void *)ptr >= end) return -1; if (!header->table_bytes) @@ -147,7 +147,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) switch (rec->tag) { case CB_TAG_FORWARD: forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward); - return cb_parse_header(forward, len, info); + return cb_parse_header(forward, forward + 0x1000, info); continue; case CB_TAG_MEMORY: cb_parse_memory(ptr, info); @@ -176,6 +176,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) } ptr += rec->size; + + if ((void *)ptr >= end) + return -1; } return 1; @@ -186,10 +189,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info); + void *base = phys_to_virt(0x00000000); + int ret = cb_parse_header(base, base + 0x1000, info); - if (ret != 1) - ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info); + if (ret != 1) { + base = phys_to_virt(0x000f0000); + ret = cb_parse_header(base, base + 0x1000, info); + } return (ret == 1) ? 0 : -1; }

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Patch set updated for coreboot: afc57f7 Cleanup access to vendor/part # info
by Patrick Georgi 28 Dec '11

28 Dec '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/502 -gerrit commit afc57f7ce4bbfcae1257108fd549d33cdfd7c151 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Sat Dec 24 22:12:37 2011 -0700 Cleanup access to vendor/part # info Instead of macros to access MAINBOARD record, use convenience functions. Store pointers to MAINBOARD and HEADER for use outside of CB code. Change-Id: I074e3a0df7d25726cbd942538bfdc5a63dd17e12 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- payloads/coreinfo/coreboot_module.c | 4 ++-- payloads/libpayload/arch/i386/coreboot.c | 5 +++++ payloads/libpayload/include/coreboot_tables.h | 16 ++++++++++------ payloads/libpayload/include/sysinfo.h | 3 +++ 4 files changed, 20 insertions(+), 8 deletions(-) diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index 7289366..d33ea9e 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr) { struct cb_mainboard *mb = (struct cb_mainboard *)ptr; - strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31); - strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31); + strncpy(cb_info.vendor, cb_mb_vendor_part(mb), 31); + strncpy(cb_info.part, cb_mb_part_string(mb), 31); } static void parse_strings(unsigned char *ptr) diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c index 709f8ae..06acc17 100644 --- a/payloads/libpayload/arch/i386/coreboot.c +++ b/payloads/libpayload/arch/i386/coreboot.c @@ -137,6 +137,8 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) header->table_bytes) != header->table_checksum) return -1; + info->header = header; + /* Now, walk the tables. */ ptr += header->header_bytes; @@ -173,6 +175,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) cb_parse_framebuffer(ptr, info); break; #endif + case CB_TAG_MAINBOARD: + info->mainboard = (struct cb_mainboard *)ptr; + break; } ptr += rec->size; diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index e362d06..c68ccc9 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -228,6 +228,16 @@ static inline u16 cb_checksum(const void *ptr, unsigned len) return ipchksum(ptr, len); } +static inline const char *cb_mb_vendor_string(const struct cb_mainboard *cbm) +{ + return (char *)(cbm->strings + cbm->vendor_idx); +} + +static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm) +{ + return (char *)(cbm->strings + cbm->part_number_idx); +} + /* Helpful macros */ #define MEM_RANGE_COUNT(_rec) \ @@ -237,10 +247,4 @@ static inline u16 cb_checksum(const void *ptr, unsigned len) (void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \ + (sizeof((_rec)->map[0]) * (_idx))) -#define MB_VENDOR_STRING(_mb) \ - (((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx) - -#define MB_PART_STRING(_mb) \ - (((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx) - #endif diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index c1d2002..778dfe9 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -56,6 +56,9 @@ struct sysinfo_t { struct cb_framebuffer *framebuffer; unsigned long *mbtable; /** Pointer to the multiboot table */ + + struct cb_header *header; + struct cb_mainboard *mainboard; }; extern struct sysinfo_t lib_sysinfo;

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Patch set updated for coreboot: 1c7c31d Eliminate magic numbers
by Patrick Georgi 28 Dec '11

28 Dec '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/504 -gerrit commit 1c7c31d5bf4243fdddb86f0d2a1a315c54703140 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Fri Dec 23 18:45:33 2011 -0700 Eliminate magic numbers Use sizeof() on vendor and part# rather than explicit memory length. Change-Id: I2b7e0e4a8df6448d027cc61867382f161eb990d3 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> --- payloads/coreinfo/coreboot_module.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index d33ea9e..77a4bb2 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr) { struct cb_mainboard *mb = (struct cb_mainboard *)ptr; - strncpy(cb_info.vendor, cb_mb_vendor_part(mb), 31); - strncpy(cb_info.part, cb_mb_part_string(mb), 31); + strncpy(cb_info.vendor, cb_mb_vendor_part(mb), sizeof(cb_info.vendor) - 1); + strncpy(cb_info.part, cb_mb_part_string(mb), sizeof(cb_info.part) - 1); } static void parse_strings(unsigned char *ptr)

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New patch to review for coreboot: 05634a9 APIC: Fixed reading MSR_FSB_FREQ register
by Vikram Narayanan 27 Dec '11

27 Dec '11

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/507 -gerrit commit 05634a9703cb7c52a882a67669800e79a5101e99 Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Mon Dec 26 23:30:23 2011 +0530 APIC: Fixed reading MSR_FSB_FREQ register According to Intel's manual, bits 0:2 of MSR 0xCDh gives the FSB frequency. But the code had a right shift of 4 which will always give 267 MHz, as the valid bits are shifted to right. Also, fixed the indentations. Change-Id: I6bf93bac1ee9123af78c003f5a0728f8f0801958 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/cpu/x86/lapic/apic_timer.c | 31 +++++++++++++++++++++---------- 1 files changed, 21 insertions(+), 10 deletions(-) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 826f5b6..312951a 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -27,9 +27,10 @@ * memory init. */ -#define FSB_CLOCK_STS 0xcd +#define FSB_CLOCK_STS 0xCD +#define FSB_FREQ_MASK 0x07 -static u32 timer_fsb = 200; // default to 200MHz +static u32 timer_fsb = 200; // default to 200MHz void init_timer(void) { @@ -42,16 +43,26 @@ void init_timer(void) lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); + lapic_write(LAPIC_TMICT, ~0UL); /* Set FSB frequency to a reasonable value */ fsb_clock_sts = rdmsr(FSB_CLOCK_STS); - switch ((fsb_clock_sts.lo >> 4) & 0x07) { - case 0: timer_fsb = 266; break; - case 1: timer_fsb = 133; break; - case 2: timer_fsb = 200; break; - case 3: timer_fsb = 166; break; - case 5: timer_fsb = 100; break; + switch (fsb_clock_sts.lo & FSB_FREQ_MASK) { + case 0: + timer_fsb = 266; + break; + case 1: + timer_fsb = 133; + break; + case 2: + timer_fsb = 200; + break; + case 3: + timer_fsb = 166; + break; + case 5: + timer_fsb = 100; + break; } } @@ -63,5 +74,5 @@ void udelay(u32 usecs) start = lapic_read(LAPIC_TMCCT); do { value = lapic_read(LAPIC_TMCCT); - } while((start - value) < ticks); + } while ((start - value) < ticks); }

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coreboot dinner in Berlin today Tuesday 27/12 at 1800 CET
by Peter Stuge 27 Dec '11

27 Dec '11

Hi all! During the 28th Chaos Communication Congress [1] which starts today there is an unusually high concentration of coreboot developers and enthusiasts in Berlin, so this is a nice opportunity to have dinner together, and perhaps chat a bit or two about firmware! After reviewing the schedule of presentations (fahrplan [2]) it seems that Day 1 may be the best suited for doing a dinner together, since we may want to spend a little bit more time than the scheduled dinner break in the evening. The particular venue is as yet undecided. If I haven't made it to dolores [3] for lunch I would be happy to go there. The food is amazing. So far I know of roughly 7 persons who might join, and although dolores is not optimal for a group of 7 sitting around and chatting, we will be able to fit easily, especially since we are starting a little bit earlier than the scheduled dinner break. Other options include a few nice nearby restaurants, or possibly even going on a slightly longer excursion eastbound to the Friedrichshain area where there are plenty of nice restaurants. Let's meet at 1800 CET somewhere around the wardrobe/exit in the bcc building. Please don't hesitate to follow up with your suggestions or wishes for a particular restaurant, and in any case I hope you see you tomorrow evening! Kind regards (and sorry for the short notice!) //Peter

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New patch to review for coreboot: e267d74 Indentation: Various indentation fixes
by Vikram Narayanan 26 Dec '11

26 Dec '11

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/506 -gerrit commit e267d74eb35f6df29e9463faf6c75b3f7989af07 Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Mon Dec 26 22:52:01 2011 +0530 Indentation: Various indentation fixes Fixed indentation using indent tool in the src/drivers/i2c tree Change-Id: I5b396e5753544aff13ac5d16afc59e193a6b1da1 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/drivers/i2c/adm1026/adm1026.c | 38 ++++++++++++++++++------------------ src/drivers/i2c/adm1027/adm1027.c | 9 +++---- src/drivers/i2c/adt7463/adt7463.c | 8 +++--- src/drivers/i2c/i2cmux/i2cmux.c | 26 +++++++++++------------- src/drivers/i2c/i2cmux2/i2cmux2.c | 24 ++++++++++------------ src/drivers/i2c/lm63/lm63.c | 24 ++++++++++------------ 6 files changed, 61 insertions(+), 68 deletions(-) diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c index 14b07aa..1aaae52 100644 --- a/src/drivers/i2c/adm1026/adm1026.c +++ b/src/drivers/i2c/adm1026/adm1026.c @@ -7,7 +7,7 @@ #include <cpu/x86/msr.h> #include "chip.h" -#define ADM1026_DEVICE 0x2d /* Either 0x2c or 0x2d or 0x2e */ +#define ADM1026_DEVICE 0x2d /* Either 0x2c or 0x2d or 0x2e */ #define ADM1026_REG_CONFIG1 0x00 #define CFG1_MONITOR 0x01 #define CFG1_INT_ENABLE 0x02 @@ -24,38 +24,38 @@ static void adm1026_enable_monitoring(device_t dev); static void adm1026_init(device_t dev) { - if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) - { - if(ops_smbus_bus(get_pbus_smbus(dev))) { - if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux + if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { + if (ops_smbus_bus(get_pbus_smbus(dev))) { + if (dev->bus->dev->path.type == DEVICE_PATH_I2C) + smbus_set_link(dev); // it is under mux adm1026_enable_monitoring(dev); } - } - } + static void adm1026_enable_monitoring(device_t dev) { - int result; - result = smbus_read_byte(dev, ADM1026_REG_CONFIG1); + int result; + result = smbus_read_byte(dev, ADM1026_REG_CONFIG1); - result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1_RESET); - result = smbus_write_byte(dev, ADM1026_REG_CONFIG1, result); + result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1_RESET); + result = smbus_write_byte(dev, ADM1026_REG_CONFIG1, result); - result = smbus_read_byte(dev, ADM1026_REG_CONFIG1); - if (!(result & CFG1_MONITOR)) { - printk(BIOS_DEBUG, "ADM1026: monitoring would not enable"); - } + result = smbus_read_byte(dev, ADM1026_REG_CONFIG1); + if (!(result & CFG1_MONITOR)) { + printk(BIOS_DEBUG, "ADM1026: monitoring would not enable"); + } } + static void adm1026_noop(device_t dummy) { } static struct device_operations adm1026_operations = { - .read_resources = adm1026_noop, - .set_resources = adm1026_noop, - .enable_resources = adm1026_noop, - .init = adm1026_init, + .read_resources = adm1026_noop, + .set_resources = adm1026_noop, + .enable_resources = adm1026_noop, + .init = adm1026_init, }; static void enable_dev(struct device *dev) diff --git a/src/drivers/i2c/adm1027/adm1027.c b/src/drivers/i2c/adm1027/adm1027.c index bca2c0d..516a889 100644 --- a/src/drivers/i2c/adm1027/adm1027.c +++ b/src/drivers/i2c/adm1027/adm1027.c @@ -47,7 +47,6 @@ static void adm1027_init(device_t dev) smbus_set_link(dev); // it is under mux adm1027_enable_monitoring(dev); } - } } @@ -56,10 +55,10 @@ static void adm1027_noop(device_t dummy) } static struct device_operations adm1027_operations = { - .read_resources = adm1027_noop, - .set_resources = adm1027_noop, - .enable_resources = adm1027_noop, - .init = adm1027_init, + .read_resources = adm1027_noop, + .set_resources = adm1027_noop, + .enable_resources = adm1027_noop, + .init = adm1027_init, }; static void enable_dev(struct device *dev) diff --git a/src/drivers/i2c/adt7463/adt7463.c b/src/drivers/i2c/adt7463/adt7463.c index 25a65c8..3967bf7 100644 --- a/src/drivers/i2c/adt7463/adt7463.c +++ b/src/drivers/i2c/adt7463/adt7463.c @@ -91,10 +91,10 @@ static void adt7463_noop(device_t dummy) } static struct device_operations adt7463_operations = { - .read_resources = adt7463_noop, - .set_resources = adt7463_noop, - .enable_resources = adt7463_noop, - .init = adt7463_init, + .read_resources = adt7463_noop, + .set_resources = adt7463_noop, + .enable_resources = adt7463_noop, + .init = adt7463_init, }; static void enable_dev(struct device *dev) diff --git a/src/drivers/i2c/i2cmux/i2cmux.c b/src/drivers/i2c/i2cmux/i2cmux.c index 14c52cc..44bf390 100644 --- a/src/drivers/i2c/i2cmux/i2cmux.c +++ b/src/drivers/i2c/i2cmux/i2cmux.c @@ -9,32 +9,30 @@ static void i2cmux_set_link(device_t dev, unsigned int link) { - if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) - { - if(ops_smbus_bus(get_pbus_smbus(dev))) { - smbus_write_byte(dev, 0x01, 1<<link); // output value - smbus_write_byte(dev, 0x03, 0); // all output + if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { + if (ops_smbus_bus(get_pbus_smbus(dev))) { + smbus_write_byte(dev, 0x01, 1 << link); // output value + smbus_write_byte(dev, 0x03, 0); // all output } - } - } + static void i2cmux_noop(device_t dummy) { } static struct device_operations i2cmux_operations = { - .read_resources = i2cmux_noop, - .set_resources = i2cmux_noop, - .enable_resources = i2cmux_noop, - .init = i2cmux_noop, - .scan_bus = scan_static_bus, - .set_link = i2cmux_set_link, + .read_resources = i2cmux_noop, + .set_resources = i2cmux_noop, + .enable_resources = i2cmux_noop, + .init = i2cmux_noop, + .scan_bus = scan_static_bus, + .set_link = i2cmux_set_link, }; static void enable_dev(struct device *dev) { - if(dev->link_list != NULL) + if (dev->link_list != NULL) dev->ops = &i2cmux_operations; } diff --git a/src/drivers/i2c/i2cmux2/i2cmux2.c b/src/drivers/i2c/i2cmux2/i2cmux2.c index c0f8e70..dc8ec25 100644 --- a/src/drivers/i2c/i2cmux2/i2cmux2.c +++ b/src/drivers/i2c/i2cmux2/i2cmux2.c @@ -9,31 +9,29 @@ static void i2cmux2_set_link(device_t dev, unsigned int link) { - if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) - { - if(ops_smbus_bus(get_pbus_smbus(dev))) { - smbus_send_byte(dev, link); // output value + if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { + if (ops_smbus_bus(get_pbus_smbus(dev))) { + smbus_send_byte(dev, link); // output value } - } - } + static void i2cmux2_noop(device_t dummy) { } static struct device_operations i2cmux2_operations = { - .read_resources = i2cmux2_noop, - .set_resources = i2cmux2_noop, - .enable_resources = i2cmux2_noop, - .init = i2cmux2_noop, - .scan_bus = scan_static_bus, - .set_link = i2cmux2_set_link, + .read_resources = i2cmux2_noop, + .set_resources = i2cmux2_noop, + .enable_resources = i2cmux2_noop, + .init = i2cmux2_noop, + .scan_bus = scan_static_bus, + .set_link = i2cmux2_set_link, }; static void enable_dev(struct device *dev) { - if(dev->link_list != NULL) + if (dev->link_list != NULL) dev->ops = &i2cmux2_operations; } diff --git a/src/drivers/i2c/lm63/lm63.c b/src/drivers/i2c/lm63/lm63.c index 05302a6..d98a245 100644 --- a/src/drivers/i2c/lm63/lm63.c +++ b/src/drivers/i2c/lm63/lm63.c @@ -7,32 +7,30 @@ #include <cpu/x86/msr.h> #include "chip.h" - static void lm63_init(device_t dev) { int result; - if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) - { - if(ops_smbus_bus(get_pbus_smbus(dev))) { - if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux + if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { + if (ops_smbus_bus(get_pbus_smbus(dev))) { + if (dev->bus->dev->path.type == DEVICE_PATH_I2C) + smbus_set_link(dev); // it is under mux result = smbus_read_byte(dev, 0x03); -// result &= ~0x04; +// result &= ~0x04; result |= 0x04; - smbus_write_byte(dev, 0x03, result & 0xff); // config lm63 + smbus_write_byte(dev, 0x03, result & 0xff); // config lm63 } - } - } + static void lm63_noop(device_t dummy) { } static struct device_operations lm63_operations = { - .read_resources = lm63_noop, - .set_resources = lm63_noop, - .enable_resources = lm63_noop, - .init = lm63_init, + .read_resources = lm63_noop, + .set_resources = lm63_noop, + .enable_resources = lm63_noop, + .init = lm63_init, }; static void enable_dev(struct device *dev)

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coreboot December 2011