coreboot October 2011

coreboot@coreboot.org

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501 discussions

Patch set updated for coreboot: 46b7be0 Prevent multiple inclusions of object files and rules
by Patrick Georgi 28 Oct '11

28 Oct '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/338 -gerrit commit 46b7be06c82f59498c876f4e06e3dacf32fb16ac Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Tue Oct 25 14:32:21 2011 -0700 Prevent multiple inclusions of object files and rules This removes 54 make warnings from the build Change-Id: I94ac9875526febe2f95334c1c3971641c1d27f8f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/Makefile b/Makefile index c543897..ce4b3e0 100644 --- a/Makefile +++ b/Makefile @@ -205,7 +205,7 @@ subdirs:=$(TOPLEVEL) $(eval $(call evaluate_subdirs)) src-to-obj=$(addsuffix .$(1).o, $(basename $(patsubst src/%, $(obj)/%, $($(1)-srcs)))) -$(foreach class,$(classes),$(eval $(class)-objs:=$(call src-to-obj,$(class)))) +$(foreach class,$(classes),$(eval $(class)-objs:=$(sort $(call src-to-obj,$(class))))) allsrcs:=$(foreach var, $(addsuffix -srcs,$(classes)), $($(var))) allobjs:=$(foreach var, $(addsuffix -objs,$(classes)), $($(var)))

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Patch set updated for coreboot: 586d9a5 Add bootstrap to select loaded romstage
by Kyösti Mälkki 28 Oct '11

28 Oct '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/304 -gerrit commit 586d9a5f5480080210a40b15b8833bf992e9d6e6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Oct 27 17:04:39 2011 +0300 Add bootstrap to select loaded romstage Just before loading romstage, read the console serial port pin (DCD). The level determines whether normal or fallback boots. Change-Id: Ib8b6984ddd886cd21638880c6f43dd90d078c844 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/init/bootblock_normal.c | 9 ++++++- src/arch/x86/init/bootblock_simple.c | 16 +++++++++++- src/arch/x86/init/bootstrap_dcd.h | 41 ++++++++++++++++++++++++++++++++++ src/console/Kconfig | 9 +++++++ 4 files changed, 72 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c index db9d0f9..f3f4e50 100644 --- a/src/arch/x86/init/bootblock_normal.c +++ b/src/arch/x86/init/bootblock_normal.c @@ -1,5 +1,6 @@ #include <bootblock_common.h> #include <pc80/mc146818rtc.h> +#include "bootstrap_dcd.h" static void main(unsigned long bist) { @@ -14,7 +15,13 @@ static void main(unsigned long bist) #endif unsigned long entry; - if (do_normal_boot()) + int boot_mode = do_normal_boot(); + +#if CONFIG_TTYS0_DCD_HOOK + /* high DCD overrides to fallback */ + boot_mode &= !early_dcd_hook(); +#endif + if (boot_mode) entry = findstage("normal/romstage"); else entry = findstage("fallback/romstage"); diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c index 5d7c611..f5f3158 100644 --- a/src/arch/x86/init/bootblock_simple.c +++ b/src/arch/x86/init/bootblock_simple.c @@ -1,4 +1,5 @@ #include <bootblock_common.h> +#include "bootstrap_dcd.h" static void main(unsigned long bist) { @@ -12,10 +13,21 @@ static void main(unsigned long bist) sanitize_cmos(); #endif - const char* target1 = "fallback/romstage"; unsigned long entry; - entry = findstage(target1); + int boot_mode = 0; + +#if CONFIG_TTYS0_DCD_HOOK + /* DCD high selects normal */ + boot_mode = early_dcd_hook(); +#endif + if (boot_mode) + entry = findstage("normal/romstage"); + else + entry = findstage("fallback/romstage"); + if (entry) call(entry, bist); + + /* duh. we're stuck */ asm volatile ("1:\n\thlt\n\tjmp 1b\n\t"); } diff --git a/src/arch/x86/init/bootstrap_dcd.h b/src/arch/x86/init/bootstrap_dcd.h new file mode 100644 index 0000000..956b116 --- /dev/null +++ b/src/arch/x86/init/bootstrap_dcd.h @@ -0,0 +1,41 @@ +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <uart8250.h> + +/* grab from devicetree.cb ? */ +#define EARLY_SERIAL_DEV PNP_DEV(0x2e, 0x04) +#define EARLY_TTYS0_BASE 0x3f8 + +#if CONFIG_TTYS0_DCD_HOOK +static int early_dcd_hook(void) +{ + device_t dev = EARLY_SERIAL_DEV; + u16 port = dev >> 8; + u16 base; + u8 dcd, i; + + /* power-up uart, set base if not already set */ + outb(0x55, port); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + base = pnp_read_iobase(dev, PNP_IDX_IO0); + if (!base) { + base = EARLY_TTYS0_BASE; + pnp_set_iobase(dev, PNP_IDX_IO0, base); + } + pnp_set_enable(dev, 1); + outb(0xaa, port); + + /* assert DTR, so you can jump-wire DCD high */ + outb(UART_MCR_DTR, base + UART_MCR); + + /* just powered up.. better not to trust the first value */ + i = 0; + do { + dcd = !!(inb(base + UART_MSR) & UART_MSR_DCD); + } while (++i<10); + return dcd; +} +#endif + diff --git a/src/console/Kconfig b/src/console/Kconfig index 8382695..b1b2fc8 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -91,6 +91,15 @@ config TTYS0_LCS default 3 depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM +config TTYS0_DCD_HOOK + bool "DCD line is bootstrap to select romstage" + default n + depends on CONSOLE_SERIAL8250 + help + Status of DCD line on the selected serial debug console + port is read at boot-time, and is used to choose from + the two romstage prefixes. + # Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code. config HAVE_USBDEBUG def_bool n

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ASRock P4i65GV: Can my platform get support by coreboot?
by fiveframe＠lavabit.com 28 Oct '11

28 Oct '11

http://www.asrock.com/mb/overview.asp?model=p4i65gv 1. My current motherboard: Vendor: ASRock Name: P4i65GV CPU: Intel Pentium 4 1.60GHz (Socket 478, Prescott) Northbridge: Intel® 865GV Southbridge: Intel® ICH5 2. Output of lspci -tvnn: -[0000:00]-+-00.0 Intel Corporation 82865G/PE/P DRAM Controller/Host-Hub Interface [8086:2570] +-02.0 Intel Corporation 82865G Integrated Graphics Controller [8086:2572] +-06.0 Intel Corporation 82865G/PE/P Processor to I/O Memory Interface [8086:2576] +-1d.0 Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1 [8086:24d2] +-1d.1 Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2 [8086:24d4] +-1d.2 Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3 [8086:24d7] +-1d.3 Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4 [8086:24de] +-1d.7 Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller [8086:24dd] +-1e.0-[01]----05.0 Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] +-1f.0 Intel Corporation 82801EB/ER (ICH5/ICH5R) LPC Interface Bridge [8086:24d0] +-1f.1 Intel Corporation 82801EB/ER (ICH5/ICH5R) IDE Controller [8086:24db] +-1f.3 Intel Corporation 82801EB/ER (ICH5/ICH5R) SMBus Controller [8086:24d3] \-1f.5 Intel Corporation 82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller [8086:24d5] 3. Output of superiotool -dV: superiotool r6543 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xc0fe, id=0x4152 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x5241, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0x5241 Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0x5241, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e Register dump: idx 02 20 21 22 23 24 25 26 28 29 2a 2b 2c 2e 2f val ff 52 41 ff fe c0 00 00 00 00 7c c0 ff 00 ff def 00 52 NA ff 00 MM 00 00 00 00 7c c0 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 01 03 f0 06 02 0e 00 ff 00 00 def 01 03 f0 06 02 0e 00 ff 00 00 LDN 0x01 (Parallel port) idx 30 60 61 70 74 f0 val 01 03 78 07 03 3b def 01 03 78 07 04 3f LDN 0x02 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 01 03 f8 04 00 LDN 0x03 (COM2) idx 30 60 61 70 f0 f1 val 00 00 00 00 00 00 def 01 02 f8 03 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 72 f0 val 01 00 60 00 64 01 0c 40 def 01 00 60 00 64 01 0c 80 LDN 0x06 (Consumer IR) idx 30 60 61 70 val 00 00 00 00 def 00 00 00 00 LDN 0x07 (Game port, MIDI port, GPIO 1) idx 30 60 61 62 63 70 f0 f1 f2 val 00 00 00 00 00 00 ff ff ff def 00 02 01 03 30 09 ff 00 00 LDN 0x08 (GPIO 2, watchdog timer) idx 30 f0 f1 f2 f3 f5 f6 f6 f7 val 01 ff 06 00 00 00 00 00 00 def 00 ff 00 00 00 00 00 00 00 LDN 0x09 (GPIO 3) idx 30 f0 f1 f2 f3 val 00 ff ff ff 40 def 00 ff 00 00 00 LDN 0x0a (ACPI) idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f3 f4 f6 f7 f9 fe ff val 00 00 00 00 6a 20 00 00 00 00 00 8f 3e 00 00 00 00 00 00 def 00 00 00 00 NA NA 00 00 00 00 00 00 00 00 00 00 00 00 00 LDN 0x0b (Hardware monitor) idx 30 60 61 70 f0 val 01 02 90 00 00 def 00 00 00 00 00 Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff 4. Output of flashrom -V: flashrom v0.9.4-r1395 on Linux 3.0-ARCH (i686), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 987M loops per second, 10 myus = 25 us, 100 myus = 94 us, 1000 myus = 927 us, 10000 myus = 10262 us, 4 myus = 11 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: " " DMI string system-product-name: "P4i65GV" DMI string system-version: "1.00" DMI string baseboard-manufacturer: " " DMI string baseboard-product-name: "P4i65GV" DMI string baseboard-version: "1.0" DMI string chassis-type: "" DMI chassis-type is not specific enough. ======================================================================== WARNING! You may be running flashrom on an unsupported laptop. We could not detect this for sure because your vendor has not setup the SMBIOS tables correctly. You can enforce execution by adding '-p internal:laptop=force_I_want_a_brick' to the command line, but please read the following warning if you are not sure. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting.

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Patch set updated for coreboot: d600ff6 Clear improper use of CONFIG_CACHE_AS_RAM
by Kyösti Mälkki 28 Oct '11

28 Oct '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/347 -gerrit commit d600ff6ef170bf01ae074c0e71560923ff2d185e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Oct 28 16:15:47 2011 +0300 Clear improper use of CONFIG_CACHE_AS_RAM Choice between printk/print_ is related to CAR, but really depends whether we compiled with GCC or ROMCC. Change-Id: I9fe831a215736462e8b3f4b96ffe231133ecf79b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/ramtest.c | 24 ++++++++++++------------ src/northbridge/intel/e7501/debug.c | 32 ++++++++++++++++---------------- 2 files changed, 28 insertions(+), 28 deletions(-) diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 3f4657f..b35c36d 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -53,7 +53,7 @@ static void ram_fill(unsigned long start, unsigned long stop) /* * Fill. */ -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "DRAM fill: 0x%08lx-0x%08lx\n", start, stop); #else print_debug("DRAM fill: "); @@ -65,7 +65,7 @@ static void ram_fill(unsigned long start, unsigned long stop) for(addr = start; addr < stop ; addr += 4) { /* Display address being filled */ if (!(addr & 0xfffff)) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "%08lx \r", addr); #else print_debug_hex32(addr); @@ -75,7 +75,7 @@ static void ram_fill(unsigned long start, unsigned long stop) write_phys(addr, (u32)addr); }; /* Display final address */ -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "%08lx\nDRAM filled\n", addr); #else print_debug_hex32(addr); @@ -90,7 +90,7 @@ static void ram_verify(unsigned long start, unsigned long stop) /* * Verify. */ -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\n", start, stop); #else print_debug("DRAM verify: "); @@ -103,7 +103,7 @@ static void ram_verify(unsigned long start, unsigned long stop) unsigned long value; /* Display address being tested */ if (!(addr & 0xfffff)) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "%08lx \r", addr); #else print_debug_hex32(addr); @@ -113,7 +113,7 @@ static void ram_verify(unsigned long start, unsigned long stop) value = read_phys(addr); if (value != addr) { /* Display address with error */ -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\n", addr, value); #else print_err("Fail: @0x"); @@ -124,7 +124,7 @@ static void ram_verify(unsigned long start, unsigned long stop) #endif i++; if(i>256) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "Aborting.\n"); #else print_debug("Aborting.\n"); @@ -134,14 +134,14 @@ static void ram_verify(unsigned long start, unsigned long stop) } } /* Display final address */ -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "%08lx", addr); #else print_debug_hex32(addr); #endif if (i) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); #else print_debug("\nDRAM did _NOT_ verify!\n"); @@ -149,7 +149,7 @@ static void ram_verify(unsigned long start, unsigned long stop) die("DRAM ERROR"); } else { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "\nDRAM range verified.\n"); #else print_debug("\nDRAM range verified.\n"); @@ -165,7 +165,7 @@ void ram_check(unsigned long start, unsigned long stop) * test than a "Is my DRAM faulty?" test. Not all bits * are tested. -Tyson */ -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\n", start, stop); #else print_debug("Testing DRAM : "); @@ -178,7 +178,7 @@ void ram_check(unsigned long start, unsigned long stop) /* Make sure we don't read before we wrote */ phys_memory_barrier(); ram_verify(start, stop); -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "Done.\n"); #else print_debug("Done.\n"); diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c index f19de0c..07f1596 100644 --- a/src/northbridge/intel/e7501/debug.c +++ b/src/northbridge/intel/e7501/debug.c @@ -39,7 +39,7 @@ static void dump_pci_device(unsigned dev) for(i = 0; i < 256; i++) { unsigned char val; if ((i & 0x0f) == 0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "\n%02x:",i); #else print_debug("\n"); @@ -48,7 +48,7 @@ static void dump_pci_device(unsigned dev) #endif } val = pci_read_config8(dev, i); -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, " %02x", val); #else print_debug_char(' '); @@ -101,7 +101,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device); #else print_debug("dimm: "); @@ -113,7 +113,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "\n%02x: ", j); #else print_debug("\n"); @@ -126,7 +126,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) break; } byte = status & 0xff; -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "%02x ", byte); #else print_debug_hex8(byte); @@ -138,7 +138,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); #else print_debug("dimm: "); @@ -150,7 +150,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "\n%02x: ", j); #else print_debug("\n"); @@ -163,7 +163,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) break; } byte = status & 0xff; -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "%02x ", byte); #else print_debug_hex8(byte); @@ -181,7 +181,7 @@ static inline void dump_smbus_registers(void) for(device = 1; device < 0x80; device++) { int j; if( smbus_read_byte(device, 0) < 0 ) continue; -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "smbus: %02x", device); #else print_debug("smbus: "); @@ -195,7 +195,7 @@ static inline void dump_smbus_registers(void) break; } if ((j & 0xf) == 0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "\n%02x: ",j); #else print_debug("\n"); @@ -204,7 +204,7 @@ static inline void dump_smbus_registers(void) #endif } byte = status & 0xff; -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "%02x ", byte); #else print_debug_hex8(byte); @@ -219,7 +219,7 @@ static inline void dump_io_resources(unsigned port) { int i; -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "%04x:\n", port); #else print_debug_hex16(port); @@ -228,7 +228,7 @@ static inline void dump_io_resources(unsigned port) for(i=0;i<256;i++) { uint8_t val; if ((i & 0x0f) == 0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "%02x:", i); #else print_debug_hex8(i); @@ -236,7 +236,7 @@ static inline void dump_io_resources(unsigned port) #endif } val = inb(port); -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, " %02x",val); #else print_debug_char(' '); @@ -255,7 +255,7 @@ static inline void dump_mem(unsigned start, unsigned end) print_debug("dump_mem:"); for(i=start;i<end;i++) { if((i & 0xf)==0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, "\n%08x:", i); #else print_debug("\n"); @@ -263,7 +263,7 @@ static inline void dump_mem(unsigned start, unsigned end) print_debug(":"); #endif } -#if CONFIG_CACHE_AS_RAM +#if !defined(__ROMCC__) printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); #else print_debug(" ");

1 0

New patch to review for coreboot: b43d315 Clear improper use of CONFIG_CACHE_AS_RAM
by Kyösti Mälkki 28 Oct '11

28 Oct '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/347 -gerrit commit b43d3153add318e930d0f576a1cbb7bfb0717e34 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Oct 28 14:17:49 2011 +0300 Clear improper use of CONFIG_CACHE_AS_RAM Choice between printk/print_ is unrelated to CAR. Change-Id: I9fe831a215736462e8b3f4b96ffe231133ecf79b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/ramtest.c | 24 ++++++++++++------------ src/northbridge/intel/e7501/debug.c | 32 ++++++++++++++++---------------- 2 files changed, 28 insertions(+), 28 deletions(-) diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 3f4657f..d71b0e9 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -53,7 +53,7 @@ static void ram_fill(unsigned long start, unsigned long stop) /* * Fill. */ -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "DRAM fill: 0x%08lx-0x%08lx\n", start, stop); #else print_debug("DRAM fill: "); @@ -65,7 +65,7 @@ static void ram_fill(unsigned long start, unsigned long stop) for(addr = start; addr < stop ; addr += 4) { /* Display address being filled */ if (!(addr & 0xfffff)) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "%08lx \r", addr); #else print_debug_hex32(addr); @@ -75,7 +75,7 @@ static void ram_fill(unsigned long start, unsigned long stop) write_phys(addr, (u32)addr); }; /* Display final address */ -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "%08lx\nDRAM filled\n", addr); #else print_debug_hex32(addr); @@ -90,7 +90,7 @@ static void ram_verify(unsigned long start, unsigned long stop) /* * Verify. */ -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\n", start, stop); #else print_debug("DRAM verify: "); @@ -103,7 +103,7 @@ static void ram_verify(unsigned long start, unsigned long stop) unsigned long value; /* Display address being tested */ if (!(addr & 0xfffff)) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "%08lx \r", addr); #else print_debug_hex32(addr); @@ -113,7 +113,7 @@ static void ram_verify(unsigned long start, unsigned long stop) value = read_phys(addr); if (value != addr) { /* Display address with error */ -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\n", addr, value); #else print_err("Fail: @0x"); @@ -124,7 +124,7 @@ static void ram_verify(unsigned long start, unsigned long stop) #endif i++; if(i>256) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "Aborting.\n"); #else print_debug("Aborting.\n"); @@ -134,14 +134,14 @@ static void ram_verify(unsigned long start, unsigned long stop) } } /* Display final address */ -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "%08lx", addr); #else print_debug_hex32(addr); #endif if (i) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); #else print_debug("\nDRAM did _NOT_ verify!\n"); @@ -149,7 +149,7 @@ static void ram_verify(unsigned long start, unsigned long stop) die("DRAM ERROR"); } else { -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "\nDRAM range verified.\n"); #else print_debug("\nDRAM range verified.\n"); @@ -165,7 +165,7 @@ void ram_check(unsigned long start, unsigned long stop) * test than a "Is my DRAM faulty?" test. Not all bits * are tested. -Tyson */ -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\n", start, stop); #else print_debug("Testing DRAM : "); @@ -178,7 +178,7 @@ void ram_check(unsigned long start, unsigned long stop) /* Make sure we don't read before we wrote */ phys_memory_barrier(); ram_verify(start, stop); -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "Done.\n"); #else print_debug("Done.\n"); diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c index f19de0c..886517d 100644 --- a/src/northbridge/intel/e7501/debug.c +++ b/src/northbridge/intel/e7501/debug.c @@ -39,7 +39,7 @@ static void dump_pci_device(unsigned dev) for(i = 0; i < 256; i++) { unsigned char val; if ((i & 0x0f) == 0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "\n%02x:",i); #else print_debug("\n"); @@ -48,7 +48,7 @@ static void dump_pci_device(unsigned dev) #endif } val = pci_read_config8(dev, i); -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, " %02x", val); #else print_debug_char(' '); @@ -101,7 +101,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device); #else print_debug("dimm: "); @@ -113,7 +113,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "\n%02x: ", j); #else print_debug("\n"); @@ -126,7 +126,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) break; } byte = status & 0xff; -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "%02x ", byte); #else print_debug_hex8(byte); @@ -138,7 +138,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); #else print_debug("dimm: "); @@ -150,7 +150,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) int status; unsigned char byte; if ((j & 0xf) == 0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "\n%02x: ", j); #else print_debug("\n"); @@ -163,7 +163,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) break; } byte = status & 0xff; -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "%02x ", byte); #else print_debug_hex8(byte); @@ -181,7 +181,7 @@ static inline void dump_smbus_registers(void) for(device = 1; device < 0x80; device++) { int j; if( smbus_read_byte(device, 0) < 0 ) continue; -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "smbus: %02x", device); #else print_debug("smbus: "); @@ -195,7 +195,7 @@ static inline void dump_smbus_registers(void) break; } if ((j & 0xf) == 0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "\n%02x: ",j); #else print_debug("\n"); @@ -204,7 +204,7 @@ static inline void dump_smbus_registers(void) #endif } byte = status & 0xff; -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "%02x ", byte); #else print_debug_hex8(byte); @@ -219,7 +219,7 @@ static inline void dump_io_resources(unsigned port) { int i; -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "%04x:\n", port); #else print_debug_hex16(port); @@ -228,7 +228,7 @@ static inline void dump_io_resources(unsigned port) for(i=0;i<256;i++) { uint8_t val; if ((i & 0x0f) == 0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "%02x:", i); #else print_debug_hex8(i); @@ -236,7 +236,7 @@ static inline void dump_io_resources(unsigned port) #endif } val = inb(port); -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, " %02x",val); #else print_debug_char(' '); @@ -255,7 +255,7 @@ static inline void dump_mem(unsigned start, unsigned end) print_debug("dump_mem:"); for(i=start;i<end;i++) { if((i & 0xf)==0) { -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, "\n%08x:", i); #else print_debug("\n"); @@ -263,7 +263,7 @@ static inline void dump_mem(unsigned start, unsigned end) print_debug(":"); #endif } -#if CONFIG_CACHE_AS_RAM +#if !defined(__PRE_RAM__) printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); #else print_debug(" ");

1 0

New patch to review for coreboot: de146c3 siemens/sitemp_g1p1: Add more devices to PIR and MP table
by Patrick Georgi 28 Oct '11

28 Oct '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/346 -gerrit commit de146c35db3a771e779726bda61224455c1433ac Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Oct 6 14:36:08 2011 +0200 siemens/sitemp_g1p1: Add more devices to PIR and MP table Linux 2.4 is happier that way Change-Id: I016609ae1e004ec856e8223893352dcdd061b291 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/mainboard/siemens/sitemp_g1p1/irq_tables.c | 5 ++ src/mainboard/siemens/sitemp_g1p1/mptable.c | 55 ++++++++++++++++++++++++ 2 files changed, 60 insertions(+), 0 deletions(-) diff --git a/src/mainboard/siemens/sitemp_g1p1/irq_tables.c b/src/mainboard/siemens/sitemp_g1p1/irq_tables.c index b2a9668..186057d 100644 --- a/src/mainboard/siemens/sitemp_g1p1/irq_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/irq_tables.c @@ -117,6 +117,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info++; slot_num++; + /* ide */ + write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 1, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 1, 0); + pirq_info++; + slot_num++; + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c index 0e18fb3..9e4a6db 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mptable.c +++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c @@ -60,6 +60,61 @@ static void *smp_write_config_table(void *v) } mptable_add_isa_interrupts(mc, isa_bus, apicid_sb600, 0); +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) + + /* usb */ + PCI_INT(0x0, 0x13, 0x0, 0x10); + PCI_INT(0x0, 0x13, 0x1, 0x11); + PCI_INT(0x0, 0x13, 0x2, 0x12); + PCI_INT(0x0, 0x13, 0x3, 0x13); + + /* sata */ + PCI_INT(0x0, 0x12, 0x1, 0x16); + + /* SMBus/ACPI */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + /* IDE */ + PCI_INT(0x0, 0x14, 0x1, 0x11); + /* HDA */ + PCI_INT(0x0, 0x14, 0x2, 0x12); + /* LPC */ + PCI_INT(0x0, 0x14, 0x3, 0x13); + + /* GFX ? */ + PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12); + PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13); + + /* PCIe slots */ + PCI_INT(0x2, 0x00, 0x00, 0x10); + PCI_INT(0x2, 0x00, 0x01, 0x11); + PCI_INT(0x2, 0x00, 0x02, 0x12); + PCI_INT(0x2, 0x00, 0x03, 0x13); + + /* PCIe slots */ + PCI_INT(0x3, 0x00, 0x00, 0x11); + PCI_INT(0x3, 0x00, 0x01, 0x12); + PCI_INT(0x3, 0x00, 0x02, 0x13); + PCI_INT(0x3, 0x00, 0x03, 0x10); + + /* PCIe slots */ + PCI_INT(0x4, 0x00, 0x00, 0x12); + PCI_INT(0x4, 0x00, 0x01, 0x13); + PCI_INT(0x4, 0x00, 0x02, 0x10); + PCI_INT(0x4, 0x00, 0x03, 0x11); + + /* PCIe slots */ + PCI_INT(0x5, 0x00, 0x00, 0x13); + PCI_INT(0x5, 0x00, 0x01, 0x10); + PCI_INT(0x5, 0x00, 0x02, 0x11); + PCI_INT(0x5, 0x00, 0x03, 0x12); + + /* onboard NIC ? */ + PCI_INT(bus_sb600[1], 0x7, 0x0, 0x13); + PCI_INT(bus_sb600[1], 0x7, 0x1, 0x10); + PCI_INT(bus_sb600[1], 0x7, 0x2, 0x11); + PCI_INT(bus_sb600[1], 0x7, 0x3, 0x12); + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus);

1 0

New patch to review for coreboot: 3c5985b sb600: Implement EHCI workaround
by Patrick Georgi 28 Oct '11

28 Oct '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/345 -gerrit commit 3c5985bcc27c9c5349451571cbf7dd20f8a354d4 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Oct 28 09:01:54 2011 +0200 sb600: Implement EHCI workaround Linux implements it itself, but older Linuxes and other systems might not. Without this, the host controller might not respond to drivers. Change-Id: I4ff0e3683c02e7aa00d188428847c64c4c5d589d Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/southbridge/amd/sb600/usb.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/sb600/usb.c b/src/southbridge/amd/sb600/usb.c index 7539f08..7ff8f5c 100644 --- a/src/southbridge/amd/sb600/usb.c +++ b/src/southbridge/amd/sb600/usb.c @@ -119,6 +119,11 @@ static void usb_init2(struct device *dev) dword &= ~(1 << 28); pci_write_config32(dev, 0x50, dword); + /* EHCI Erratum (adapted from Linux) */ + dword = pci_read_config32(dev, 0x53); + dword |= (1 << 3); + pci_write_config32(dev, 0x53, dword); + /* RPR5.14 Disable USB PHY PLL Reset signal to come from ACPI */ byte = pci_read_config8(dev, 0x54); byte &= ~(1 << 0);

1 0

New patch to review for filo: de5b214 linux_load: Put initrd before FILO
by Patrick Georgi 28 Oct '11

28 Oct '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/344 -gerrit commit de5b2140a1ff7595b8988a903f9a4d175c05c3ad Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Oct 28 12:02:58 2011 +0200 linux_load: Put initrd before FILO off by one that made Linux reject some initrds. Change-Id: Ifc2d4446d78992298f656cfc92f01cf5ac0c6d90 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- i386/linux_load.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/i386/linux_load.c b/i386/linux_load.c index 8d00ca2..07855bd 100644 --- a/i386/linux_load.c +++ b/i386/linux_load.c @@ -576,7 +576,7 @@ static int load_initrd(struct linux_header *hdr, /* FILO itself is at the top of RAM. (relocated) * So, try putting initrd just below us. */ - end = virt_to_phys(_start); + end = virt_to_phys(_start - 1); if (end > max) end = max;

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Patch merged into coreboot/master: 269d109 Fix checksum calculation both in romstage and ramstage.
by gerrit＠coreboot.org 28 Oct '11

28 Oct '11

the following patch was just integrated into master: commit 269d1090d86f65b4fe674ee28142b4cdaa1b088f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Oct 27 18:42:53 2011 +0200 Fix checksum calculation both in romstage and ramstage. The earlier fix for CMOS checksums only fixed the function rtc_set_checksum, which would fix the checksum, but then coreboot would no longer honor the settings because it assumed the checksum is wrong after this. This change fixes the remaining functions. Change-Id: I3f52d074df29fc29ae1d940b3dcec3aa2cfc96a5 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Oct 28 09:09:39 2011, giving +2 See http://review.coreboot.org/342 for details. -gerrit

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Patch merged into coreboot/master: 8d6fdfc Add support for AMD IMC controller.
by gerrit＠coreboot.org 27 Oct '11

27 Oct '11

the following patch was just integrated into master: commit 8d6fdfc9686dcce013225a9e15eec32c78a73df7 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Thu Oct 27 20:42:11 2011 +0200 Add support for AMD IMC controller. This patch adds support to dump SIO like interface of AMD Embedded Controller in the SB7xx and SB8xxx southbridges. Parts of the register interface are documented in SBxxx RRG BDG. Change-Id: Ib2ccaa3dfe33cfa8e7cba19d8ab0798286ad2f92 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Build-Tested: build bot (Jenkins) at Thu Oct 27 21:13:38 2011, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Thu Oct 27 22:28:55 2011, giving +2 See http://review.coreboot.org/343 for details. -gerrit

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coreboot October 2011